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stringlengths 6
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PhilippMundhenk/AutomotiveEthernetSwitch
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aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd
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1
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38606
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-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_0 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_0_arch : ARCHITECTURE IS "fifo_generator_0,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 16,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 2,
C_AXIS_TKEEP_WIDTH => 2,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc706/temac_testbench_source/sources_1/imports/example_design/axi_lite_sm/tri_mode_ethernet_mac_0_axi_lite_sm.vhd
|
1
|
36859
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_axi_lite_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end tri_mode_ethernet_mac_0_axi_lite_sm;
architecture rtl of tri_mode_ethernet_mac_0_axi_lite_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
CHANGE_SPEED,
MDIO_RD,
MDIO_POLL_CHECK,
MDIO_1G,
MDIO_10_100,
MDIO_RESTART,
MDIO_LOOPBACK,
MDIO_STATS,
MDIO_STATS_POLL_CHECK,
RESET_MAC_RX,
RESET_MAC_TX,
CNFG_MDIO,
CNFG_FLOW,
CNFG_FILTER,
CNFG_FRM_FILTER_1,
CNFG_FRM_FILTER_2,
CNFG_FRM_FILTER_3,
CNFG_FRM_FILTER_MASK_1,
CNFG_FRM_FILTER_MASK_2,
CNFG_FRM_FILTER_MASK_3,
CHECK_SPEED);
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Flow control configuration register address (0x40C0)
constant CONFIG_FLOW_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"40C";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- Unicast Word 0 configuration register address (0x7000)
constant CONFIG_UNI0_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"700";
-- Unicast Word 1 configuration register address (0x7040)
constant CONFIG_UNI1_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"704";
-- Address Filter configuration register address (0x7080)
constant CONFIG_ADDR_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"708";
-- Frame filter bytes (3 to 0) register address (0x710)
constant CONFIG_FRAME_FILTER_1 : std_logic_vector(16 downto 0) := "00000" & X"710";
-- Frame filter bytes (7 to 4) register address (0x714)
constant CONFIG_FRAME_FILTER_2 : std_logic_vector(16 downto 0) := "00000" & X"714";
-- Frame filter bytes (11 to 8) register address (0x718)
constant CONFIG_FRAME_FILTER_3 : std_logic_vector(16 downto 0) := "00000" & X"718";
-- Frame filter mask bytes (3 to 0) register address (0x750)
constant CONFIG_FRAME_FILTER_MASK_1 : std_logic_vector(16 downto 0) := "00000" & X"750";
-- Frame filter mask bytes (7 to 4) register address (0x754)
constant CONFIG_FRAME_FILTER_MASK_2 : std_logic_vector(16 downto 0) := "00000" & X"754";
-- Frame filter mask bytes (11 to 8) register address (0x758)
constant CONFIG_FRAME_FILTER_MASK_3 : std_logic_vector(16 downto 0) := "00000" & X"758";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0);
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0);
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal speedis10 : std_logic;
signal speedis100 : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
signal design_on_board : std_logic_vector(3 downto 0) := X"0";
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
speedis10 <= '1' when speed = "00" else '0';
speedis100 <= '1' when speed = "01" else '0';
update_speed_sync_inst :tri_mode_ethernet_mac_0_sync_block
port map (
clk => s_axi_aclk,
data_in => update_speed,
data_out => update_speed_sync
);
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write 2E to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
-- enable mdio)
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000068";
axi_state <= CHANGE_SPEED;
end if;
when CHANGE_SPEED =>
-- program the MAC to the required speed
assert false
report "Programming MAC speed" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= speed & X"0000000" & "00";
axi_state <= MDIO_RD;
when MDIO_RD =>
-- read phy status - if response is all ones then do not perform any
-- further MDIO accesses
assert false
report "Checking for PHY" & cr
severity note;
drive_mdio <= '1'; -- switch axi transactions to use mdio values..
start_mdio <= '1';
writenread <= '0';
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_POLL_CHECK;
when MDIO_POLL_CHECK =>
if axi_rd_data(15 downto 0) = X"ffff" then
-- if status is all ones then no PHY exists at this address
-- (this is used by the tri_mode_ethernet_mac_0_demo_tb to avoid performing lots of phy accesses)
design_on_board <= X"0";
axi_state <= RESET_MAC_RX;
else
design_on_board <= X"8";
axi_state <= MDIO_1G;
end if;
when MDIO_1G =>
-- set 1G advertisement
assert false
report "Setting PHY 1G advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_1000BASET_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- 0x200 is 1G full duplex, 0x100 is 1G half duplex
-- only advertise the mode we want..
axi_wr_data <= X"0000" & "000000" & speed(1) & '0' & X"00";
axi_state <= MDIO_10_100;
when MDIO_10_100 =>
-- set 10/100 advertisement
assert false
report "Setting PHY 10/100M advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_ABILITY_REG;
mdio_op <= MDIO_OP_WR;
-- bit8 : full 100M, bit7 : half 100M, bit6 : full 10M, bit5 : half 10M
-- only advertise the mode we want..
axi_wr_data <= X"00000" & "000" & speedis100 & '0' & speedis10 & "000000";
axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
if phy_loopback = '1' then
-- bit15: software reset, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "10" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= MDIO_LOOPBACK;
else
-- bit15: software reset, bit12 : AN enable (set after power up)
axi_wr_data <= X"0000" & X"9" & X"000";
axi_state <= MDIO_STATS;
end if;
when MDIO_LOOPBACK =>
-- set phy loopback
assert false
report "Applying PHY loopback" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- bit14: loopback, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "01" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= RESET_MAC_RX;
when MDIO_STATS =>
start_mdio <= '1';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= RESET_MAC_RX;
else
axi_state <= MDIO_STATS;
end if;
-- once here the PHY is ACTIVE - NOTE only IEEE registers are used
when RESET_MAC_RX =>
assert false
report "Reseting MAC RX" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= RECEIVER_ADD;
axi_wr_data <= X"90000000";
axi_state <= RESET_MAC_TX;
when RESET_MAC_TX =>
assert false
report "Reseting MAC TX" & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= TRANSMITTER_ADD;
axi_wr_data <= X"90000000";
axi_state <= CNFG_MDIO;
when CNFG_MDIO =>
-- set up MDC frequency. Write 2E to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
-- enable mdio)
assert false
report "Setting MDC Frequency to 2.5MHZ...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000068";
axi_state <= CNFG_FLOW;
when CNFG_FLOW =>
assert false
report "Disabling Flow control...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= (others => '0');
axi_state <= CNFG_FILTER;
when CNFG_FILTER =>
if design_on_board = X"0" then
assert false
report "Setting core to non-promiscuous mode...." & cr
severity note;
else
assert false
report "Setting core to promiscuous mode...." & cr
severity note;
end if;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= design_on_board & X"0000000";
axi_state <= CNFG_FRM_FILTER_1;
when CNFG_FRM_FILTER_1 =>
assert false
report "Configuring FRAME FILTER 1 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_1;
axi_wr_data <= X"040302DA";
axi_state <= CNFG_FRM_FILTER_MASK_1;
when CNFG_FRM_FILTER_MASK_1 =>
assert false
report "Configuring FRAME FILTER mask 1 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_1;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CNFG_FRM_FILTER_2;
when CNFG_FRM_FILTER_2 =>
assert false
report "Configuring FRAME FILTER 2 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_2;
axi_wr_data <= X"025A0605";
axi_state <= CNFG_FRM_FILTER_MASK_2;
when CNFG_FRM_FILTER_MASK_2 =>
assert false
report "Configuring FRAME FILTER mask 2 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_2;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CNFG_FRM_FILTER_3;
when CNFG_FRM_FILTER_3 =>
assert false
report "Configuring FRAME FILTER 3 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_3;
axi_wr_data <= X"06050403";
axi_state <= CNFG_FRM_FILTER_MASK_3;
when CNFG_FRM_FILTER_MASK_3 =>
assert false
report "Configuring FRAME FILTER mask 3 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_3;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
if update_speed_reg = '1' then
axi_state <= CHANGE_SPEED;
speed <= mac_speed;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/fifo_generator_v12_0_pkg.vhd
|
5
|
136312
|
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/fifo_generator_top.vhd
|
5
|
36480
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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k7iO5XNwiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25264)
`protect data_block
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`protect end_protected
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_analog_io/_primary.vhd
|
3
|
212
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.vhdl
|
1
|
1511
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:39:23 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.vhdl
-- Design : fifo_generator_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_generator_1 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end fifo_generator_1;
architecture stub of fifo_generator_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[93:0],wr_en,rd_en,dout[93:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2014.1";
begin
end;
|
mit
|
Nic30/hwtHdlParsers
|
hwtHdlParsers/tests/vhdlCodesign/vhdl/ap_vldWithParam.vhd
|
1
|
231
|
library ieee;
use ieee.std_logic_1164.all;
entity Axi_basic_slave is
generic(
DATA_WIDTH : integer := 13
);
port(
data_vld : in std_logic;
data_data : in std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end Axi_basic_slave;
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f@a@b@r@i@c@i@f_@h@m/_primary.vhd
|
3
|
1589
|
library verilog;
use verilog.vl_types.all;
entity FABRICIF_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
FPGAGOOD : in vl_logic;
DS_HM_HADDR : in vl_logic_vector(19 downto 0);
DS_HM_HMASTLOCK : in vl_logic;
DS_HM_HSIZE : in vl_logic_vector(1 downto 0);
DS_HM_HTRANS1 : in vl_logic;
DS_HM_HSEL : in vl_logic;
DS_HM_HWRITE : in vl_logic;
DS_HM_HWDATA : in vl_logic_vector(31 downto 0);
DS_HM_HREADY : in vl_logic;
DS_HM_HREADYOUT : out vl_logic;
DS_HM_HRESP : out vl_logic;
DS_HM_HRDATA : out vl_logic_vector(31 downto 0);
F_HM_ADDR : out vl_logic_vector(19 downto 0);
F_HM_WDATA : out vl_logic_vector(31 downto 0);
F_HM_RDATA : in vl_logic_vector(31 downto 0);
F_HM_HMASTLOCK : out vl_logic;
F_HM_HSIZE : out vl_logic_vector(1 downto 0);
F_HM_HTRANS1 : out vl_logic;
F_HM_HWRITE : out vl_logic;
F_HM_HREADY : in vl_logic;
F_HM_HRESP : in vl_logic;
F_HM_PSEL : out vl_logic;
F_HM_PENABLE : out vl_logic;
F_HM_PWRITE : out vl_logic;
F_HM_PREADY : in vl_logic;
F_HM_PSLVERR : in vl_logic
);
end FABRICIF_HM;
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@m@i@s@c_@s@y@n@c12/_primary.vhd
|
3
|
330
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
Q : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MISC_SYNC12;
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@c@m@master3@stage/_primary.vhd
|
3
|
1817
|
library verilog;
use verilog.vl_types.all;
entity CMMaster3Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic
);
end CMMaster3Stage;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd
|
11
|
75944
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Dyq68Z0n4A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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YARDA5WTDfJYYxDul0c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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q2ZAih3XkHZ90+WBcpM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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LlFbftiFAQxmRnLdMHxJB54hIudPFuXG21000Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 54480)
`protect data_block
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`protect end_protected
|
mit
|
Nic30/hwtHdlParsers
|
hwtHdlParsers/tests/vhdlCodesign/vhdl/fifo.vhd
|
1
|
2062
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity Fifo is
Generic (
constant DATA_WIDTH : positive := 64;
constant DEPTH : positive := 200
);
Port (
clk : in STD_LOGIC;
rst_n : in STD_LOGIC;
data_in_en : in STD_LOGIC;
data_in_data : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
data_in_wait : out STD_LOGIC;
data_out_en : in STD_LOGIC;
data_out_data : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
data_out_wait : out STD_LOGIC
);
end Fifo;
architecture Behavioral of Fifo is
begin
-- Memory Pointer Process
fifo_proc : process (clk)
type FIFO_Memory is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
variable Memory : FIFO_Memory;
variable Head : natural range 0 to DEPTH - 1;
variable Tail : natural range 0 to DEPTH - 1;
variable Looped : boolean;
begin
if rising_edge(clk) then
if rst_n = '0' then
Head := 0;
Tail := 0;
Looped := false;
data_in_wait <= '0';
data_out_wait <= '1';
else
if (data_out_en = '1') then
if ((Looped = true) or (Head /= Tail)) then
-- Update data output
data_out_data <= Memory(Tail);
-- Update Tail pointer as needed
if (Tail = DEPTH - 1) then
Tail := 0;
Looped := false;
else
Tail := Tail + 1;
end if;
end if;
end if;
if (data_in_en = '1') then
if ((Looped = false) or (Head /= Tail)) then
-- Write Data to Memory
Memory(Head) := data_in_data;
-- Increment Head pointer as needed
if (Head = DEPTH - 1) then
Head := 0;
Looped := true;
else
Head := Head + 1;
end if;
end if;
end if;
-- Update Empty and Full flags
if (Head = Tail) then
if Looped then
data_in_wait <= '1';
else
data_out_wait <= '1';
end if;
else
data_out_wait <= '0';
data_in_wait <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/fifo_generator_v12_0_defaults.vhd
|
5
|
30145
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/dc_ss_fwft.vhd
|
5
|
9156
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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jRny4T5vWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/sim/fifo_generator_1.vhd
|
1
|
33376
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_1 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_1;
ARCHITECTURE fifo_generator_1_arch OF fifo_generator_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_1_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 7,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 94,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 94,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 63,
C_PROG_FULL_THRESH_NEGATE_VAL => 62,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 7,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 7,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_1_arch;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_low_latency.vhd
|
5
|
43742
|
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc706/aes_zc706.srcs/sources_1/rtl/clocking/aeg_design_clocks.vhd
|
2
|
7348
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_clocks.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates the clocking logic required for the
-- example design.
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity aeg_design_0_clocks is
port (
-- clocks
clk_in_p : in std_logic;
clk_in_n : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
dcm_locked : out std_logic;
-- clock outputs
gtx_clk_bufg : out std_logic;
refclk_bufg : out std_logic;
s_axi_aclk : out std_logic
);
end aeg_design_0_clocks;
architecture RTL of aeg_design_0_clocks is
------------------------------------------------------------------------------
-- Component declaration for the clock generator
------------------------------------------------------------------------------
component aeg_design_0_clk_wiz
port
( -- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component aeg_design_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal clkin1 : std_logic;
signal clkin1_bufg : std_logic;
signal mmcm_rst : std_logic;
signal dcm_locked_int : std_logic;
signal dcm_locked_sync : std_logic;
signal dcm_locked_reg : std_logic := '1';
signal dcm_locked_edge : std_logic := '1';
signal mmcm_reset_in : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFDS
port map
(O => clkin1,
I => clk_in_p,
IB => clk_in_n);
-- route clkin1 through a BUFGCE for the MMCM reset generation logic
bufg_clkin1 : BUFGCE port map (I => clkin1, CE => '1', O => clkin1_bufg);
-- detect a falling edge on dcm_locked (after resyncing to this domain)
lock_sync : aeg_design_0_sync_block
port map (
clk => clkin1_bufg,
data_in => dcm_locked_int,
data_out => dcm_locked_sync
);
-- for the falling edge detect we want to force this at power on so init the flop to 1
dcm_lock_detect_p : process(clkin1_bufg)
begin
if clkin1_bufg'event and clkin1_bufg = '1' then
dcm_locked_reg <= dcm_locked_sync;
dcm_locked_edge <= dcm_locked_reg and not dcm_locked_sync;
end if;
end process dcm_lock_detect_p;
mmcm_reset_in <= glbl_rst or dcm_locked_edge;
-- the MMCM reset should be at least 5ns - that is one cycle of the input clock -
-- since the source of the input reset is unknown (a push switch in board design)
-- this needs to be debounced
mmcm_reset_gen : aeg_design_0_reset_sync
port map (
clk => clkin1_bufg,
enable => '1',
reset_in => mmcm_reset_in,
reset_out => mmcm_rst
);
------------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
------------------------------------------------------------------------------
clock_generator : aeg_design_0_clk_wiz
port map (
-- Clock in ports
CLK_IN1 => clkin1,
-- Clock out ports
CLK_OUT1 => gtx_clk_bufg,
CLK_OUT2 => s_axi_aclk,
CLK_OUT3 => refclk_bufg,
-- Status and control signals
RESET => mmcm_rst,
LOCKED => dcm_locked_int
);
dcm_locked <= dcm_locked_int;
end RTL;
|
mit
|
Nic30/hwtHdlParsers
|
hwtHdlParsers/tests/vhdlCodesign/vhdl/fnImport/package0.vhd
|
1
|
347
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package package0 is
function max(l, r : integer) return integer;
end package0;
package body package0 is
function max(l, r : integer) return integer is
begin
if l > r then
return l;
else
return r;
end if;
end;
end package0;
|
mit
|
caiopo/mips-multiciclo
|
src/extensaoSinal.vhd
|
1
|
992
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity extensaoSinal is
generic(
larguraOriginal: natural := 8;
larguraExtendida: natural := 8);
port(
entrada: in std_logic_vector(larguraOriginal-1 downto 0);
saida: out std_logic_vector(larguraExtendida-1 downto 0)
);
end entity;
architecture comportamental of extensaoSinal is
begin
saida(larguraOriginal-1 downto 0) <= entrada;
saida(larguraExtendida-1 downto larguraOriginal) <= (others => entrada(larguraOriginal-1));
end architecture;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/ramfifo/bram_sync_reg.vhd
|
5
|
7904
|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl
|
1
|
1566
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:50:48 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl
-- Design : blk_mem_gen_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blk_mem_gen_0 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end blk_mem_gen_0;
architecture stub of blk_mem_gen_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[8:0],dina[63:0],clkb,enb,addrb[8:0],doutb[63:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_2,Vivado 2014.1";
begin
end;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_top.vhd
|
11
|
73440
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52624)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/ramfifo/wr_dc_fwft_ext_as.vhd
|
5
|
13630
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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76bcgq4rtw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd
|
5
|
19078
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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hkKu2/ksag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_arbitration.vhd
|
2
|
8870
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.12.2013 10:00:16
-- Design Name:
-- Module Name: output_queue_arbitration - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: This module forwards the frames in the output queue memory to the transmitter-side of the MAC
-- The output queue fifo provides the start address in the output queue memory and the length in bytes
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity output_queue_arbitration is
Generic (
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_DATA_WIDTH : integer;
OQ_FIFO_LENGTH_START : integer;
OQ_FIFO_TIMESTAMP_START : integer;
OQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fifo
oqarb_in_fifo_enable : out std_logic;
oqarb_in_fifo_prio : out std_logic;
oqarb_in_fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqarb_in_fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
-- timestamp
oqarb_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oqarb_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- input interface memory
oqarb_in_mem_data : in std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_in_mem_enable : out std_logic;
oqarb_in_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
oqarb_in_mem_prio : out std_logic;
-- output interface mac
oqarb_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_out_valid : out std_logic;
oqarb_out_last : out std_logic;
oqarb_out_ready : in std_logic
);
end output_queue_arbitration;
architecture rtl of output_queue_arbitration is
-- state machine
type state is (
IDLE,
ARBITRATE,
READ_MEM
);
-- state signals
signal cur_state : state;
signal nxt_state : state;
signal empty_const : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '1');
-- config_output_state machine signals
signal update_cnt_sig : std_logic;
signal reset_frame_length_sig : std_logic;
signal measure_latency_sig : std_logic;
signal choose_fifo_sig : std_logic;
-- process registers
signal frame_length_cnt : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal latency_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal winner_fifo_reg : std_logic_vector(0 downto 0);
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next data_input_state, combinitorial logic
output_logic_p : process(cur_state, oqarb_in_fifo_empty, oqarb_out_ready, frame_length_cnt, oqarb_in_fifo_data, empty_const, winner_fifo_reg)
begin
-- default signal assignments
nxt_state <= IDLE;
update_cnt_sig <= '0';
measure_latency_sig <= '0';
reset_frame_length_sig <= '0';
oqarb_in_fifo_enable <= '0';
oqarb_out_last <= '0';
oqarb_out_valid <= '0';
oqarb_in_fifo_prio <= '0';
choose_fifo_sig <= '0';
case cur_state is
when IDLE =>
if oqarb_in_fifo_empty /= empty_const and oqarb_out_ready = '1' then
nxt_state <= ARBITRATE;
choose_fifo_sig <= '1'; -- choose_fifo_p
end if;
when ARBITRATE =>
nxt_state <= READ_MEM;
update_cnt_sig <= '1'; -- cnt_frame_length_p
measure_latency_sig <= '1'; -- timestamp_p
when READ_MEM =>
if frame_length_cnt >= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START+FRAME_LENGTH_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START)
and oqarb_out_ready = '1' then
nxt_state <= IDLE;
reset_frame_length_sig <= '1'; -- cnt_frame_length_p
oqarb_in_fifo_enable <= '1';
oqarb_in_fifo_prio <= winner_fifo_reg(0);
oqarb_out_last <= '1';
oqarb_out_valid <= '1';
else
nxt_state <= READ_MEM;
update_cnt_sig <= oqarb_out_ready; -- cnt_frame_length_p
oqarb_out_valid <= oqarb_out_ready;
end if;
end case;
end process output_logic_p;
-- count frame bytes received from fabric
cnt_frame_length_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
frame_length_cnt <= (others => '0');
else
frame_length_cnt <= frame_length_cnt;
if reset_frame_length_sig = '1' then
frame_length_cnt <= (others => '0');
elsif update_cnt_sig = '1' then
frame_length_cnt <= frame_length_cnt + 1;
end if;
end if;
end if;
end process;
-- take transmission timestamp of the message
timestamp_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
latency_reg <= (others => '0');
else
latency_reg <= latency_reg;
if measure_latency_sig = '1' then
latency_reg <= oqarb_in_timestamp_cnt - oqarb_in_fifo_data
(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START)
+ 50; -- considering the clock cycles through mac, rx, tx_fifo
end if;
end if;
end if;
end process;
-- determine the fifo to be read from
choose_fifo_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
winner_fifo_reg <= (others => '0');
else
winner_fifo_reg <= winner_fifo_reg;
if choose_fifo_sig = '1' then
if NR_OQ_FIFOS = 2 and oqarb_in_fifo_empty(NR_OQ_FIFOS-1) = '0' then -- high priority fifo
winner_fifo_reg(0) <= '1';
else
winner_fifo_reg(0) <= '0';
end if;
end if;
end if;
end if;
end process;
output_p : process(oqarb_in_mem_data, winner_fifo_reg)
begin
if NR_OQ_FIFOS = 1 then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
if winner_fifo_reg(0) = '0' then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
oqarb_out_data <= oqarb_in_mem_data(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto TRANSMITTER_DATA_WIDTH);
end if;
end if;
end process;
oqarb_in_mem_enable <= oqarb_out_ready;
oqarb_in_mem_addr <= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START) + frame_length_cnt;
oqarb_out_latency <= latency_reg;
oqarb_in_mem_prio <= winner_fifo_reg(0);
end rtl;
|
mit
|
rkujawa/cr2amiga
|
clk_gen.vhd
|
1
|
599
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clk_gen is
port( clk : in STD_LOGIC;
clkmod : out STD_LOGIC;
divval : in integer);
end clk_gen;
architecture Behavioral of clk_gen is
signal counter,divide : integer := 0;
begin
divide <= divval;
process(clk)
begin
if( rising_edge(clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
clkmod <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
clkmod <= '1';
else
clkmod <= '0';
counter <= 0;
end if;
end if;
end process;
end Behavioral;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/sim/blk_mem_gen_2.vhd
|
1
|
12117
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_2;
ARCHITECTURE blk_mem_gen_2_arch OF blk_mem_gen_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.9418 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_2_arch;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_sshft.vhd
|
5
|
23122
|
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_comps_builtin.vhd
|
5
|
32006
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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ox5JUUKzHA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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8QdyG+52y+v4Z4n70Yc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
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`protect end_protected
|
mit
|
gihankarunarathne/vhdl-learn
|
DataFlow/ConditionBasedOn1Matching.vhd
|
1
|
1307
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:20:40 08/27/2013
-- Design Name:
-- Module Name: ConditionBasedOn1Matching - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ConditionBasedOn1Matching is
port(s0,s1: in STD_LOGIC;
input: in STD_LOGIC_VECTOR (3 downto 0);
z: out STD_LOGIC);
end ConditionBasedOn1Matching;
architecture Behavioral of ConditionBasedOn1Matching is
begin
z <= input(0) when s0='0' else -- if stop after first matching condition
-- So, here it out put input(0) when (s0=0 and s1=0) or (s0=0 and s1=1)
input(1) when s0='1' and s1='0' else
input(2) when s0='0' and s1='1' else
input(3);
end Behavioral;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/builtin/logic_builtin.vhd
|
5
|
30579
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20896)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_as.vhd
|
5
|
20484
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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JgZBPy8Keg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424)
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`protect end_protected
|
mit
|
Nic30/hwtHdlParsers
|
hwtHdlParsers/tests/vhdlCodesign/vhdl/minimals/functionBody.vhd
|
1
|
158
|
package body package0 is
function fn0 (param0 : bit_vector)
return bit is
begin
-- function code
end fn0;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup_mod.vhd
|
1
|
14503
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 12:06:03
-- Design Name: rx_path_lookup.vhd
-- Module Name: rx_path_lookup - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- this module handles the frame lookup
-- according to the header input the output ports for each frame are searched for in the lookup memory
-- the lookup memory constists of one base configuration, frame confiugrations and one default configuration
-- - base configuration gives the entry to the frame configuration
-- - frame configurations returns a one-hot-encoded output ports vector for each valid mac destination address
-- and the priority of the frame
-- - for mac address not in the lookup table the default configuration decides whether to skip this frame or
-- to send it to default output ports
-- transmitting the frame on the receiving port is prevented by setting the corresponding bit in the ports vector to '0'
--
-- for more details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
-- for more detail on the lookup module see switch_port_rxpath_lookup.svg
--
-- base_address is an internal register pointing to the base configuration; lateron it has to be connected to a processor
-- the housekeeping processor also has to take care of writing all the configurations to the lookup memory
-- thereby, an overflow of the memory address space of the binary list must not happen as no overflow control is
-- implemented in the lookup algorithm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_lookup is
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
-- lookup memory address constants
LOWER_ADDR_START : integer := 20;
UPPER_ADDR_START : integer := 40;
DEF_ADDR_START : integer := 0;
ENABLE_START : integer := 63;
PORTS_START : integer := 60;
PRIO_START : integer := 48;
SKIP_FRAME_START : integer := 0;
DEST_MAC_START : integer := 0
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end rx_path_lookup;
architecture rtl of rx_path_lookup is
-- determine the next search address (median) of the binary search
-- upper and lower are the corresponding border memory adresses of the remaining search space
-- return value median = (upper + lower) / 2
function upper_add_lower_by2_f (upper, lower : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0))
return std_logic_vector is
variable x1 : integer;
variable x2 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH downto 0);
variable x3 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
x1 := to_integer(unsigned(upper)) + to_integer(unsigned(lower));
x2 := std_logic_vector(to_unsigned(x1,x2'length));
x3 := x2(LOOKUP_MEM_ADDR_WIDTH downto 1);
return x3;
end upper_add_lower_by2_f;
-- lookup state machine
type state is (
IDLE,
READ_BASE,
LOOKUP,
READ_DEFAULT
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal read_header_sig : std_logic := '0';
signal read_base_sig : std_logic := '0';
signal read_default_sig : std_logic := '0';
signal lookup_valid_sig : std_logic := '0';
signal read_lookup_sig : std_logic := '0';
signal update_sig : std_logic := '0';
signal lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
-- process registers
signal dest_mac_reg : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
signal vlan_enable_reg : std_logic;
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lower_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal default_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal skip_frame_reg : std_logic;
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- alias signals for memory read access
signal mem_lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_default_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_lookup_enable_sig : std_logic;
signal mem_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal mem_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_skip_frame_sig : std_logic;
signal mem_dest_mac_sig : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
-- internal registers (to be connected to the outside, e.g. housekeeping processor)
signal base_address : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0) := "000000000";
signal mem_addr_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
-- alias names (signals) for lookup memory output ranges
mem_lower_sig <= mem_data(LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto LOWER_ADDR_START);
mem_upper_sig <= mem_data(UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto UPPER_ADDR_START);
mem_default_sig <= mem_data(DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto DEF_ADDR_START);
mem_lookup_enable_sig <= mem_data(ENABLE_START);
mem_ports_sig <= mem_data(PORTS_START+NR_PORTS-1 downto PORTS_START);
mem_prio_sig <= mem_data(PRIO_START+VLAN_PRIO_WIDTH-1 downto PRIO_START);
mem_skip_frame_sig <= mem_data(SKIP_FRAME_START);
mem_dest_mac_sig <= mem_data(DEST_MAC_START+DEST_MAC_WIDTH-1 downto DEST_MAC_START);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, lookup_in_valid, mem_lookup_enable_sig, mem_default_sig,
BASE_ADDRESS, median_sig, upper_reg, lower_reg, median_reg, default_reg, dest_mac_reg,
mem_dest_mac_sig, mem_upper_sig, mem_lower_sig)
begin
-- default signal assignments
nxt_state <= IDLE;
read_header_sig <= '0'; -- read_header_p
read_base_sig <= '0'; -- write_internal_registers_p
read_default_sig <= '0'; -- output_reg_p
lookup_valid_sig <= '0'; -- output_valid_p
read_lookup_sig <= '0'; -- output_reg_p
update_sig <= '0'; -- write_internal_registers_p
upper_sig <= (others => '0'); -- upper_add_lower_by2_f
lower_sig <= (others => '0'); -- upper_add_lower_by2_f
-- default output values
mem_enable <= '0';
mem_addr_sig <= (others => '1');
case cur_state is
when IDLE => -- waiting for a new header
if lookup_in_valid = '1' then
nxt_state <= READ_BASE;
read_header_sig <= '1'; -- read_header_p
mem_enable <= '1';
mem_addr_sig <= BASE_ADDRESS;
end if;
when READ_BASE => -- read base address, determine if lookup is enabled
read_base_sig <= '1'; -- internal_reg_p
mem_enable <= '1';
if mem_lookup_enable_sig = '0' then -- lookup disabled, read default configuration
nxt_state <= READ_DEFAULT;
mem_addr_sig <= mem_default_sig;
else -- lookup enabled, search for address in the middle of binary lookup list
nxt_state <= LOOKUP;
upper_sig <= mem_upper_sig; -- upper_add_lower_by2_f
lower_sig <= mem_lower_sig; -- upper_add_lower_by2_f
mem_addr_sig <= median_sig; -- upper_add_lower_by2_f
end if;
when LOOKUP => -- lookup the median memory address and check if the memory mac address matches the frame mac address
if dest_mac_reg = mem_dest_mac_sig then -- MAC ADDRESS found -> Algorithm terminates
nxt_state <= IDLE;
read_lookup_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
elsif upper_reg <= lower_reg then -- MAC ADDRESS not found -> Algorithm terminats with default configuration
nxt_state <= READ_DEFAULT;
mem_addr_sig <= default_reg;
mem_enable <= '1';
else -- MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= '1'; -- internal_reg_p
mem_addr_sig <= median_sig; -- upper_add_lower_by2_f
mem_enable <= '1';
nxt_state <= LOOKUP;
if dest_mac_reg > mem_dest_mac_sig then
upper_sig <= upper_reg; -- upper_add_lower_by2_f
lower_sig <= median_reg + 1; -- upper_add_lower_by2_f
else -- dest_mac_reg < mem_dest_mac_sig
upper_sig <= median_reg - 1; -- upper_add_lower_by2_f
lower_sig <= lower_reg; -- upper_add_lower_by2_f
end if;
end if;
when READ_DEFAULT =>
nxt_state <= IDLE;
read_default_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
end case;
end process;
-- handshake protocol to read header from previous module and store header into internal buffer
read_header_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_mac_reg <= (others => '0');
vlan_enable_reg <= '0';
vlan_prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
lookup_in_ready <= '0';
else
dest_mac_reg <= dest_mac_reg;
vlan_enable_reg <= vlan_enable_reg;
vlan_prio_reg <= vlan_prio_reg;
timestamp_reg <= timestamp_reg;
lookup_in_ready <= '0';
if read_header_sig = '1' then
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= '1';
end if;
end if;
end if;
end process;
-- handles access to the internal registers needed for lookup
internal_reg_p : process (clk) -- to be done
begin
if clk'event and clk = '1' then
if reset = '1' then
lower_reg <= (others => '0');
upper_reg <= (others => '0');
default_reg <= (others => '0');
median_reg <= (others => '0');
mem_addr <= (others => '1');
else
lower_reg <= lower_reg;
upper_reg <= upper_reg;
default_reg <= default_reg;
median_reg <= median_reg;
mem_addr <= mem_addr_sig;
if read_base_sig = '1' then -- read inital values from base configuration
lower_reg <= mem_lower_sig;
upper_reg <= mem_upper_sig;
default_reg <= mem_default_sig;
median_reg <= median_sig;
elsif update_sig = '1' then -- update registers according to remaining search space
lower_reg <= lower_sig;
upper_reg <= upper_sig;
median_reg <= median_sig;
end if;
end if;
end if;
end process;
-- assign next memory search address: median address in the remaining address search space
median_sig <= upper_add_lower_by2_f(upper_sig, lower_sig);
-- updates the output value registers (ports, priority and skip)
output_reg_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
ports_reg <= (others => '0');
prio_reg <= (others => '0');
skip_frame_reg <= '0';
else
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if read_default_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0';
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= mem_skip_frame_sig;
elsif read_lookup_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0'; -- comment for loopback functionality
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= '0';
end if;
end if;
end if;
end process;
-- sets the output valid bit
output_valid_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
lookup_out_valid <= '0';
else
lookup_out_valid <= '0';
if lookup_valid_sig = '1' then
lookup_out_valid <= '1';
end if;
end if;
end if;
end process;
-- other outputs
lookup_out_ports <= ports_reg;
lookup_out_prio <= prio_reg;
lookup_out_skip <= skip_frame_reg;
lookup_out_timestamp <= timestamp_reg;
end rtl;
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@client@addr@data_@h@m/_primary.vhd
|
3
|
1234
|
library verilog;
use verilog.vl_types.all;
entity ClientAddrData_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
mergedWrite : in vl_logic;
mergedHsize : in vl_logic_vector(1 downto 0);
mergedHmastlock : in vl_logic;
mergedAddr : in vl_logic_vector(19 downto 0);
regAddr : in vl_logic_vector(19 downto 0);
regWrite : in vl_logic;
hAddrPhAck : in vl_logic;
hDataClkEn : in vl_logic;
pAddrPhAck : in vl_logic;
pDataClkEn : in vl_logic;
F_HM_HMASTLOCK : out vl_logic;
F_HM_HWRITE : out vl_logic;
F_HM_HSIZE : out vl_logic_vector(1 downto 0);
F_HM_PWRITE : out vl_logic;
F_HM_ADDR : out vl_logic_vector(19 downto 0);
F_HM_WDATA : out vl_logic_vector(31 downto 0);
F_HM_RDATA : in vl_logic_vector(31 downto 0);
DS_HM_HRDATA : out vl_logic_vector(31 downto 0);
DS_HM_HWDATA : in vl_logic_vector(31 downto 0)
);
end ClientAddrData_HM;
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@d@p@r@a@m/_primary.vhd
|
3
|
1382
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_DPRAM is
port(
CLKA : in vl_logic;
CSBA : in vl_logic;
RWBA : in vl_logic;
AA : in vl_logic_vector(8 downto 0);
DIA : in vl_logic_vector(31 downto 0);
DOA : out vl_logic_vector(31 downto 0);
CLKB : in vl_logic;
CSBB : in vl_logic;
RWBB : in vl_logic;
AB : in vl_logic_vector(8 downto 0);
DIB : in vl_logic_vector(31 downto 0);
DOB : out vl_logic_vector(31 downto 0);
TEST_MODE : in vl_logic;
RB_TEST : in vl_logic;
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_DPRAM;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/fifo_generator_top_bi_sim.vhd
|
5
|
28804
|
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dwu+/i7zNaTdGyATccZTvAjQLzFaSsUFyUaE8a8uHZ4M
`protect end_protected
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@a@d@d@e@r/_primary.vhd
|
3
|
561
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_ADDER is
port(
a : in vl_logic_vector(31 downto 0);
b : in vl_logic_vector(31 downto 0);
ci : in vl_logic;
pos_sat_en : in vl_logic;
neg_sat_en : in vl_logic;
s : out vl_logic_vector(31 downto 0);
co : out vl_logic;
pos_sat : out vl_logic;
neg_sat : out vl_logic
);
end F2DSS_ACE_PPE_ADDER;
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/common/shft_ram.vhd
|
5
|
17157
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
MpyGJnakVe4eFwHNRrtXIa+RCuZaQ0qVqBUYSuXeBLDMviHSfY1mCzj/qJyuFPr2ICIcOEezrjcn
MbxPF9P92A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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dfixFhvGx8OVLViTKeg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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Ih2ZyJBgc56RetQuSlE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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sGb0DHhBkeZfnxSgW6BV6WX8CrYlM1Fweo7XMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
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283XXugFpvFZl4EtslJvwA==
`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd
|
5
|
17522
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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ssJcnXF1WJvc84SEnjo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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etrB
`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd
|
5
|
17522
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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etrB
`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/fifo_generator_v12_0_synth.vhd
|
5
|
240450
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 176256)
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
11
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_getinit_pkg.vhd
|
11
|
62911
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 44832)
`protect data_block
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`protect end_protected
|
mit
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd
|
11
|
57813
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41056)
`protect data_block
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`protect end_protected
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/bb7c21cce22cede6/ila_0_sim_netlist.vhdl
|
1
|
4948509
| null |
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/1c687287191d4ca1/dbg_ila_stub.vhdl
|
1
|
3025
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Oct 31 15:07:48 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/8a453cb79bc1df52/dbg_ila_stub.vhdl
|
1
|
3209
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Nov 01 12:03:22 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 );
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe30 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[7:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/1fbc3bf5a77a343d/dbg_ila_sim_netlist.vhdl
|
1
|
5022635
| null |
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/848354e54845ca3d/dbg_ila_sim_netlist.vhdl
|
1
|
3242916
| null |
mit
|
bwootton/Dator
|
manage_ui/static/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
superboy0712/MIPS
|
testbench/MIPS_ALU_tb.vhd
|
1
|
4653
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:20:40 10/16/2014
-- Design Name:
-- Module Name: D:/Documents/Xilinx Projects/multi_cycle_cpu/MIPS_ALU_tb.vhd
-- Project Name: multi_cycle_cpu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MIPS_ALU_tb IS
END MIPS_ALU_tb;
ARCHITECTURE behavior OF MIPS_ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
alu_ctrl : IN std_logic_vector(3 downto 0);
alu_src1 : IN std_logic_vector(31 downto 0);
alu_src2 : IN std_logic_vector(31 downto 0);
alu_zero : OUT std_logic;
alu_result : OUT std_logic_vector(31 downto 0);
alu_carry : OUT std_logic
);
END COMPONENT;
signal clock : std_logic;
--Inputs
signal alu_ctrl : std_logic_vector(3 downto 0) := (others => '0');
signal alu_src1 : std_logic_vector(31 downto 0) := (others => '0');
signal alu_src2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal alu_zero : std_logic;
signal alu_result : std_logic_vector(31 downto 0);
signal alu_carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
alu_ctrl => alu_ctrl,
alu_src1 => alu_src1,
alu_src2 => alu_src2,
alu_zero => alu_zero,
alu_result => alu_result,
alu_carry => alu_carry
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
--test add
alu_src1 <= X"f0f0f0f0";
alu_src2 <= X"0f0f0f0f";
alu_ctrl <= "0000";
wait for 10 ns;
assert alu_result = X"00000000" report "and failed" severity error;
-- test or
wait for 10 ns;
alu_src1 <= X"f0f0f0f0";
alu_src2 <= X"0f0f0f0f";
alu_ctrl <= "0001";
wait for 10 ns;
assert alu_result = X"ffffffff" report "or failed" severity error;
-- test add
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(1234567,32));
alu_src2 <= std_logic_vector(to_signed(7654321,32));
alu_ctrl <= "0010";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(8888888,32)) report "add failed" severity error;
-- test sub
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(7777777,32));
alu_src2 <= std_logic_vector(to_signed(4444444,32));
alu_ctrl <= "0110";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(3333333,32)) report "sub failed" severity error;
-- test sub2
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(4444444,32));
alu_src2 <= std_logic_vector(to_signed(7777777,32));
alu_ctrl <= "0110";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(-3333333,32)) report "sub2 failed" severity error;
-- test slt
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(4444444,32));
alu_src2 <= std_logic_vector(to_signed(7777777,32));
alu_ctrl <= "0111";
wait for 10 ns;
assert alu_result = x"00000001" report "slt failed" severity error;
-- test nor
wait for 10 ns;
alu_src1 <= X"00000000";
alu_src2 <= X"00000000";
alu_ctrl <= "1100";
wait for 10 ns;
assert alu_result = x"ffffffff" report "nor failed" severity error;
wait;
end process;
END;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/a27f5e107e0af35c/ila_0_stub.vhdl
|
1
|
2653
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 13:30:12 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe14 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[7:0],probe21[7:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/c5918a3d400116a5/ila_0_sim_netlist.vhdl
|
1
|
4818659
| null |
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/83ee88fd74348eb5/srio_gen2_0_stub.vhdl
|
1
|
6142
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:17:34 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k160tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
|
mit
|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/01b1ddbaf2a615e4/ila_0_sim_netlist.vhdl
|
1
|
3712825
| null |
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_sincos_fused.vhd
|
10
|
17997
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sincos_fused IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_sin : OUT STD_LOGIC;
exponentout_sin : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_sin : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_cos : OUT STD_LOGIC;
exponentout_cos : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_cos : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sincos_fused;
ARCHITECTURE rtl of fp_sincos_fused IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign_sin, quadrantsign_cos, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff_sin,signcalcff_cos : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4+cordic_depth DOWNTO 1);
signal fixed_sin : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sinnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sinff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_cosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_sin : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_sin : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_sin : STD_LOGIC;
signal countnode_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_cos : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_cos : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_cos : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1_fused
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign_sin <= circle(36); -- sin negative in quadrants 3&4
quadrantsign_cos <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= '0';
signcalcff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+cordic_depth LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff_sin(1) <= quadrantsign_sin XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= signcalcff_sin(k-1);
END LOOP;
signcalcff_cos(1) <= quadrantsign_cos;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_cos(k) <= signcalcff_cos(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
-- Here is an interesting thing - depending on the quadrant the input is in, computation
-- or a sin or cosine can use sin or cosine result. What this means is that we may have to swap
-- results when they come out of the cordic block.
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4+cordic_depth LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1_fused
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sin_out=>fixed_sin,
cos_out=>fixed_cos);
gfxa: IF (width < 36) GENERATE
fixed_sinnode <= (fixed_sin & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_cos & zerovec(36-width DOWNTO 1));
fixed_cosnode <= (fixed_cos & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_sin & zerovec(36-width DOWNTO 1));
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sinnode <= fixed_sin when (select_sincosff(4+cordic_depth) = '1') else fixed_cos;
fixed_cosnode <= fixed_cos when (select_sincosff(4+cordic_depth) = '1') else fixed_sin;
END GENERATE;
clz1: fp_clz36
PORT MAP (mantissa=>fixed_sinnode,leading=>countnode_sin);
clz2: fp_clz36
PORT MAP (mantissa=>fixed_cosnode,leading=>countnode_cos);
sft1: fp_lsft36
PORT MAP (inbus=>fixed_sinff,shift=>countff_sin,
outbus=>mantissanormnode_sin);
sft2: fp_lsft36
PORT MAP (inbus=>fixed_cosff,shift=>countff_cos,
outbus=>mantissanormnode_cos);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode_sin <= "10000000" - ("00" & countff_sin);
exponentnormnode_cos <= "10000000" - ("00" & countff_cos);
overflownode_sin(1) <= mantissanormnode_sin(12);
gova1: FOR k IN 2 TO 24 GENERATE
overflownode_sin(k) <= mantissanormnode_sin(k+11) AND overflownode_sin(k-1);
END GENERATE;
overflownode_cos(1) <= mantissanormnode_cos(12);
gova2: FOR k IN 2 TO 24 GENERATE
overflownode_cos(k) <= mantissanormnode_cos(k+11) AND overflownode_cos(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sinff(k) <= '0';
fixed_cosff(k) <= '0';
END LOOP;
countff_sin <= "000000";
countff_cos <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff_sin(k) <= '0';
mantissaoutff_sin(k) <= '0';
mantissanormff_cos(k) <= '0';
mantissaoutff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff_sin(k) <= '0';
exponentoutff_sin(k) <= '0';
exponentnormff_cos(k) <= '0';
exponentoutff_cos(k) <= '0';
END LOOP;
signoutff_sin <= '0';
signoutff_cos <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sinff <= fixed_sinnode; -- level range_depth+cordic_depth+5
fixed_cosff <= fixed_cosnode; -- level range_depth+cordic_depth+5
countff_sin <= countnode_sin; -- level range_depth+4+cordic_depth+5
countff_cos <= countnode_cos; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff_cos <= mantissanormnode_cos(35 DOWNTO 13) + mantissanormnode_cos(12);
exponentnormff_cos <= exponentnormnode_cos(8 DOWNTO 1) + overflownode_cos(24);
mantissanormff_sin <= mantissanormnode_sin(35 DOWNTO 13) + mantissanormnode_sin(12);
exponentnormff_sin <= exponentnormnode_sin(8 DOWNTO 1) + overflownode_sin(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff_sin(k) <= (mantissanormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff_sin(k) <= (exponentnormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff_sin <= (signcalcff_sin(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
mantissaoutff_cos <= mantissanormff_cos;
exponentoutff_cos <= exponentnormff_cos;
signoutff_cos <= signcalcff_cos(cordic_depth+6);
END IF;
END IF;
END PROCESS;
mantissaout_sin <= mantissaoutff_sin;
exponentout_sin <= exponentoutff_sin;
signout_sin <= signoutff_sin;
mantissaout_cos <= mantissaoutff_cos;
exponentout_cos <= exponentoutff_cos;
signout_cos <= signoutff_cos;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_exp.vhd
|
10
|
7681
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION EXPONENT(e) - TOP LEVEL ***
--*** ***
--*** FP_EXP.VHD ***
--*** ***
--*** Function: IEEE754 SP EXP() ***
--*** ***
--*** 05/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 16 ***
--***************************************************
ENTITY fp_exp IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exp;
ARCHITECTURE rtl OF fp_exp IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 14;
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal rangeerror : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_exp_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
end component;
component fp_exprnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--****************
--*** EXP CORE ***
--****************
expcore: fp_exp_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aasgn=>signin,aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,
rangeerror=>rangeerror);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_exprnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode,
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
signout <= '0';
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_exp.vhd
|
10
|
7681
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION EXPONENT(e) - TOP LEVEL ***
--*** ***
--*** FP_EXP.VHD ***
--*** ***
--*** Function: IEEE754 SP EXP() ***
--*** ***
--*** 05/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 16 ***
--***************************************************
ENTITY fp_exp IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exp;
ARCHITECTURE rtl OF fp_exp IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 14;
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal rangeerror : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_exp_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
end component;
component fp_exprnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--****************
--*** EXP CORE ***
--****************
expcore: fp_exp_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aasgn=>signin,aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,
rangeerror=>rangeerror);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_exprnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode,
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
signout <= '0';
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_exp_core.vhd
|
10
|
24362
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION EXPONENT(e) - CORE ***
--*** ***
--*** DP_EXP_CORE.VHD ***
--*** ***
--*** Function: Double Precision Exponent Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublespeed ***
--*** SIII/IV Latency = 17 ***
--***************************************************
ENTITY dp_exp_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (54 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
END dp_exp_core;
ARCHITECTURE rtl OF dp_exp_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
constant ranlatency : positive := 15+2*doublespeed-device*(2+2*doublespeed);
type expcalcfftype IS ARRAY ((ranlatency-4) DOWNTO 1) OF
STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- INPUT BLOCK & SHIFTER
signal signff : STD_LOGIC_VECTOR (ranlatency+3 DOWNTO 1);
signal aamanff, aamandelff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal leftshift, rightshift : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal leftshiftff, rightshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal cmpexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal bigexpff : STD_LOGIC_VECTOR(2 DOWNTO 1);
signal smallrightshift : STD_LOGIC;
signal selshiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal powerbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftone, lefttwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal rightone, righttwo, rightthree : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftff, rightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal powerff : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal decimalleft : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal decimalright : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal fractionalleft, fractionalright : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- TABLES
signal addlutposff, addlutnegff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal addluttwoff, addlutthrff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutposmanff, lutnegmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal luttwomanff, lutthrmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutposexpff, lutnegexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpff : STD_LOGIC;
signal manpos, manneg, mantwo, manthr : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exppos, expneg : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal exptwo : STD_LOGIC;
signal lutonemanff, luttwomandelff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutoneexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpdelff : STD_LOGIC;
signal expcalcff : expcalcfftype;
-- OVER & UNDERFLOW
signal powercheck : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal rangeff : STD_LOGIC_VECTOR (ranlatency DOWNTO 1);
-- TAYLOR SERIES
signal fraction : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal xterm : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal xsquareterm : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal approxff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutthrmandel : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- MULTIPLY
signal resultone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultonedel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resulttwo, resultthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
-- NORMALIZE
signal normshift : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal expout, expoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
component dp_explutpos
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explutneg
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explut10
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
end component;
component dp_explut20
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO (ranlatency+3) LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
aamandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
leftshiftff(k) <= '0';
rightshiftff(k) <= '0';
END LOOP;
selshiftff <= "00";
FOR k IN 1 TO 64 LOOP
leftff(k) <= '0';
rightff(k) <= '0';
powerff(k) <= '0';
END LOOP;
powerff(65) <= '0';
bigexpff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= aasgn;
FOR k IN 2 TO (ranlatency+3) LOOP
signff(k) <= signff(k-1);
END LOOP;
aamanff <= aaman;
aamandelff <= aamanff;
aaexpff <= aaexp;
leftshiftff <= leftshift(10 DOWNTO 1);
rightshiftff <= rightshift(10 DOWNTO 1);
selshiftff(1) <= leftshift(12);
selshiftff(2) <= selshiftff(1);
-- level 3
leftff <= lefttwo;
-- mask out right barrel shifter output when shifting by 64 or more positions
FOR k IN 1 TO 64 LOOP
rightff(k) <= rightthree(k) AND smallrightshift;
END LOOP;
-- overflow of left shifter matters only when the left shifted mantissa result is to be used
bigexpff(2) <= bigexpff(1) AND NOT(selshiftff(2));
bigexpff(1) <= NOT(cmpexp(11));
-- level 4
FOR k IN 1 TO 54 LOOP
powerff(k) <= (fractionalleft(k) AND NOT(selshiftff(2))) OR
(fractionalright(k) AND selshiftff(2));
END LOOP;
FOR k IN 1 TO 10 LOOP
powerff(k+54) <= (decimalleft(k) AND NOT(selshiftff(2))) OR
(decimalright(k) AND selshiftff(2));
END LOOP;
powerff(65) <= (decimalleft(11) AND NOT(selshiftff(2)));
-- overflow bit required to catch exp(-1023.frac) case
END IF;
END IF;
END PROCESS;
leftshift <= ('0' & aaexpff) - "001111111111";
rightshift <= "001111111111" - ('0' & aaexpff);
powerbus <= "0000000001" & aamandelff & "00";
decimalleft <= ('0' & leftff(64 DOWNTO 55)) + ("0000000000" & signff(3));
-- decimalleft may overflow to bit 11 when exp(x), -1024 < x <= -1023
decimalright <= rightff(64 DOWNTO 55) + ("000000000" & signff(3));
gfa: FOR k IN 1 TO 54 GENERATE
fractionalleft(k) <= leftff(k) XOR signff(3);
fractionalright(k) <= rightff(k) XOR signff(3);
END GENERATE;
--**********************
--*** BARREL SHIFTER ***
--**********************
leftone(1) <= powerbus(1) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1));
leftone(2) <= (powerbus(2) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(1) AND NOT(leftshiftff(2)) AND leftshiftff(1));
leftone(3) <= (powerbus(3) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(2) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(1) AND leftshiftff(2) AND NOT(leftshiftff(1)));
gla: FOR k IN 4 TO 64 GENERATE
leftone(k) <= (powerbus(k) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(k-1) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(k-2) AND leftshiftff(2) AND NOT(leftshiftff(1))) OR
(powerbus(k-3) AND leftshiftff(2) AND leftshiftff(1));
END GENERATE;
glb: FOR k IN 1 TO 4 GENERATE
lefttwo(k) <= leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3));
END GENERATE;
glc: FOR k IN 5 TO 8 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3));
END GENERATE;
gld: FOR k IN 9 TO 12 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3)));
END GENERATE;
gle: FOR k IN 13 TO 64 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3))) OR
(leftone(k-12) AND leftshiftff(4) AND leftshiftff(3));
END GENERATE;
cmpexp <= ('0' & leftshiftff) - "00000001010";
-- detect when left barrel shifter overflows (i.e. leftshiftff > 9)
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (powerbus(k) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(k+1) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(k+2) AND rightshiftff(2) AND NOT(rightshiftff(1))) OR
(powerbus(k+3) AND rightshiftff(2) AND rightshiftff(1));
END GENERATE;
rightone(62) <= (powerbus(62) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(63) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(64) AND rightshiftff(2) AND NOT(rightshiftff(1)));
rightone(63) <= (powerbus(63) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(64) AND NOT(rightshiftff(2)) AND rightshiftff(1));
rightone(64) <= powerbus(64) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3))) OR
(rightone(k+12) AND rightshiftff(4) AND rightshiftff(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5))) OR
(righttwo(k+48) AND rightshiftff(6) AND rightshiftff(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5)));
END GENERATE;
grh: FOR k IN 33 TO 48 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5));
END GENERATE;
gri: FOR k IN 49 TO 64 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5)));
END GENERATE;
-- is rightshiftff < 64, otherwise right barrel shifter output will be masked out
smallrightshift <= NOT(rightshiftff(7) OR rightshiftff(8) OR rightshiftff(9) OR rightshiftff(10));
--******************************************
--*** TABLES - NO RESET, FORCE TO MEMORY ***
--******************************************
-- level: 4 in, 6 out
pla: PROCESS (sysclk)
BEGIN
IF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addlutposff <= powerff(64 DOWNTO 55);
addlutnegff <= powerff(64 DOWNTO 55);
addluttwoff <= powerff(54 DOWNTO 45);
addlutthrff <= powerff(44 DOWNTO 35);
lutposmanff <= '1' & manpos & '0';
lutposexpff <= exppos;
lutnegmanff <= '1' & manneg & '0';
lutnegexpff <= expneg;
luttwomanff <= '1' & mantwo & '0';
luttwoexpff <= exptwo;
lutthrmanff <= '1' & manthr & '0';
END IF;
END IF;
END PROCESS;
declut: dp_explutpos
PORT MAP (add=>addlutposff,
manhi=>manpos(52 DOWNTO 29),manlo=>manpos(28 DOWNTO 1),exponent=>exppos);
neglut: dp_explutneg
PORT MAP (add=>addlutnegff,
manhi=>manneg(52 DOWNTO 29),manlo=>manneg(28 DOWNTO 1),exponent=>expneg);
frachilut: dp_explut10
PORT MAP (add=>addluttwoff,
manhi=>mantwo(52 DOWNTO 29),manlo=>mantwo(28 DOWNTO 1),exponent=>exptwo);
fraclolut: dp_explut20
PORT MAP (add=>addlutthrff,
manhi=>manthr(52 DOWNTO 29),manlo=>manthr(28 DOWNTO 1));
-- level: 6 in, 7 out
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= '0';
luttwomandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= '0';
END LOOP;
luttwoexpdelff <= '0';
FOR k IN 1 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= "00000000000";
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= (lutposmanff(k) AND NOT(signff(6))) OR (lutnegmanff(k) AND signff(6));
END LOOP;
luttwomandelff <= luttwomanff;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= (lutposexpff(k) AND NOT(signff(6))) OR (lutnegexpff(k) AND signff(6));
END LOOP;
luttwoexpdelff <= luttwoexpff;
-- level: 8 in
-- SII: 19+2*doublespeed out
-- SII: 17+2*doublespeed out
expcalcff(1)(11 DOWNTO 1) <= lutoneexpff + ("0000000000" & luttwoexpdelff);
FOR k IN 2 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= expcalcff(k-1)(11 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************
--*** PREDICT OVERFLOW AND UNDERFLOW ***
--**************************************
-- overflow or underflow if power > 709
-- overflow or underflow if power != 0 and explut = 0
powercheck <= powerff(65 DOWNTO 55) - "1011000110"; -- 710
-- level 4 in
-- SII: level 19+2 out
-- SIII/IV: level 17 out
ppca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO ranlatency LOOP
rangeff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
rangeff(1) <= bigexpff(2) OR NOT(powercheck(11));
-- exp(x) -> 0 or Inf, when abs(x)>=710 or has overflowed the left shifter
FOR k IN 2 TO (ranlatency-1) LOOP
rangeff(k) <= rangeff(k-1);
END LOOP;
rangeff(ranlatency) <= rangeff(ranlatency-1) AND NOT(signff(ranlatency+3));
-- overflow only if input x is large and positive, exp(x) -> Inf
END IF;
END IF;
END PROCESS;
--***********************
--*** TAYLOR's SERIES ***
--***********************
-- approximation : sequence = 1 + x + x^2/2 + x^3/6 + x^4/24
-- but x^3/6 term is about 62 bits down, so just try 1 + x + x^2/2
-- ('1' & zero) + (zero(21:1) & x(34:2)) + (zero(42:1) & square(72:61))
fraction <= powerff(34 DOWNTO 1) & "00";
-- level: 4 in, 7 out
mulsqr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>12,
pipes=>3,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>fraction,databb=>fraction,
result=>xsquareterm);
delfrac: fp_del
GENERIC MAP (width=>33,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>powerff(34 DOWNTO 2),
cc=>xterm);
delthr: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>lutthrmanff,
cc=>lutthrmandel);
-- level 8
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
approxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
approxff <= ('1' & zerovec(20 DOWNTO 1) & xterm) + (zerovec(42 DOWNTO 1) & xsquareterm);
END IF;
END IF;
END PROCESS;
--*************************************
--*** MULTIPLY ALL EXP(X) SUBRANGES ***
--*************************************
-- SII level in 7, level out 12+speed
-- SIII/IV level in 7, level out 11
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutonemanff,databb=>luttwomandelff,
result=>resultone);
-- SII level in 12+speed, level out 13+speed
-- SIII/IV level in 11, level out 12
delone: fp_del
GENERIC MAP (width=>54,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>resultone(72 DOWNTO 19),
cc=>resultonedel);
-- SII level in 8, level out 13+speed
-- SIII/IV level in 8, level out 12
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutthrmandel,databb=>approxff,
result=>resulttwo);
-- SII level in 13+speed, level out 18+2*speed
-- SIII/IV level in 12, level out 16
multhr: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>resultonedel,databb=>resulttwo(72 DOWNTO 19),
result=>resultthr);
--************************
--*** NORMALIZE OUTPUT ***
--************************
pns: PROCESS (resultthr)
BEGIN
CASE resultthr(72 DOWNTO 69) IS
WHEN "0000" => normshift <= "11";
WHEN "0001" => normshift <= "11";
WHEN "0010" => normshift <= "10";
WHEN "0011" => normshift <= "10";
WHEN "0100" => normshift <= "01";
WHEN "0101" => normshift <= "01";
WHEN "0110" => normshift <= "01";
WHEN "0111" => normshift <= "01";
WHEN "1000" => normshift <= "00";
WHEN "1001" => normshift <= "00";
WHEN "1010" => normshift <= "00";
WHEN "1011" => normshift <= "00";
WHEN "1100" => normshift <= "00";
WHEN "1101" => normshift <= "00";
WHEN "1110" => normshift <= "00";
WHEN "1111" => normshift <= "00";
WHEN others => normshift <= "00";
END CASE;
END PROCESS;
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII level in 18+2*doublespeed, level out 19+2*doublespeed
-- SIII/IV level in 16, level out 17
FOR k IN 1 TO 54 LOOP
manoutff(k) <= (resultthr(k+18) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(resultthr(k+17) AND NOT(normshift(2)) AND normshift(1)) OR
(resultthr(k+16) AND normshift(2) AND NOT(normshift(1))) OR
(resultthr(k+15) AND normshift(2) AND normshift(1));
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= expout(k) AND NOT(rangeff(ranlatency-1) AND signff(ranlatency+3));
END LOOP;
-- IEEE exponent field is set to zero when x = large negative, exp(x) -> 0
END IF;
END IF;
END PROCESS;
expout <= expcalcff(ranlatency-4)(11 DOWNTO 1) - ("000000000" & normshift) + "00000000011";
--***************
--*** OUTPUTS ***
--***************
ccman <= manoutff;
ccexp <= expoutff;
rangeerror <= rangeff(ranlatency);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_exp_core.vhd
|
10
|
24362
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION EXPONENT(e) - CORE ***
--*** ***
--*** DP_EXP_CORE.VHD ***
--*** ***
--*** Function: Double Precision Exponent Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublespeed ***
--*** SIII/IV Latency = 17 ***
--***************************************************
ENTITY dp_exp_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (54 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
END dp_exp_core;
ARCHITECTURE rtl OF dp_exp_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
constant ranlatency : positive := 15+2*doublespeed-device*(2+2*doublespeed);
type expcalcfftype IS ARRAY ((ranlatency-4) DOWNTO 1) OF
STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- INPUT BLOCK & SHIFTER
signal signff : STD_LOGIC_VECTOR (ranlatency+3 DOWNTO 1);
signal aamanff, aamandelff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal leftshift, rightshift : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal leftshiftff, rightshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal cmpexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal bigexpff : STD_LOGIC_VECTOR(2 DOWNTO 1);
signal smallrightshift : STD_LOGIC;
signal selshiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal powerbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftone, lefttwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal rightone, righttwo, rightthree : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal leftff, rightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal powerff : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal decimalleft : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal decimalright : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal fractionalleft, fractionalright : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- TABLES
signal addlutposff, addlutnegff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal addluttwoff, addlutthrff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutposmanff, lutnegmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal luttwomanff, lutthrmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutposexpff, lutnegexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpff : STD_LOGIC;
signal manpos, manneg, mantwo, manthr : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exppos, expneg : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal exptwo : STD_LOGIC;
signal lutonemanff, luttwomandelff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutoneexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal luttwoexpdelff : STD_LOGIC;
signal expcalcff : expcalcfftype;
-- OVER & UNDERFLOW
signal powercheck : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal rangeff : STD_LOGIC_VECTOR (ranlatency DOWNTO 1);
-- TAYLOR SERIES
signal fraction : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal xterm : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal xsquareterm : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal approxff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal lutthrmandel : STD_LOGIC_VECTOR (54 DOWNTO 1);
-- MULTIPLY
signal resultone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultonedel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resulttwo, resultthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
-- NORMALIZE
signal normshift : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal expout, expoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
component dp_explutpos
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explutneg
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_explut10
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
end component;
component dp_explut20
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO (ranlatency+3) LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
aamandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
leftshiftff(k) <= '0';
rightshiftff(k) <= '0';
END LOOP;
selshiftff <= "00";
FOR k IN 1 TO 64 LOOP
leftff(k) <= '0';
rightff(k) <= '0';
powerff(k) <= '0';
END LOOP;
powerff(65) <= '0';
bigexpff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= aasgn;
FOR k IN 2 TO (ranlatency+3) LOOP
signff(k) <= signff(k-1);
END LOOP;
aamanff <= aaman;
aamandelff <= aamanff;
aaexpff <= aaexp;
leftshiftff <= leftshift(10 DOWNTO 1);
rightshiftff <= rightshift(10 DOWNTO 1);
selshiftff(1) <= leftshift(12);
selshiftff(2) <= selshiftff(1);
-- level 3
leftff <= lefttwo;
-- mask out right barrel shifter output when shifting by 64 or more positions
FOR k IN 1 TO 64 LOOP
rightff(k) <= rightthree(k) AND smallrightshift;
END LOOP;
-- overflow of left shifter matters only when the left shifted mantissa result is to be used
bigexpff(2) <= bigexpff(1) AND NOT(selshiftff(2));
bigexpff(1) <= NOT(cmpexp(11));
-- level 4
FOR k IN 1 TO 54 LOOP
powerff(k) <= (fractionalleft(k) AND NOT(selshiftff(2))) OR
(fractionalright(k) AND selshiftff(2));
END LOOP;
FOR k IN 1 TO 10 LOOP
powerff(k+54) <= (decimalleft(k) AND NOT(selshiftff(2))) OR
(decimalright(k) AND selshiftff(2));
END LOOP;
powerff(65) <= (decimalleft(11) AND NOT(selshiftff(2)));
-- overflow bit required to catch exp(-1023.frac) case
END IF;
END IF;
END PROCESS;
leftshift <= ('0' & aaexpff) - "001111111111";
rightshift <= "001111111111" - ('0' & aaexpff);
powerbus <= "0000000001" & aamandelff & "00";
decimalleft <= ('0' & leftff(64 DOWNTO 55)) + ("0000000000" & signff(3));
-- decimalleft may overflow to bit 11 when exp(x), -1024 < x <= -1023
decimalright <= rightff(64 DOWNTO 55) + ("000000000" & signff(3));
gfa: FOR k IN 1 TO 54 GENERATE
fractionalleft(k) <= leftff(k) XOR signff(3);
fractionalright(k) <= rightff(k) XOR signff(3);
END GENERATE;
--**********************
--*** BARREL SHIFTER ***
--**********************
leftone(1) <= powerbus(1) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1));
leftone(2) <= (powerbus(2) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(1) AND NOT(leftshiftff(2)) AND leftshiftff(1));
leftone(3) <= (powerbus(3) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(2) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(1) AND leftshiftff(2) AND NOT(leftshiftff(1)));
gla: FOR k IN 4 TO 64 GENERATE
leftone(k) <= (powerbus(k) AND NOT(leftshiftff(2)) AND NOT(leftshiftff(1))) OR
(powerbus(k-1) AND NOT(leftshiftff(2)) AND leftshiftff(1)) OR
(powerbus(k-2) AND leftshiftff(2) AND NOT(leftshiftff(1))) OR
(powerbus(k-3) AND leftshiftff(2) AND leftshiftff(1));
END GENERATE;
glb: FOR k IN 1 TO 4 GENERATE
lefttwo(k) <= leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3));
END GENERATE;
glc: FOR k IN 5 TO 8 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3));
END GENERATE;
gld: FOR k IN 9 TO 12 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3)));
END GENERATE;
gle: FOR k IN 13 TO 64 GENERATE
lefttwo(k) <= (leftone(k) AND NOT(leftshiftff(4)) AND NOT(leftshiftff(3))) OR
(leftone(k-4) AND NOT(leftshiftff(4)) AND leftshiftff(3)) OR
(leftone(k-8) AND leftshiftff(4) AND NOT(leftshiftff(3))) OR
(leftone(k-12) AND leftshiftff(4) AND leftshiftff(3));
END GENERATE;
cmpexp <= ('0' & leftshiftff) - "00000001010";
-- detect when left barrel shifter overflows (i.e. leftshiftff > 9)
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (powerbus(k) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(k+1) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(k+2) AND rightshiftff(2) AND NOT(rightshiftff(1))) OR
(powerbus(k+3) AND rightshiftff(2) AND rightshiftff(1));
END GENERATE;
rightone(62) <= (powerbus(62) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(63) AND NOT(rightshiftff(2)) AND rightshiftff(1)) OR
(powerbus(64) AND rightshiftff(2) AND NOT(rightshiftff(1)));
rightone(63) <= (powerbus(63) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1))) OR
(powerbus(64) AND NOT(rightshiftff(2)) AND rightshiftff(1));
rightone(64) <= powerbus(64) AND NOT(rightshiftff(2)) AND NOT(rightshiftff(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3))) OR
(rightone(k+12) AND rightshiftff(4) AND rightshiftff(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3)) OR
(rightone(k+8) AND rightshiftff(4) AND NOT(rightshiftff(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3))) OR
(rightone(k+4) AND NOT(rightshiftff(4)) AND rightshiftff(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(rightshiftff(4)) AND NOT(rightshiftff(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5))) OR
(righttwo(k+48) AND rightshiftff(6) AND rightshiftff(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5)) OR
(righttwo(k+32) AND rightshiftff(6) AND NOT(rightshiftff(5)));
END GENERATE;
grh: FOR k IN 33 TO 48 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5))) OR
(righttwo(k+16) AND NOT(rightshiftff(6)) AND rightshiftff(5));
END GENERATE;
gri: FOR k IN 49 TO 64 GENERATE
rightthree(k) <= (righttwo(k) AND NOT(rightshiftff(6)) AND NOT(rightshiftff(5)));
END GENERATE;
-- is rightshiftff < 64, otherwise right barrel shifter output will be masked out
smallrightshift <= NOT(rightshiftff(7) OR rightshiftff(8) OR rightshiftff(9) OR rightshiftff(10));
--******************************************
--*** TABLES - NO RESET, FORCE TO MEMORY ***
--******************************************
-- level: 4 in, 6 out
pla: PROCESS (sysclk)
BEGIN
IF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addlutposff <= powerff(64 DOWNTO 55);
addlutnegff <= powerff(64 DOWNTO 55);
addluttwoff <= powerff(54 DOWNTO 45);
addlutthrff <= powerff(44 DOWNTO 35);
lutposmanff <= '1' & manpos & '0';
lutposexpff <= exppos;
lutnegmanff <= '1' & manneg & '0';
lutnegexpff <= expneg;
luttwomanff <= '1' & mantwo & '0';
luttwoexpff <= exptwo;
lutthrmanff <= '1' & manthr & '0';
END IF;
END IF;
END PROCESS;
declut: dp_explutpos
PORT MAP (add=>addlutposff,
manhi=>manpos(52 DOWNTO 29),manlo=>manpos(28 DOWNTO 1),exponent=>exppos);
neglut: dp_explutneg
PORT MAP (add=>addlutnegff,
manhi=>manneg(52 DOWNTO 29),manlo=>manneg(28 DOWNTO 1),exponent=>expneg);
frachilut: dp_explut10
PORT MAP (add=>addluttwoff,
manhi=>mantwo(52 DOWNTO 29),manlo=>mantwo(28 DOWNTO 1),exponent=>exptwo);
fraclolut: dp_explut20
PORT MAP (add=>addlutthrff,
manhi=>manthr(52 DOWNTO 29),manlo=>manthr(28 DOWNTO 1));
-- level: 6 in, 7 out
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= '0';
luttwomandelff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= '0';
END LOOP;
luttwoexpdelff <= '0';
FOR k IN 1 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= "00000000000";
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 54 LOOP
lutonemanff(k) <= (lutposmanff(k) AND NOT(signff(6))) OR (lutnegmanff(k) AND signff(6));
END LOOP;
luttwomandelff <= luttwomanff;
FOR k IN 1 TO 11 LOOP
lutoneexpff(k) <= (lutposexpff(k) AND NOT(signff(6))) OR (lutnegexpff(k) AND signff(6));
END LOOP;
luttwoexpdelff <= luttwoexpff;
-- level: 8 in
-- SII: 19+2*doublespeed out
-- SII: 17+2*doublespeed out
expcalcff(1)(11 DOWNTO 1) <= lutoneexpff + ("0000000000" & luttwoexpdelff);
FOR k IN 2 TO (ranlatency-4) LOOP
expcalcff(k)(11 DOWNTO 1) <= expcalcff(k-1)(11 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************
--*** PREDICT OVERFLOW AND UNDERFLOW ***
--**************************************
-- overflow or underflow if power > 709
-- overflow or underflow if power != 0 and explut = 0
powercheck <= powerff(65 DOWNTO 55) - "1011000110"; -- 710
-- level 4 in
-- SII: level 19+2 out
-- SIII/IV: level 17 out
ppca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO ranlatency LOOP
rangeff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
rangeff(1) <= bigexpff(2) OR NOT(powercheck(11));
-- exp(x) -> 0 or Inf, when abs(x)>=710 or has overflowed the left shifter
FOR k IN 2 TO (ranlatency-1) LOOP
rangeff(k) <= rangeff(k-1);
END LOOP;
rangeff(ranlatency) <= rangeff(ranlatency-1) AND NOT(signff(ranlatency+3));
-- overflow only if input x is large and positive, exp(x) -> Inf
END IF;
END IF;
END PROCESS;
--***********************
--*** TAYLOR's SERIES ***
--***********************
-- approximation : sequence = 1 + x + x^2/2 + x^3/6 + x^4/24
-- but x^3/6 term is about 62 bits down, so just try 1 + x + x^2/2
-- ('1' & zero) + (zero(21:1) & x(34:2)) + (zero(42:1) & square(72:61))
fraction <= powerff(34 DOWNTO 1) & "00";
-- level: 4 in, 7 out
mulsqr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>12,
pipes=>3,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>fraction,databb=>fraction,
result=>xsquareterm);
delfrac: fp_del
GENERIC MAP (width=>33,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>powerff(34 DOWNTO 2),
cc=>xterm);
delthr: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>lutthrmanff,
cc=>lutthrmandel);
-- level 8
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
approxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
approxff <= ('1' & zerovec(20 DOWNTO 1) & xterm) + (zerovec(42 DOWNTO 1) & xsquareterm);
END IF;
END IF;
END PROCESS;
--*************************************
--*** MULTIPLY ALL EXP(X) SUBRANGES ***
--*************************************
-- SII level in 7, level out 12+speed
-- SIII/IV level in 7, level out 11
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutonemanff,databb=>luttwomandelff,
result=>resultone);
-- SII level in 12+speed, level out 13+speed
-- SIII/IV level in 11, level out 12
delone: fp_del
GENERIC MAP (width=>54,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>resultone(72 DOWNTO 19),
cc=>resultonedel);
-- SII level in 8, level out 13+speed
-- SIII/IV level in 8, level out 12
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>lutthrmandel,databb=>approxff,
result=>resulttwo);
-- SII level in 13+speed, level out 18+2*speed
-- SIII/IV level in 12, level out 16
multhr: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,
pipes=>mullatency,accuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>resultonedel,databb=>resulttwo(72 DOWNTO 19),
result=>resultthr);
--************************
--*** NORMALIZE OUTPUT ***
--************************
pns: PROCESS (resultthr)
BEGIN
CASE resultthr(72 DOWNTO 69) IS
WHEN "0000" => normshift <= "11";
WHEN "0001" => normshift <= "11";
WHEN "0010" => normshift <= "10";
WHEN "0011" => normshift <= "10";
WHEN "0100" => normshift <= "01";
WHEN "0101" => normshift <= "01";
WHEN "0110" => normshift <= "01";
WHEN "0111" => normshift <= "01";
WHEN "1000" => normshift <= "00";
WHEN "1001" => normshift <= "00";
WHEN "1010" => normshift <= "00";
WHEN "1011" => normshift <= "00";
WHEN "1100" => normshift <= "00";
WHEN "1101" => normshift <= "00";
WHEN "1110" => normshift <= "00";
WHEN "1111" => normshift <= "00";
WHEN others => normshift <= "00";
END CASE;
END PROCESS;
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII level in 18+2*doublespeed, level out 19+2*doublespeed
-- SIII/IV level in 16, level out 17
FOR k IN 1 TO 54 LOOP
manoutff(k) <= (resultthr(k+18) AND NOT(normshift(2)) AND NOT(normshift(1))) OR
(resultthr(k+17) AND NOT(normshift(2)) AND normshift(1)) OR
(resultthr(k+16) AND normshift(2) AND NOT(normshift(1))) OR
(resultthr(k+15) AND normshift(2) AND normshift(1));
END LOOP;
FOR k IN 1 TO 11 LOOP
expoutff(k) <= expout(k) AND NOT(rangeff(ranlatency-1) AND signff(ranlatency+3));
END LOOP;
-- IEEE exponent field is set to zero when x = large negative, exp(x) -> 0
END IF;
END IF;
END PROCESS;
expout <= expcalcff(ranlatency-4)(11 DOWNTO 1) - ("000000000" & normshift) + "00000000011";
--***************
--*** OUTPUTS ***
--***************
ccman <= manoutff;
ccexp <= expoutff;
rangeerror <= rangeff(ranlatency);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_rsftpipe32_sv.vhd
|
20
|
4318
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dotProduct64_dut_prim_sv.vhd
|
10
|
186942
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from dotProduct64_dut_prim
-- VHDL created on Fri Oct 19 16:38:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package.all;
use work.math_package.all;
use work.fpc_library_package.all;
use work.dspba_library_package.all;
USE work.dotProduct64_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/SJ/nightly/12.1/173/w64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity dotProduct64_dut_prim is
port (
valid_s : in std_logic_vector(0 downto 0);
channel_s : in std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
vout_s : out std_logic_vector(0 downto 0);
cout_s : out std_logic_vector(7 downto 0);
dout_s : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of dotProduct64_dut_prim is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal Mult_0_f_reset : std_logic;
signal Mult_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_0_f_a_real : REAL;
signal Mult_0_f_b_real : REAL;
signal Mult_0_f_q_real : REAL;
-- synopsys translate on
signal Mult_1_f_reset : std_logic;
signal Mult_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_1_f_a_real : REAL;
signal Mult_1_f_b_real : REAL;
signal Mult_1_f_q_real : REAL;
-- synopsys translate on
signal Mult_2_f_reset : std_logic;
signal Mult_2_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_2_f_a_real : REAL;
signal Mult_2_f_b_real : REAL;
signal Mult_2_f_q_real : REAL;
-- synopsys translate on
signal Mult_3_f_reset : std_logic;
signal Mult_3_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_3_f_a_real : REAL;
signal Mult_3_f_b_real : REAL;
signal Mult_3_f_q_real : REAL;
-- synopsys translate on
signal Mult_4_f_reset : std_logic;
signal Mult_4_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_4_f_a_real : REAL;
signal Mult_4_f_b_real : REAL;
signal Mult_4_f_q_real : REAL;
-- synopsys translate on
signal Mult_5_f_reset : std_logic;
signal Mult_5_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_5_f_a_real : REAL;
signal Mult_5_f_b_real : REAL;
signal Mult_5_f_q_real : REAL;
-- synopsys translate on
signal Mult_6_f_reset : std_logic;
signal Mult_6_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_6_f_a_real : REAL;
signal Mult_6_f_b_real : REAL;
signal Mult_6_f_q_real : REAL;
-- synopsys translate on
signal Mult_7_f_reset : std_logic;
signal Mult_7_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_7_f_a_real : REAL;
signal Mult_7_f_b_real : REAL;
signal Mult_7_f_q_real : REAL;
-- synopsys translate on
signal Mult_8_f_reset : std_logic;
signal Mult_8_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_8_f_a_real : REAL;
signal Mult_8_f_b_real : REAL;
signal Mult_8_f_q_real : REAL;
-- synopsys translate on
signal Mult_9_f_reset : std_logic;
signal Mult_9_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_9_f_a_real : REAL;
signal Mult_9_f_b_real : REAL;
signal Mult_9_f_q_real : REAL;
-- synopsys translate on
signal Mult_10_f_reset : std_logic;
signal Mult_10_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_10_f_a_real : REAL;
signal Mult_10_f_b_real : REAL;
signal Mult_10_f_q_real : REAL;
-- synopsys translate on
signal Mult_11_f_reset : std_logic;
signal Mult_11_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_11_f_a_real : REAL;
signal Mult_11_f_b_real : REAL;
signal Mult_11_f_q_real : REAL;
-- synopsys translate on
signal Mult_12_f_reset : std_logic;
signal Mult_12_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_12_f_a_real : REAL;
signal Mult_12_f_b_real : REAL;
signal Mult_12_f_q_real : REAL;
-- synopsys translate on
signal Mult_13_f_reset : std_logic;
signal Mult_13_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_13_f_a_real : REAL;
signal Mult_13_f_b_real : REAL;
signal Mult_13_f_q_real : REAL;
-- synopsys translate on
signal Mult_14_f_reset : std_logic;
signal Mult_14_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_14_f_a_real : REAL;
signal Mult_14_f_b_real : REAL;
signal Mult_14_f_q_real : REAL;
-- synopsys translate on
signal Mult_15_f_reset : std_logic;
signal Mult_15_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_15_f_a_real : REAL;
signal Mult_15_f_b_real : REAL;
signal Mult_15_f_q_real : REAL;
-- synopsys translate on
signal Mult_16_f_reset : std_logic;
signal Mult_16_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_16_f_a_real : REAL;
signal Mult_16_f_b_real : REAL;
signal Mult_16_f_q_real : REAL;
-- synopsys translate on
signal Mult_17_f_reset : std_logic;
signal Mult_17_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_17_f_a_real : REAL;
signal Mult_17_f_b_real : REAL;
signal Mult_17_f_q_real : REAL;
-- synopsys translate on
signal Mult_18_f_reset : std_logic;
signal Mult_18_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_18_f_a_real : REAL;
signal Mult_18_f_b_real : REAL;
signal Mult_18_f_q_real : REAL;
-- synopsys translate on
signal Mult_19_f_reset : std_logic;
signal Mult_19_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_19_f_a_real : REAL;
signal Mult_19_f_b_real : REAL;
signal Mult_19_f_q_real : REAL;
-- synopsys translate on
signal Mult_20_f_reset : std_logic;
signal Mult_20_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_20_f_a_real : REAL;
signal Mult_20_f_b_real : REAL;
signal Mult_20_f_q_real : REAL;
-- synopsys translate on
signal Mult_21_f_reset : std_logic;
signal Mult_21_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_21_f_a_real : REAL;
signal Mult_21_f_b_real : REAL;
signal Mult_21_f_q_real : REAL;
-- synopsys translate on
signal Mult_22_f_reset : std_logic;
signal Mult_22_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_22_f_a_real : REAL;
signal Mult_22_f_b_real : REAL;
signal Mult_22_f_q_real : REAL;
-- synopsys translate on
signal Mult_23_f_reset : std_logic;
signal Mult_23_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_23_f_a_real : REAL;
signal Mult_23_f_b_real : REAL;
signal Mult_23_f_q_real : REAL;
-- synopsys translate on
signal Mult_24_f_reset : std_logic;
signal Mult_24_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_24_f_a_real : REAL;
signal Mult_24_f_b_real : REAL;
signal Mult_24_f_q_real : REAL;
-- synopsys translate on
signal Mult_25_f_reset : std_logic;
signal Mult_25_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_25_f_a_real : REAL;
signal Mult_25_f_b_real : REAL;
signal Mult_25_f_q_real : REAL;
-- synopsys translate on
signal Mult_26_f_reset : std_logic;
signal Mult_26_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_26_f_a_real : REAL;
signal Mult_26_f_b_real : REAL;
signal Mult_26_f_q_real : REAL;
-- synopsys translate on
signal Mult_27_f_reset : std_logic;
signal Mult_27_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_27_f_a_real : REAL;
signal Mult_27_f_b_real : REAL;
signal Mult_27_f_q_real : REAL;
-- synopsys translate on
signal Mult_28_f_reset : std_logic;
signal Mult_28_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_28_f_a_real : REAL;
signal Mult_28_f_b_real : REAL;
signal Mult_28_f_q_real : REAL;
-- synopsys translate on
signal Mult_29_f_reset : std_logic;
signal Mult_29_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_29_f_a_real : REAL;
signal Mult_29_f_b_real : REAL;
signal Mult_29_f_q_real : REAL;
-- synopsys translate on
signal Mult_30_f_reset : std_logic;
signal Mult_30_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_30_f_a_real : REAL;
signal Mult_30_f_b_real : REAL;
signal Mult_30_f_q_real : REAL;
-- synopsys translate on
signal Mult_31_f_reset : std_logic;
signal Mult_31_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_31_f_a_real : REAL;
signal Mult_31_f_b_real : REAL;
signal Mult_31_f_q_real : REAL;
-- synopsys translate on
signal Mult_32_f_reset : std_logic;
signal Mult_32_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_32_f_a_real : REAL;
signal Mult_32_f_b_real : REAL;
signal Mult_32_f_q_real : REAL;
-- synopsys translate on
signal Mult_33_f_reset : std_logic;
signal Mult_33_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_33_f_a_real : REAL;
signal Mult_33_f_b_real : REAL;
signal Mult_33_f_q_real : REAL;
-- synopsys translate on
signal Mult_34_f_reset : std_logic;
signal Mult_34_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_34_f_a_real : REAL;
signal Mult_34_f_b_real : REAL;
signal Mult_34_f_q_real : REAL;
-- synopsys translate on
signal Mult_35_f_reset : std_logic;
signal Mult_35_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_35_f_a_real : REAL;
signal Mult_35_f_b_real : REAL;
signal Mult_35_f_q_real : REAL;
-- synopsys translate on
signal Mult_36_f_reset : std_logic;
signal Mult_36_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_36_f_a_real : REAL;
signal Mult_36_f_b_real : REAL;
signal Mult_36_f_q_real : REAL;
-- synopsys translate on
signal Mult_37_f_reset : std_logic;
signal Mult_37_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_37_f_a_real : REAL;
signal Mult_37_f_b_real : REAL;
signal Mult_37_f_q_real : REAL;
-- synopsys translate on
signal Mult_38_f_reset : std_logic;
signal Mult_38_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_38_f_a_real : REAL;
signal Mult_38_f_b_real : REAL;
signal Mult_38_f_q_real : REAL;
-- synopsys translate on
signal Mult_39_f_reset : std_logic;
signal Mult_39_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_39_f_a_real : REAL;
signal Mult_39_f_b_real : REAL;
signal Mult_39_f_q_real : REAL;
-- synopsys translate on
signal Mult_40_f_reset : std_logic;
signal Mult_40_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_40_f_a_real : REAL;
signal Mult_40_f_b_real : REAL;
signal Mult_40_f_q_real : REAL;
-- synopsys translate on
signal Mult_41_f_reset : std_logic;
signal Mult_41_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_41_f_a_real : REAL;
signal Mult_41_f_b_real : REAL;
signal Mult_41_f_q_real : REAL;
-- synopsys translate on
signal Mult_42_f_reset : std_logic;
signal Mult_42_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_42_f_a_real : REAL;
signal Mult_42_f_b_real : REAL;
signal Mult_42_f_q_real : REAL;
-- synopsys translate on
signal Mult_43_f_reset : std_logic;
signal Mult_43_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_43_f_a_real : REAL;
signal Mult_43_f_b_real : REAL;
signal Mult_43_f_q_real : REAL;
-- synopsys translate on
signal Mult_44_f_reset : std_logic;
signal Mult_44_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_44_f_a_real : REAL;
signal Mult_44_f_b_real : REAL;
signal Mult_44_f_q_real : REAL;
-- synopsys translate on
signal Mult_45_f_reset : std_logic;
signal Mult_45_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_45_f_a_real : REAL;
signal Mult_45_f_b_real : REAL;
signal Mult_45_f_q_real : REAL;
-- synopsys translate on
signal Mult_46_f_reset : std_logic;
signal Mult_46_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_46_f_a_real : REAL;
signal Mult_46_f_b_real : REAL;
signal Mult_46_f_q_real : REAL;
-- synopsys translate on
signal Mult_47_f_reset : std_logic;
signal Mult_47_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_47_f_a_real : REAL;
signal Mult_47_f_b_real : REAL;
signal Mult_47_f_q_real : REAL;
-- synopsys translate on
signal Mult_48_f_reset : std_logic;
signal Mult_48_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_48_f_a_real : REAL;
signal Mult_48_f_b_real : REAL;
signal Mult_48_f_q_real : REAL;
-- synopsys translate on
signal Mult_49_f_reset : std_logic;
signal Mult_49_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_49_f_a_real : REAL;
signal Mult_49_f_b_real : REAL;
signal Mult_49_f_q_real : REAL;
-- synopsys translate on
signal Mult_50_f_reset : std_logic;
signal Mult_50_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_50_f_a_real : REAL;
signal Mult_50_f_b_real : REAL;
signal Mult_50_f_q_real : REAL;
-- synopsys translate on
signal Mult_51_f_reset : std_logic;
signal Mult_51_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_51_f_a_real : REAL;
signal Mult_51_f_b_real : REAL;
signal Mult_51_f_q_real : REAL;
-- synopsys translate on
signal Mult_52_f_reset : std_logic;
signal Mult_52_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_52_f_a_real : REAL;
signal Mult_52_f_b_real : REAL;
signal Mult_52_f_q_real : REAL;
-- synopsys translate on
signal Mult_53_f_reset : std_logic;
signal Mult_53_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_53_f_a_real : REAL;
signal Mult_53_f_b_real : REAL;
signal Mult_53_f_q_real : REAL;
-- synopsys translate on
signal Mult_54_f_reset : std_logic;
signal Mult_54_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_54_f_a_real : REAL;
signal Mult_54_f_b_real : REAL;
signal Mult_54_f_q_real : REAL;
-- synopsys translate on
signal Mult_55_f_reset : std_logic;
signal Mult_55_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_55_f_a_real : REAL;
signal Mult_55_f_b_real : REAL;
signal Mult_55_f_q_real : REAL;
-- synopsys translate on
signal Mult_56_f_reset : std_logic;
signal Mult_56_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_56_f_a_real : REAL;
signal Mult_56_f_b_real : REAL;
signal Mult_56_f_q_real : REAL;
-- synopsys translate on
signal Mult_57_f_reset : std_logic;
signal Mult_57_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_57_f_a_real : REAL;
signal Mult_57_f_b_real : REAL;
signal Mult_57_f_q_real : REAL;
-- synopsys translate on
signal Mult_58_f_reset : std_logic;
signal Mult_58_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_58_f_a_real : REAL;
signal Mult_58_f_b_real : REAL;
signal Mult_58_f_q_real : REAL;
-- synopsys translate on
signal Mult_59_f_reset : std_logic;
signal Mult_59_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_59_f_a_real : REAL;
signal Mult_59_f_b_real : REAL;
signal Mult_59_f_q_real : REAL;
-- synopsys translate on
signal Mult_60_f_reset : std_logic;
signal Mult_60_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_60_f_a_real : REAL;
signal Mult_60_f_b_real : REAL;
signal Mult_60_f_q_real : REAL;
-- synopsys translate on
signal Mult_61_f_reset : std_logic;
signal Mult_61_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_61_f_a_real : REAL;
signal Mult_61_f_b_real : REAL;
signal Mult_61_f_q_real : REAL;
-- synopsys translate on
signal Mult_62_f_reset : std_logic;
signal Mult_62_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_62_f_a_real : REAL;
signal Mult_62_f_b_real : REAL;
signal Mult_62_f_q_real : REAL;
-- synopsys translate on
signal Mult_63_f_reset : std_logic;
signal Mult_63_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal Mult_63_f_a_real : REAL;
signal Mult_63_f_b_real : REAL;
signal Mult_63_f_q_real : REAL;
-- synopsys translate on
signal ChannelOut_2_cast_reset : std_logic;
signal ChannelOut_2_cast_a : std_logic_vector (44 downto 0);
signal ChannelOut_2_cast_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal ChannelOut_2_cast_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_0_f_reset : std_logic;
signal SumOfElements_0_0_add_0_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_0_f_a_real : REAL;
signal SumOfElements_0_0_add_0_0_f_b_real : REAL;
signal SumOfElements_0_0_add_0_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_1_f_reset : std_logic;
signal SumOfElements_0_0_add_0_1_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_1_f_a_real : REAL;
signal SumOfElements_0_0_add_0_1_f_b_real : REAL;
signal SumOfElements_0_0_add_0_1_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_1_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_1_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_2_f_reset : std_logic;
signal SumOfElements_0_0_add_0_2_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_2_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_2_f_a_real : REAL;
signal SumOfElements_0_0_add_0_2_f_b_real : REAL;
signal SumOfElements_0_0_add_0_2_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_2_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_2_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_3_f_reset : std_logic;
signal SumOfElements_0_0_add_0_3_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_3_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_3_f_a_real : REAL;
signal SumOfElements_0_0_add_0_3_f_b_real : REAL;
signal SumOfElements_0_0_add_0_3_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_3_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_3_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_4_f_reset : std_logic;
signal SumOfElements_0_0_add_0_4_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_4_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_4_f_a_real : REAL;
signal SumOfElements_0_0_add_0_4_f_b_real : REAL;
signal SumOfElements_0_0_add_0_4_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_4_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_4_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_5_f_reset : std_logic;
signal SumOfElements_0_0_add_0_5_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_5_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_5_f_a_real : REAL;
signal SumOfElements_0_0_add_0_5_f_b_real : REAL;
signal SumOfElements_0_0_add_0_5_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_5_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_5_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_6_f_reset : std_logic;
signal SumOfElements_0_0_add_0_6_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_6_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_6_f_a_real : REAL;
signal SumOfElements_0_0_add_0_6_f_b_real : REAL;
signal SumOfElements_0_0_add_0_6_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_6_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_6_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_7_f_reset : std_logic;
signal SumOfElements_0_0_add_0_7_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_7_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_7_f_a_real : REAL;
signal SumOfElements_0_0_add_0_7_f_b_real : REAL;
signal SumOfElements_0_0_add_0_7_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_7_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_7_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_8_f_reset : std_logic;
signal SumOfElements_0_0_add_0_8_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_8_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_8_f_a_real : REAL;
signal SumOfElements_0_0_add_0_8_f_b_real : REAL;
signal SumOfElements_0_0_add_0_8_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_8_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_8_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_9_f_reset : std_logic;
signal SumOfElements_0_0_add_0_9_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_9_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_9_f_a_real : REAL;
signal SumOfElements_0_0_add_0_9_f_b_real : REAL;
signal SumOfElements_0_0_add_0_9_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_9_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_9_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_10_f_reset : std_logic;
signal SumOfElements_0_0_add_0_10_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_10_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_10_f_a_real : REAL;
signal SumOfElements_0_0_add_0_10_f_b_real : REAL;
signal SumOfElements_0_0_add_0_10_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_10_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_10_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_11_f_reset : std_logic;
signal SumOfElements_0_0_add_0_11_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_11_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_11_f_a_real : REAL;
signal SumOfElements_0_0_add_0_11_f_b_real : REAL;
signal SumOfElements_0_0_add_0_11_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_11_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_11_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_12_f_reset : std_logic;
signal SumOfElements_0_0_add_0_12_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_12_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_12_f_a_real : REAL;
signal SumOfElements_0_0_add_0_12_f_b_real : REAL;
signal SumOfElements_0_0_add_0_12_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_12_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_12_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_13_f_reset : std_logic;
signal SumOfElements_0_0_add_0_13_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_13_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_13_f_a_real : REAL;
signal SumOfElements_0_0_add_0_13_f_b_real : REAL;
signal SumOfElements_0_0_add_0_13_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_13_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_13_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_14_f_reset : std_logic;
signal SumOfElements_0_0_add_0_14_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_14_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_14_f_a_real : REAL;
signal SumOfElements_0_0_add_0_14_f_b_real : REAL;
signal SumOfElements_0_0_add_0_14_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_14_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_14_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_15_f_reset : std_logic;
signal SumOfElements_0_0_add_0_15_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_15_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_15_f_a_real : REAL;
signal SumOfElements_0_0_add_0_15_f_b_real : REAL;
signal SumOfElements_0_0_add_0_15_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_15_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_15_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_16_f_reset : std_logic;
signal SumOfElements_0_0_add_0_16_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_16_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_16_f_a_real : REAL;
signal SumOfElements_0_0_add_0_16_f_b_real : REAL;
signal SumOfElements_0_0_add_0_16_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_16_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_16_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_17_f_reset : std_logic;
signal SumOfElements_0_0_add_0_17_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_17_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_17_f_a_real : REAL;
signal SumOfElements_0_0_add_0_17_f_b_real : REAL;
signal SumOfElements_0_0_add_0_17_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_17_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_17_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_18_f_reset : std_logic;
signal SumOfElements_0_0_add_0_18_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_18_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_18_f_a_real : REAL;
signal SumOfElements_0_0_add_0_18_f_b_real : REAL;
signal SumOfElements_0_0_add_0_18_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_18_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_18_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_19_f_reset : std_logic;
signal SumOfElements_0_0_add_0_19_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_19_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_19_f_a_real : REAL;
signal SumOfElements_0_0_add_0_19_f_b_real : REAL;
signal SumOfElements_0_0_add_0_19_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_19_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_19_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_20_f_reset : std_logic;
signal SumOfElements_0_0_add_0_20_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_20_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_20_f_a_real : REAL;
signal SumOfElements_0_0_add_0_20_f_b_real : REAL;
signal SumOfElements_0_0_add_0_20_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_20_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_20_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_21_f_reset : std_logic;
signal SumOfElements_0_0_add_0_21_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_21_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_21_f_a_real : REAL;
signal SumOfElements_0_0_add_0_21_f_b_real : REAL;
signal SumOfElements_0_0_add_0_21_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_21_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_21_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_22_f_reset : std_logic;
signal SumOfElements_0_0_add_0_22_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_22_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_22_f_a_real : REAL;
signal SumOfElements_0_0_add_0_22_f_b_real : REAL;
signal SumOfElements_0_0_add_0_22_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_22_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_22_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_23_f_reset : std_logic;
signal SumOfElements_0_0_add_0_23_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_23_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_23_f_a_real : REAL;
signal SumOfElements_0_0_add_0_23_f_b_real : REAL;
signal SumOfElements_0_0_add_0_23_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_23_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_23_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_24_f_reset : std_logic;
signal SumOfElements_0_0_add_0_24_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_24_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_24_f_a_real : REAL;
signal SumOfElements_0_0_add_0_24_f_b_real : REAL;
signal SumOfElements_0_0_add_0_24_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_24_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_24_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_25_f_reset : std_logic;
signal SumOfElements_0_0_add_0_25_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_25_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_25_f_a_real : REAL;
signal SumOfElements_0_0_add_0_25_f_b_real : REAL;
signal SumOfElements_0_0_add_0_25_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_25_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_25_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_26_f_reset : std_logic;
signal SumOfElements_0_0_add_0_26_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_26_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_26_f_a_real : REAL;
signal SumOfElements_0_0_add_0_26_f_b_real : REAL;
signal SumOfElements_0_0_add_0_26_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_26_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_26_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_27_f_reset : std_logic;
signal SumOfElements_0_0_add_0_27_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_27_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_27_f_a_real : REAL;
signal SumOfElements_0_0_add_0_27_f_b_real : REAL;
signal SumOfElements_0_0_add_0_27_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_27_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_27_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_28_f_reset : std_logic;
signal SumOfElements_0_0_add_0_28_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_28_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_28_f_a_real : REAL;
signal SumOfElements_0_0_add_0_28_f_b_real : REAL;
signal SumOfElements_0_0_add_0_28_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_28_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_28_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_29_f_reset : std_logic;
signal SumOfElements_0_0_add_0_29_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_29_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_29_f_a_real : REAL;
signal SumOfElements_0_0_add_0_29_f_b_real : REAL;
signal SumOfElements_0_0_add_0_29_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_29_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_29_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_30_f_reset : std_logic;
signal SumOfElements_0_0_add_0_30_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_30_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_30_f_a_real : REAL;
signal SumOfElements_0_0_add_0_30_f_b_real : REAL;
signal SumOfElements_0_0_add_0_30_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_30_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_30_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_31_f_reset : std_logic;
signal SumOfElements_0_0_add_0_31_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_31_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_0_31_f_a_real : REAL;
signal SumOfElements_0_0_add_0_31_f_b_real : REAL;
signal SumOfElements_0_0_add_0_31_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_0_31_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_0_31_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_0_f_reset : std_logic;
signal SumOfElements_0_0_add_1_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_0_f_a_real : REAL;
signal SumOfElements_0_0_add_1_0_f_b_real : REAL;
signal SumOfElements_0_0_add_1_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_1_f_reset : std_logic;
signal SumOfElements_0_0_add_1_1_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_1_f_a_real : REAL;
signal SumOfElements_0_0_add_1_1_f_b_real : REAL;
signal SumOfElements_0_0_add_1_1_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_1_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_1_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_2_f_reset : std_logic;
signal SumOfElements_0_0_add_1_2_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_2_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_2_f_a_real : REAL;
signal SumOfElements_0_0_add_1_2_f_b_real : REAL;
signal SumOfElements_0_0_add_1_2_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_2_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_2_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_3_f_reset : std_logic;
signal SumOfElements_0_0_add_1_3_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_3_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_3_f_a_real : REAL;
signal SumOfElements_0_0_add_1_3_f_b_real : REAL;
signal SumOfElements_0_0_add_1_3_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_3_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_3_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_4_f_reset : std_logic;
signal SumOfElements_0_0_add_1_4_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_4_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_4_f_a_real : REAL;
signal SumOfElements_0_0_add_1_4_f_b_real : REAL;
signal SumOfElements_0_0_add_1_4_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_4_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_4_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_5_f_reset : std_logic;
signal SumOfElements_0_0_add_1_5_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_5_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_5_f_a_real : REAL;
signal SumOfElements_0_0_add_1_5_f_b_real : REAL;
signal SumOfElements_0_0_add_1_5_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_5_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_5_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_6_f_reset : std_logic;
signal SumOfElements_0_0_add_1_6_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_6_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_6_f_a_real : REAL;
signal SumOfElements_0_0_add_1_6_f_b_real : REAL;
signal SumOfElements_0_0_add_1_6_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_6_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_6_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_7_f_reset : std_logic;
signal SumOfElements_0_0_add_1_7_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_7_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_7_f_a_real : REAL;
signal SumOfElements_0_0_add_1_7_f_b_real : REAL;
signal SumOfElements_0_0_add_1_7_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_7_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_7_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_8_f_reset : std_logic;
signal SumOfElements_0_0_add_1_8_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_8_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_8_f_a_real : REAL;
signal SumOfElements_0_0_add_1_8_f_b_real : REAL;
signal SumOfElements_0_0_add_1_8_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_8_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_8_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_9_f_reset : std_logic;
signal SumOfElements_0_0_add_1_9_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_9_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_9_f_a_real : REAL;
signal SumOfElements_0_0_add_1_9_f_b_real : REAL;
signal SumOfElements_0_0_add_1_9_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_9_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_9_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_10_f_reset : std_logic;
signal SumOfElements_0_0_add_1_10_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_10_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_10_f_a_real : REAL;
signal SumOfElements_0_0_add_1_10_f_b_real : REAL;
signal SumOfElements_0_0_add_1_10_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_10_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_10_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_11_f_reset : std_logic;
signal SumOfElements_0_0_add_1_11_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_11_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_11_f_a_real : REAL;
signal SumOfElements_0_0_add_1_11_f_b_real : REAL;
signal SumOfElements_0_0_add_1_11_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_11_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_11_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_12_f_reset : std_logic;
signal SumOfElements_0_0_add_1_12_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_12_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_12_f_a_real : REAL;
signal SumOfElements_0_0_add_1_12_f_b_real : REAL;
signal SumOfElements_0_0_add_1_12_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_12_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_12_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_13_f_reset : std_logic;
signal SumOfElements_0_0_add_1_13_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_13_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_13_f_a_real : REAL;
signal SumOfElements_0_0_add_1_13_f_b_real : REAL;
signal SumOfElements_0_0_add_1_13_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_13_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_13_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_14_f_reset : std_logic;
signal SumOfElements_0_0_add_1_14_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_14_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_14_f_a_real : REAL;
signal SumOfElements_0_0_add_1_14_f_b_real : REAL;
signal SumOfElements_0_0_add_1_14_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_14_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_14_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_15_f_reset : std_logic;
signal SumOfElements_0_0_add_1_15_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_15_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_1_15_f_a_real : REAL;
signal SumOfElements_0_0_add_1_15_f_b_real : REAL;
signal SumOfElements_0_0_add_1_15_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_1_15_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_1_15_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_0_f_reset : std_logic;
signal SumOfElements_0_0_add_2_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_0_f_a_real : REAL;
signal SumOfElements_0_0_add_2_0_f_b_real : REAL;
signal SumOfElements_0_0_add_2_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_1_f_reset : std_logic;
signal SumOfElements_0_0_add_2_1_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_1_f_a_real : REAL;
signal SumOfElements_0_0_add_2_1_f_b_real : REAL;
signal SumOfElements_0_0_add_2_1_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_1_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_1_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_2_f_reset : std_logic;
signal SumOfElements_0_0_add_2_2_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_2_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_2_f_a_real : REAL;
signal SumOfElements_0_0_add_2_2_f_b_real : REAL;
signal SumOfElements_0_0_add_2_2_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_2_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_2_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_3_f_reset : std_logic;
signal SumOfElements_0_0_add_2_3_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_3_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_3_f_a_real : REAL;
signal SumOfElements_0_0_add_2_3_f_b_real : REAL;
signal SumOfElements_0_0_add_2_3_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_3_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_3_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_4_f_reset : std_logic;
signal SumOfElements_0_0_add_2_4_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_4_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_4_f_a_real : REAL;
signal SumOfElements_0_0_add_2_4_f_b_real : REAL;
signal SumOfElements_0_0_add_2_4_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_4_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_4_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_5_f_reset : std_logic;
signal SumOfElements_0_0_add_2_5_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_5_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_5_f_a_real : REAL;
signal SumOfElements_0_0_add_2_5_f_b_real : REAL;
signal SumOfElements_0_0_add_2_5_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_5_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_5_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_6_f_reset : std_logic;
signal SumOfElements_0_0_add_2_6_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_6_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_6_f_a_real : REAL;
signal SumOfElements_0_0_add_2_6_f_b_real : REAL;
signal SumOfElements_0_0_add_2_6_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_6_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_6_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_7_f_reset : std_logic;
signal SumOfElements_0_0_add_2_7_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_7_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_2_7_f_a_real : REAL;
signal SumOfElements_0_0_add_2_7_f_b_real : REAL;
signal SumOfElements_0_0_add_2_7_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_2_7_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_2_7_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_0_f_reset : std_logic;
signal SumOfElements_0_0_add_3_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_0_f_a_real : REAL;
signal SumOfElements_0_0_add_3_0_f_b_real : REAL;
signal SumOfElements_0_0_add_3_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_1_f_reset : std_logic;
signal SumOfElements_0_0_add_3_1_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_1_f_a_real : REAL;
signal SumOfElements_0_0_add_3_1_f_b_real : REAL;
signal SumOfElements_0_0_add_3_1_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_1_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_1_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_2_f_reset : std_logic;
signal SumOfElements_0_0_add_3_2_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_2_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_2_f_a_real : REAL;
signal SumOfElements_0_0_add_3_2_f_b_real : REAL;
signal SumOfElements_0_0_add_3_2_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_2_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_2_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_3_f_reset : std_logic;
signal SumOfElements_0_0_add_3_3_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_3_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_3_f_a_real : REAL;
signal SumOfElements_0_0_add_3_3_f_b_real : REAL;
signal SumOfElements_0_0_add_3_3_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_3_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_3_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_0_f_reset : std_logic;
signal SumOfElements_0_0_add_4_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_4_0_f_a_real : REAL;
signal SumOfElements_0_0_add_4_0_f_b_real : REAL;
signal SumOfElements_0_0_add_4_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_4_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_1_f_reset : std_logic;
signal SumOfElements_0_0_add_4_1_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_1_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_4_1_f_a_real : REAL;
signal SumOfElements_0_0_add_4_1_f_b_real : REAL;
signal SumOfElements_0_0_add_4_1_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_4_1_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_4_1_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_5_0_f_reset : std_logic;
signal SumOfElements_0_0_add_5_0_f_add_sub : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_5_0_f_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_5_0_f_a_real : REAL;
signal SumOfElements_0_0_add_5_0_f_b_real : REAL;
signal SumOfElements_0_0_add_5_0_f_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_5_0_f_p : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_5_0_f_n : std_logic_vector (0 downto 0);
signal SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_reset : std_logic;
signal SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_reset : std_logic;
signal SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_reset : std_logic;
signal SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q_real : REAL;
-- synopsys translate on
signal SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_reset : std_logic;
signal SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q : std_logic_vector (44 downto 0);
-- synopsys translate off
signal SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q_real : REAL;
-- synopsys translate on
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_reset0 : std_logic;
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_eq : std_logic;
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_mem_top_q : std_logic_vector (6 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_reset0 : std_logic;
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_a : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_q : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_a : std_logic_vector(6 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_b : std_logic_vector(6 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_q : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_a : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_b : std_logic_vector(0 downto 0);
signal ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_q : std_logic_vector(0 downto 0);
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
VCC_q <= "1";
--ChannelIn(PORTIN,2)@0
--Mult_63_f(FLOATMULT,265)@0
Mult_63_f_reset <= areset;
Mult_63_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_63_f_reset,
dataa => datain_a_63,
datab => datain_b_63,
result => Mult_63_f_q
);
-- synopsys translate off
Mult_63_f_a_real <= sIEEE_2_real(datain_a_63);
Mult_63_f_b_real <= sIEEE_2_real(datain_b_63);
Mult_63_f_q_real <= sInternalSM_2_real(Mult_63_f_q);
-- synopsys translate on
--Mult_62_f(FLOATMULT,264)@0
Mult_62_f_reset <= areset;
Mult_62_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_62_f_reset,
dataa => datain_a_62,
datab => datain_b_62,
result => Mult_62_f_q
);
-- synopsys translate off
Mult_62_f_a_real <= sIEEE_2_real(datain_a_62);
Mult_62_f_b_real <= sIEEE_2_real(datain_b_62);
Mult_62_f_q_real <= sInternalSM_2_real(Mult_62_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_31_f(FLOATADDSUB,330)@3
SumOfElements_0_0_add_0_31_f_reset <= areset;
SumOfElements_0_0_add_0_31_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_31_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_31_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_31_f_reset,
dataa => Mult_62_f_q,
datab => Mult_63_f_q,
result => SumOfElements_0_0_add_0_31_f_q
);
SumOfElements_0_0_add_0_31_f_p <= not SumOfElements_0_0_add_0_31_f_q(41 downto 41);
SumOfElements_0_0_add_0_31_f_n <= SumOfElements_0_0_add_0_31_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_31_f_a_real <= sInternalSM_2_real(Mult_62_f_q);
SumOfElements_0_0_add_0_31_f_b_real <= sInternalSM_2_real(Mult_63_f_q);
SumOfElements_0_0_add_0_31_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_31_f_q);
-- synopsys translate on
--Mult_61_f(FLOATMULT,263)@0
Mult_61_f_reset <= areset;
Mult_61_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_61_f_reset,
dataa => datain_a_61,
datab => datain_b_61,
result => Mult_61_f_q
);
-- synopsys translate off
Mult_61_f_a_real <= sIEEE_2_real(datain_a_61);
Mult_61_f_b_real <= sIEEE_2_real(datain_b_61);
Mult_61_f_q_real <= sInternalSM_2_real(Mult_61_f_q);
-- synopsys translate on
--Mult_60_f(FLOATMULT,262)@0
Mult_60_f_reset <= areset;
Mult_60_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_60_f_reset,
dataa => datain_a_60,
datab => datain_b_60,
result => Mult_60_f_q
);
-- synopsys translate off
Mult_60_f_a_real <= sIEEE_2_real(datain_a_60);
Mult_60_f_b_real <= sIEEE_2_real(datain_b_60);
Mult_60_f_q_real <= sInternalSM_2_real(Mult_60_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_30_f(FLOATADDSUB,328)@3
SumOfElements_0_0_add_0_30_f_reset <= areset;
SumOfElements_0_0_add_0_30_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_30_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_30_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_30_f_reset,
dataa => Mult_60_f_q,
datab => Mult_61_f_q,
result => SumOfElements_0_0_add_0_30_f_q
);
SumOfElements_0_0_add_0_30_f_p <= not SumOfElements_0_0_add_0_30_f_q(41 downto 41);
SumOfElements_0_0_add_0_30_f_n <= SumOfElements_0_0_add_0_30_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_30_f_a_real <= sInternalSM_2_real(Mult_60_f_q);
SumOfElements_0_0_add_0_30_f_b_real <= sInternalSM_2_real(Mult_61_f_q);
SumOfElements_0_0_add_0_30_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_30_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_15_f(FLOATADDSUB,362)@8
SumOfElements_0_0_add_1_15_f_reset <= areset;
SumOfElements_0_0_add_1_15_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_15_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_15_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_15_f_reset,
dataa => SumOfElements_0_0_add_0_30_f_q,
datab => SumOfElements_0_0_add_0_31_f_q,
result => SumOfElements_0_0_add_1_15_f_q
);
SumOfElements_0_0_add_1_15_f_p <= not SumOfElements_0_0_add_1_15_f_q(41 downto 41);
SumOfElements_0_0_add_1_15_f_n <= SumOfElements_0_0_add_1_15_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_15_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_30_f_q);
SumOfElements_0_0_add_1_15_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_31_f_q);
SumOfElements_0_0_add_1_15_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_15_f_q);
-- synopsys translate on
--Mult_59_f(FLOATMULT,261)@0
Mult_59_f_reset <= areset;
Mult_59_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_59_f_reset,
dataa => datain_a_59,
datab => datain_b_59,
result => Mult_59_f_q
);
-- synopsys translate off
Mult_59_f_a_real <= sIEEE_2_real(datain_a_59);
Mult_59_f_b_real <= sIEEE_2_real(datain_b_59);
Mult_59_f_q_real <= sInternalSM_2_real(Mult_59_f_q);
-- synopsys translate on
--Mult_58_f(FLOATMULT,260)@0
Mult_58_f_reset <= areset;
Mult_58_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_58_f_reset,
dataa => datain_a_58,
datab => datain_b_58,
result => Mult_58_f_q
);
-- synopsys translate off
Mult_58_f_a_real <= sIEEE_2_real(datain_a_58);
Mult_58_f_b_real <= sIEEE_2_real(datain_b_58);
Mult_58_f_q_real <= sInternalSM_2_real(Mult_58_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_29_f(FLOATADDSUB,326)@3
SumOfElements_0_0_add_0_29_f_reset <= areset;
SumOfElements_0_0_add_0_29_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_29_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_29_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_29_f_reset,
dataa => Mult_58_f_q,
datab => Mult_59_f_q,
result => SumOfElements_0_0_add_0_29_f_q
);
SumOfElements_0_0_add_0_29_f_p <= not SumOfElements_0_0_add_0_29_f_q(41 downto 41);
SumOfElements_0_0_add_0_29_f_n <= SumOfElements_0_0_add_0_29_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_29_f_a_real <= sInternalSM_2_real(Mult_58_f_q);
SumOfElements_0_0_add_0_29_f_b_real <= sInternalSM_2_real(Mult_59_f_q);
SumOfElements_0_0_add_0_29_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_29_f_q);
-- synopsys translate on
--Mult_57_f(FLOATMULT,259)@0
Mult_57_f_reset <= areset;
Mult_57_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_57_f_reset,
dataa => datain_a_57,
datab => datain_b_57,
result => Mult_57_f_q
);
-- synopsys translate off
Mult_57_f_a_real <= sIEEE_2_real(datain_a_57);
Mult_57_f_b_real <= sIEEE_2_real(datain_b_57);
Mult_57_f_q_real <= sInternalSM_2_real(Mult_57_f_q);
-- synopsys translate on
--Mult_56_f(FLOATMULT,258)@0
Mult_56_f_reset <= areset;
Mult_56_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_56_f_reset,
dataa => datain_a_56,
datab => datain_b_56,
result => Mult_56_f_q
);
-- synopsys translate off
Mult_56_f_a_real <= sIEEE_2_real(datain_a_56);
Mult_56_f_b_real <= sIEEE_2_real(datain_b_56);
Mult_56_f_q_real <= sInternalSM_2_real(Mult_56_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_28_f(FLOATADDSUB,324)@3
SumOfElements_0_0_add_0_28_f_reset <= areset;
SumOfElements_0_0_add_0_28_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_28_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_28_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_28_f_reset,
dataa => Mult_56_f_q,
datab => Mult_57_f_q,
result => SumOfElements_0_0_add_0_28_f_q
);
SumOfElements_0_0_add_0_28_f_p <= not SumOfElements_0_0_add_0_28_f_q(41 downto 41);
SumOfElements_0_0_add_0_28_f_n <= SumOfElements_0_0_add_0_28_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_28_f_a_real <= sInternalSM_2_real(Mult_56_f_q);
SumOfElements_0_0_add_0_28_f_b_real <= sInternalSM_2_real(Mult_57_f_q);
SumOfElements_0_0_add_0_28_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_28_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_14_f(FLOATADDSUB,360)@8
SumOfElements_0_0_add_1_14_f_reset <= areset;
SumOfElements_0_0_add_1_14_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_14_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_14_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_14_f_reset,
dataa => SumOfElements_0_0_add_0_28_f_q,
datab => SumOfElements_0_0_add_0_29_f_q,
result => SumOfElements_0_0_add_1_14_f_q
);
SumOfElements_0_0_add_1_14_f_p <= not SumOfElements_0_0_add_1_14_f_q(41 downto 41);
SumOfElements_0_0_add_1_14_f_n <= SumOfElements_0_0_add_1_14_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_14_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_28_f_q);
SumOfElements_0_0_add_1_14_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_29_f_q);
SumOfElements_0_0_add_1_14_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_14_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_7_f(FLOATADDSUB,378)@13
SumOfElements_0_0_add_2_7_f_reset <= areset;
SumOfElements_0_0_add_2_7_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_7_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_7_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_7_f_reset,
dataa => SumOfElements_0_0_add_1_14_f_q,
datab => SumOfElements_0_0_add_1_15_f_q,
result => SumOfElements_0_0_add_2_7_f_q
);
SumOfElements_0_0_add_2_7_f_p <= not SumOfElements_0_0_add_2_7_f_q(41 downto 41);
SumOfElements_0_0_add_2_7_f_n <= SumOfElements_0_0_add_2_7_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_7_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_14_f_q);
SumOfElements_0_0_add_2_7_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_15_f_q);
SumOfElements_0_0_add_2_7_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_7_f_q);
-- synopsys translate on
--Mult_55_f(FLOATMULT,257)@0
Mult_55_f_reset <= areset;
Mult_55_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_55_f_reset,
dataa => datain_a_55,
datab => datain_b_55,
result => Mult_55_f_q
);
-- synopsys translate off
Mult_55_f_a_real <= sIEEE_2_real(datain_a_55);
Mult_55_f_b_real <= sIEEE_2_real(datain_b_55);
Mult_55_f_q_real <= sInternalSM_2_real(Mult_55_f_q);
-- synopsys translate on
--Mult_54_f(FLOATMULT,256)@0
Mult_54_f_reset <= areset;
Mult_54_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_54_f_reset,
dataa => datain_a_54,
datab => datain_b_54,
result => Mult_54_f_q
);
-- synopsys translate off
Mult_54_f_a_real <= sIEEE_2_real(datain_a_54);
Mult_54_f_b_real <= sIEEE_2_real(datain_b_54);
Mult_54_f_q_real <= sInternalSM_2_real(Mult_54_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_27_f(FLOATADDSUB,322)@3
SumOfElements_0_0_add_0_27_f_reset <= areset;
SumOfElements_0_0_add_0_27_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_27_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_27_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_27_f_reset,
dataa => Mult_54_f_q,
datab => Mult_55_f_q,
result => SumOfElements_0_0_add_0_27_f_q
);
SumOfElements_0_0_add_0_27_f_p <= not SumOfElements_0_0_add_0_27_f_q(41 downto 41);
SumOfElements_0_0_add_0_27_f_n <= SumOfElements_0_0_add_0_27_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_27_f_a_real <= sInternalSM_2_real(Mult_54_f_q);
SumOfElements_0_0_add_0_27_f_b_real <= sInternalSM_2_real(Mult_55_f_q);
SumOfElements_0_0_add_0_27_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_27_f_q);
-- synopsys translate on
--Mult_53_f(FLOATMULT,255)@0
Mult_53_f_reset <= areset;
Mult_53_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_53_f_reset,
dataa => datain_a_53,
datab => datain_b_53,
result => Mult_53_f_q
);
-- synopsys translate off
Mult_53_f_a_real <= sIEEE_2_real(datain_a_53);
Mult_53_f_b_real <= sIEEE_2_real(datain_b_53);
Mult_53_f_q_real <= sInternalSM_2_real(Mult_53_f_q);
-- synopsys translate on
--Mult_52_f(FLOATMULT,254)@0
Mult_52_f_reset <= areset;
Mult_52_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_52_f_reset,
dataa => datain_a_52,
datab => datain_b_52,
result => Mult_52_f_q
);
-- synopsys translate off
Mult_52_f_a_real <= sIEEE_2_real(datain_a_52);
Mult_52_f_b_real <= sIEEE_2_real(datain_b_52);
Mult_52_f_q_real <= sInternalSM_2_real(Mult_52_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_26_f(FLOATADDSUB,320)@3
SumOfElements_0_0_add_0_26_f_reset <= areset;
SumOfElements_0_0_add_0_26_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_26_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_26_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_26_f_reset,
dataa => Mult_52_f_q,
datab => Mult_53_f_q,
result => SumOfElements_0_0_add_0_26_f_q
);
SumOfElements_0_0_add_0_26_f_p <= not SumOfElements_0_0_add_0_26_f_q(41 downto 41);
SumOfElements_0_0_add_0_26_f_n <= SumOfElements_0_0_add_0_26_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_26_f_a_real <= sInternalSM_2_real(Mult_52_f_q);
SumOfElements_0_0_add_0_26_f_b_real <= sInternalSM_2_real(Mult_53_f_q);
SumOfElements_0_0_add_0_26_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_26_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_13_f(FLOATADDSUB,358)@8
SumOfElements_0_0_add_1_13_f_reset <= areset;
SumOfElements_0_0_add_1_13_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_13_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_13_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_13_f_reset,
dataa => SumOfElements_0_0_add_0_26_f_q,
datab => SumOfElements_0_0_add_0_27_f_q,
result => SumOfElements_0_0_add_1_13_f_q
);
SumOfElements_0_0_add_1_13_f_p <= not SumOfElements_0_0_add_1_13_f_q(41 downto 41);
SumOfElements_0_0_add_1_13_f_n <= SumOfElements_0_0_add_1_13_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_13_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_26_f_q);
SumOfElements_0_0_add_1_13_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_27_f_q);
SumOfElements_0_0_add_1_13_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_13_f_q);
-- synopsys translate on
--Mult_51_f(FLOATMULT,253)@0
Mult_51_f_reset <= areset;
Mult_51_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_51_f_reset,
dataa => datain_a_51,
datab => datain_b_51,
result => Mult_51_f_q
);
-- synopsys translate off
Mult_51_f_a_real <= sIEEE_2_real(datain_a_51);
Mult_51_f_b_real <= sIEEE_2_real(datain_b_51);
Mult_51_f_q_real <= sInternalSM_2_real(Mult_51_f_q);
-- synopsys translate on
--Mult_50_f(FLOATMULT,252)@0
Mult_50_f_reset <= areset;
Mult_50_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_50_f_reset,
dataa => datain_a_50,
datab => datain_b_50,
result => Mult_50_f_q
);
-- synopsys translate off
Mult_50_f_a_real <= sIEEE_2_real(datain_a_50);
Mult_50_f_b_real <= sIEEE_2_real(datain_b_50);
Mult_50_f_q_real <= sInternalSM_2_real(Mult_50_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_25_f(FLOATADDSUB,318)@3
SumOfElements_0_0_add_0_25_f_reset <= areset;
SumOfElements_0_0_add_0_25_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_25_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_25_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_25_f_reset,
dataa => Mult_50_f_q,
datab => Mult_51_f_q,
result => SumOfElements_0_0_add_0_25_f_q
);
SumOfElements_0_0_add_0_25_f_p <= not SumOfElements_0_0_add_0_25_f_q(41 downto 41);
SumOfElements_0_0_add_0_25_f_n <= SumOfElements_0_0_add_0_25_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_25_f_a_real <= sInternalSM_2_real(Mult_50_f_q);
SumOfElements_0_0_add_0_25_f_b_real <= sInternalSM_2_real(Mult_51_f_q);
SumOfElements_0_0_add_0_25_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_25_f_q);
-- synopsys translate on
--Mult_49_f(FLOATMULT,251)@0
Mult_49_f_reset <= areset;
Mult_49_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_49_f_reset,
dataa => datain_a_49,
datab => datain_b_49,
result => Mult_49_f_q
);
-- synopsys translate off
Mult_49_f_a_real <= sIEEE_2_real(datain_a_49);
Mult_49_f_b_real <= sIEEE_2_real(datain_b_49);
Mult_49_f_q_real <= sInternalSM_2_real(Mult_49_f_q);
-- synopsys translate on
--Mult_48_f(FLOATMULT,250)@0
Mult_48_f_reset <= areset;
Mult_48_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_48_f_reset,
dataa => datain_a_48,
datab => datain_b_48,
result => Mult_48_f_q
);
-- synopsys translate off
Mult_48_f_a_real <= sIEEE_2_real(datain_a_48);
Mult_48_f_b_real <= sIEEE_2_real(datain_b_48);
Mult_48_f_q_real <= sInternalSM_2_real(Mult_48_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_24_f(FLOATADDSUB,316)@3
SumOfElements_0_0_add_0_24_f_reset <= areset;
SumOfElements_0_0_add_0_24_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_24_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_24_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_24_f_reset,
dataa => Mult_48_f_q,
datab => Mult_49_f_q,
result => SumOfElements_0_0_add_0_24_f_q
);
SumOfElements_0_0_add_0_24_f_p <= not SumOfElements_0_0_add_0_24_f_q(41 downto 41);
SumOfElements_0_0_add_0_24_f_n <= SumOfElements_0_0_add_0_24_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_24_f_a_real <= sInternalSM_2_real(Mult_48_f_q);
SumOfElements_0_0_add_0_24_f_b_real <= sInternalSM_2_real(Mult_49_f_q);
SumOfElements_0_0_add_0_24_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_24_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_12_f(FLOATADDSUB,356)@8
SumOfElements_0_0_add_1_12_f_reset <= areset;
SumOfElements_0_0_add_1_12_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_12_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_12_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_12_f_reset,
dataa => SumOfElements_0_0_add_0_24_f_q,
datab => SumOfElements_0_0_add_0_25_f_q,
result => SumOfElements_0_0_add_1_12_f_q
);
SumOfElements_0_0_add_1_12_f_p <= not SumOfElements_0_0_add_1_12_f_q(41 downto 41);
SumOfElements_0_0_add_1_12_f_n <= SumOfElements_0_0_add_1_12_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_12_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_24_f_q);
SumOfElements_0_0_add_1_12_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_25_f_q);
SumOfElements_0_0_add_1_12_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_12_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_6_f(FLOATADDSUB,376)@13
SumOfElements_0_0_add_2_6_f_reset <= areset;
SumOfElements_0_0_add_2_6_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_6_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_6_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_6_f_reset,
dataa => SumOfElements_0_0_add_1_12_f_q,
datab => SumOfElements_0_0_add_1_13_f_q,
result => SumOfElements_0_0_add_2_6_f_q
);
SumOfElements_0_0_add_2_6_f_p <= not SumOfElements_0_0_add_2_6_f_q(41 downto 41);
SumOfElements_0_0_add_2_6_f_n <= SumOfElements_0_0_add_2_6_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_6_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_12_f_q);
SumOfElements_0_0_add_2_6_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_13_f_q);
SumOfElements_0_0_add_2_6_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_6_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_3_f(FLOATADDSUB,386)@18
SumOfElements_0_0_add_3_3_f_reset <= areset;
SumOfElements_0_0_add_3_3_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_3_3_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_3_3_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_3_f_reset,
dataa => SumOfElements_0_0_add_2_6_f_q,
datab => SumOfElements_0_0_add_2_7_f_q,
result => SumOfElements_0_0_add_3_3_f_q
);
SumOfElements_0_0_add_3_3_f_p <= not SumOfElements_0_0_add_3_3_f_q(41 downto 41);
SumOfElements_0_0_add_3_3_f_n <= SumOfElements_0_0_add_3_3_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_3_3_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_2_6_f_q);
SumOfElements_0_0_add_3_3_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_2_7_f_q);
SumOfElements_0_0_add_3_3_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_3_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1((null),395)@23
SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_reset <= areset;
SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_inst : fp_norm_sInternal_2_sInternal
PORT MAP (
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_reset,
dataa => SumOfElements_0_0_add_3_3_f_q,
result => SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q
);
-- synopsys translate off
SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q);
-- synopsys translate on
--Mult_47_f(FLOATMULT,249)@0
Mult_47_f_reset <= areset;
Mult_47_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_47_f_reset,
dataa => datain_a_47,
datab => datain_b_47,
result => Mult_47_f_q
);
-- synopsys translate off
Mult_47_f_a_real <= sIEEE_2_real(datain_a_47);
Mult_47_f_b_real <= sIEEE_2_real(datain_b_47);
Mult_47_f_q_real <= sInternalSM_2_real(Mult_47_f_q);
-- synopsys translate on
--Mult_46_f(FLOATMULT,248)@0
Mult_46_f_reset <= areset;
Mult_46_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_46_f_reset,
dataa => datain_a_46,
datab => datain_b_46,
result => Mult_46_f_q
);
-- synopsys translate off
Mult_46_f_a_real <= sIEEE_2_real(datain_a_46);
Mult_46_f_b_real <= sIEEE_2_real(datain_b_46);
Mult_46_f_q_real <= sInternalSM_2_real(Mult_46_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_23_f(FLOATADDSUB,314)@3
SumOfElements_0_0_add_0_23_f_reset <= areset;
SumOfElements_0_0_add_0_23_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_23_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_23_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_23_f_reset,
dataa => Mult_46_f_q,
datab => Mult_47_f_q,
result => SumOfElements_0_0_add_0_23_f_q
);
SumOfElements_0_0_add_0_23_f_p <= not SumOfElements_0_0_add_0_23_f_q(41 downto 41);
SumOfElements_0_0_add_0_23_f_n <= SumOfElements_0_0_add_0_23_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_23_f_a_real <= sInternalSM_2_real(Mult_46_f_q);
SumOfElements_0_0_add_0_23_f_b_real <= sInternalSM_2_real(Mult_47_f_q);
SumOfElements_0_0_add_0_23_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_23_f_q);
-- synopsys translate on
--Mult_45_f(FLOATMULT,247)@0
Mult_45_f_reset <= areset;
Mult_45_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_45_f_reset,
dataa => datain_a_45,
datab => datain_b_45,
result => Mult_45_f_q
);
-- synopsys translate off
Mult_45_f_a_real <= sIEEE_2_real(datain_a_45);
Mult_45_f_b_real <= sIEEE_2_real(datain_b_45);
Mult_45_f_q_real <= sInternalSM_2_real(Mult_45_f_q);
-- synopsys translate on
--Mult_44_f(FLOATMULT,246)@0
Mult_44_f_reset <= areset;
Mult_44_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_44_f_reset,
dataa => datain_a_44,
datab => datain_b_44,
result => Mult_44_f_q
);
-- synopsys translate off
Mult_44_f_a_real <= sIEEE_2_real(datain_a_44);
Mult_44_f_b_real <= sIEEE_2_real(datain_b_44);
Mult_44_f_q_real <= sInternalSM_2_real(Mult_44_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_22_f(FLOATADDSUB,312)@3
SumOfElements_0_0_add_0_22_f_reset <= areset;
SumOfElements_0_0_add_0_22_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_22_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_22_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_22_f_reset,
dataa => Mult_44_f_q,
datab => Mult_45_f_q,
result => SumOfElements_0_0_add_0_22_f_q
);
SumOfElements_0_0_add_0_22_f_p <= not SumOfElements_0_0_add_0_22_f_q(41 downto 41);
SumOfElements_0_0_add_0_22_f_n <= SumOfElements_0_0_add_0_22_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_22_f_a_real <= sInternalSM_2_real(Mult_44_f_q);
SumOfElements_0_0_add_0_22_f_b_real <= sInternalSM_2_real(Mult_45_f_q);
SumOfElements_0_0_add_0_22_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_22_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_11_f(FLOATADDSUB,354)@8
SumOfElements_0_0_add_1_11_f_reset <= areset;
SumOfElements_0_0_add_1_11_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_11_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_11_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_11_f_reset,
dataa => SumOfElements_0_0_add_0_22_f_q,
datab => SumOfElements_0_0_add_0_23_f_q,
result => SumOfElements_0_0_add_1_11_f_q
);
SumOfElements_0_0_add_1_11_f_p <= not SumOfElements_0_0_add_1_11_f_q(41 downto 41);
SumOfElements_0_0_add_1_11_f_n <= SumOfElements_0_0_add_1_11_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_11_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_22_f_q);
SumOfElements_0_0_add_1_11_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_23_f_q);
SumOfElements_0_0_add_1_11_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_11_f_q);
-- synopsys translate on
--Mult_43_f(FLOATMULT,245)@0
Mult_43_f_reset <= areset;
Mult_43_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_43_f_reset,
dataa => datain_a_43,
datab => datain_b_43,
result => Mult_43_f_q
);
-- synopsys translate off
Mult_43_f_a_real <= sIEEE_2_real(datain_a_43);
Mult_43_f_b_real <= sIEEE_2_real(datain_b_43);
Mult_43_f_q_real <= sInternalSM_2_real(Mult_43_f_q);
-- synopsys translate on
--Mult_42_f(FLOATMULT,244)@0
Mult_42_f_reset <= areset;
Mult_42_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_42_f_reset,
dataa => datain_a_42,
datab => datain_b_42,
result => Mult_42_f_q
);
-- synopsys translate off
Mult_42_f_a_real <= sIEEE_2_real(datain_a_42);
Mult_42_f_b_real <= sIEEE_2_real(datain_b_42);
Mult_42_f_q_real <= sInternalSM_2_real(Mult_42_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_21_f(FLOATADDSUB,310)@3
SumOfElements_0_0_add_0_21_f_reset <= areset;
SumOfElements_0_0_add_0_21_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_21_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_21_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_21_f_reset,
dataa => Mult_42_f_q,
datab => Mult_43_f_q,
result => SumOfElements_0_0_add_0_21_f_q
);
SumOfElements_0_0_add_0_21_f_p <= not SumOfElements_0_0_add_0_21_f_q(41 downto 41);
SumOfElements_0_0_add_0_21_f_n <= SumOfElements_0_0_add_0_21_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_21_f_a_real <= sInternalSM_2_real(Mult_42_f_q);
SumOfElements_0_0_add_0_21_f_b_real <= sInternalSM_2_real(Mult_43_f_q);
SumOfElements_0_0_add_0_21_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_21_f_q);
-- synopsys translate on
--Mult_41_f(FLOATMULT,243)@0
Mult_41_f_reset <= areset;
Mult_41_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_41_f_reset,
dataa => datain_a_41,
datab => datain_b_41,
result => Mult_41_f_q
);
-- synopsys translate off
Mult_41_f_a_real <= sIEEE_2_real(datain_a_41);
Mult_41_f_b_real <= sIEEE_2_real(datain_b_41);
Mult_41_f_q_real <= sInternalSM_2_real(Mult_41_f_q);
-- synopsys translate on
--Mult_40_f(FLOATMULT,242)@0
Mult_40_f_reset <= areset;
Mult_40_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_40_f_reset,
dataa => datain_a_40,
datab => datain_b_40,
result => Mult_40_f_q
);
-- synopsys translate off
Mult_40_f_a_real <= sIEEE_2_real(datain_a_40);
Mult_40_f_b_real <= sIEEE_2_real(datain_b_40);
Mult_40_f_q_real <= sInternalSM_2_real(Mult_40_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_20_f(FLOATADDSUB,308)@3
SumOfElements_0_0_add_0_20_f_reset <= areset;
SumOfElements_0_0_add_0_20_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_20_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_20_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_20_f_reset,
dataa => Mult_40_f_q,
datab => Mult_41_f_q,
result => SumOfElements_0_0_add_0_20_f_q
);
SumOfElements_0_0_add_0_20_f_p <= not SumOfElements_0_0_add_0_20_f_q(41 downto 41);
SumOfElements_0_0_add_0_20_f_n <= SumOfElements_0_0_add_0_20_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_20_f_a_real <= sInternalSM_2_real(Mult_40_f_q);
SumOfElements_0_0_add_0_20_f_b_real <= sInternalSM_2_real(Mult_41_f_q);
SumOfElements_0_0_add_0_20_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_20_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_10_f(FLOATADDSUB,352)@8
SumOfElements_0_0_add_1_10_f_reset <= areset;
SumOfElements_0_0_add_1_10_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_10_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_10_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_10_f_reset,
dataa => SumOfElements_0_0_add_0_20_f_q,
datab => SumOfElements_0_0_add_0_21_f_q,
result => SumOfElements_0_0_add_1_10_f_q
);
SumOfElements_0_0_add_1_10_f_p <= not SumOfElements_0_0_add_1_10_f_q(41 downto 41);
SumOfElements_0_0_add_1_10_f_n <= SumOfElements_0_0_add_1_10_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_10_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_20_f_q);
SumOfElements_0_0_add_1_10_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_21_f_q);
SumOfElements_0_0_add_1_10_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_10_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_5_f(FLOATADDSUB,374)@13
SumOfElements_0_0_add_2_5_f_reset <= areset;
SumOfElements_0_0_add_2_5_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_5_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_5_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_5_f_reset,
dataa => SumOfElements_0_0_add_1_10_f_q,
datab => SumOfElements_0_0_add_1_11_f_q,
result => SumOfElements_0_0_add_2_5_f_q
);
SumOfElements_0_0_add_2_5_f_p <= not SumOfElements_0_0_add_2_5_f_q(41 downto 41);
SumOfElements_0_0_add_2_5_f_n <= SumOfElements_0_0_add_2_5_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_5_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_10_f_q);
SumOfElements_0_0_add_2_5_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_11_f_q);
SumOfElements_0_0_add_2_5_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_5_f_q);
-- synopsys translate on
--Mult_39_f(FLOATMULT,241)@0
Mult_39_f_reset <= areset;
Mult_39_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_39_f_reset,
dataa => datain_a_39,
datab => datain_b_39,
result => Mult_39_f_q
);
-- synopsys translate off
Mult_39_f_a_real <= sIEEE_2_real(datain_a_39);
Mult_39_f_b_real <= sIEEE_2_real(datain_b_39);
Mult_39_f_q_real <= sInternalSM_2_real(Mult_39_f_q);
-- synopsys translate on
--Mult_38_f(FLOATMULT,240)@0
Mult_38_f_reset <= areset;
Mult_38_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_38_f_reset,
dataa => datain_a_38,
datab => datain_b_38,
result => Mult_38_f_q
);
-- synopsys translate off
Mult_38_f_a_real <= sIEEE_2_real(datain_a_38);
Mult_38_f_b_real <= sIEEE_2_real(datain_b_38);
Mult_38_f_q_real <= sInternalSM_2_real(Mult_38_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_19_f(FLOATADDSUB,306)@3
SumOfElements_0_0_add_0_19_f_reset <= areset;
SumOfElements_0_0_add_0_19_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_19_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_19_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_19_f_reset,
dataa => Mult_38_f_q,
datab => Mult_39_f_q,
result => SumOfElements_0_0_add_0_19_f_q
);
SumOfElements_0_0_add_0_19_f_p <= not SumOfElements_0_0_add_0_19_f_q(41 downto 41);
SumOfElements_0_0_add_0_19_f_n <= SumOfElements_0_0_add_0_19_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_19_f_a_real <= sInternalSM_2_real(Mult_38_f_q);
SumOfElements_0_0_add_0_19_f_b_real <= sInternalSM_2_real(Mult_39_f_q);
SumOfElements_0_0_add_0_19_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_19_f_q);
-- synopsys translate on
--Mult_37_f(FLOATMULT,239)@0
Mult_37_f_reset <= areset;
Mult_37_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_37_f_reset,
dataa => datain_a_37,
datab => datain_b_37,
result => Mult_37_f_q
);
-- synopsys translate off
Mult_37_f_a_real <= sIEEE_2_real(datain_a_37);
Mult_37_f_b_real <= sIEEE_2_real(datain_b_37);
Mult_37_f_q_real <= sInternalSM_2_real(Mult_37_f_q);
-- synopsys translate on
--Mult_36_f(FLOATMULT,238)@0
Mult_36_f_reset <= areset;
Mult_36_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_36_f_reset,
dataa => datain_a_36,
datab => datain_b_36,
result => Mult_36_f_q
);
-- synopsys translate off
Mult_36_f_a_real <= sIEEE_2_real(datain_a_36);
Mult_36_f_b_real <= sIEEE_2_real(datain_b_36);
Mult_36_f_q_real <= sInternalSM_2_real(Mult_36_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_18_f(FLOATADDSUB,304)@3
SumOfElements_0_0_add_0_18_f_reset <= areset;
SumOfElements_0_0_add_0_18_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_18_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_18_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_18_f_reset,
dataa => Mult_36_f_q,
datab => Mult_37_f_q,
result => SumOfElements_0_0_add_0_18_f_q
);
SumOfElements_0_0_add_0_18_f_p <= not SumOfElements_0_0_add_0_18_f_q(41 downto 41);
SumOfElements_0_0_add_0_18_f_n <= SumOfElements_0_0_add_0_18_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_18_f_a_real <= sInternalSM_2_real(Mult_36_f_q);
SumOfElements_0_0_add_0_18_f_b_real <= sInternalSM_2_real(Mult_37_f_q);
SumOfElements_0_0_add_0_18_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_18_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_9_f(FLOATADDSUB,350)@8
SumOfElements_0_0_add_1_9_f_reset <= areset;
SumOfElements_0_0_add_1_9_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_9_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_9_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_9_f_reset,
dataa => SumOfElements_0_0_add_0_18_f_q,
datab => SumOfElements_0_0_add_0_19_f_q,
result => SumOfElements_0_0_add_1_9_f_q
);
SumOfElements_0_0_add_1_9_f_p <= not SumOfElements_0_0_add_1_9_f_q(41 downto 41);
SumOfElements_0_0_add_1_9_f_n <= SumOfElements_0_0_add_1_9_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_9_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_18_f_q);
SumOfElements_0_0_add_1_9_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_19_f_q);
SumOfElements_0_0_add_1_9_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_9_f_q);
-- synopsys translate on
--Mult_35_f(FLOATMULT,237)@0
Mult_35_f_reset <= areset;
Mult_35_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_35_f_reset,
dataa => datain_a_35,
datab => datain_b_35,
result => Mult_35_f_q
);
-- synopsys translate off
Mult_35_f_a_real <= sIEEE_2_real(datain_a_35);
Mult_35_f_b_real <= sIEEE_2_real(datain_b_35);
Mult_35_f_q_real <= sInternalSM_2_real(Mult_35_f_q);
-- synopsys translate on
--Mult_34_f(FLOATMULT,236)@0
Mult_34_f_reset <= areset;
Mult_34_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_34_f_reset,
dataa => datain_a_34,
datab => datain_b_34,
result => Mult_34_f_q
);
-- synopsys translate off
Mult_34_f_a_real <= sIEEE_2_real(datain_a_34);
Mult_34_f_b_real <= sIEEE_2_real(datain_b_34);
Mult_34_f_q_real <= sInternalSM_2_real(Mult_34_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_17_f(FLOATADDSUB,302)@3
SumOfElements_0_0_add_0_17_f_reset <= areset;
SumOfElements_0_0_add_0_17_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_17_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_17_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_17_f_reset,
dataa => Mult_34_f_q,
datab => Mult_35_f_q,
result => SumOfElements_0_0_add_0_17_f_q
);
SumOfElements_0_0_add_0_17_f_p <= not SumOfElements_0_0_add_0_17_f_q(41 downto 41);
SumOfElements_0_0_add_0_17_f_n <= SumOfElements_0_0_add_0_17_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_17_f_a_real <= sInternalSM_2_real(Mult_34_f_q);
SumOfElements_0_0_add_0_17_f_b_real <= sInternalSM_2_real(Mult_35_f_q);
SumOfElements_0_0_add_0_17_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_17_f_q);
-- synopsys translate on
--Mult_33_f(FLOATMULT,235)@0
Mult_33_f_reset <= areset;
Mult_33_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_33_f_reset,
dataa => datain_a_33,
datab => datain_b_33,
result => Mult_33_f_q
);
-- synopsys translate off
Mult_33_f_a_real <= sIEEE_2_real(datain_a_33);
Mult_33_f_b_real <= sIEEE_2_real(datain_b_33);
Mult_33_f_q_real <= sInternalSM_2_real(Mult_33_f_q);
-- synopsys translate on
--Mult_32_f(FLOATMULT,234)@0
Mult_32_f_reset <= areset;
Mult_32_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_32_f_reset,
dataa => datain_a_32,
datab => datain_b_32,
result => Mult_32_f_q
);
-- synopsys translate off
Mult_32_f_a_real <= sIEEE_2_real(datain_a_32);
Mult_32_f_b_real <= sIEEE_2_real(datain_b_32);
Mult_32_f_q_real <= sInternalSM_2_real(Mult_32_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_16_f(FLOATADDSUB,300)@3
SumOfElements_0_0_add_0_16_f_reset <= areset;
SumOfElements_0_0_add_0_16_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_16_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_16_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_16_f_reset,
dataa => Mult_32_f_q,
datab => Mult_33_f_q,
result => SumOfElements_0_0_add_0_16_f_q
);
SumOfElements_0_0_add_0_16_f_p <= not SumOfElements_0_0_add_0_16_f_q(41 downto 41);
SumOfElements_0_0_add_0_16_f_n <= SumOfElements_0_0_add_0_16_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_16_f_a_real <= sInternalSM_2_real(Mult_32_f_q);
SumOfElements_0_0_add_0_16_f_b_real <= sInternalSM_2_real(Mult_33_f_q);
SumOfElements_0_0_add_0_16_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_16_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_8_f(FLOATADDSUB,348)@8
SumOfElements_0_0_add_1_8_f_reset <= areset;
SumOfElements_0_0_add_1_8_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_8_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_8_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_8_f_reset,
dataa => SumOfElements_0_0_add_0_16_f_q,
datab => SumOfElements_0_0_add_0_17_f_q,
result => SumOfElements_0_0_add_1_8_f_q
);
SumOfElements_0_0_add_1_8_f_p <= not SumOfElements_0_0_add_1_8_f_q(41 downto 41);
SumOfElements_0_0_add_1_8_f_n <= SumOfElements_0_0_add_1_8_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_8_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_16_f_q);
SumOfElements_0_0_add_1_8_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_17_f_q);
SumOfElements_0_0_add_1_8_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_8_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_4_f(FLOATADDSUB,372)@13
SumOfElements_0_0_add_2_4_f_reset <= areset;
SumOfElements_0_0_add_2_4_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_4_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_4_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_4_f_reset,
dataa => SumOfElements_0_0_add_1_8_f_q,
datab => SumOfElements_0_0_add_1_9_f_q,
result => SumOfElements_0_0_add_2_4_f_q
);
SumOfElements_0_0_add_2_4_f_p <= not SumOfElements_0_0_add_2_4_f_q(41 downto 41);
SumOfElements_0_0_add_2_4_f_n <= SumOfElements_0_0_add_2_4_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_4_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_8_f_q);
SumOfElements_0_0_add_2_4_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_9_f_q);
SumOfElements_0_0_add_2_4_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_4_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_2_f(FLOATADDSUB,384)@18
SumOfElements_0_0_add_3_2_f_reset <= areset;
SumOfElements_0_0_add_3_2_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_3_2_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_3_2_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_2_f_reset,
dataa => SumOfElements_0_0_add_2_4_f_q,
datab => SumOfElements_0_0_add_2_5_f_q,
result => SumOfElements_0_0_add_3_2_f_q
);
SumOfElements_0_0_add_3_2_f_p <= not SumOfElements_0_0_add_3_2_f_q(41 downto 41);
SumOfElements_0_0_add_3_2_f_n <= SumOfElements_0_0_add_3_2_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_3_2_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_2_4_f_q);
SumOfElements_0_0_add_3_2_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_2_5_f_q);
SumOfElements_0_0_add_3_2_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_2_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0((null),396)@23
SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_reset <= areset;
SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_inst : fp_norm_sInternal_2_sInternal
PORT MAP (
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_reset,
dataa => SumOfElements_0_0_add_3_2_f_q,
result => SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q
);
-- synopsys translate off
SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q);
-- synopsys translate on
--SumOfElements_0_0_add_4_1_f(FLOATADDSUB,390)@28
SumOfElements_0_0_add_4_1_f_reset <= areset;
SumOfElements_0_0_add_4_1_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_4_1_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_4_1_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_4_1_f_reset,
dataa => SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q,
datab => SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q,
result => SumOfElements_0_0_add_4_1_f_q
);
SumOfElements_0_0_add_4_1_f_p <= not SumOfElements_0_0_add_4_1_f_q(41 downto 41);
SumOfElements_0_0_add_4_1_f_n <= SumOfElements_0_0_add_4_1_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_4_1_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_3_2_f_0_norm_SumOfElements_0_0_add_4_1_f_0_q);
SumOfElements_0_0_add_4_1_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_3_3_f_0_norm_SumOfElements_0_0_add_4_1_f_1_q);
SumOfElements_0_0_add_4_1_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_4_1_f_q);
-- synopsys translate on
--Mult_31_f(FLOATMULT,233)@0
Mult_31_f_reset <= areset;
Mult_31_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_31_f_reset,
dataa => datain_a_31,
datab => datain_b_31,
result => Mult_31_f_q
);
-- synopsys translate off
Mult_31_f_a_real <= sIEEE_2_real(datain_a_31);
Mult_31_f_b_real <= sIEEE_2_real(datain_b_31);
Mult_31_f_q_real <= sInternalSM_2_real(Mult_31_f_q);
-- synopsys translate on
--Mult_30_f(FLOATMULT,232)@0
Mult_30_f_reset <= areset;
Mult_30_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_30_f_reset,
dataa => datain_a_30,
datab => datain_b_30,
result => Mult_30_f_q
);
-- synopsys translate off
Mult_30_f_a_real <= sIEEE_2_real(datain_a_30);
Mult_30_f_b_real <= sIEEE_2_real(datain_b_30);
Mult_30_f_q_real <= sInternalSM_2_real(Mult_30_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_15_f(FLOATADDSUB,298)@3
SumOfElements_0_0_add_0_15_f_reset <= areset;
SumOfElements_0_0_add_0_15_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_15_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_15_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_15_f_reset,
dataa => Mult_30_f_q,
datab => Mult_31_f_q,
result => SumOfElements_0_0_add_0_15_f_q
);
SumOfElements_0_0_add_0_15_f_p <= not SumOfElements_0_0_add_0_15_f_q(41 downto 41);
SumOfElements_0_0_add_0_15_f_n <= SumOfElements_0_0_add_0_15_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_15_f_a_real <= sInternalSM_2_real(Mult_30_f_q);
SumOfElements_0_0_add_0_15_f_b_real <= sInternalSM_2_real(Mult_31_f_q);
SumOfElements_0_0_add_0_15_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_15_f_q);
-- synopsys translate on
--Mult_29_f(FLOATMULT,231)@0
Mult_29_f_reset <= areset;
Mult_29_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_29_f_reset,
dataa => datain_a_29,
datab => datain_b_29,
result => Mult_29_f_q
);
-- synopsys translate off
Mult_29_f_a_real <= sIEEE_2_real(datain_a_29);
Mult_29_f_b_real <= sIEEE_2_real(datain_b_29);
Mult_29_f_q_real <= sInternalSM_2_real(Mult_29_f_q);
-- synopsys translate on
--Mult_28_f(FLOATMULT,230)@0
Mult_28_f_reset <= areset;
Mult_28_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_28_f_reset,
dataa => datain_a_28,
datab => datain_b_28,
result => Mult_28_f_q
);
-- synopsys translate off
Mult_28_f_a_real <= sIEEE_2_real(datain_a_28);
Mult_28_f_b_real <= sIEEE_2_real(datain_b_28);
Mult_28_f_q_real <= sInternalSM_2_real(Mult_28_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_14_f(FLOATADDSUB,296)@3
SumOfElements_0_0_add_0_14_f_reset <= areset;
SumOfElements_0_0_add_0_14_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_14_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_14_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_14_f_reset,
dataa => Mult_28_f_q,
datab => Mult_29_f_q,
result => SumOfElements_0_0_add_0_14_f_q
);
SumOfElements_0_0_add_0_14_f_p <= not SumOfElements_0_0_add_0_14_f_q(41 downto 41);
SumOfElements_0_0_add_0_14_f_n <= SumOfElements_0_0_add_0_14_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_14_f_a_real <= sInternalSM_2_real(Mult_28_f_q);
SumOfElements_0_0_add_0_14_f_b_real <= sInternalSM_2_real(Mult_29_f_q);
SumOfElements_0_0_add_0_14_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_14_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_7_f(FLOATADDSUB,346)@8
SumOfElements_0_0_add_1_7_f_reset <= areset;
SumOfElements_0_0_add_1_7_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_7_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_7_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_7_f_reset,
dataa => SumOfElements_0_0_add_0_14_f_q,
datab => SumOfElements_0_0_add_0_15_f_q,
result => SumOfElements_0_0_add_1_7_f_q
);
SumOfElements_0_0_add_1_7_f_p <= not SumOfElements_0_0_add_1_7_f_q(41 downto 41);
SumOfElements_0_0_add_1_7_f_n <= SumOfElements_0_0_add_1_7_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_7_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_14_f_q);
SumOfElements_0_0_add_1_7_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_15_f_q);
SumOfElements_0_0_add_1_7_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_7_f_q);
-- synopsys translate on
--Mult_27_f(FLOATMULT,229)@0
Mult_27_f_reset <= areset;
Mult_27_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_27_f_reset,
dataa => datain_a_27,
datab => datain_b_27,
result => Mult_27_f_q
);
-- synopsys translate off
Mult_27_f_a_real <= sIEEE_2_real(datain_a_27);
Mult_27_f_b_real <= sIEEE_2_real(datain_b_27);
Mult_27_f_q_real <= sInternalSM_2_real(Mult_27_f_q);
-- synopsys translate on
--Mult_26_f(FLOATMULT,228)@0
Mult_26_f_reset <= areset;
Mult_26_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_26_f_reset,
dataa => datain_a_26,
datab => datain_b_26,
result => Mult_26_f_q
);
-- synopsys translate off
Mult_26_f_a_real <= sIEEE_2_real(datain_a_26);
Mult_26_f_b_real <= sIEEE_2_real(datain_b_26);
Mult_26_f_q_real <= sInternalSM_2_real(Mult_26_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_13_f(FLOATADDSUB,294)@3
SumOfElements_0_0_add_0_13_f_reset <= areset;
SumOfElements_0_0_add_0_13_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_13_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_13_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_13_f_reset,
dataa => Mult_26_f_q,
datab => Mult_27_f_q,
result => SumOfElements_0_0_add_0_13_f_q
);
SumOfElements_0_0_add_0_13_f_p <= not SumOfElements_0_0_add_0_13_f_q(41 downto 41);
SumOfElements_0_0_add_0_13_f_n <= SumOfElements_0_0_add_0_13_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_13_f_a_real <= sInternalSM_2_real(Mult_26_f_q);
SumOfElements_0_0_add_0_13_f_b_real <= sInternalSM_2_real(Mult_27_f_q);
SumOfElements_0_0_add_0_13_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_13_f_q);
-- synopsys translate on
--Mult_25_f(FLOATMULT,227)@0
Mult_25_f_reset <= areset;
Mult_25_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_25_f_reset,
dataa => datain_a_25,
datab => datain_b_25,
result => Mult_25_f_q
);
-- synopsys translate off
Mult_25_f_a_real <= sIEEE_2_real(datain_a_25);
Mult_25_f_b_real <= sIEEE_2_real(datain_b_25);
Mult_25_f_q_real <= sInternalSM_2_real(Mult_25_f_q);
-- synopsys translate on
--Mult_24_f(FLOATMULT,226)@0
Mult_24_f_reset <= areset;
Mult_24_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_24_f_reset,
dataa => datain_a_24,
datab => datain_b_24,
result => Mult_24_f_q
);
-- synopsys translate off
Mult_24_f_a_real <= sIEEE_2_real(datain_a_24);
Mult_24_f_b_real <= sIEEE_2_real(datain_b_24);
Mult_24_f_q_real <= sInternalSM_2_real(Mult_24_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_12_f(FLOATADDSUB,292)@3
SumOfElements_0_0_add_0_12_f_reset <= areset;
SumOfElements_0_0_add_0_12_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_12_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_12_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_12_f_reset,
dataa => Mult_24_f_q,
datab => Mult_25_f_q,
result => SumOfElements_0_0_add_0_12_f_q
);
SumOfElements_0_0_add_0_12_f_p <= not SumOfElements_0_0_add_0_12_f_q(41 downto 41);
SumOfElements_0_0_add_0_12_f_n <= SumOfElements_0_0_add_0_12_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_12_f_a_real <= sInternalSM_2_real(Mult_24_f_q);
SumOfElements_0_0_add_0_12_f_b_real <= sInternalSM_2_real(Mult_25_f_q);
SumOfElements_0_0_add_0_12_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_12_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_6_f(FLOATADDSUB,344)@8
SumOfElements_0_0_add_1_6_f_reset <= areset;
SumOfElements_0_0_add_1_6_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_6_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_6_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_6_f_reset,
dataa => SumOfElements_0_0_add_0_12_f_q,
datab => SumOfElements_0_0_add_0_13_f_q,
result => SumOfElements_0_0_add_1_6_f_q
);
SumOfElements_0_0_add_1_6_f_p <= not SumOfElements_0_0_add_1_6_f_q(41 downto 41);
SumOfElements_0_0_add_1_6_f_n <= SumOfElements_0_0_add_1_6_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_6_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_12_f_q);
SumOfElements_0_0_add_1_6_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_13_f_q);
SumOfElements_0_0_add_1_6_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_6_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_3_f(FLOATADDSUB,370)@13
SumOfElements_0_0_add_2_3_f_reset <= areset;
SumOfElements_0_0_add_2_3_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_3_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_3_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_3_f_reset,
dataa => SumOfElements_0_0_add_1_6_f_q,
datab => SumOfElements_0_0_add_1_7_f_q,
result => SumOfElements_0_0_add_2_3_f_q
);
SumOfElements_0_0_add_2_3_f_p <= not SumOfElements_0_0_add_2_3_f_q(41 downto 41);
SumOfElements_0_0_add_2_3_f_n <= SumOfElements_0_0_add_2_3_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_3_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_6_f_q);
SumOfElements_0_0_add_2_3_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_7_f_q);
SumOfElements_0_0_add_2_3_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_3_f_q);
-- synopsys translate on
--Mult_23_f(FLOATMULT,225)@0
Mult_23_f_reset <= areset;
Mult_23_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_23_f_reset,
dataa => datain_a_23,
datab => datain_b_23,
result => Mult_23_f_q
);
-- synopsys translate off
Mult_23_f_a_real <= sIEEE_2_real(datain_a_23);
Mult_23_f_b_real <= sIEEE_2_real(datain_b_23);
Mult_23_f_q_real <= sInternalSM_2_real(Mult_23_f_q);
-- synopsys translate on
--Mult_22_f(FLOATMULT,224)@0
Mult_22_f_reset <= areset;
Mult_22_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_22_f_reset,
dataa => datain_a_22,
datab => datain_b_22,
result => Mult_22_f_q
);
-- synopsys translate off
Mult_22_f_a_real <= sIEEE_2_real(datain_a_22);
Mult_22_f_b_real <= sIEEE_2_real(datain_b_22);
Mult_22_f_q_real <= sInternalSM_2_real(Mult_22_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_11_f(FLOATADDSUB,290)@3
SumOfElements_0_0_add_0_11_f_reset <= areset;
SumOfElements_0_0_add_0_11_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_11_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_11_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_11_f_reset,
dataa => Mult_22_f_q,
datab => Mult_23_f_q,
result => SumOfElements_0_0_add_0_11_f_q
);
SumOfElements_0_0_add_0_11_f_p <= not SumOfElements_0_0_add_0_11_f_q(41 downto 41);
SumOfElements_0_0_add_0_11_f_n <= SumOfElements_0_0_add_0_11_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_11_f_a_real <= sInternalSM_2_real(Mult_22_f_q);
SumOfElements_0_0_add_0_11_f_b_real <= sInternalSM_2_real(Mult_23_f_q);
SumOfElements_0_0_add_0_11_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_11_f_q);
-- synopsys translate on
--Mult_21_f(FLOATMULT,223)@0
Mult_21_f_reset <= areset;
Mult_21_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_21_f_reset,
dataa => datain_a_21,
datab => datain_b_21,
result => Mult_21_f_q
);
-- synopsys translate off
Mult_21_f_a_real <= sIEEE_2_real(datain_a_21);
Mult_21_f_b_real <= sIEEE_2_real(datain_b_21);
Mult_21_f_q_real <= sInternalSM_2_real(Mult_21_f_q);
-- synopsys translate on
--Mult_20_f(FLOATMULT,222)@0
Mult_20_f_reset <= areset;
Mult_20_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_20_f_reset,
dataa => datain_a_20,
datab => datain_b_20,
result => Mult_20_f_q
);
-- synopsys translate off
Mult_20_f_a_real <= sIEEE_2_real(datain_a_20);
Mult_20_f_b_real <= sIEEE_2_real(datain_b_20);
Mult_20_f_q_real <= sInternalSM_2_real(Mult_20_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_10_f(FLOATADDSUB,288)@3
SumOfElements_0_0_add_0_10_f_reset <= areset;
SumOfElements_0_0_add_0_10_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_10_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_10_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_10_f_reset,
dataa => Mult_20_f_q,
datab => Mult_21_f_q,
result => SumOfElements_0_0_add_0_10_f_q
);
SumOfElements_0_0_add_0_10_f_p <= not SumOfElements_0_0_add_0_10_f_q(41 downto 41);
SumOfElements_0_0_add_0_10_f_n <= SumOfElements_0_0_add_0_10_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_10_f_a_real <= sInternalSM_2_real(Mult_20_f_q);
SumOfElements_0_0_add_0_10_f_b_real <= sInternalSM_2_real(Mult_21_f_q);
SumOfElements_0_0_add_0_10_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_10_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_5_f(FLOATADDSUB,342)@8
SumOfElements_0_0_add_1_5_f_reset <= areset;
SumOfElements_0_0_add_1_5_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_5_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_5_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_5_f_reset,
dataa => SumOfElements_0_0_add_0_10_f_q,
datab => SumOfElements_0_0_add_0_11_f_q,
result => SumOfElements_0_0_add_1_5_f_q
);
SumOfElements_0_0_add_1_5_f_p <= not SumOfElements_0_0_add_1_5_f_q(41 downto 41);
SumOfElements_0_0_add_1_5_f_n <= SumOfElements_0_0_add_1_5_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_5_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_10_f_q);
SumOfElements_0_0_add_1_5_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_11_f_q);
SumOfElements_0_0_add_1_5_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_5_f_q);
-- synopsys translate on
--Mult_19_f(FLOATMULT,221)@0
Mult_19_f_reset <= areset;
Mult_19_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_19_f_reset,
dataa => datain_a_19,
datab => datain_b_19,
result => Mult_19_f_q
);
-- synopsys translate off
Mult_19_f_a_real <= sIEEE_2_real(datain_a_19);
Mult_19_f_b_real <= sIEEE_2_real(datain_b_19);
Mult_19_f_q_real <= sInternalSM_2_real(Mult_19_f_q);
-- synopsys translate on
--Mult_18_f(FLOATMULT,220)@0
Mult_18_f_reset <= areset;
Mult_18_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_18_f_reset,
dataa => datain_a_18,
datab => datain_b_18,
result => Mult_18_f_q
);
-- synopsys translate off
Mult_18_f_a_real <= sIEEE_2_real(datain_a_18);
Mult_18_f_b_real <= sIEEE_2_real(datain_b_18);
Mult_18_f_q_real <= sInternalSM_2_real(Mult_18_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_9_f(FLOATADDSUB,286)@3
SumOfElements_0_0_add_0_9_f_reset <= areset;
SumOfElements_0_0_add_0_9_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_9_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_9_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_9_f_reset,
dataa => Mult_18_f_q,
datab => Mult_19_f_q,
result => SumOfElements_0_0_add_0_9_f_q
);
SumOfElements_0_0_add_0_9_f_p <= not SumOfElements_0_0_add_0_9_f_q(41 downto 41);
SumOfElements_0_0_add_0_9_f_n <= SumOfElements_0_0_add_0_9_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_9_f_a_real <= sInternalSM_2_real(Mult_18_f_q);
SumOfElements_0_0_add_0_9_f_b_real <= sInternalSM_2_real(Mult_19_f_q);
SumOfElements_0_0_add_0_9_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_9_f_q);
-- synopsys translate on
--Mult_17_f(FLOATMULT,219)@0
Mult_17_f_reset <= areset;
Mult_17_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_17_f_reset,
dataa => datain_a_17,
datab => datain_b_17,
result => Mult_17_f_q
);
-- synopsys translate off
Mult_17_f_a_real <= sIEEE_2_real(datain_a_17);
Mult_17_f_b_real <= sIEEE_2_real(datain_b_17);
Mult_17_f_q_real <= sInternalSM_2_real(Mult_17_f_q);
-- synopsys translate on
--Mult_16_f(FLOATMULT,218)@0
Mult_16_f_reset <= areset;
Mult_16_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_16_f_reset,
dataa => datain_a_16,
datab => datain_b_16,
result => Mult_16_f_q
);
-- synopsys translate off
Mult_16_f_a_real <= sIEEE_2_real(datain_a_16);
Mult_16_f_b_real <= sIEEE_2_real(datain_b_16);
Mult_16_f_q_real <= sInternalSM_2_real(Mult_16_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_8_f(FLOATADDSUB,284)@3
SumOfElements_0_0_add_0_8_f_reset <= areset;
SumOfElements_0_0_add_0_8_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_8_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_8_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_8_f_reset,
dataa => Mult_16_f_q,
datab => Mult_17_f_q,
result => SumOfElements_0_0_add_0_8_f_q
);
SumOfElements_0_0_add_0_8_f_p <= not SumOfElements_0_0_add_0_8_f_q(41 downto 41);
SumOfElements_0_0_add_0_8_f_n <= SumOfElements_0_0_add_0_8_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_8_f_a_real <= sInternalSM_2_real(Mult_16_f_q);
SumOfElements_0_0_add_0_8_f_b_real <= sInternalSM_2_real(Mult_17_f_q);
SumOfElements_0_0_add_0_8_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_8_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_4_f(FLOATADDSUB,340)@8
SumOfElements_0_0_add_1_4_f_reset <= areset;
SumOfElements_0_0_add_1_4_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_4_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_4_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_4_f_reset,
dataa => SumOfElements_0_0_add_0_8_f_q,
datab => SumOfElements_0_0_add_0_9_f_q,
result => SumOfElements_0_0_add_1_4_f_q
);
SumOfElements_0_0_add_1_4_f_p <= not SumOfElements_0_0_add_1_4_f_q(41 downto 41);
SumOfElements_0_0_add_1_4_f_n <= SumOfElements_0_0_add_1_4_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_4_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_8_f_q);
SumOfElements_0_0_add_1_4_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_9_f_q);
SumOfElements_0_0_add_1_4_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_4_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_2_f(FLOATADDSUB,368)@13
SumOfElements_0_0_add_2_2_f_reset <= areset;
SumOfElements_0_0_add_2_2_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_2_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_2_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_2_f_reset,
dataa => SumOfElements_0_0_add_1_4_f_q,
datab => SumOfElements_0_0_add_1_5_f_q,
result => SumOfElements_0_0_add_2_2_f_q
);
SumOfElements_0_0_add_2_2_f_p <= not SumOfElements_0_0_add_2_2_f_q(41 downto 41);
SumOfElements_0_0_add_2_2_f_n <= SumOfElements_0_0_add_2_2_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_2_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_4_f_q);
SumOfElements_0_0_add_2_2_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_5_f_q);
SumOfElements_0_0_add_2_2_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_2_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_1_f(FLOATADDSUB,382)@18
SumOfElements_0_0_add_3_1_f_reset <= areset;
SumOfElements_0_0_add_3_1_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_3_1_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_3_1_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_1_f_reset,
dataa => SumOfElements_0_0_add_2_2_f_q,
datab => SumOfElements_0_0_add_2_3_f_q,
result => SumOfElements_0_0_add_3_1_f_q
);
SumOfElements_0_0_add_3_1_f_p <= not SumOfElements_0_0_add_3_1_f_q(41 downto 41);
SumOfElements_0_0_add_3_1_f_n <= SumOfElements_0_0_add_3_1_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_3_1_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_2_2_f_q);
SumOfElements_0_0_add_3_1_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_2_3_f_q);
SumOfElements_0_0_add_3_1_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_1_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1((null),393)@23
SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_reset <= areset;
SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_inst : fp_norm_sInternal_2_sInternal
PORT MAP (
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_reset,
dataa => SumOfElements_0_0_add_3_1_f_q,
result => SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q
);
-- synopsys translate off
SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q);
-- synopsys translate on
--Mult_15_f(FLOATMULT,217)@0
Mult_15_f_reset <= areset;
Mult_15_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_15_f_reset,
dataa => datain_a_15,
datab => datain_b_15,
result => Mult_15_f_q
);
-- synopsys translate off
Mult_15_f_a_real <= sIEEE_2_real(datain_a_15);
Mult_15_f_b_real <= sIEEE_2_real(datain_b_15);
Mult_15_f_q_real <= sInternalSM_2_real(Mult_15_f_q);
-- synopsys translate on
--Mult_14_f(FLOATMULT,216)@0
Mult_14_f_reset <= areset;
Mult_14_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_14_f_reset,
dataa => datain_a_14,
datab => datain_b_14,
result => Mult_14_f_q
);
-- synopsys translate off
Mult_14_f_a_real <= sIEEE_2_real(datain_a_14);
Mult_14_f_b_real <= sIEEE_2_real(datain_b_14);
Mult_14_f_q_real <= sInternalSM_2_real(Mult_14_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_7_f(FLOATADDSUB,282)@3
SumOfElements_0_0_add_0_7_f_reset <= areset;
SumOfElements_0_0_add_0_7_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_7_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_7_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_7_f_reset,
dataa => Mult_14_f_q,
datab => Mult_15_f_q,
result => SumOfElements_0_0_add_0_7_f_q
);
SumOfElements_0_0_add_0_7_f_p <= not SumOfElements_0_0_add_0_7_f_q(41 downto 41);
SumOfElements_0_0_add_0_7_f_n <= SumOfElements_0_0_add_0_7_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_7_f_a_real <= sInternalSM_2_real(Mult_14_f_q);
SumOfElements_0_0_add_0_7_f_b_real <= sInternalSM_2_real(Mult_15_f_q);
SumOfElements_0_0_add_0_7_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_7_f_q);
-- synopsys translate on
--Mult_13_f(FLOATMULT,215)@0
Mult_13_f_reset <= areset;
Mult_13_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_13_f_reset,
dataa => datain_a_13,
datab => datain_b_13,
result => Mult_13_f_q
);
-- synopsys translate off
Mult_13_f_a_real <= sIEEE_2_real(datain_a_13);
Mult_13_f_b_real <= sIEEE_2_real(datain_b_13);
Mult_13_f_q_real <= sInternalSM_2_real(Mult_13_f_q);
-- synopsys translate on
--Mult_12_f(FLOATMULT,214)@0
Mult_12_f_reset <= areset;
Mult_12_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_12_f_reset,
dataa => datain_a_12,
datab => datain_b_12,
result => Mult_12_f_q
);
-- synopsys translate off
Mult_12_f_a_real <= sIEEE_2_real(datain_a_12);
Mult_12_f_b_real <= sIEEE_2_real(datain_b_12);
Mult_12_f_q_real <= sInternalSM_2_real(Mult_12_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_6_f(FLOATADDSUB,280)@3
SumOfElements_0_0_add_0_6_f_reset <= areset;
SumOfElements_0_0_add_0_6_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_6_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_6_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_6_f_reset,
dataa => Mult_12_f_q,
datab => Mult_13_f_q,
result => SumOfElements_0_0_add_0_6_f_q
);
SumOfElements_0_0_add_0_6_f_p <= not SumOfElements_0_0_add_0_6_f_q(41 downto 41);
SumOfElements_0_0_add_0_6_f_n <= SumOfElements_0_0_add_0_6_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_6_f_a_real <= sInternalSM_2_real(Mult_12_f_q);
SumOfElements_0_0_add_0_6_f_b_real <= sInternalSM_2_real(Mult_13_f_q);
SumOfElements_0_0_add_0_6_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_6_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_3_f(FLOATADDSUB,338)@8
SumOfElements_0_0_add_1_3_f_reset <= areset;
SumOfElements_0_0_add_1_3_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_3_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_3_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_3_f_reset,
dataa => SumOfElements_0_0_add_0_6_f_q,
datab => SumOfElements_0_0_add_0_7_f_q,
result => SumOfElements_0_0_add_1_3_f_q
);
SumOfElements_0_0_add_1_3_f_p <= not SumOfElements_0_0_add_1_3_f_q(41 downto 41);
SumOfElements_0_0_add_1_3_f_n <= SumOfElements_0_0_add_1_3_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_3_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_6_f_q);
SumOfElements_0_0_add_1_3_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_7_f_q);
SumOfElements_0_0_add_1_3_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_3_f_q);
-- synopsys translate on
--Mult_11_f(FLOATMULT,213)@0
Mult_11_f_reset <= areset;
Mult_11_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_11_f_reset,
dataa => datain_a_11,
datab => datain_b_11,
result => Mult_11_f_q
);
-- synopsys translate off
Mult_11_f_a_real <= sIEEE_2_real(datain_a_11);
Mult_11_f_b_real <= sIEEE_2_real(datain_b_11);
Mult_11_f_q_real <= sInternalSM_2_real(Mult_11_f_q);
-- synopsys translate on
--Mult_10_f(FLOATMULT,212)@0
Mult_10_f_reset <= areset;
Mult_10_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_10_f_reset,
dataa => datain_a_10,
datab => datain_b_10,
result => Mult_10_f_q
);
-- synopsys translate off
Mult_10_f_a_real <= sIEEE_2_real(datain_a_10);
Mult_10_f_b_real <= sIEEE_2_real(datain_b_10);
Mult_10_f_q_real <= sInternalSM_2_real(Mult_10_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_5_f(FLOATADDSUB,278)@3
SumOfElements_0_0_add_0_5_f_reset <= areset;
SumOfElements_0_0_add_0_5_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_5_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_5_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_5_f_reset,
dataa => Mult_10_f_q,
datab => Mult_11_f_q,
result => SumOfElements_0_0_add_0_5_f_q
);
SumOfElements_0_0_add_0_5_f_p <= not SumOfElements_0_0_add_0_5_f_q(41 downto 41);
SumOfElements_0_0_add_0_5_f_n <= SumOfElements_0_0_add_0_5_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_5_f_a_real <= sInternalSM_2_real(Mult_10_f_q);
SumOfElements_0_0_add_0_5_f_b_real <= sInternalSM_2_real(Mult_11_f_q);
SumOfElements_0_0_add_0_5_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_5_f_q);
-- synopsys translate on
--Mult_9_f(FLOATMULT,211)@0
Mult_9_f_reset <= areset;
Mult_9_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_9_f_reset,
dataa => datain_a_09,
datab => datain_b_09,
result => Mult_9_f_q
);
-- synopsys translate off
Mult_9_f_a_real <= sIEEE_2_real(datain_a_09);
Mult_9_f_b_real <= sIEEE_2_real(datain_b_09);
Mult_9_f_q_real <= sInternalSM_2_real(Mult_9_f_q);
-- synopsys translate on
--Mult_8_f(FLOATMULT,210)@0
Mult_8_f_reset <= areset;
Mult_8_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_8_f_reset,
dataa => datain_a_08,
datab => datain_b_08,
result => Mult_8_f_q
);
-- synopsys translate off
Mult_8_f_a_real <= sIEEE_2_real(datain_a_08);
Mult_8_f_b_real <= sIEEE_2_real(datain_b_08);
Mult_8_f_q_real <= sInternalSM_2_real(Mult_8_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_4_f(FLOATADDSUB,276)@3
SumOfElements_0_0_add_0_4_f_reset <= areset;
SumOfElements_0_0_add_0_4_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_4_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_4_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_4_f_reset,
dataa => Mult_8_f_q,
datab => Mult_9_f_q,
result => SumOfElements_0_0_add_0_4_f_q
);
SumOfElements_0_0_add_0_4_f_p <= not SumOfElements_0_0_add_0_4_f_q(41 downto 41);
SumOfElements_0_0_add_0_4_f_n <= SumOfElements_0_0_add_0_4_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_4_f_a_real <= sInternalSM_2_real(Mult_8_f_q);
SumOfElements_0_0_add_0_4_f_b_real <= sInternalSM_2_real(Mult_9_f_q);
SumOfElements_0_0_add_0_4_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_4_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_2_f(FLOATADDSUB,336)@8
SumOfElements_0_0_add_1_2_f_reset <= areset;
SumOfElements_0_0_add_1_2_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_2_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_2_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_2_f_reset,
dataa => SumOfElements_0_0_add_0_4_f_q,
datab => SumOfElements_0_0_add_0_5_f_q,
result => SumOfElements_0_0_add_1_2_f_q
);
SumOfElements_0_0_add_1_2_f_p <= not SumOfElements_0_0_add_1_2_f_q(41 downto 41);
SumOfElements_0_0_add_1_2_f_n <= SumOfElements_0_0_add_1_2_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_2_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_4_f_q);
SumOfElements_0_0_add_1_2_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_5_f_q);
SumOfElements_0_0_add_1_2_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_2_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_1_f(FLOATADDSUB,366)@13
SumOfElements_0_0_add_2_1_f_reset <= areset;
SumOfElements_0_0_add_2_1_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_1_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_1_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_1_f_reset,
dataa => SumOfElements_0_0_add_1_2_f_q,
datab => SumOfElements_0_0_add_1_3_f_q,
result => SumOfElements_0_0_add_2_1_f_q
);
SumOfElements_0_0_add_2_1_f_p <= not SumOfElements_0_0_add_2_1_f_q(41 downto 41);
SumOfElements_0_0_add_2_1_f_n <= SumOfElements_0_0_add_2_1_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_1_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_2_f_q);
SumOfElements_0_0_add_2_1_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_3_f_q);
SumOfElements_0_0_add_2_1_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_1_f_q);
-- synopsys translate on
--Mult_7_f(FLOATMULT,209)@0
Mult_7_f_reset <= areset;
Mult_7_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_7_f_reset,
dataa => datain_a_07,
datab => datain_b_07,
result => Mult_7_f_q
);
-- synopsys translate off
Mult_7_f_a_real <= sIEEE_2_real(datain_a_07);
Mult_7_f_b_real <= sIEEE_2_real(datain_b_07);
Mult_7_f_q_real <= sInternalSM_2_real(Mult_7_f_q);
-- synopsys translate on
--Mult_6_f(FLOATMULT,208)@0
Mult_6_f_reset <= areset;
Mult_6_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_6_f_reset,
dataa => datain_a_06,
datab => datain_b_06,
result => Mult_6_f_q
);
-- synopsys translate off
Mult_6_f_a_real <= sIEEE_2_real(datain_a_06);
Mult_6_f_b_real <= sIEEE_2_real(datain_b_06);
Mult_6_f_q_real <= sInternalSM_2_real(Mult_6_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_3_f(FLOATADDSUB,274)@3
SumOfElements_0_0_add_0_3_f_reset <= areset;
SumOfElements_0_0_add_0_3_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_3_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_3_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_3_f_reset,
dataa => Mult_6_f_q,
datab => Mult_7_f_q,
result => SumOfElements_0_0_add_0_3_f_q
);
SumOfElements_0_0_add_0_3_f_p <= not SumOfElements_0_0_add_0_3_f_q(41 downto 41);
SumOfElements_0_0_add_0_3_f_n <= SumOfElements_0_0_add_0_3_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_3_f_a_real <= sInternalSM_2_real(Mult_6_f_q);
SumOfElements_0_0_add_0_3_f_b_real <= sInternalSM_2_real(Mult_7_f_q);
SumOfElements_0_0_add_0_3_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_3_f_q);
-- synopsys translate on
--Mult_5_f(FLOATMULT,207)@0
Mult_5_f_reset <= areset;
Mult_5_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_5_f_reset,
dataa => datain_a_05,
datab => datain_b_05,
result => Mult_5_f_q
);
-- synopsys translate off
Mult_5_f_a_real <= sIEEE_2_real(datain_a_05);
Mult_5_f_b_real <= sIEEE_2_real(datain_b_05);
Mult_5_f_q_real <= sInternalSM_2_real(Mult_5_f_q);
-- synopsys translate on
--Mult_4_f(FLOATMULT,206)@0
Mult_4_f_reset <= areset;
Mult_4_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_4_f_reset,
dataa => datain_a_04,
datab => datain_b_04,
result => Mult_4_f_q
);
-- synopsys translate off
Mult_4_f_a_real <= sIEEE_2_real(datain_a_04);
Mult_4_f_b_real <= sIEEE_2_real(datain_b_04);
Mult_4_f_q_real <= sInternalSM_2_real(Mult_4_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_2_f(FLOATADDSUB,272)@3
SumOfElements_0_0_add_0_2_f_reset <= areset;
SumOfElements_0_0_add_0_2_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_2_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_2_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_2_f_reset,
dataa => Mult_4_f_q,
datab => Mult_5_f_q,
result => SumOfElements_0_0_add_0_2_f_q
);
SumOfElements_0_0_add_0_2_f_p <= not SumOfElements_0_0_add_0_2_f_q(41 downto 41);
SumOfElements_0_0_add_0_2_f_n <= SumOfElements_0_0_add_0_2_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_2_f_a_real <= sInternalSM_2_real(Mult_4_f_q);
SumOfElements_0_0_add_0_2_f_b_real <= sInternalSM_2_real(Mult_5_f_q);
SumOfElements_0_0_add_0_2_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_2_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_1_f(FLOATADDSUB,334)@8
SumOfElements_0_0_add_1_1_f_reset <= areset;
SumOfElements_0_0_add_1_1_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_1_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_1_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_1_f_reset,
dataa => SumOfElements_0_0_add_0_2_f_q,
datab => SumOfElements_0_0_add_0_3_f_q,
result => SumOfElements_0_0_add_1_1_f_q
);
SumOfElements_0_0_add_1_1_f_p <= not SumOfElements_0_0_add_1_1_f_q(41 downto 41);
SumOfElements_0_0_add_1_1_f_n <= SumOfElements_0_0_add_1_1_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_1_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_2_f_q);
SumOfElements_0_0_add_1_1_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_3_f_q);
SumOfElements_0_0_add_1_1_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_1_f_q);
-- synopsys translate on
--Mult_3_f(FLOATMULT,205)@0
Mult_3_f_reset <= areset;
Mult_3_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_3_f_reset,
dataa => datain_a_03,
datab => datain_b_03,
result => Mult_3_f_q
);
-- synopsys translate off
Mult_3_f_a_real <= sIEEE_2_real(datain_a_03);
Mult_3_f_b_real <= sIEEE_2_real(datain_b_03);
Mult_3_f_q_real <= sInternalSM_2_real(Mult_3_f_q);
-- synopsys translate on
--Mult_2_f(FLOATMULT,204)@0
Mult_2_f_reset <= areset;
Mult_2_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_2_f_reset,
dataa => datain_a_02,
datab => datain_b_02,
result => Mult_2_f_q
);
-- synopsys translate off
Mult_2_f_a_real <= sIEEE_2_real(datain_a_02);
Mult_2_f_b_real <= sIEEE_2_real(datain_b_02);
Mult_2_f_q_real <= sInternalSM_2_real(Mult_2_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_1_f(FLOATADDSUB,270)@3
SumOfElements_0_0_add_0_1_f_reset <= areset;
SumOfElements_0_0_add_0_1_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_1_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_1_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_1_f_reset,
dataa => Mult_2_f_q,
datab => Mult_3_f_q,
result => SumOfElements_0_0_add_0_1_f_q
);
SumOfElements_0_0_add_0_1_f_p <= not SumOfElements_0_0_add_0_1_f_q(41 downto 41);
SumOfElements_0_0_add_0_1_f_n <= SumOfElements_0_0_add_0_1_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_1_f_a_real <= sInternalSM_2_real(Mult_2_f_q);
SumOfElements_0_0_add_0_1_f_b_real <= sInternalSM_2_real(Mult_3_f_q);
SumOfElements_0_0_add_0_1_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_1_f_q);
-- synopsys translate on
--Mult_1_f(FLOATMULT,203)@0
Mult_1_f_reset <= areset;
Mult_1_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_1_f_reset,
dataa => datain_a_01,
datab => datain_b_01,
result => Mult_1_f_q
);
-- synopsys translate off
Mult_1_f_a_real <= sIEEE_2_real(datain_a_01);
Mult_1_f_b_real <= sIEEE_2_real(datain_b_01);
Mult_1_f_q_real <= sInternalSM_2_real(Mult_1_f_q);
-- synopsys translate on
--Mult_0_f(FLOATMULT,202)@0
Mult_0_f_reset <= areset;
Mult_0_f_inst : fp_mult_sIEEE_2_sInternalSM
GENERIC MAP ( m_family => "Stratix V", m_dotopt => 2)
PORT MAP (
clk_en => '1',
clock => clk,
reset => Mult_0_f_reset,
dataa => datain_a_00,
datab => datain_b_00,
result => Mult_0_f_q
);
-- synopsys translate off
Mult_0_f_a_real <= sIEEE_2_real(datain_a_00);
Mult_0_f_b_real <= sIEEE_2_real(datain_b_00);
Mult_0_f_q_real <= sInternalSM_2_real(Mult_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_0_0_f(FLOATADDSUB,268)@3
SumOfElements_0_0_add_0_0_f_reset <= areset;
SumOfElements_0_0_add_0_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_0_0_f_inst : fp_addsub_sInternalSM_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_0_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_0_0_f_reset,
dataa => Mult_0_f_q,
datab => Mult_1_f_q,
result => SumOfElements_0_0_add_0_0_f_q
);
SumOfElements_0_0_add_0_0_f_p <= not SumOfElements_0_0_add_0_0_f_q(41 downto 41);
SumOfElements_0_0_add_0_0_f_n <= SumOfElements_0_0_add_0_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_0_0_f_a_real <= sInternalSM_2_real(Mult_0_f_q);
SumOfElements_0_0_add_0_0_f_b_real <= sInternalSM_2_real(Mult_1_f_q);
SumOfElements_0_0_add_0_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_0_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_1_0_f(FLOATADDSUB,332)@8
SumOfElements_0_0_add_1_0_f_reset <= areset;
SumOfElements_0_0_add_1_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_1_0_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_1_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_1_0_f_reset,
dataa => SumOfElements_0_0_add_0_0_f_q,
datab => SumOfElements_0_0_add_0_1_f_q,
result => SumOfElements_0_0_add_1_0_f_q
);
SumOfElements_0_0_add_1_0_f_p <= not SumOfElements_0_0_add_1_0_f_q(41 downto 41);
SumOfElements_0_0_add_1_0_f_n <= SumOfElements_0_0_add_1_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_1_0_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_0_0_f_q);
SumOfElements_0_0_add_1_0_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_0_1_f_q);
SumOfElements_0_0_add_1_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_1_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_2_0_f(FLOATADDSUB,364)@13
SumOfElements_0_0_add_2_0_f_reset <= areset;
SumOfElements_0_0_add_2_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_2_0_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_2_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_2_0_f_reset,
dataa => SumOfElements_0_0_add_1_0_f_q,
datab => SumOfElements_0_0_add_1_1_f_q,
result => SumOfElements_0_0_add_2_0_f_q
);
SumOfElements_0_0_add_2_0_f_p <= not SumOfElements_0_0_add_2_0_f_q(41 downto 41);
SumOfElements_0_0_add_2_0_f_n <= SumOfElements_0_0_add_2_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_2_0_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_1_0_f_q);
SumOfElements_0_0_add_2_0_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_1_1_f_q);
SumOfElements_0_0_add_2_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_2_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_0_f(FLOATADDSUB,380)@18
SumOfElements_0_0_add_3_0_f_reset <= areset;
SumOfElements_0_0_add_3_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_3_0_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_3_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_0_f_reset,
dataa => SumOfElements_0_0_add_2_0_f_q,
datab => SumOfElements_0_0_add_2_1_f_q,
result => SumOfElements_0_0_add_3_0_f_q
);
SumOfElements_0_0_add_3_0_f_p <= not SumOfElements_0_0_add_3_0_f_q(41 downto 41);
SumOfElements_0_0_add_3_0_f_n <= SumOfElements_0_0_add_3_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_3_0_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_2_0_f_q);
SumOfElements_0_0_add_3_0_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_2_1_f_q);
SumOfElements_0_0_add_3_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0((null),394)@23
SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_reset <= areset;
SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_inst : fp_norm_sInternal_2_sInternal
PORT MAP (
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_reset,
dataa => SumOfElements_0_0_add_3_0_f_q,
result => SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q
);
-- synopsys translate off
SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q_real <= sInternal_2_real(SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q);
-- synopsys translate on
--SumOfElements_0_0_add_4_0_f(FLOATADDSUB,388)@28
SumOfElements_0_0_add_4_0_f_reset <= areset;
SumOfElements_0_0_add_4_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_4_0_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_4_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_4_0_f_reset,
dataa => SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q,
datab => SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q,
result => SumOfElements_0_0_add_4_0_f_q
);
SumOfElements_0_0_add_4_0_f_p <= not SumOfElements_0_0_add_4_0_f_q(41 downto 41);
SumOfElements_0_0_add_4_0_f_n <= SumOfElements_0_0_add_4_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_4_0_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_3_0_f_0_norm_SumOfElements_0_0_add_4_0_f_0_q);
SumOfElements_0_0_add_4_0_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_3_1_f_0_norm_SumOfElements_0_0_add_4_0_f_1_q);
SumOfElements_0_0_add_4_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_4_0_f_q);
-- synopsys translate on
--SumOfElements_0_0_add_5_0_f(FLOATADDSUB,392)@33
SumOfElements_0_0_add_5_0_f_reset <= areset;
SumOfElements_0_0_add_5_0_f_add_sub <= not VCC_q;
SumOfElements_0_0_add_5_0_f_inst : fp_addsub_sInternal_2_sInternal
GENERIC MAP (
addsub_resetval => '0'
) PORT MAP (
add_sub => SumOfElements_0_0_add_5_0_f_add_sub,
clk_en => '1',
clock => clk,
reset => SumOfElements_0_0_add_5_0_f_reset,
dataa => SumOfElements_0_0_add_4_0_f_q,
datab => SumOfElements_0_0_add_4_1_f_q,
result => SumOfElements_0_0_add_5_0_f_q
);
SumOfElements_0_0_add_5_0_f_p <= not SumOfElements_0_0_add_5_0_f_q(41 downto 41);
SumOfElements_0_0_add_5_0_f_n <= SumOfElements_0_0_add_5_0_f_q(41 downto 41);
-- synopsys translate off
SumOfElements_0_0_add_5_0_f_a_real <= sInternal_2_real(SumOfElements_0_0_add_4_0_f_q);
SumOfElements_0_0_add_5_0_f_b_real <= sInternal_2_real(SumOfElements_0_0_add_4_1_f_q);
SumOfElements_0_0_add_5_0_f_q_real <= sInternal_2_real(SumOfElements_0_0_add_5_0_f_q);
-- synopsys translate on
--ChannelOut_2_cast(FLOATCAST,266)@38
ChannelOut_2_cast_reset <= areset;
ChannelOut_2_cast_a <= SumOfElements_0_0_add_5_0_f_q;
ChannelOut_2_cast_inst : cast_sInternal_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => ChannelOut_2_cast_reset,
dataa => ChannelOut_2_cast_a,
result => ChannelOut_2_cast_q
);
-- synopsys translate off
ChannelOut_2_cast_q_real <= sIEEE_2_real(ChannelOut_2_cast_q);
-- synopsys translate on
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable(LOGICAL,667)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_a <= VCC_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_q <= not ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_a;
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor(LOGICAL,668)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_a <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_notEnable_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_b <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_q <= not (ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_a or ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_b);
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_mem_top(CONSTANT,664)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_mem_top_q <= "0101011";
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp(LOGICAL,665)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_a <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_mem_top_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_b <= STD_LOGIC_VECTOR("0" & ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q);
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_q <= "1" when ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_a = ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_b else "0";
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg(REG,666)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmp_q;
END IF;
END PROCESS;
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena(REG,669)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_ChannelIn_valid_s_to_ChannelOut_vout_s_nor_q = "1") THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd(LOGICAL,670)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_a <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_sticky_ena_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_b <= VCC_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_a and ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_b;
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt(COUNTER,660)
-- every=1, low=0, high=43, step=1, init=1
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i = 42 THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_eq <= '1';
ELSE
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_eq <= '0';
END IF;
IF (ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_eq = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i - 43;
ELSE
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_i,6));
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg(REG,661)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux(MUX,662)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_s <= VCC_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux: PROCESS (ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_s, ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q, ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_q)
BEGIN
CASE ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_s IS
WHEN "0" => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q;
WHEN "1" => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdcnt_q;
WHEN OTHERS => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem(DUALMEM,671)
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_reset0 <= areset;
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ia <= channel_s;
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_aa <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q;
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ab <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q;
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 44,
width_b => 8,
widthad_b => 6,
numwords_b => 44,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_reset0,
clock1 => clk,
address_b => ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_iq,
address_a => ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_aa,
data_a => ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_ia
);
ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_q <= ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_iq(7 downto 0);
--ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem(DUALMEM,659)
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_reset0 <= areset;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ia <= valid_s;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_aa <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdreg_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ab <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_rdmux_q;
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 44,
width_b => 1,
widthad_b => 6,
numwords_b => 44,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_reset0,
clock1 => clk,
address_b => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_iq,
address_a => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_aa,
data_a => ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_ia
);
ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_q <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_iq(0 downto 0);
--ChannelOut(PORTOUT,3)@45
vout_s <= ld_ChannelIn_valid_s_to_ChannelOut_vout_s_replace_mem_q;
cout_s <= ld_ChannelIn_channel_s_to_ChannelOut_cout_s_replace_mem_q;
dout_s <= ChannelOut_2_cast_q;
end normal;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/dp_rsft64x5pipe.vhd
|
10
|
3985
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LSFT64X6.VHD ***
--*** ***
--*** Function: Double Precision Left Shift ***
--*** (Combinatorial) ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x5pipe IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_rsft64x5pipe;
ARCHITECTURE rtl OF dp_rsft64x5pipe IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal righttwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC;
BEGIN
gra: FOR k IN 1 TO 61 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(62) <= (inbus(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(63) AND NOT(shift(2)) AND shift(1)) OR
(inbus(64) AND shift(2) AND NOT(shift(1)));
rightone(63) <= (inbus(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(64) AND NOT(shift(2)) AND shift(1));
rightone(64) <= inbus(64) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 52 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 53 TO 56 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 57 TO 60 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 61 TO 64 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
righttwoff(k) <= '0';
END LOOP;
shiftff <= '0';
ELSIF (rising_edge(sysclk)) THEN
righttwoff <= righttwo;
shiftff <= shift(5);
END IF;
END PROCESS;
grf: FOR k IN 1 TO 48 GENERATE
rightthr(k) <= (righttwoff(k) AND NOT(shiftff)) OR
(righttwoff(k+16) AND shiftff);
END GENERATE;
grg: FOR k IN 49 TO 64 GENERATE
rightthr(k) <= (righttwoff(k) AND NOT(shiftff));
END GENERATE;
outbus <= rightthr;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_castltoy.vhd
|
10
|
2035
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOY.VHD ***
--*** ***
--*** Function: Cast Long to Internal Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltoy IS
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltoy;
ARCHITECTURE rtl OF hcc_castltoy IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(77 DOWNTO 73) <= "00000";
END GENERATE;
cc(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
cc(k) <= '0';
END GENERATE;
cc(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
ccsat <= '0';
cczip <= '0';
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/CosPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/dp_exprnd.vhd
|
10
|
6808
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPRND.VHD ***
--*** ***
--*** Function: DP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_exprnd;
ARCHITECTURE rtl OF dp_exprnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
|
mit
|
boztalay/OZ-3
|
FPGA/OZ-3_System/Output_Port_MUX.vhd
|
2
|
3497
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Output_Port_MUX
--Module Description:
-- This module holds four 32-bit latches,
-- one for each extended output port, and the multiplexer that handles
-- sending data to the correct latch. This is tied to output pins 15
-- and 14, which select which one of the four latches get the output of the OZ-3.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Output_Port_MUX is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output0 : out STD_LOGIC_VECTOR (31 downto 0);
output1 : out STD_LOGIC_VECTOR (31 downto 0);
output2 : out STD_LOGIC_VECTOR (31 downto 0);
output3 : out STD_LOGIC_VECTOR (31 downto 0));
end Output_Port_MUX;
architecture Behavioral of Output_Port_MUX is
--//Signals\\--
signal reg0 : STD_LOGIC_VECTOR(31 downto 0);
signal reg1 : STD_LOGIC_VECTOR(31 downto 0);
signal reg2 : STD_LOGIC_VECTOR(31 downto 0);
signal reg3 : STD_LOGIC_VECTOR(31 downto 0);
signal enable0 : STD_LOGIC;
signal enable1 : STD_LOGIC;
signal enable2 : STD_LOGIC;
signal enable3 : STD_LOGIC;
--\\Signals//--
--//Components\\--
component GenRegFalling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
begin
main : process (sel, data)
begin
reg0 <= (others => '0');
reg1 <= (others => '0');
reg2 <= (others => '0');
reg3 <= (others => '0');
case sel is
when "00" =>
reg0 <= data;
when "01" =>
reg1 <= data;
when "10" =>
reg2 <= data;
when "11" =>
reg3 <= data;
when others =>
reg0 <= (others => '0');
end case;
end process;
reg_0 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable0,
reset => reset,
data => reg0,
output => output0);
reg_1 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable1,
reset => reset,
data => reg1,
output => output1);
reg_2 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable2,
reset => reset,
data => reg2,
output => output2);
reg_3 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable3,
reset => reset,
data => reg3,
output => output3);
enable0 <= ((not sel(0)) and (not sel(1))) and enable;
enable1 <= (sel(0) and (not sel(1))) and enable;
enable2 <= ((not sel(0)) and sel(1)) and enable;
enable3 <= (sel(0) and sel(1)) and enable;
end Behavioral;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_mul54us_38s.vhd
|
10
|
3962
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY fp_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_38s;
ARCHITECTURE rtl OF fp_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone + (zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 19));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_cos_s5.vhd
|
10
|
397588
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/FPSinCosXDPS4f375_safe_path.vhd
|
10
|
427
|
-- safe_path for FPSinCosXDPS4f375 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE FPSinCosXDPS4f375_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END FPSinCosXDPS4f375_safe_path;
PACKAGE body FPSinCosXDPS4f375_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END FPSinCosXDPS4f375_safe_path;
|
mit
|
LorhanSohaky/UFSCar
|
2017/lab_cd/aula9/circuitoAdicional/simulation/modelsim/rtl_work/circuito@adicional/_primary.vhd
|
1
|
339
|
library verilog;
use verilog.vl_types.all;
entity circuitoAdicional is
port(
KEY : in vl_logic_vector(0 downto 0);
LEDG : out vl_logic_vector(0 downto 0);
LEDR : out vl_logic_vector(0 downto 0);
CLK : in vl_logic
);
end circuitoAdicional;
|
mit
|
LorhanSohaky/UFSCar
|
2018/lab-arq1/aula_03-26/Lorhan740951/work/tcounter/_primary.vhd
|
2
|
76
|
library verilog;
use verilog.vl_types.all;
entity tcounter is
end tcounter;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_lsft78.vhd
|
10
|
3733
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT78.VHD ***
--*** ***
--*** Function: 78 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft78 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
END fp_lsft78;
ARCHITECTURE rtl of fp_lsft78 IS
signal levzip, levone, levtwo : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levthr, levfor, levfiv : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levsix : STD_LOGIC_VECTOR (78 DOWNTO 1);
BEGIN
levzip <= inbus;
levone(1) <= levzip(1) AND NOT(shift(1));
gaa: FOR k IN 2 TO 78 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(1))) OR (levzip(k-1) AND shift(1));
END GENERATE;
levtwo(1) <= levone(1) AND NOT(shift(2));
levtwo(2) <= levone(2) AND NOT(shift(2));
gba: FOR k IN 3 TO 78 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(2))) OR (levone(k-2) AND shift(2));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= levtwo(k) AND NOT(shift(3));
END GENERATE;
gcb: FOR k IN 5 TO 78 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(3))) OR (levtwo(k-4) AND shift(3));
END GENERATE;
gda: FOR k IN 1 TO 8 GENERATE
levfor(k) <= levthr(k) AND NOT(shift(4));
END GENERATE;
gdb: FOR k IN 9 TO 78 GENERATE
levfor(k) <= (levthr(k) AND NOT(shift(4))) OR (levthr(k-8) AND shift(4));
END GENERATE;
gea: FOR k IN 1 TO 16 GENERATE
levfiv(k) <= levfor(k) AND NOT(shift(5));
END GENERATE;
geb: FOR k IN 17 TO 78 GENERATE
levfiv(k) <= (levfor(k) AND NOT(shift(5))) OR (levfor(k-16) AND shift(5));
END GENERATE;
gfa: FOR k IN 1 TO 32 GENERATE
levsix(k) <= levfiv(k) AND NOT(shift(6));
END GENERATE;
gfb: FOR k IN 33 TO 78 GENERATE
levsix(k) <= (levfiv(k) AND NOT(shift(6))) OR (levfiv(k-32) AND shift(6));
END GENERATE;
outbus <= levsix;
END;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_castdtoy.vhd
|
10
|
9123
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- double <=> internal double
ENTITY hcc_castdtoy IS
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtoy;
ARCHITECTURE rtl OF hcc_castdtoy IS
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (53+11*target DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal fracnode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentff : exponentfftype;
signal satdelff, zipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- ieee754: sign (64), 8 exponent (63:53), 52 mantissa (52:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(13:1)
-- multiplier, divider : (SIGN)('1')(52:1), exponent(13:1)
-- (multiplier & divider use unsigned numbers, sign packed with input)
gza: IF (roundconvert = 1) GENERATE
gzb: FOR k IN 1 TO 53+11*target GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
-- if exponent = 1023 => saturate, if 0 => 0
satnode <= aaff(63) AND aaff(62) AND aaff(61) AND aaff(60) AND
aaff(59) AND aaff(58) AND aaff(57) AND aaff(56) AND
aaff(55) AND aaff(54) AND aaff(53);
zipnode <= NOT(aaff(63) OR aaff(62) OR aaff(61) OR aaff(60) OR
aaff(59) OR aaff(58) OR aaff(57) OR aaff(56) OR
aaff(55) OR aaff(54) OR aaff(53));
gexpa: FOR k IN 1 TO 11 GENERATE
expnode(k) <= (aaff(k+52) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(12) <= satnode;
expnode(13) <= '0';
--**************************************
--*** direct to multipier or divider ***
--**************************************
gmda: IF (target = 0) GENERATE
-- already in "01"&mantissa format used by multiplier and divider
--fracnode <= aaff(64) & '1' & aaff(52 DOWNTO 1);
-- 13/07/09
fracnode(54) <= aaff(64);
fracnode(53) <= NOT(zipnode);
fracnode(52 DOWNTO 1) <= aaff(52 DOWNTO 1);
gmdb: IF (outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gmdc: IF (outputpipe = 1) GENERATE
pmda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 67 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fracnode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
END GENERATE;
--***********************
--*** internal format ***
--***********************
gxa: IF (target = 1) GENERATE
fracnode(64) <= aaff(64);
fracnode(63) <= aaff(64);
fracnode(62) <= aaff(64);
fracnode(61) <= aaff(64);
fracnode(60) <= aaff(64);
--fracnode(59) <= NOT(aaff(64)); -- '1' XOR sign
-- 13/07/09
fracnode(59) <= aaff(64) XOR NOT(zipnode);
gfa: FOR k IN 1 TO 52 GENERATE
fracnode(k+6)<= (aaff(k) XOR aaff(64));
END GENERATE;
gfb: FOR k IN 1 TO 6 GENERATE
fracnode(k)<= aaff(64); -- '0' XOR sign
END GENERATE;
--*** OUTPUT STAGE(S) ***
gsa: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
cc <= fracnode & expnode;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
gsb: IF (outputpipe = 1 AND
((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0))) GENERATE
gsc: IF (roundconvert = 0) GENERATE
mantissanode <= fracnode;
END GENERATE;
gsd: IF (roundconvert = 1) GENERATE
mantissanode <= fracnode + (zerovec(63 DOWNTO 1) & aaff(64));
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= mantissanode & expnode;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gse: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsf: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracnode,bb=>zerovec(64 DOWNTO 1),carryin=>aaff(64),
cc=>mantissanode);
END GENERATE;
prcb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
exponentff(1)(k) <= '0';
exponentff(2)(k) <= '0';
END LOOP;
satdelff <= "00";
zipdelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentff(1)(13 DOWNTO 1) <= expnode;
exponentff(2)(13 DOWNTO 1) <= exponentff(1)(13 DOWNTO 1);
satdelff(1) <= satnode;
satdelff(2) <= satdelff(1);
zipdelff(1) <= zipnode;
zipdelff(2) <= zipdelff(1);
END IF;
END IF;
END PROCESS;
cc <= mantissanode & exponentff(2)(13 DOWNTO 1);
ccsat <= satdelff(2);
cczip <= zipdelff(2);
END GENERATE;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_lnlut8.vhd
|
10
|
50006
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlut8 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlut8;
ARCHITECTURE rtl OF fp_lnlut8 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
inv <= conv_std_logic_vector(1024,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "00000001" =>
inv <= conv_std_logic_vector(2041,11);
logman <= conv_std_logic_vector(6316601,23);
logexp <= conv_std_logic_vector(118,8);
WHEN "00000010" =>
inv <= conv_std_logic_vector(2033,11);
logman <= conv_std_logic_vector(7397915,23);
logexp <= conv_std_logic_vector(119,8);
WHEN "00000011" =>
inv <= conv_std_logic_vector(2025,11);
logman <= conv_std_logic_vector(3738239,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000100" =>
inv <= conv_std_logic_vector(2017,11);
logman <= conv_std_logic_vector(7988584,23);
logexp <= conv_std_logic_vector(120,8);
WHEN "00000101" =>
inv <= conv_std_logic_vector(2009,11);
logman <= conv_std_logic_vector(1933606,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000110" =>
inv <= conv_std_logic_vector(2002,11);
logman <= conv_std_logic_vector(3807503,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00000111" =>
inv <= conv_std_logic_vector(1994,11);
logman <= conv_std_logic_vector(5957139,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001000" =>
inv <= conv_std_logic_vector(1986,11);
logman <= conv_std_logic_vector(8115417,23);
logexp <= conv_std_logic_vector(121,8);
WHEN "00001001" =>
inv <= conv_std_logic_vector(1979,11);
logman <= conv_std_logic_vector(811223,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001010" =>
inv <= conv_std_logic_vector(1972,11);
logman <= conv_std_logic_vector(1762400,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001011" =>
inv <= conv_std_logic_vector(1964,11);
logman <= conv_std_logic_vector(2853602,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001100" =>
inv <= conv_std_logic_vector(1957,11);
logman <= conv_std_logic_vector(3812057,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001101" =>
inv <= conv_std_logic_vector(1950,11);
logman <= conv_std_logic_vector(4773946,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001110" =>
inv <= conv_std_logic_vector(1942,11);
logman <= conv_std_logic_vector(5877485,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00001111" =>
inv <= conv_std_logic_vector(1935,11);
logman <= conv_std_logic_vector(6846817,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010000" =>
inv <= conv_std_logic_vector(1928,11);
logman <= conv_std_logic_vector(7819662,23);
logexp <= conv_std_logic_vector(122,8);
WHEN "00010001" =>
inv <= conv_std_logic_vector(1921,11);
logman <= conv_std_logic_vector(203719,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010010" =>
inv <= conv_std_logic_vector(1914,11);
logman <= conv_std_logic_vector(693693,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010011" =>
inv <= conv_std_logic_vector(1907,11);
logman <= conv_std_logic_vector(1185462,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010100" =>
inv <= conv_std_logic_vector(1900,11);
logman <= conv_std_logic_vector(1679040,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010101" =>
inv <= conv_std_logic_vector(1893,11);
logman <= conv_std_logic_vector(2174439,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010110" =>
inv <= conv_std_logic_vector(1886,11);
logman <= conv_std_logic_vector(2671674,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00010111" =>
inv <= conv_std_logic_vector(1880,11);
logman <= conv_std_logic_vector(3099346,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011000" =>
inv <= conv_std_logic_vector(1873,11);
logman <= conv_std_logic_vector(3600026,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011001" =>
inv <= conv_std_logic_vector(1866,11);
logman <= conv_std_logic_vector(4102580,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011010" =>
inv <= conv_std_logic_vector(1860,11);
logman <= conv_std_logic_vector(4534844,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011011" =>
inv <= conv_std_logic_vector(1853,11);
logman <= conv_std_logic_vector(5040917,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011100" =>
inv <= conv_std_logic_vector(1847,11);
logman <= conv_std_logic_vector(5476218,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011101" =>
inv <= conv_std_logic_vector(1840,11);
logman <= conv_std_logic_vector(5985860,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011110" =>
inv <= conv_std_logic_vector(1834,11);
logman <= conv_std_logic_vector(6424242,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00011111" =>
inv <= conv_std_logic_vector(1827,11);
logman <= conv_std_logic_vector(6937504,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100000" =>
inv <= conv_std_logic_vector(1821,11);
logman <= conv_std_logic_vector(7379010,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100001" =>
inv <= conv_std_logic_vector(1815,11);
logman <= conv_std_logic_vector(7821973,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100010" =>
inv <= conv_std_logic_vector(1808,11);
logman <= conv_std_logic_vector(8340618,23);
logexp <= conv_std_logic_vector(123,8);
WHEN "00100011" =>
inv <= conv_std_logic_vector(1802,11);
logman <= conv_std_logic_vector(199082,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100100" =>
inv <= conv_std_logic_vector(1796,11);
logman <= conv_std_logic_vector(422902,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100101" =>
inv <= conv_std_logic_vector(1790,11);
logman <= conv_std_logic_vector(647472,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100110" =>
inv <= conv_std_logic_vector(1784,11);
logman <= conv_std_logic_vector(872796,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00100111" =>
inv <= conv_std_logic_vector(1778,11);
logman <= conv_std_logic_vector(1098879,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101000" =>
inv <= conv_std_logic_vector(1772,11);
logman <= conv_std_logic_vector(1325726,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101001" =>
inv <= conv_std_logic_vector(1766,11);
logman <= conv_std_logic_vector(1553342,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101010" =>
inv <= conv_std_logic_vector(1760,11);
logman <= conv_std_logic_vector(1781734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101011" =>
inv <= conv_std_logic_vector(1754,11);
logman <= conv_std_logic_vector(2010905,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101100" =>
inv <= conv_std_logic_vector(1748,11);
logman <= conv_std_logic_vector(2240861,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101101" =>
inv <= conv_std_logic_vector(1742,11);
logman <= conv_std_logic_vector(2471608,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101110" =>
inv <= conv_std_logic_vector(1737,11);
logman <= conv_std_logic_vector(2664505,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00101111" =>
inv <= conv_std_logic_vector(1731,11);
logman <= conv_std_logic_vector(2896716,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110000" =>
inv <= conv_std_logic_vector(1725,11);
logman <= conv_std_logic_vector(3129733,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110001" =>
inv <= conv_std_logic_vector(1719,11);
logman <= conv_std_logic_vector(3363562,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110010" =>
inv <= conv_std_logic_vector(1714,11);
logman <= conv_std_logic_vector(3559044,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110011" =>
inv <= conv_std_logic_vector(1708,11);
logman <= conv_std_logic_vector(3794376,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110100" =>
inv <= conv_std_logic_vector(1703,11);
logman <= conv_std_logic_vector(3991119,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110101" =>
inv <= conv_std_logic_vector(1697,11);
logman <= conv_std_logic_vector(4227974,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110110" =>
inv <= conv_std_logic_vector(1692,11);
logman <= conv_std_logic_vector(4425994,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00110111" =>
inv <= conv_std_logic_vector(1686,11);
logman <= conv_std_logic_vector(4664391,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111000" =>
inv <= conv_std_logic_vector(1681,11);
logman <= conv_std_logic_vector(4863705,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111001" =>
inv <= conv_std_logic_vector(1676,11);
logman <= conv_std_logic_vector(5063612,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111010" =>
inv <= conv_std_logic_vector(1670,11);
logman <= conv_std_logic_vector(5304290,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111011" =>
inv <= conv_std_logic_vector(1665,11);
logman <= conv_std_logic_vector(5505516,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111100" =>
inv <= conv_std_logic_vector(1660,11);
logman <= conv_std_logic_vector(5707347,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111101" =>
inv <= conv_std_logic_vector(1654,11);
logman <= conv_std_logic_vector(5950349,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111110" =>
inv <= conv_std_logic_vector(1649,11);
logman <= conv_std_logic_vector(6153525,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "00111111" =>
inv <= conv_std_logic_vector(1644,11);
logman <= conv_std_logic_vector(6357317,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000000" =>
inv <= conv_std_logic_vector(1639,11);
logman <= conv_std_logic_vector(6561731,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000001" =>
inv <= conv_std_logic_vector(1634,11);
logman <= conv_std_logic_vector(6766769,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000010" =>
inv <= conv_std_logic_vector(1629,11);
logman <= conv_std_logic_vector(6972435,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000011" =>
inv <= conv_std_logic_vector(1624,11);
logman <= conv_std_logic_vector(7178734,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000100" =>
inv <= conv_std_logic_vector(1619,11);
logman <= conv_std_logic_vector(7385668,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000101" =>
inv <= conv_std_logic_vector(1614,11);
logman <= conv_std_logic_vector(7593243,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000110" =>
inv <= conv_std_logic_vector(1609,11);
logman <= conv_std_logic_vector(7801462,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01000111" =>
inv <= conv_std_logic_vector(1604,11);
logman <= conv_std_logic_vector(8010329,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001000" =>
inv <= conv_std_logic_vector(1599,11);
logman <= conv_std_logic_vector(8219848,23);
logexp <= conv_std_logic_vector(124,8);
WHEN "01001001" =>
inv <= conv_std_logic_vector(1594,11);
logman <= conv_std_logic_vector(20707,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001010" =>
inv <= conv_std_logic_vector(1589,11);
logman <= conv_std_logic_vector(126125,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001011" =>
inv <= conv_std_logic_vector(1584,11);
logman <= conv_std_logic_vector(231875,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001100" =>
inv <= conv_std_logic_vector(1580,11);
logman <= conv_std_logic_vector(316716,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001101" =>
inv <= conv_std_logic_vector(1575,11);
logman <= conv_std_logic_vector(423069,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001110" =>
inv <= conv_std_logic_vector(1570,11);
logman <= conv_std_logic_vector(529760,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01001111" =>
inv <= conv_std_logic_vector(1566,11);
logman <= conv_std_logic_vector(615358,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010000" =>
inv <= conv_std_logic_vector(1561,11);
logman <= conv_std_logic_vector(722664,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010001" =>
inv <= conv_std_logic_vector(1556,11);
logman <= conv_std_logic_vector(830314,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010010" =>
inv <= conv_std_logic_vector(1552,11);
logman <= conv_std_logic_vector(916683,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010011" =>
inv <= conv_std_logic_vector(1547,11);
logman <= conv_std_logic_vector(1024958,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010100" =>
inv <= conv_std_logic_vector(1543,11);
logman <= conv_std_logic_vector(1111831,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010101" =>
inv <= conv_std_logic_vector(1538,11);
logman <= conv_std_logic_vector(1220738,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010110" =>
inv <= conv_std_logic_vector(1534,11);
logman <= conv_std_logic_vector(1308120,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01010111" =>
inv <= conv_std_logic_vector(1529,11);
logman <= conv_std_logic_vector(1417667,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011000" =>
inv <= conv_std_logic_vector(1525,11);
logman <= conv_std_logic_vector(1505564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011001" =>
inv <= conv_std_logic_vector(1520,11);
logman <= conv_std_logic_vector(1615759,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011010" =>
inv <= conv_std_logic_vector(1516,11);
logman <= conv_std_logic_vector(1704177,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011011" =>
inv <= conv_std_logic_vector(1511,11);
logman <= conv_std_logic_vector(1815027,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011100" =>
inv <= conv_std_logic_vector(1507,11);
logman <= conv_std_logic_vector(1903972,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011101" =>
inv <= conv_std_logic_vector(1503,11);
logman <= conv_std_logic_vector(1993153,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011110" =>
inv <= conv_std_logic_vector(1498,11);
logman <= conv_std_logic_vector(2104964,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01011111" =>
inv <= conv_std_logic_vector(1494,11);
logman <= conv_std_logic_vector(2194682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100000" =>
inv <= conv_std_logic_vector(1490,11);
logman <= conv_std_logic_vector(2284640,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100001" =>
inv <= conv_std_logic_vector(1486,11);
logman <= conv_std_logic_vector(2374840,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100010" =>
inv <= conv_std_logic_vector(1482,11);
logman <= conv_std_logic_vector(2465284,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100011" =>
inv <= conv_std_logic_vector(1477,11);
logman <= conv_std_logic_vector(2578682,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100100" =>
inv <= conv_std_logic_vector(1473,11);
logman <= conv_std_logic_vector(2669677,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100101" =>
inv <= conv_std_logic_vector(1469,11);
logman <= conv_std_logic_vector(2760919,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100110" =>
inv <= conv_std_logic_vector(1465,11);
logman <= conv_std_logic_vector(2852411,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01100111" =>
inv <= conv_std_logic_vector(1461,11);
logman <= conv_std_logic_vector(2944152,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101000" =>
inv <= conv_std_logic_vector(1457,11);
logman <= conv_std_logic_vector(3036145,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101001" =>
inv <= conv_std_logic_vector(1453,11);
logman <= conv_std_logic_vector(3128391,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101010" =>
inv <= conv_std_logic_vector(1449,11);
logman <= conv_std_logic_vector(3220891,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101011" =>
inv <= conv_std_logic_vector(1445,11);
logman <= conv_std_logic_vector(3313647,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101100" =>
inv <= conv_std_logic_vector(1441,11);
logman <= conv_std_logic_vector(3406660,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101101" =>
inv <= conv_std_logic_vector(1437,11);
logman <= conv_std_logic_vector(3499932,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101110" =>
inv <= conv_std_logic_vector(1433,11);
logman <= conv_std_logic_vector(3593464,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01101111" =>
inv <= conv_std_logic_vector(1429,11);
logman <= conv_std_logic_vector(3687257,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110000" =>
inv <= conv_std_logic_vector(1425,11);
logman <= conv_std_logic_vector(3781312,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110001" =>
inv <= conv_std_logic_vector(1421,11);
logman <= conv_std_logic_vector(3875633,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110010" =>
inv <= conv_std_logic_vector(1417,11);
logman <= conv_std_logic_vector(3970219,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110011" =>
inv <= conv_std_logic_vector(1414,11);
logman <= conv_std_logic_vector(4041334,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110100" =>
inv <= conv_std_logic_vector(1410,11);
logman <= conv_std_logic_vector(4136389,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110101" =>
inv <= conv_std_logic_vector(1406,11);
logman <= conv_std_logic_vector(4231714,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110110" =>
inv <= conv_std_logic_vector(1402,11);
logman <= conv_std_logic_vector(4327311,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01110111" =>
inv <= conv_std_logic_vector(1399,11);
logman <= conv_std_logic_vector(4399188,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111000" =>
inv <= conv_std_logic_vector(1395,11);
logman <= conv_std_logic_vector(4495263,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111001" =>
inv <= conv_std_logic_vector(1391,11);
logman <= conv_std_logic_vector(4591615,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111010" =>
inv <= conv_std_logic_vector(1388,11);
logman <= conv_std_logic_vector(4664061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111011" =>
inv <= conv_std_logic_vector(1384,11);
logman <= conv_std_logic_vector(4760899,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111100" =>
inv <= conv_std_logic_vector(1380,11);
logman <= conv_std_logic_vector(4858018,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111101" =>
inv <= conv_std_logic_vector(1377,11);
logman <= conv_std_logic_vector(4931041,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111110" =>
inv <= conv_std_logic_vector(1373,11);
logman <= conv_std_logic_vector(5028654,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "01111111" =>
inv <= conv_std_logic_vector(1369,11);
logman <= conv_std_logic_vector(5126552,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000000" =>
inv <= conv_std_logic_vector(1366,11);
logman <= conv_std_logic_vector(5200163,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000001" =>
inv <= conv_std_logic_vector(1362,11);
logman <= conv_std_logic_vector(5298564,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000010" =>
inv <= conv_std_logic_vector(1359,11);
logman <= conv_std_logic_vector(5372554,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000011" =>
inv <= conv_std_logic_vector(1355,11);
logman <= conv_std_logic_vector(5471461,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000100" =>
inv <= conv_std_logic_vector(1352,11);
logman <= conv_std_logic_vector(5545834,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000101" =>
inv <= conv_std_logic_vector(1348,11);
logman <= conv_std_logic_vector(5645255,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000110" =>
inv <= conv_std_logic_vector(1345,11);
logman <= conv_std_logic_vector(5720014,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10000111" =>
inv <= conv_std_logic_vector(1341,11);
logman <= conv_std_logic_vector(5819953,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001000" =>
inv <= conv_std_logic_vector(1338,11);
logman <= conv_std_logic_vector(5895103,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001001" =>
inv <= conv_std_logic_vector(1335,11);
logman <= conv_std_logic_vector(5970421,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001010" =>
inv <= conv_std_logic_vector(1331,11);
logman <= conv_std_logic_vector(6071110,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001011" =>
inv <= conv_std_logic_vector(1328,11);
logman <= conv_std_logic_vector(6146825,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001100" =>
inv <= conv_std_logic_vector(1324,11);
logman <= conv_std_logic_vector(6248045,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001101" =>
inv <= conv_std_logic_vector(1321,11);
logman <= conv_std_logic_vector(6324161,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001110" =>
inv <= conv_std_logic_vector(1318,11);
logman <= conv_std_logic_vector(6400450,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10001111" =>
inv <= conv_std_logic_vector(1315,11);
logman <= conv_std_logic_vector(6476913,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010000" =>
inv <= conv_std_logic_vector(1311,11);
logman <= conv_std_logic_vector(6579135,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010001" =>
inv <= conv_std_logic_vector(1308,11);
logman <= conv_std_logic_vector(6656007,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010010" =>
inv <= conv_std_logic_vector(1305,11);
logman <= conv_std_logic_vector(6733055,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010011" =>
inv <= conv_std_logic_vector(1301,11);
logman <= conv_std_logic_vector(6836061,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010100" =>
inv <= conv_std_logic_vector(1298,11);
logman <= conv_std_logic_vector(6913525,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010101" =>
inv <= conv_std_logic_vector(1295,11);
logman <= conv_std_logic_vector(6991167,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010110" =>
inv <= conv_std_logic_vector(1292,11);
logman <= conv_std_logic_vector(7068989,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10010111" =>
inv <= conv_std_logic_vector(1289,11);
logman <= conv_std_logic_vector(7146993,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011000" =>
inv <= conv_std_logic_vector(1286,11);
logman <= conv_std_logic_vector(7225178,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011001" =>
inv <= conv_std_logic_vector(1282,11);
logman <= conv_std_logic_vector(7329709,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011010" =>
inv <= conv_std_logic_vector(1279,11);
logman <= conv_std_logic_vector(7408321,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011011" =>
inv <= conv_std_logic_vector(1276,11);
logman <= conv_std_logic_vector(7487119,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011100" =>
inv <= conv_std_logic_vector(1273,11);
logman <= conv_std_logic_vector(7566101,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011101" =>
inv <= conv_std_logic_vector(1270,11);
logman <= conv_std_logic_vector(7645270,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011110" =>
inv <= conv_std_logic_vector(1267,11);
logman <= conv_std_logic_vector(7724626,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10011111" =>
inv <= conv_std_logic_vector(1264,11);
logman <= conv_std_logic_vector(7804171,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100000" =>
inv <= conv_std_logic_vector(1261,11);
logman <= conv_std_logic_vector(7883904,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100001" =>
inv <= conv_std_logic_vector(1258,11);
logman <= conv_std_logic_vector(7963827,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100010" =>
inv <= conv_std_logic_vector(1255,11);
logman <= conv_std_logic_vector(8043941,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100011" =>
inv <= conv_std_logic_vector(1252,11);
logman <= conv_std_logic_vector(8124247,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100100" =>
inv <= conv_std_logic_vector(1249,11);
logman <= conv_std_logic_vector(8204746,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100101" =>
inv <= conv_std_logic_vector(1246,11);
logman <= conv_std_logic_vector(8285438,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100110" =>
inv <= conv_std_logic_vector(1243,11);
logman <= conv_std_logic_vector(8366324,23);
logexp <= conv_std_logic_vector(125,8);
WHEN "10100111" =>
inv <= conv_std_logic_vector(1240,11);
logman <= conv_std_logic_vector(29399,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101000" =>
inv <= conv_std_logic_vector(1237,11);
logman <= conv_std_logic_vector(70038,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101001" =>
inv <= conv_std_logic_vector(1234,11);
logman <= conv_std_logic_vector(110776,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101010" =>
inv <= conv_std_logic_vector(1231,11);
logman <= conv_std_logic_vector(151613,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101011" =>
inv <= conv_std_logic_vector(1228,11);
logman <= conv_std_logic_vector(192550,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101100" =>
inv <= conv_std_logic_vector(1225,11);
logman <= conv_std_logic_vector(233587,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101101" =>
inv <= conv_std_logic_vector(1223,11);
logman <= conv_std_logic_vector(261001,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101110" =>
inv <= conv_std_logic_vector(1220,11);
logman <= conv_std_logic_vector(302205,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10101111" =>
inv <= conv_std_logic_vector(1217,11);
logman <= conv_std_logic_vector(343512,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110000" =>
inv <= conv_std_logic_vector(1214,11);
logman <= conv_std_logic_vector(384920,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110001" =>
inv <= conv_std_logic_vector(1211,11);
logman <= conv_std_logic_vector(426431,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110010" =>
inv <= conv_std_logic_vector(1209,11);
logman <= conv_std_logic_vector(454162,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110011" =>
inv <= conv_std_logic_vector(1206,11);
logman <= conv_std_logic_vector(495844,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110100" =>
inv <= conv_std_logic_vector(1203,11);
logman <= conv_std_logic_vector(537630,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110101" =>
inv <= conv_std_logic_vector(1200,11);
logman <= conv_std_logic_vector(579521,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110110" =>
inv <= conv_std_logic_vector(1198,11);
logman <= conv_std_logic_vector(607506,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10110111" =>
inv <= conv_std_logic_vector(1195,11);
logman <= conv_std_logic_vector(649572,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111000" =>
inv <= conv_std_logic_vector(1192,11);
logman <= conv_std_logic_vector(691744,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111001" =>
inv <= conv_std_logic_vector(1189,11);
logman <= conv_std_logic_vector(734021,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111010" =>
inv <= conv_std_logic_vector(1187,11);
logman <= conv_std_logic_vector(762266,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111011" =>
inv <= conv_std_logic_vector(1184,11);
logman <= conv_std_logic_vector(804722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111100" =>
inv <= conv_std_logic_vector(1181,11);
logman <= conv_std_logic_vector(847286,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111101" =>
inv <= conv_std_logic_vector(1179,11);
logman <= conv_std_logic_vector(875722,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111110" =>
inv <= conv_std_logic_vector(1176,11);
logman <= conv_std_logic_vector(918466,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "10111111" =>
inv <= conv_std_logic_vector(1173,11);
logman <= conv_std_logic_vector(961320,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000000" =>
inv <= conv_std_logic_vector(1171,11);
logman <= conv_std_logic_vector(989950,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000001" =>
inv <= conv_std_logic_vector(1168,11);
logman <= conv_std_logic_vector(1032987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000010" =>
inv <= conv_std_logic_vector(1166,11);
logman <= conv_std_logic_vector(1061740,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000011" =>
inv <= conv_std_logic_vector(1163,11);
logman <= conv_std_logic_vector(1104961,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000100" =>
inv <= conv_std_logic_vector(1160,11);
logman <= conv_std_logic_vector(1148295,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000101" =>
inv <= conv_std_logic_vector(1158,11);
logman <= conv_std_logic_vector(1177246,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000110" =>
inv <= conv_std_logic_vector(1155,11);
logman <= conv_std_logic_vector(1220767,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11000111" =>
inv <= conv_std_logic_vector(1153,11);
logman <= conv_std_logic_vector(1249843,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001000" =>
inv <= conv_std_logic_vector(1150,11);
logman <= conv_std_logic_vector(1293553,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001001" =>
inv <= conv_std_logic_vector(1148,11);
logman <= conv_std_logic_vector(1322756,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001010" =>
inv <= conv_std_logic_vector(1145,11);
logman <= conv_std_logic_vector(1366656,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001011" =>
inv <= conv_std_logic_vector(1143,11);
logman <= conv_std_logic_vector(1395987,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001100" =>
inv <= conv_std_logic_vector(1140,11);
logman <= conv_std_logic_vector(1440080,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001101" =>
inv <= conv_std_logic_vector(1138,11);
logman <= conv_std_logic_vector(1469539,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001110" =>
inv <= conv_std_logic_vector(1135,11);
logman <= conv_std_logic_vector(1513826,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11001111" =>
inv <= conv_std_logic_vector(1133,11);
logman <= conv_std_logic_vector(1543415,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010000" =>
inv <= conv_std_logic_vector(1130,11);
logman <= conv_std_logic_vector(1587898,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010001" =>
inv <= conv_std_logic_vector(1128,11);
logman <= conv_std_logic_vector(1617618,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010010" =>
inv <= conv_std_logic_vector(1126,11);
logman <= conv_std_logic_vector(1647391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010011" =>
inv <= conv_std_logic_vector(1123,11);
logman <= conv_std_logic_vector(1692151,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010100" =>
inv <= conv_std_logic_vector(1121,11);
logman <= conv_std_logic_vector(1722056,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010101" =>
inv <= conv_std_logic_vector(1118,11);
logman <= conv_std_logic_vector(1767016,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010110" =>
inv <= conv_std_logic_vector(1116,11);
logman <= conv_std_logic_vector(1797055,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11010111" =>
inv <= conv_std_logic_vector(1114,11);
logman <= conv_std_logic_vector(1827149,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011000" =>
inv <= conv_std_logic_vector(1111,11);
logman <= conv_std_logic_vector(1872391,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011001" =>
inv <= conv_std_logic_vector(1109,11);
logman <= conv_std_logic_vector(1902620,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011010" =>
inv <= conv_std_logic_vector(1107,11);
logman <= conv_std_logic_vector(1932904,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011011" =>
inv <= conv_std_logic_vector(1104,11);
logman <= conv_std_logic_vector(1978432,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011100" =>
inv <= conv_std_logic_vector(1102,11);
logman <= conv_std_logic_vector(2008853,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011101" =>
inv <= conv_std_logic_vector(1100,11);
logman <= conv_std_logic_vector(2039330,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011110" =>
inv <= conv_std_logic_vector(1097,11);
logman <= conv_std_logic_vector(2085148,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11011111" =>
inv <= conv_std_logic_vector(1095,11);
logman <= conv_std_logic_vector(2115764,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100000" =>
inv <= conv_std_logic_vector(1093,11);
logman <= conv_std_logic_vector(2146435,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100001" =>
inv <= conv_std_logic_vector(1090,11);
logman <= conv_std_logic_vector(2192547,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100010" =>
inv <= conv_std_logic_vector(1088,11);
logman <= conv_std_logic_vector(2223360,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100011" =>
inv <= conv_std_logic_vector(1086,11);
logman <= conv_std_logic_vector(2254228,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100100" =>
inv <= conv_std_logic_vector(1084,11);
logman <= conv_std_logic_vector(2285154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100101" =>
inv <= conv_std_logic_vector(1082,11);
logman <= conv_std_logic_vector(2316137,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100110" =>
inv <= conv_std_logic_vector(1079,11);
logman <= conv_std_logic_vector(2362719,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11100111" =>
inv <= conv_std_logic_vector(1077,11);
logman <= conv_std_logic_vector(2393845,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101000" =>
inv <= conv_std_logic_vector(1075,11);
logman <= conv_std_logic_vector(2425030,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101001" =>
inv <= conv_std_logic_vector(1073,11);
logman <= conv_std_logic_vector(2456272,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101010" =>
inv <= conv_std_logic_vector(1070,11);
logman <= conv_std_logic_vector(2503245,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101011" =>
inv <= conv_std_logic_vector(1068,11);
logman <= conv_std_logic_vector(2534634,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101100" =>
inv <= conv_std_logic_vector(1066,11);
logman <= conv_std_logic_vector(2566082,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101101" =>
inv <= conv_std_logic_vector(1064,11);
logman <= conv_std_logic_vector(2597588,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101110" =>
inv <= conv_std_logic_vector(1062,11);
logman <= conv_std_logic_vector(2629154,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11101111" =>
inv <= conv_std_logic_vector(1060,11);
logman <= conv_std_logic_vector(2660779,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110000" =>
inv <= conv_std_logic_vector(1058,11);
logman <= conv_std_logic_vector(2692464,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110001" =>
inv <= conv_std_logic_vector(1055,11);
logman <= conv_std_logic_vector(2740104,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110010" =>
inv <= conv_std_logic_vector(1053,11);
logman <= conv_std_logic_vector(2771940,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110011" =>
inv <= conv_std_logic_vector(1051,11);
logman <= conv_std_logic_vector(2803835,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110100" =>
inv <= conv_std_logic_vector(1049,11);
logman <= conv_std_logic_vector(2835792,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110101" =>
inv <= conv_std_logic_vector(1047,11);
logman <= conv_std_logic_vector(2867810,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110110" =>
inv <= conv_std_logic_vector(1045,11);
logman <= conv_std_logic_vector(2899888,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11110111" =>
inv <= conv_std_logic_vector(1043,11);
logman <= conv_std_logic_vector(2932029,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111000" =>
inv <= conv_std_logic_vector(1041,11);
logman <= conv_std_logic_vector(2964231,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111001" =>
inv <= conv_std_logic_vector(1039,11);
logman <= conv_std_logic_vector(2996495,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111010" =>
inv <= conv_std_logic_vector(1037,11);
logman <= conv_std_logic_vector(3028821,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111011" =>
inv <= conv_std_logic_vector(1035,11);
logman <= conv_std_logic_vector(3061209,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111100" =>
inv <= conv_std_logic_vector(1033,11);
logman <= conv_std_logic_vector(3093660,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111101" =>
inv <= conv_std_logic_vector(1031,11);
logman <= conv_std_logic_vector(3126174,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111110" =>
inv <= conv_std_logic_vector(1029,11);
logman <= conv_std_logic_vector(3158751,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "11111111" =>
inv <= conv_std_logic_vector(1027,11);
logman <= conv_std_logic_vector(3191392,23);
logexp <= conv_std_logic_vector(126,8);
WHEN others =>
inv <= conv_std_logic_vector(0,11);
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_atan.vhd
|
10
|
17028
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATAN.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ArcTangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
-- slight improvement when "roundbit" is used i.e. round up from
-- X.4999 - exact number of bits to be used needs to be tweaked
ENTITY fp_atan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_atan;
ARCHITECTURE rtl OF fp_atan IS
constant coredepth : positive := 12;
constant b_precision : positive := 10;
type exponentinfftype IS ARRAY (coredepth-2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type exponenttopfftype IS ARRAY (coredepth-3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type mantissabpfftype IS ARRAY (2*coredepth+10 DOWNTO 1) OF STD_LOGIC_VECTOR (23 DOWNTO 1); -- SPR: 380600
type termfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi_over_two : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delinputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topquotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topquotientnumber : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal exponentoffset : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentinff : exponentinfftype;
signal idselectff : STD_LOGIC_VECTOR (2*coredepth+10 DOWNTO 1); -- SPR: 380600
signal pathselectff : STD_LOGIC_VECTOR (2*coredepth+9 DOWNTO 1);
signal exponenttopff : exponenttopfftype;
signal forward_shiftff, inverse_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal a_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_fixedpointbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pathcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal ab_plusone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2*coredepth+11 DOWNTO 1);
signal mantissabpff : mantissabpfftype; -- SPR: 380600
signal atantermff : termfftype;
signal large_atanff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal small_mantissa, small_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal large_mantissa, large_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mux_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal small_count, small_countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal small_overflowbus, large_overflowbus : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal small_overflowff, large_overflowff : STD_LOGIC;
signal mux_overflow : STD_LOGIC;
signal roundbit : STD_LOGIC;
signal mantissa_roundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissa_bypass : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponent_outff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_exponent_adjust, large_exponent_adjust : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponent_adjust, exponent_adjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- SPR: 380600
signal expinzero : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero : STD_LOGIC;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_atanlut
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pi_over_two <= x"C90FDAA22"; -- 1.57...
--*** Invert Input ***
inputnumber <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>inputnumber,
quotient=>topquotient);
exponentoffset <= conv_std_logic_vector (127,10);
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-2 LOOP
FOR j IN 1 TO 8 LOOP
exponentinff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2*coredepth+9 LOOP
pathselectff(k) <= '0';
END LOOP;
-- SPR: 380600
FOR k IN 1 TO 2*coredepth+10 LOOP
idselectff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-3 LOOP
FOR j IN 1 TO 10 LOOP
exponenttopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 10 LOOP
forward_shiftff(k) <= '0';
inverse_shiftff(k) <= '0';
a_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
a_fixedpointff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
exponentinff(1)(8 DOWNTO 1) <= exponentin;
FOR k IN 2 TO coredepth-2 LOOP
exponentinff(k)(8 DOWNTO 1) <= exponentinff(k-1)(8 DOWNTO 1);
END LOOP;
pathselectff(1) <= pathcheck(9);
FOR k IN 2 TO 2*coredepth+9 LOOP
pathselectff(k) <= pathselectff(k-1);
END LOOP;
-- SPR: 380600
idselectff(1) <= expzero;
FOR k IN 2 TO 2*coredepth+10 LOOP
idselectff(k) <= idselectff(k-1);
END LOOP;
-- exponent for inverse, used when exponent > 126
exponenttopff(1)(10 DOWNTO 1) <= exponentoffset - ("00" & exponentinff(1)(8 DOWNTO 1));
exponenttopff(2)(10 DOWNTO 1) <= exponenttopff(1)(10 DOWNTO 1) + exponentoffset;
exponenttopff(3)(10 DOWNTO 1) <= exponenttopff(2)(10 DOWNTO 1) - 1;
-- inverse always less than 1, decrement exponent
FOR k IN 4 TO coredepth-3 LOOP
exponenttopff(k)(10 DOWNTO 1) <= exponenttopff(k-1)(10 DOWNTO 1);
END LOOP;
forward_shiftff <= "0001111111" - ("00" & exponentinff(coredepth-2)(8 DOWNTO 1));
inverse_shiftff <= "0001111111" - exponenttopff(coredepth-3)(10 DOWNTO 1);
FOR k IN 1 TO 6 LOOP
a_shiftff(k) <= (forward_shiftff(k) AND NOT(pathselectff(coredepth-2))) OR
(inverse_shiftff(k) AND pathselectff(coredepth-2));
END LOOP;
a_fixedpointff <= a_fixedpointbus;
END IF;
END IF;
END PROCESS;
-- if <=126 (<= 0.999999), use atan(x) path, else use (pi/2-atan(1/x)) path
pathcheck <= "001111110" - ('0' & exponentinff(1)(8 DOWNTO 1));
cdma: fp_del
GENERIC MAP (width=>36,pipes=>coredepth) -- 12 for inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>inputnumber,
cc=>delinputnumber);
topquotientnumber <= topquotient(35 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 36 GENERATE
a_mantissanode(k) <= (delinputnumber(k) AND NOT(pathselectff(coredepth-1))) OR
(topquotientnumber(k) AND pathselectff(coredepth-1));
END GENERATE;
casr: fp_rsft36
PORT MAP (inbus=>a_mantissanode,shift=>a_shiftff(6 DOWNTO 1),
outbus=>a_fixedpointbus);
a_fixedpoint <= a_fixedpointff;
b_fixedpoint <= a_fixedpointff(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1);
c_fixedpoint <= a_fixedpointff(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1);
cmone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,
pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>a_fixedpoint,databb=>b_fixedpoint,
result=>ab_fixedpoint);
ab_plusone <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value
invtwo: fp_inv_core
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>ab_plusone,
quotient=>denominator);
cdc: fp_del
GENERIC MAP (width=>36,pipes=>coredepth+3) -- inv_core and 3 for 36*36 mult
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>c_fixedpoint,
cc=>numerator);
cmtwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,
pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>numerator,databb=>denominator,
result=>addterm);
b_address <= a_fixedpoint(36 DOWNTO 37-b_precision);
clut: fp_atanlut
PORT MAP (add=>b_address,
data=>lutterm);
cdlut: fp_del
GENERIC MAP (width=>36,pipes=>18) -- 12 for inv_core and 3 for 36*36 mult
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>lutterm,
cc=>dellutterm);
pimo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2*coredepth+11 LOOP
signff(k) <= '0';
END LOOP;
-- SPR: 380600
FOR k IN 1 TO 2*coredepth+10 LOOP
FOR j IN 1 TO 23 LOOP
mantissabpff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 36 LOOP
atantermff(1)(k) <= '0';
atantermff(2)(k) <= '0';
large_atanff(k) <= '0';
small_mantissaff(k) <= '0';
large_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
small_countff(k) <= '0';
END LOOP;
small_overflowff <= '0';
large_overflowff <= '0';
FOR k IN 1 TO 23 LOOP
mantissa_roundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponent_outff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
mantissabpff(1)(23 DOWNTO 1) <= mantissain(23 DOWNTO 1);
FOR k IN 2 TO 2*coredepth+11 LOOP
signff(k) <= signff(k-1);
END LOOP;
-- SPR: 380600
FOR k IN 2 TO 2*coredepth+10 LOOP
mantissabpff(k)(23 DOWNTO 1) <= mantissabpff(k-1)(23 DOWNTO 1);
END LOOP;
atantermff(1)(36 DOWNTO 1) <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10));
atantermff(2)(36 DOWNTO 1) <= atantermff(1)(36 DOWNTO 1);
-- always in the range 0.78 to pi/2
large_atanff(36 DOWNTO 1) <= pi_over_two - atantermff(1)(36 DOWNTO 1);
small_countff <= small_count;
large_mantissaff <= large_mantissa;
small_mantissaff <= small_mantissa;
small_overflowff <= small_overflowbus(24);
large_overflowff <= large_overflowbus(24);
exponent_adjustff <= exponent_adjust;
--mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + mux_mantissa(12);
mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + roundbit;
exponent_outff <= "01111111" - exponent_adjustff + mux_overflow;
END IF;
END IF;
END PROCESS;
roundbit <= mux_mantissa(12) OR
(mux_mantissa(11) AND mux_mantissa(10) AND mux_mantissa(9) AND mux_mantissa(8) AND
mux_mantissa(7) AND mux_mantissa(6) AND mux_mantissa(5) AND mux_mantissa(4) AND
mux_mantissa(3) AND mux_mantissa(2));
ccsat: fp_clz36
PORT MAP (mantissa=>atantermff(1)(36 DOWNTO 1),
leading=>small_count);
cssat: fp_lsft36
PORT MAP (inbus=>atantermff(2)(36 DOWNTO 1),shift=>small_countff,
outbus=>small_mantissa);
small_overflowbus(1) <= small_mantissa(12);
gova: FOR k IN 2 TO 24 GENERATE
small_overflowbus(k) <= small_overflowbus(k-1) AND small_mantissa(k+11);
END GENERATE;
glma: FOR k IN 1 TO 35 GENERATE
large_mantissa(k+1) <= (large_atanff(k) AND NOT(large_atanff(36))) OR
(large_atanff(k+1) AND large_atanff(36));
END GENERATE;
large_mantissa(1) <= '0';
large_overflowbus(1) <= large_mantissa(12);
govb: FOR k IN 2 TO 24 GENERATE
large_overflowbus(k) <= large_overflowbus(k-1) AND large_mantissa(k+11);
END GENERATE;
gmma: FOR k IN 1 TO 36 GENERATE
mux_mantissa(k) <= (small_mantissaff(k) AND NOT(pathselectff(2*coredepth+9))) OR
(large_mantissaff(k) AND pathselectff(2*coredepth+9));
END GENERATE;
mux_overflow <= (small_overflowff AND NOT(pathselectff(2*coredepth+9))) OR
(large_overflowff AND pathselectff(2*coredepth+9));
large_exponent_adjust <= "0000000" & NOT(large_atanff(36));
small_exponent_adjust <= "00" & small_countff;
gxa: FOR k IN 1 TO 8 GENERATE
exponent_adjust(k) <= (small_exponent_adjust(k) AND NOT(pathselectff(2*coredepth+8))) OR
(large_exponent_adjust(k) AND pathselectff(2*coredepth+8));
END GENERATE;
-- SPR: 380600
bypass: FOR k IN 1 TO 23 GENERATE
mantissa_bypass(k) <= (mantissa_roundff(k) AND NOT(idselectff(2*coredepth+10))) OR
(mantissabpff(2*coredepth+10)(k) AND idselectff(2*coredepth+10));
END GENERATE;
-- SPR: 380600
expinzero(1) <= exponentinff(1)(1);
gxza: FOR k IN 2 TO 8 GENERATE
expinzero(k) <= expinzero(k-1) OR exponentinff(1)(k);
END GENERATE;
expzero <= NOT(expinzero(8)); -- '0' when zero
--*** OUTPUTS ***
signout <= signff(2*coredepth+11);
exponentout <= (others => '0') when idselectff(2*coredepth+10) = '1' else exponent_outff; -- SPR: 380600
mantissaout <= mantissa_bypass;
end rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_cordic_m1.vhd
|
10
|
13050
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_ln1p_double_s5.vhd
|
10
|
825320
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_castxtoy.vhd
|
10
|
2116
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOY.VHD ***
--*** ***
--*** Function: Cast Internal Single to ***
--*** Internal Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castxtoy;
ARCHITECTURE rtl OF hcc_castxtoy IS
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
BEGIN
-- x : 32/36 signed mantissa, 10 bit exponent
-- y : (internal) 64 signed mantissa, 13 bit exponent
exponentadjust <= conv_std_logic_vector (896,13);
cc(67+10*target DOWNTO 68+10*target-mantissa) <= aa(mantissa+10 DOWNTO 11);
gxa: FOR k IN 14 TO 67+10*target-mantissa GENERATE
cc(k) <= aa(11);
END GENERATE;
cc(13 DOWNTO 1) <= ("000" & aa(10 DOWNTO 1)) + exponentadjust;
ccsat <= aasat;
cczip <= aazip;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_pos.vhd
|
10
|
6915
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT LIBRARY ***
--*** ***
--*** FP_POS.VHD ***
--*** ***
--*** Function: Local Count Leading Zeroes ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_pos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_pos;
ARCHITECTURE rtl of fp_pos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,5);
WHEN "000001" => position <= conv_std_logic_vector(start+5,5);
WHEN "000010" => position <= conv_std_logic_vector(start+4,5);
WHEN "000011" => position <= conv_std_logic_vector(start+4,5);
WHEN "000100" => position <= conv_std_logic_vector(start+3,5);
WHEN "000101" => position <= conv_std_logic_vector(start+3,5);
WHEN "000110" => position <= conv_std_logic_vector(start+3,5);
WHEN "000111" => position <= conv_std_logic_vector(start+3,5);
WHEN "001000" => position <= conv_std_logic_vector(start+2,5);
WHEN "001001" => position <= conv_std_logic_vector(start+2,5);
WHEN "001010" => position <= conv_std_logic_vector(start+2,5);
WHEN "001011" => position <= conv_std_logic_vector(start+2,5);
WHEN "001100" => position <= conv_std_logic_vector(start+2,5);
WHEN "001101" => position <= conv_std_logic_vector(start+2,5);
WHEN "001110" => position <= conv_std_logic_vector(start+2,5);
WHEN "001111" => position <= conv_std_logic_vector(start+2,5);
WHEN "010000" => position <= conv_std_logic_vector(start+1,5);
WHEN "010001" => position <= conv_std_logic_vector(start+1,5);
WHEN "010010" => position <= conv_std_logic_vector(start+1,5);
WHEN "010011" => position <= conv_std_logic_vector(start+1,5);
WHEN "010100" => position <= conv_std_logic_vector(start+1,5);
WHEN "010101" => position <= conv_std_logic_vector(start+1,5);
WHEN "010110" => position <= conv_std_logic_vector(start+1,5);
WHEN "010111" => position <= conv_std_logic_vector(start+1,5);
WHEN "011000" => position <= conv_std_logic_vector(start+1,5);
WHEN "011001" => position <= conv_std_logic_vector(start+1,5);
WHEN "011010" => position <= conv_std_logic_vector(start+1,5);
WHEN "011011" => position <= conv_std_logic_vector(start+1,5);
WHEN "011100" => position <= conv_std_logic_vector(start+1,5);
WHEN "011101" => position <= conv_std_logic_vector(start+1,5);
WHEN "011110" => position <= conv_std_logic_vector(start+1,5);
WHEN "011111" => position <= conv_std_logic_vector(start+1,5);
WHEN "100000" => position <= conv_std_logic_vector(start,5);
WHEN "100001" => position <= conv_std_logic_vector(start,5);
WHEN "100010" => position <= conv_std_logic_vector(start,5);
WHEN "100011" => position <= conv_std_logic_vector(start,5);
WHEN "100100" => position <= conv_std_logic_vector(start,5);
WHEN "100101" => position <= conv_std_logic_vector(start,5);
WHEN "100110" => position <= conv_std_logic_vector(start,5);
WHEN "100111" => position <= conv_std_logic_vector(start,5);
WHEN "101000" => position <= conv_std_logic_vector(start,5);
WHEN "101001" => position <= conv_std_logic_vector(start,5);
WHEN "101010" => position <= conv_std_logic_vector(start,5);
WHEN "101011" => position <= conv_std_logic_vector(start,5);
WHEN "101100" => position <= conv_std_logic_vector(start,5);
WHEN "101101" => position <= conv_std_logic_vector(start,5);
WHEN "101110" => position <= conv_std_logic_vector(start,5);
WHEN "101111" => position <= conv_std_logic_vector(start,5);
WHEN "110000" => position <= conv_std_logic_vector(start,5);
WHEN "110001" => position <= conv_std_logic_vector(start,5);
WHEN "110010" => position <= conv_std_logic_vector(start,5);
WHEN "110011" => position <= conv_std_logic_vector(start,5);
WHEN "110100" => position <= conv_std_logic_vector(start,5);
WHEN "110101" => position <= conv_std_logic_vector(start,5);
WHEN "110110" => position <= conv_std_logic_vector(start,5);
WHEN "110111" => position <= conv_std_logic_vector(start,5);
WHEN "111000" => position <= conv_std_logic_vector(start,5);
WHEN "111001" => position <= conv_std_logic_vector(start,5);
WHEN "111010" => position <= conv_std_logic_vector(start,5);
WHEN "111011" => position <= conv_std_logic_vector(start,5);
WHEN "111100" => position <= conv_std_logic_vector(start,5);
WHEN "111101" => position <= conv_std_logic_vector(start,5);
WHEN "111110" => position <= conv_std_logic_vector(start,5);
WHEN "111111" => position <= conv_std_logic_vector(start,5);
WHEN others => position <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_lnnorm.vhd
|
10
|
6140
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNNORM.VHD ***
--*** ***
--*** Function: Double Precision Normalization ***
--*** of LN calculation ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 3 + 2*Speed ***
--***************************************************
ENTITY dp_lnnorm IS
GENERIC (
speed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
inexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
outman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
outexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
zero : OUT STD_LOGIC
);
END dp_lnnorm;
ARCHITECTURE rtl OF dp_lnnorm IS
-- 3+2*speed
signal shift, shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal inmanff, outmanff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal inexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal inmandelbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal outmanbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expaddbus, expsubbus : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expmidbus, expoutbus : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2+2*speed DOWNTO 1);
component dp_lnclz
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lnclzpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64x6
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsft64x6pipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
ppin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
inmanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
inexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2+2*speed LOOP
zeroff(k) <= '0';
END LOOP;
shiftff <= "000000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
inmanff <= inman;
inexpff <= inexp;
zeroff(1) <= zerochk(64);
FOR k IN 2 TO 2+2*speed LOOP
zeroff(k) <= zeroff(k-1);
END LOOP;
shiftff <= shift;
END IF;
END IF;
END PROCESS;
zerochk(1) <= inmanff(1);
gza: FOR k IN 2 TO 64 GENERATE
zerochk(k) <= zerochk(k-1) OR inmanff(k);
END GENERATE;
delma: fp_del
GENERIC MAP (width=>64,pipes=>1+speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>inmanff,cc=>inmandelbus);
gsa: IF (speed = 0) GENERATE
clz: dp_lnclz
PORT MAP (mantissa=>inmanff,leading=>shift);
sft: dp_lsft64x6
PORT MAP (inbus=>inmandelbus,shift=>shiftff,
outbus=>outmanbus);
END GENERATE;
gsb: IF (speed = 1) GENERATE
clzp: dp_lnclzpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>inmanff,
leading=>shift);
sftp: dp_lsft64x6pipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>inmandelbus,shift=>shiftff,
outbus=>outmanbus);
END GENERATE;
-- add 2 - 1 for right shift to avoid overflow
expaddbus <= inexpff + 1;
delxa: fp_del
GENERIC MAP (width=>11,pipes=>1+speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>expaddbus,cc=>expmidbus);
expsubbus <= expmidbus - ("00000" & shiftff);
delxb: fp_del
GENERIC MAP (width=>11,pipes=>1+speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>expsubbus,cc=>expoutbus);
ppout: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
outmanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
outmanff <= outmanbus;
END IF;
END IF;
END PROCESS;
--*** OUTPUTS ***
outman <= outmanff;
outexp <= expoutbus;
zero <= zeroff(2+2*speed);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_mul54us_3xs.vhd
|
10
|
2903
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_3XS.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 3XS: Stratix 3, 10 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. For QII8.0 LPM_MULT always creates a 10 ***
--*** 18x18 multiplier 54x54 core ***
--*** 2. Identical to HCC_MUL54US_3XS, but 72 ***
--*** outputs ***
--*** ***
--***************************************************
ENTITY fp_mul54us_3xs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_3xs;
ARCHITECTURE syn of fp_mul54us_3xs IS
component lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
end component;
BEGIN
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => 4,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 54,
lpm_widthb => 54,
lpm_widthp => 72
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_lsftcomb32.vhd
|
10
|
3504
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftcomb32;
ARCHITECTURE rtl OF hcc_lsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
LorhanSohaky/UFSCar
|
2017/lab_cd/aula9/maquina/simulation/modelsim/rtl_work/inicial/_primary.vhd
|
1
|
1082
|
library verilog;
use verilog.vl_types.all;
entity inicial is
generic(
\Fechado\ : vl_logic_vector(0 to 1) := (Hi0, Hi0);
Abrindo : vl_logic_vector(0 to 1) := (Hi0, Hi1);
\Aberto\ : vl_logic_vector(0 to 1) := (Hi1, Hi0);
Fechando : vl_logic_vector(0 to 1) := (Hi1, Hi1)
);
port(
botao : in vl_logic;
aberto : in vl_logic;
fechado : in vl_logic;
motor : in vl_logic;
sentido : in vl_logic;
ledVerde : out vl_logic;
ledVermelho : out vl_logic;
display : out vl_logic_vector(6 downto 0);
clock : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of \Fechado\ : constant is 1;
attribute mti_svvh_generic_type of Abrindo : constant is 1;
attribute mti_svvh_generic_type of \Aberto\ : constant is 1;
attribute mti_svvh_generic_type of Fechando : constant is 1;
end inicial;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_ln_double_s5.vhd
|
10
|
543973
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_double_s5
-- VHDL created on Mon Apr 8 15:29:06 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (10 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (53 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (53 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q_i : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(117 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (11 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (12 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (12 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (51 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid130_natLogPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid142_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid147_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal mO_uid150_countZ_uid54_fpLogETest_q : std_logic_vector (8 downto 0);
signal zs_uid155_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal zs_uid161_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid167_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal zs_uid173_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q : std_logic_vector (5 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid238_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm0_uid238_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid241_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm1_uid241_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid98_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid99_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid100_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid101_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid102_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid104_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid105_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid106_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid107_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid108_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid110_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid111_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid112_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid113_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid115_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid116_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid117_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid119_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid120_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q : std_logic_vector (53 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q : std_logic_vector (49 downto 0);
signal reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (65 downto 0);
signal reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q : std_logic_vector (51 downto 0);
signal reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q : std_logic_vector (10 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q : std_logic_vector (54 downto 0);
signal ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q : std_logic_vector (116 downto 0);
signal ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q : std_logic_vector (114 downto 0);
signal ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q : std_logic_vector (112 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (52 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (63 downto 0);
signal pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (66 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (51 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (51 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (11 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (11 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (53 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (118 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (118 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (10 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid132_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid132_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid138_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid138_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid144_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid144_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_a : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_b : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (53 downto 0);
signal leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cIncludingRoundingBit_uid131_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid137_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal cIncludingRoundingBit_uid143_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cStage_uid152_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal os_uid103_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid109_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid114_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid121_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid118_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (117 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (63 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q : std_logic_vector (134 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (41 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (41 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid134_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT3_uid134_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (52 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (51 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (63 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (10 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (51 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (9 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (5 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (10 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_b : std_logic_vector (26 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_in : std_logic_vector (118 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_b : std_logic_vector (63 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_in : std_logic_vector (54 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_b : std_logic_vector (54 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_in : std_logic_vector (86 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_b : std_logic_vector (86 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_b : std_logic_vector (22 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid133_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid133_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid139_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid139_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid145_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid145_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in : std_logic_vector (116 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b : std_logic_vector (116 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in : std_logic_vector (114 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b : std_logic_vector (114 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in : std_logic_vector (112 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b : std_logic_vector (112 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal lowRangeB_uid124_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid124_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid125_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid125_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal FullSumAB117_uid50_fpLogETest_in : std_logic_vector (117 downto 0);
signal FullSumAB117_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b : std_logic_vector (117 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_in : std_logic_vector (63 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal yT1_uid122_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT1_uid122_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid128_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT2_uid128_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_b : std_logic_vector (14 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (61 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (54 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid126_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal r_uid188_countZ_uid54_fpLogETest_q : std_logic_vector (6 downto 0);
signal s1_uid124_uid127_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid258_uid261_pT3_uid135_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid273_uid276_pT4_uid141_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (49 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (49 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (108 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (58 downto 0);
signal pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (117 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (52 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (65 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in : std_logic_vector (110 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b : std_logic_vector (110 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in : std_logic_vector (94 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b : std_logic_vector (94 downto 0);
signal leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
begin
--xIn(GPIN,3)@0
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,902)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor(LOGICAL,914)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a or ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg(REG,912)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena(REG,915)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd(LOGICAL,916)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b;
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(51 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(51 downto 0);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg(DELAY,906)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt(COUNTER,908)
-- every=1, low=0, high=1, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i,1));
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg(REG,909)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux(MUX,910)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem(DUALMEM,907)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 1,
numwords_a => 2,
width_b => 52,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq(51 downto 0);
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@4
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q(41 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(41 downto 0);
--yT2_uid128_natLogPolyEval(BITSELECT,127)@4
yT2_uid128_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT2_uid128_natLogPolyEval_b <= yT2_uid128_natLogPolyEval_in(41 downto 14);
--sSM1W_uid240_pT2_uid129_natLogPolyEval(BITSELECT,239)@4
sSM1W_uid240_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b(0 downto 0);
sSM1W_uid240_pT2_uid129_natLogPolyEval_b <= sSM1W_uid240_pT2_uid129_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1(REG,369)@4
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= sSM1W_uid240_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b(DELAY,672)@5
ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(62 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(62 downto 52);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(51 downto 42);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0(REG,322)@0
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid120_natLogTabGen_lutmem(DUALMEM,316)@1
memoryC4_uid120_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid120_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid120_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid120_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid120_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid120_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid120_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid120_natLogTabGen_lutmem_ia
);
memoryC4_uid120_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid120_natLogTabGen_lutmem_q <= memoryC4_uid120_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1(REG,355)@3
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= memoryC4_uid120_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid119_natLogTabGen_lutmem(DUALMEM,315)@1
memoryC4_uid119_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid119_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid119_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid119_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid119_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid119_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid119_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid119_natLogTabGen_lutmem_ia
);
memoryC4_uid119_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid119_natLogTabGen_lutmem_q <= memoryC4_uid119_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0(REG,354)@3
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= memoryC4_uid119_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid121_natLogTabGen(BITJOIN,120)@4
os_uid121_natLogTabGen_q <= reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q & reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q;
--reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1(REG,357)@4
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= os_uid121_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid122_natLogPolyEval(BITSELECT,121)@4
yT1_uid122_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid122_natLogPolyEval_b <= yT1_uid122_natLogPolyEval_in(41 downto 25);
--reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0(REG,356)@4
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= yT1_uid122_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid230_pT1_uid123_natLogPolyEval(MULT,229)@5
prodXY_uid230_pT1_uid123_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_a),18)) * SIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_b);
prodXY_uid230_pT1_uid123_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid230_pT1_uid123_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid230_pT1_uid123_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= prodXY_uid230_pT1_uid123_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval(BITSELECT,230)@8
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in <= prodXY_uid230_pT1_uid123_natLogPolyEval_q;
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in(33 downto 15);
--highBBits_uid125_natLogPolyEval(BITSELECT,124)@8
highBBits_uid125_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b;
highBBits_uid125_natLogPolyEval_b <= highBBits_uid125_natLogPolyEval_in(18 downto 1);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor(LOGICAL,1029)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q <= not (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a or ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena(REG,1030)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd(LOGICAL,1031)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a and ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid117_natLogTabGen_lutmem(DUALMEM,314)@1
memoryC3_uid117_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid117_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid117_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid117_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid117_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid117_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid117_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid117_natLogTabGen_lutmem_ia
);
memoryC3_uid117_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid117_natLogTabGen_lutmem_q <= memoryC3_uid117_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2(REG,363)@3
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= memoryC3_uid117_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid116_natLogTabGen_lutmem(DUALMEM,313)@1
memoryC3_uid116_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid116_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid116_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid116_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid116_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid116_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid116_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid116_natLogTabGen_lutmem_ia
);
memoryC3_uid116_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid116_natLogTabGen_lutmem_q <= memoryC3_uid116_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1(REG,362)@3
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= memoryC3_uid116_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid115_natLogTabGen_lutmem(DUALMEM,312)@1
memoryC3_uid115_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid115_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid115_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid115_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid115_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid115_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid115_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid115_natLogTabGen_lutmem_ia
);
memoryC3_uid115_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid115_natLogTabGen_lutmem_q <= memoryC3_uid115_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0(REG,361)@3
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= memoryC3_uid115_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid118_natLogTabGen(BITJOIN,117)@4
os_uid118_natLogTabGen_q <= reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q & reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q & reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg(DELAY,1021)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid118_natLogTabGen_q, xout => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem(DUALMEM,1022)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid126_natLogPolyEval(ADD,125)@8
sumAHighB_uid126_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid126_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid125_natLogPolyEval_b(17)) & highBBits_uid125_natLogPolyEval_b);
sumAHighB_uid126_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid126_natLogPolyEval_a) + SIGNED(sumAHighB_uid126_natLogPolyEval_b));
sumAHighB_uid126_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid124_natLogPolyEval(BITSELECT,123)@8
lowRangeB_uid124_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b(0 downto 0);
lowRangeB_uid124_natLogPolyEval_b <= lowRangeB_uid124_natLogPolyEval_in(0 downto 0);
--s1_uid124_uid127_natLogPolyEval(BITJOIN,126)@8
s1_uid124_uid127_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_q & lowRangeB_uid124_natLogPolyEval_b;
--sSM1H_uid239_pT2_uid129_natLogPolyEval(BITSELECT,238)@8
sSM1H_uid239_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
sSM1H_uid239_pT2_uid129_natLogPolyEval_b <= sSM1H_uid239_pT2_uid129_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0(REG,368)@8
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= sSM1H_uid239_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid241_pT2_uid129_natLogPolyEval(MULT,240)@9
sm1_uid241_pT2_uid129_natLogPolyEval_pr <= SIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_b),2));
sm1_uid241_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q;
sm1_uid241_pT2_uid129_natLogPolyEval_b <= ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q;
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid241_pT2_uid129_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid241_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval(BITJOIN,242)@12
pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid237_pT2_uid129_natLogPolyEval(BITSELECT,236)@4
sSM0W_uid237_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
sSM0W_uid237_pT2_uid129_natLogPolyEval_b <= sSM0W_uid237_pT2_uid129_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a(DELAY,822)@4
ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid237_pT2_uid129_natLogPolyEval_b, xout => ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1(REG,367)@8
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid236_pT2_uid129_natLogPolyEval(BITSELECT,235)@8
sSM0H_uid236_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q(2 downto 0);
sSM0H_uid236_pT2_uid129_natLogPolyEval_b <= sSM0H_uid236_pT2_uid129_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0(REG,366)@8
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= sSM0H_uid236_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid238_pT2_uid129_natLogPolyEval(MULT,237)@9
sm0_uid238_pT2_uid129_natLogPolyEval_pr <= UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_a) * UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_b);
sm0_uid238_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q;
sm0_uid238_pT2_uid129_natLogPolyEval_b <= reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q;
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid238_pT2_uid129_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid238_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval(BITJOIN,241)@12
pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid234_pT2_uid129_natLogPolyEval(BITSELECT,233)@8
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1(REG,365)@8
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor(LOGICAL,1151)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena(REG,1152)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd(LOGICAL,1153)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid233_pT2_uid129_natLogPolyEval(BITSELECT,232)@4
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b <= xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg(DELAY,1143)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b, xout => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem(DUALMEM,1144)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0(REG,364)@8
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid235_pT2_uid129_natLogPolyEval(MULT,234)@9
topProd_uid235_pT2_uid129_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_a),28)) * SIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_b);
topProd_uid235_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_b <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q;
topProd_uid235_pT2_uid129_natLogPolyEval_b <= reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q;
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid235_pT2_uid129_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid235_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= topProd_uid235_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid242_pT2_uid129_natLogPolyEval(ADDSUB3,243)@12
add0_uid242_pT2_uid129_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid235_pT2_uid129_natLogPolyEval_q(53)) & topProd_uid235_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q(26)) & pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_a) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_b) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_c));
add0_uid242_pT2_uid129_natLogPolyEval_q <= add0_uid242_pT2_uid129_natLogPolyEval_o(54 downto 0);
--R_uid245_pT2_uid129_natLogPolyEval(BITSELECT,244)@12
R_uid245_pT2_uid129_natLogPolyEval_in <= add0_uid242_pT2_uid129_natLogPolyEval_q(53 downto 0);
R_uid245_pT2_uid129_natLogPolyEval_b <= R_uid245_pT2_uid129_natLogPolyEval_in(53 downto 24);
--reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1(REG,371)@12
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= R_uid245_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor(LOGICAL,1042)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q <= not (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a or ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b);
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top(CONSTANT,1038)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp(LOGICAL,1039)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a = ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg(REG,1040)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena(REG,1043)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd(LOGICAL,1044)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a and ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid113_natLogTabGen_lutmem(DUALMEM,311)@1
memoryC2_uid113_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid113_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid113_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid113_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid113_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid113_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid113_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid113_natLogTabGen_lutmem_ia
);
memoryC2_uid113_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid113_natLogTabGen_lutmem_q <= memoryC2_uid113_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3(REG,351)@3
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= memoryC2_uid113_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid112_natLogTabGen_lutmem(DUALMEM,310)@1
memoryC2_uid112_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid112_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid112_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid112_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid112_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid112_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid112_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid112_natLogTabGen_lutmem_ia
);
memoryC2_uid112_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid112_natLogTabGen_lutmem_q <= memoryC2_uid112_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2(REG,350)@3
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= memoryC2_uid112_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid111_natLogTabGen_lutmem(DUALMEM,309)@1
memoryC2_uid111_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid111_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid111_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid111_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid111_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid111_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid111_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid111_natLogTabGen_lutmem_ia
);
memoryC2_uid111_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid111_natLogTabGen_lutmem_q <= memoryC2_uid111_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1(REG,349)@3
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= memoryC2_uid111_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid110_natLogTabGen_lutmem(DUALMEM,308)@1
memoryC2_uid110_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid110_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid110_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid110_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid110_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid110_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid110_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid110_natLogTabGen_lutmem_ia
);
memoryC2_uid110_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid110_natLogTabGen_lutmem_q <= memoryC2_uid110_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0(REG,348)@3
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= memoryC2_uid110_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid114_natLogTabGen(BITJOIN,113)@4
os_uid114_natLogTabGen_q <= reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q & reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q & reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q & reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg(DELAY,1032)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid114_natLogTabGen_q, xout => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg(REG,1035)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux(MUX,1036)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem(DUALMEM,1033)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--rndBit_uid130_natLogPolyEval(CONSTANT,129)
rndBit_uid130_natLogPolyEval_q <= "01";
--cIncludingRoundingBit_uid131_natLogPolyEval(BITJOIN,130)@12
cIncludingRoundingBit_uid131_natLogPolyEval_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0(REG,370)@12
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= cIncludingRoundingBit_uid131_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid132_natLogPolyEval(ADD,131)@13
ts2_uid132_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q);
ts2_uid132_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q(29)) & reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q);
ts2_uid132_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid132_natLogPolyEval_a) + SIGNED(ts2_uid132_natLogPolyEval_b));
ts2_uid132_natLogPolyEval_q <= ts2_uid132_natLogPolyEval_o(40 downto 0);
--s2_uid133_natLogPolyEval(BITSELECT,132)@13
s2_uid133_natLogPolyEval_in <= ts2_uid132_natLogPolyEval_q;
s2_uid133_natLogPolyEval_b <= s2_uid133_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid252_pT3_uid135_natLogPolyEval(BITSELECT,251)@13
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9(REG,375)@13
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg(DELAY,1045)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 3,
numwords_a => 7,
width_b => 42,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--yT3_uid134_natLogPolyEval(BITSELECT,133)@13
yT3_uid134_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q;
yT3_uid134_natLogPolyEval_b <= yT3_uid134_natLogPolyEval_in(41 downto 4);
--xBottomBits_uid251_pT3_uid135_natLogPolyEval(BITSELECT,250)@13
xBottomBits_uid251_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b(10 downto 0);
xBottomBits_uid251_pT3_uid135_natLogPolyEval_b <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval(BITJOIN,253)@13
pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7(REG,374)@13
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid250_pT3_uid135_natLogPolyEval(BITSELECT,249)@13
yBottomBits_uid250_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b(12 downto 0);
yBottomBits_uid250_pT3_uid135_natLogPolyEval_b <= yBottomBits_uid250_pT3_uid135_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval(BITJOIN,252)@13
spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q <= GND_q & yBottomBits_uid250_pT3_uid135_natLogPolyEval_b;
--pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval(BITJOIN,254)@13
pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q <= spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6(REG,373)@13
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid249_pT3_uid135_natLogPolyEval(BITSELECT,248)@13
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4(REG,372)@13
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma(CHAINMULTADD,317)@14
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval(BITSELECT,256)@17
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in(36 downto 4);
--highBBits_uid259_pT3_uid135_natLogPolyEval(BITSELECT,258)@17
highBBits_uid259_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b;
highBBits_uid259_pT3_uid135_natLogPolyEval_b <= highBBits_uid259_pT3_uid135_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid247_pT3_uid135_natLogPolyEval(BITSELECT,246)@13
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1(REG,377)@13
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid246_pT3_uid135_natLogPolyEval(BITSELECT,245)@13
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0(REG,376)@13
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid248_pT3_uid135_natLogPolyEval(MULT,247)@14
topProd_uid248_pT3_uid135_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_a),28)) * SIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_b);
topProd_uid248_pT3_uid135_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_b <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q;
topProd_uid248_pT3_uid135_natLogPolyEval_b <= reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q;
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid248_pT3_uid135_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid248_pT3_uid135_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= topProd_uid248_pT3_uid135_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid260_pT3_uid135_natLogPolyEval(ADD,259)@17
sumAHighB_uid260_pT3_uid135_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid248_pT3_uid135_natLogPolyEval_q(53)) & topProd_uid248_pT3_uid135_natLogPolyEval_q);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid259_pT3_uid135_natLogPolyEval_b(28)) & highBBits_uid259_pT3_uid135_natLogPolyEval_b);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_a) + SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_b));
sumAHighB_uid260_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid258_pT3_uid135_natLogPolyEval(BITSELECT,257)@17
lowRangeB_uid258_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b(3 downto 0);
lowRangeB_uid258_pT3_uid135_natLogPolyEval_b <= lowRangeB_uid258_pT3_uid135_natLogPolyEval_in(3 downto 0);
--add0_uid258_uid261_pT3_uid135_natLogPolyEval(BITJOIN,260)@17
add0_uid258_uid261_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_q & lowRangeB_uid258_pT3_uid135_natLogPolyEval_b;
--R_uid262_pT3_uid135_natLogPolyEval(BITSELECT,261)@17
R_uid262_pT3_uid135_natLogPolyEval_in <= add0_uid258_uid261_pT3_uid135_natLogPolyEval_q(57 downto 0);
R_uid262_pT3_uid135_natLogPolyEval_b <= R_uid262_pT3_uid135_natLogPolyEval_in(57 downto 17);
--reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1(REG,379)@17
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= R_uid262_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor(LOGICAL,1068)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q <= not (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a or ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b);
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top(CONSTANT,1064)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp(LOGICAL,1065)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a = ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg(REG,1066)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena(REG,1069)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd(LOGICAL,1070)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a and ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid108_natLogTabGen_lutmem(DUALMEM,307)@1
memoryC1_uid108_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid108_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid108_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid108_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid108_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid108_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid108_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid108_natLogTabGen_lutmem_ia
);
memoryC1_uid108_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid108_natLogTabGen_lutmem_q <= memoryC1_uid108_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4(REG,343)@3
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= memoryC1_uid108_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid107_natLogTabGen_lutmem(DUALMEM,306)@1
memoryC1_uid107_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid107_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid107_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid107_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid107_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid107_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid107_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid107_natLogTabGen_lutmem_ia
);
memoryC1_uid107_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid107_natLogTabGen_lutmem_q <= memoryC1_uid107_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3(REG,342)@3
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= memoryC1_uid107_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid106_natLogTabGen_lutmem(DUALMEM,305)@1
memoryC1_uid106_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid106_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid106_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid106_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid106_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid106_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid106_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid106_natLogTabGen_lutmem_ia
);
memoryC1_uid106_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid106_natLogTabGen_lutmem_q <= memoryC1_uid106_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2(REG,341)@3
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= memoryC1_uid106_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid105_natLogTabGen_lutmem(DUALMEM,304)@1
memoryC1_uid105_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid105_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid105_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid105_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid105_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid105_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid105_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid105_natLogTabGen_lutmem_ia
);
memoryC1_uid105_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid105_natLogTabGen_lutmem_q <= memoryC1_uid105_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1(REG,340)@3
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= memoryC1_uid105_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid104_natLogTabGen_lutmem(DUALMEM,303)@1
memoryC1_uid104_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid104_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid104_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid104_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid104_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid104_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid104_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid104_natLogTabGen_lutmem_ia
);
memoryC1_uid104_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid104_natLogTabGen_lutmem_q <= memoryC1_uid104_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0(REG,339)@3
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= memoryC1_uid104_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid109_natLogTabGen(BITJOIN,108)@4
os_uid109_natLogTabGen_q <= reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q & reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q & reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q & reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q & reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg(DELAY,1058)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid109_natLogTabGen_q, xout => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt(COUNTER,1060)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg(REG,1061)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux(MUX,1062)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem(DUALMEM,1059)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid137_natLogPolyEval(BITJOIN,136)@17
cIncludingRoundingBit_uid137_natLogPolyEval_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0(REG,378)@17
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= cIncludingRoundingBit_uid137_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid138_natLogPolyEval(ADD,137)@18
ts3_uid138_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q);
ts3_uid138_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q(40)) & reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q);
ts3_uid138_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid138_natLogPolyEval_a) + SIGNED(ts3_uid138_natLogPolyEval_b));
ts3_uid138_natLogPolyEval_q <= ts3_uid138_natLogPolyEval_o(50 downto 0);
--s3_uid139_natLogPolyEval(BITSELECT,138)@18
s3_uid139_natLogPolyEval_in <= ts3_uid138_natLogPolyEval_q;
s3_uid139_natLogPolyEval_b <= s3_uid139_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid264_pT4_uid141_natLogPolyEval(BITSELECT,263)@18
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b;
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9(REG,383)@18
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor(LOGICAL,1140)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a or ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top(CONSTANT,1136)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp(LOGICAL,1137)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg(REG,1138)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena(REG,1141)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd(LOGICAL,1142)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid267_pT4_uid141_natLogPolyEval(BITSELECT,266)@4
xBottomBits_uid267_pT4_uid141_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b(14 downto 0);
xBottomBits_uid267_pT4_uid141_natLogPolyEval_b <= xBottomBits_uid267_pT4_uid141_natLogPolyEval_in(14 downto 0);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg(DELAY,1130)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => xBottomBits_uid267_pT4_uid141_natLogPolyEval_b, xout => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt(COUNTER,1132)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg(REG,1133)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux(MUX,1134)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem(DUALMEM,1131)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 4,
numwords_a => 12,
width_b => 15,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq(14 downto 0);
--pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval(BITJOIN,268)@18
pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((10 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7(REG,382)@18
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid266_pT4_uid141_natLogPolyEval(BITSELECT,265)@18
yBottomBits_uid266_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b(22 downto 0);
yBottomBits_uid266_pT4_uid141_natLogPolyEval_b <= yBottomBits_uid266_pT4_uid141_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a(DELAY,704)@18
ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid266_pT4_uid141_natLogPolyEval_b, xout => ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval(BITJOIN,267)@19
spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q;
--pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval(BITJOIN,269)@19
pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q <= spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6(REG,381)@19
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor(LOGICAL,1127)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top(CONSTANT,1123)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp(LOGICAL,1124)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg(REG,1125)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena(REG,1128)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd(LOGICAL,1129)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt(COUNTER,1119)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg(REG,1120)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux(MUX,1121)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem(DUALMEM,1118)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 4,
numwords_a => 13,
width_b => 42,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--xTop27Bits_uid263_pT4_uid141_natLogPolyEval(BITSELECT,262)@19
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in(41 downto 15);
--reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4(REG,380)@19
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma(CHAINMULTADD,318)@20
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval(BITSELECT,271)@23
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in(54 downto 3);
--highBBits_uid274_pT4_uid141_natLogPolyEval(BITSELECT,273)@23
highBBits_uid274_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b;
highBBits_uid274_pT4_uid141_natLogPolyEval_b <= highBBits_uid274_pT4_uid141_natLogPolyEval_in(51 downto 23);
--ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b(DELAY,701)@19
ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid265_pT4_uid141_natLogPolyEval(MULT,264)@20
topProd_uid265_pT4_uid141_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_a),28)) * SIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_b);
topProd_uid265_pT4_uid141_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_b <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q;
topProd_uid265_pT4_uid141_natLogPolyEval_b <= ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q;
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid265_pT4_uid141_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid265_pT4_uid141_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= topProd_uid265_pT4_uid141_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid275_pT4_uid141_natLogPolyEval(ADD,274)@23
sumAHighB_uid275_pT4_uid141_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid265_pT4_uid141_natLogPolyEval_q(53)) & topProd_uid265_pT4_uid141_natLogPolyEval_q);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid274_pT4_uid141_natLogPolyEval_b(28)) & highBBits_uid274_pT4_uid141_natLogPolyEval_b);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_a) + SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_b));
sumAHighB_uid275_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid273_pT4_uid141_natLogPolyEval(BITSELECT,272)@23
lowRangeB_uid273_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b(22 downto 0);
lowRangeB_uid273_pT4_uid141_natLogPolyEval_b <= lowRangeB_uid273_pT4_uid141_natLogPolyEval_in(22 downto 0);
--add0_uid273_uid276_pT4_uid141_natLogPolyEval(BITJOIN,275)@23
add0_uid273_uid276_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_q & lowRangeB_uid273_pT4_uid141_natLogPolyEval_b;
--R_uid277_pT4_uid141_natLogPolyEval(BITSELECT,276)@23
R_uid277_pT4_uid141_natLogPolyEval_in <= add0_uid273_uid276_pT4_uid141_natLogPolyEval_q(76 downto 0);
R_uid277_pT4_uid141_natLogPolyEval_b <= R_uid277_pT4_uid141_natLogPolyEval_in(76 downto 25);
--reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1(REG,387)@23
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= R_uid277_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor(LOGICAL,1081)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q <= not (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a or ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b);
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top(CONSTANT,1077)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp(LOGICAL,1078)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a = ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg(REG,1079)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena(REG,1082)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd(LOGICAL,1083)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a and ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid102_natLogTabGen_lutmem(DUALMEM,302)@1
memoryC0_uid102_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid102_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid102_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid102_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid102_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid102_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid102_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid102_natLogTabGen_lutmem_ia
);
memoryC0_uid102_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid102_natLogTabGen_lutmem_q <= memoryC0_uid102_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5(REG,333)@3
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= memoryC0_uid102_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid101_natLogTabGen_lutmem(DUALMEM,301)@1
memoryC0_uid101_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid101_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid101_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid101_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid101_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid101_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid101_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid101_natLogTabGen_lutmem_ia
);
memoryC0_uid101_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid101_natLogTabGen_lutmem_q <= memoryC0_uid101_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4(REG,332)@3
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= memoryC0_uid101_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid100_natLogTabGen_lutmem(DUALMEM,300)@1
memoryC0_uid100_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid100_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid100_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid100_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid100_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid100_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid100_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid100_natLogTabGen_lutmem_ia
);
memoryC0_uid100_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid100_natLogTabGen_lutmem_q <= memoryC0_uid100_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3(REG,331)@3
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= memoryC0_uid100_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid99_natLogTabGen_lutmem(DUALMEM,299)@1
memoryC0_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid99_natLogTabGen_lutmem_ia
);
memoryC0_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid99_natLogTabGen_lutmem_q <= memoryC0_uid99_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2(REG,330)@3
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= memoryC0_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid98_natLogTabGen_lutmem(DUALMEM,298)@1
memoryC0_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid98_natLogTabGen_lutmem_ia
);
memoryC0_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid98_natLogTabGen_lutmem_q <= memoryC0_uid98_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1(REG,329)@3
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= memoryC0_uid98_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,297)@1
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0(REG,328)@3
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= memoryC0_uid97_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid103_natLogTabGen(BITJOIN,102)@4
os_uid103_natLogTabGen_q <= reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q & reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q & reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q & reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q & reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q & reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg(DELAY,1071)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid103_natLogTabGen_q, xout => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg(REG,1074)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux(MUX,1075)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem(DUALMEM,1072)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid142_natLogPolyEval(CONSTANT,141)
rndBit_uid142_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid143_natLogPolyEval(BITJOIN,142)@23
cIncludingRoundingBit_uid143_natLogPolyEval_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q & rndBit_uid142_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0(REG,386)@23
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= cIncludingRoundingBit_uid143_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid144_natLogPolyEval(ADD,143)@24
ts4_uid144_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q);
ts4_uid144_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q(51)) & reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q);
ts4_uid144_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid144_natLogPolyEval_a) + SIGNED(ts4_uid144_natLogPolyEval_b));
ts4_uid144_natLogPolyEval_q <= ts4_uid144_natLogPolyEval_o(63 downto 0);
--s4_uid145_natLogPolyEval(BITSELECT,144)@24
s4_uid145_natLogPolyEval_in <= ts4_uid144_natLogPolyEval_q;
s4_uid145_natLogPolyEval_b <= s4_uid145_natLogPolyEval_in(63 downto 1);
--peOR_uid37_fpLogETest(BITSELECT,36)@24
peOR_uid37_fpLogETest_in <= s4_uid145_natLogPolyEval_b(61 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(61 downto 7);
--postPEMul_uid43_fpLogETest_b_2(BITSELECT,281)@24
postPEMul_uid43_fpLogETest_b_2_in <= STD_LOGIC_VECTOR((80 downto 55 => peOR_uid37_fpLogETest_b(54)) & peOR_uid37_fpLogETest_b);
postPEMul_uid43_fpLogETest_b_2_b <= postPEMul_uid43_fpLogETest_b_2_in(80 downto 54);
--reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1(REG,398)@24
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= postPEMul_uid43_fpLogETest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor(LOGICAL,927)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a or ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b);
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top(CONSTANT,923)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q <= "010100";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp(LOGICAL,924)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q <= "1" when ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a = ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b else "0";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg(REG,925)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena(REG,928)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd(LOGICAL,929)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt(COUNTER,919)
-- every=1, low=0, high=20, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i = 19 THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i - 20;
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i,5));
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg(REG,920)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux(MUX,921)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem(DUALMEM,918)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 21,
width_b => 52,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq(51 downto 0);
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@23
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((51 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@23
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q);
oMz_uid38_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMz_uid38_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
END IF;
END IF;
END PROCESS;
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(53 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@23
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q;
--reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2(REG,321)@23
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= sEz_uid41_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor(LOGICAL,940)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena(REG,941)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd(LOGICAL,942)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b;
--reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1(REG,320)@0
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= c_uid31_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg(DELAY,930)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q, xout => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem(DUALMEM,931)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq(0 downto 0);
--multTermOne_uid42_fpLogETest(MUX,41)@24
multTermOne_uid42_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q;
multTermOne_uid42_fpLogETest: PROCESS (multTermOne_uid42_fpLogETest_s, en, reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q, oMz_uid38_fpLogETest_q)
BEGIN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid43_fpLogETest_a_1(BITSELECT,278)@24
postPEMul_uid43_fpLogETest_a_1_in <= multTermOne_uid42_fpLogETest_q;
postPEMul_uid43_fpLogETest_a_1_b <= postPEMul_uid43_fpLogETest_a_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0(REG,390)@24
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= postPEMul_uid43_fpLogETest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b2(MULT,287)@25
postPEMul_uid43_fpLogETest_a1_b2_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b2_a) * SIGNED(postPEMul_uid43_fpLogETest_a1_b2_b);
postPEMul_uid43_fpLogETest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= postPEMul_uid43_fpLogETest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a(DELAY,739)@28
ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_a1_b2_q, xout => ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_3(BITSHIFT,293)@30
postPEMul_uid43_fpLogETest_align_3_q_int <= ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_3_q <= postPEMul_uid43_fpLogETest_align_3_q_int(134 downto 0);
--postPEMul_uid43_fpLogETest_a_0(BITSELECT,277)@24
postPEMul_uid43_fpLogETest_a_0_in <= multTermOne_uid42_fpLogETest_q(26 downto 0);
postPEMul_uid43_fpLogETest_a_0_b <= postPEMul_uid43_fpLogETest_a_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0(REG,388)@24
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= postPEMul_uid43_fpLogETest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a0_b2(MULT,286)@25
postPEMul_uid43_fpLogETest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a0_b2_a),28)) * SIGNED(postPEMul_uid43_fpLogETest_a0_b2_b);
postPEMul_uid43_fpLogETest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= postPEMul_uid43_fpLogETest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_1(BITSELECT,280)@24
postPEMul_uid43_fpLogETest_b_1_in <= peOR_uid37_fpLogETest_b(53 downto 0);
postPEMul_uid43_fpLogETest_b_1_b <= postPEMul_uid43_fpLogETest_b_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1(REG,393)@24
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= postPEMul_uid43_fpLogETest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b1(MULT,285)@25
postPEMul_uid43_fpLogETest_a1_b1_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b1_b),28));
postPEMul_uid43_fpLogETest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= postPEMul_uid43_fpLogETest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_2_add_0_0(ADD,289)@28
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a1_b1_q(53)) & postPEMul_uid43_fpLogETest_a1_b1_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a0_b2_q(53)) & postPEMul_uid43_fpLogETest_a0_b2_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a(DELAY,738)@28
ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_2(BITSHIFT,292)@29
postPEMul_uid43_fpLogETest_align_2_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_2_q <= postPEMul_uid43_fpLogETest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0(REG,401)@29
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= postPEMul_uid43_fpLogETest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_1(ADD,295)@30
postPEMul_uid43_fpLogETest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q(108)) & reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q);
postPEMul_uid43_fpLogETest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid43_fpLogETest_align_3_q(134)) & postPEMul_uid43_fpLogETest_align_3_q);
postPEMul_uid43_fpLogETest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_b));
postPEMul_uid43_fpLogETest_result_add_0_1_q <= postPEMul_uid43_fpLogETest_result_add_0_1_o(135 downto 0);
--postPEMul_uid43_fpLogETest_a0_b1(MULT,284)@25
postPEMul_uid43_fpLogETest_a0_b1_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_b);
postPEMul_uid43_fpLogETest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= postPEMul_uid43_fpLogETest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_0(BITSELECT,279)@24
postPEMul_uid43_fpLogETest_b_0_in <= peOR_uid37_fpLogETest_b(26 downto 0);
postPEMul_uid43_fpLogETest_b_0_b <= postPEMul_uid43_fpLogETest_b_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1(REG,389)@24
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= postPEMul_uid43_fpLogETest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b0(MULT,283)@25
postPEMul_uid43_fpLogETest_a1_b0_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b0_b),28));
postPEMul_uid43_fpLogETest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= postPEMul_uid43_fpLogETest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_1_add_0_0(ADD,288)@28
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid43_fpLogETest_a1_b0_q(53)) & postPEMul_uid43_fpLogETest_a1_b0_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid43_fpLogETest_a0_b1_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a(DELAY,737)@28
ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_1(BITSHIFT,291)@29
postPEMul_uid43_fpLogETest_align_1_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_1_q <= postPEMul_uid43_fpLogETest_align_1_q_int(82 downto 0);
--postPEMul_uid43_fpLogETest_a0_b0(MULT,282)@25
postPEMul_uid43_fpLogETest_a0_b0_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_b);
postPEMul_uid43_fpLogETest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= postPEMul_uid43_fpLogETest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_align_0(BITSHIFT,290)@28
postPEMul_uid43_fpLogETest_align_0_q_int <= postPEMul_uid43_fpLogETest_a0_b0_q;
postPEMul_uid43_fpLogETest_align_0_q <= postPEMul_uid43_fpLogETest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0(REG,394)@28
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= postPEMul_uid43_fpLogETest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_0(ADD,294)@29
postPEMul_uid43_fpLogETest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q);
postPEMul_uid43_fpLogETest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid43_fpLogETest_align_1_q(82)) & postPEMul_uid43_fpLogETest_align_1_q);
postPEMul_uid43_fpLogETest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_result_add_0_0_q <= postPEMul_uid43_fpLogETest_result_add_0_0_o(83 downto 0);
--postPEMul_uid43_fpLogETest_result_add_1_0(ADD,296)@30
postPEMul_uid43_fpLogETest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid43_fpLogETest_result_add_0_0_q(83)) & postPEMul_uid43_fpLogETest_result_add_0_0_q);
postPEMul_uid43_fpLogETest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid43_fpLogETest_result_add_0_1_q(135)) & postPEMul_uid43_fpLogETest_result_add_0_1_q);
postPEMul_uid43_fpLogETest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_b));
postPEMul_uid43_fpLogETest_result_add_1_0_q <= postPEMul_uid43_fpLogETest_result_add_1_0_o(136 downto 0);
--highBBits_uid47_fpLogETest(BITSELECT,46)@30
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(108 downto 0);
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(108 downto 50);
--reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1(REG,406)@30
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= highBBits_uid47_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,903)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,899)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "011000";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,900)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,901)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,904)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,905)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg(DELAY,893)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogETest_b, xout => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=24, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 23 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 24;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,5));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,896)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,897)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,894)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 25,
width_b => 11,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(10 downto 0);
--e_uid29_fpLogETest(SUB,28)@27
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(11 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@27
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a(DELAY,858)@27
ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv0_uid90_constMult_b, xout => ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0(REG,403)@28
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid93_constMult(LOOKUP,92)@29
p0_uid93_constMult: PROCESS (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q) IS
WHEN "000000" => p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid93_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid93_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid93_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid93_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid93_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid93_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid93_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid93_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid93_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid93_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid93_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid93_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid93_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid93_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid93_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid93_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid93_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid93_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid93_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid93_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid93_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid93_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid93_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid93_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid93_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid93_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid93_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid93_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid93_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid93_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid93_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid93_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid93_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid93_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid93_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid93_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid93_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid93_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid93_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid93_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid93_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid93_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid93_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid93_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid93_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid93_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid93_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid93_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid93_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid93_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid93_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid93_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid93_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid93_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid93_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid93_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid93_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid93_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid93_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid93_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid93_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid93_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@27
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(11 downto 6);
--reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0(REG,402)@27
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= xv1_uid91_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid92_constMult(LOOKUP,91)@28
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q) IS
WHEN "000000" => p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid92_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid92_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid92_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid92_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid92_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid92_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid92_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid92_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid92_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid92_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid92_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid92_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid92_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid92_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid92_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid92_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid92_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid92_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid92_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid92_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid92_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid92_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid92_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid92_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid92_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid92_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid92_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid92_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid92_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid92_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid92_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid92_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid92_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid92_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid92_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid92_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid92_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid92_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid92_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid92_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid92_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid92_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid92_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid92_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid92_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid92_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid92_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid92_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid92_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid92_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid92_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid92_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid92_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid92_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid92_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid92_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid92_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid92_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid92_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid92_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid92_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid92_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid92_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@29
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid92_constMult_q(68)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(69 downto 0);
--sR_uid95_constMult(BITSELECT,94)@29
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(68 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(68 downto 2);
--reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2(REG,405)@29
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= sR_uid95_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor(LOGICAL,953)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top(CONSTANT,949)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q <= "011010";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp(LOGICAL,950)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q <= "1" when ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a = ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b else "0";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg(REG,951)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena(REG,954)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd(LOGICAL,955)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt(COUNTER,945)
-- every=1, low=0, high=26, step=1, init=1
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i = 25 THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i - 26;
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i,5));
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg(REG,946)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux(MUX,947)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux: PROCESS (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem(DUALMEM,944)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 27,
width_b => 1,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq(0 downto 0);
--addTermOne_uid45_fpLogETest(MUX,44)@30
addTermOne_uid45_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@31
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid45_fpLogETest_q(66)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q(58)) & reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(67 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@30
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(49 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(49 downto 0);
--reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0(REG,407)@30
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= lowRangeB_uid46_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@31
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q;
--FullSumAB117_uid50_fpLogETest(BITSELECT,49)@31
FullSumAB117_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB117_uid50_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_in(117 downto 117);
--notC_uid71_fpLogETest(LOGICAL,70)@31
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@31
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor(LOGICAL,966)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q <= not (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a or ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b);
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top(CONSTANT,962)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q <= "011100";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp(LOGICAL,963)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q <= "1" when ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a = ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b else "0";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg(REG,964)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena(REG,967)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd(LOGICAL,968)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a and ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg(DELAY,956)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt(COUNTER,958)
-- every=1, low=0, high=28, step=1, init=1
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i = 27 THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i - 28;
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i,5));
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg(REG,959)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux(MUX,960)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux: PROCESS (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem(DUALMEM,957)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq,
address_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa,
data_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia
);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 <= areset;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC1_uid73_fpLogETest(LOGICAL,72)@31
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest_q_i <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
signRC1_uid73_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRC1_uid73_fpLogETest_q, xin => signRC1_uid73_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor(LOGICAL,979)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q <= not (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a or ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena(REG,980)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q = "1") THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd(LOGICAL,981)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b <= en;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a and ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest_q_i <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
exc_R_uid27_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid27_fpLogETest_q, xin => exc_R_uid27_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg(DELAY,969)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem(DUALMEM,970)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq,
address_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa,
data_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia
);
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC11_uid74_fpLogETest(LOGICAL,73)@32
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor(LOGICAL,992)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q <= not (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a or ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b);
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena(REG,993)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q = "1") THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd(LOGICAL,994)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b <= en;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a and ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,437)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg(DELAY,982)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem(DUALMEM,983)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia
);
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq(0 downto 0);
--signR_uid75_fpLogETest(LOGICAL,74)@32
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor(LOGICAL,1005)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q <= not (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a or ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b);
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena(REG,1006)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q = "1") THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd(LOGICAL,1007)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b <= en;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a and ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(63 downto 63);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg(DELAY,995)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem(DUALMEM,996)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq,
address_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa,
data_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia
);
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 <= areset;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq(0 downto 0);
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@31
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q;
InvExcRNaN_uid76_fpLogETest_q_i <= not InvExcRNaN_uid76_fpLogETest_a;
InvExcRNaN_uid76_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => InvExcRNaN_uid76_fpLogETest_q, xin => InvExcRNaN_uid76_fpLogETest_q_i, clk => clk, aclr => areset);
--signRFull_uid77_fpLogETest(LOGICAL,76)@32
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q_i <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
signRFull_uid77_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRFull_uid77_fpLogETest_q, xin => signRFull_uid77_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,522)@33
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid147_countZ_uid54_fpLogETest(CONSTANT,146)
zs_uid147_countZ_uid54_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,481)@31
ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB117_uid50_fpLogETest_b, xout => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@31
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((117 downto 1 => FullSumAB117_uid50_fpLogETest_b(0)) & FullSumAB117_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest_q_i <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
finalSumOneComp_uid52_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 118, depth => 1)
PORT MAP (xout => finalSumOneComp_uid52_fpLogETest_q, xin => finalSumOneComp_uid52_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid53_fpLogETest(ADD,52)@32
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((118 downto 118 => finalSumOneComp_uid52_fpLogETest_q(117)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((118 downto 1 => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(118 downto 0);
--rVStage_uid148_countZ_uid54_fpLogETest(BITSELECT,147)@32
rVStage_uid148_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid148_countZ_uid54_fpLogETest_b <= rVStage_uid148_countZ_uid54_fpLogETest_in(118 downto 55);
--reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1(REG,408)@32
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= rVStage_uid148_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid149_countZ_uid54_fpLogETest(LOGICAL,148)@33
vCount_uid149_countZ_uid54_fpLogETest_a <= reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q;
vCount_uid149_countZ_uid54_fpLogETest_b <= zs_uid147_countZ_uid54_fpLogETest_q;
vCount_uid149_countZ_uid54_fpLogETest_q <= "1" when vCount_uid149_countZ_uid54_fpLogETest_a = vCount_uid149_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6(REG,422)@33
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= vCount_uid149_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g(DELAY,616)@34
ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q, xout => ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid155_countZ_uid54_fpLogETest(CONSTANT,154)
zs_uid155_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--vStage_uid151_countZ_uid54_fpLogETest(BITSELECT,150)@32
vStage_uid151_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(54 downto 0);
vStage_uid151_countZ_uid54_fpLogETest_b <= vStage_uid151_countZ_uid54_fpLogETest_in(54 downto 0);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b(DELAY,574)@32
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => vStage_uid151_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid150_countZ_uid54_fpLogETest(CONSTANT,149)
mO_uid150_countZ_uid54_fpLogETest_q <= "111111111";
--cStage_uid152_countZ_uid54_fpLogETest(BITJOIN,151)@33
cStage_uid152_countZ_uid54_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q & mO_uid150_countZ_uid54_fpLogETest_q;
--ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c(DELAY,576)@32
ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid148_countZ_uid54_fpLogETest_b, xout => ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid154_countZ_uid54_fpLogETest(MUX,153)@33
vStagei_uid154_countZ_uid54_fpLogETest_s <= vCount_uid149_countZ_uid54_fpLogETest_q;
vStagei_uid154_countZ_uid54_fpLogETest: PROCESS (vStagei_uid154_countZ_uid54_fpLogETest_s, en, ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, cStage_uid152_countZ_uid54_fpLogETest_q)
BEGIN
CASE vStagei_uid154_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid154_countZ_uid54_fpLogETest_q <= ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q;
WHEN "1" => vStagei_uid154_countZ_uid54_fpLogETest_q <= cStage_uid152_countZ_uid54_fpLogETest_q;
WHEN OTHERS => vStagei_uid154_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid156_countZ_uid54_fpLogETest(BITSELECT,155)@33
rVStage_uid156_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q;
rVStage_uid156_countZ_uid54_fpLogETest_b <= rVStage_uid156_countZ_uid54_fpLogETest_in(63 downto 32);
--reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1(REG,409)@33
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= rVStage_uid156_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid157_countZ_uid54_fpLogETest(LOGICAL,156)@34
vCount_uid157_countZ_uid54_fpLogETest_a <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
vCount_uid157_countZ_uid54_fpLogETest_b <= zs_uid155_countZ_uid54_fpLogETest_q;
vCount_uid157_countZ_uid54_fpLogETest_q <= "1" when vCount_uid157_countZ_uid54_fpLogETest_a = vCount_uid157_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a(DELAY,876)@34
ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid157_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5(REG,421)@36
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid161_countZ_uid54_fpLogETest(CONSTANT,160)
zs_uid161_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid158_countZ_uid54_fpLogETest(BITSELECT,157)@33
vStage_uid158_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q(31 downto 0);
vStage_uid158_countZ_uid54_fpLogETest_b <= vStage_uid158_countZ_uid54_fpLogETest_in(31 downto 0);
--reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3(REG,411)@33
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= vStage_uid158_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid160_countZ_uid54_fpLogETest(MUX,159)@34
vStagei_uid160_countZ_uid54_fpLogETest_s <= vCount_uid157_countZ_uid54_fpLogETest_q;
vStagei_uid160_countZ_uid54_fpLogETest: PROCESS (vStagei_uid160_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q, reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid160_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid160_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid162_countZ_uid54_fpLogETest(BITSELECT,161)@34
rVStage_uid162_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q;
rVStage_uid162_countZ_uid54_fpLogETest_b <= rVStage_uid162_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1(REG,412)@34
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= rVStage_uid162_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid163_countZ_uid54_fpLogETest(LOGICAL,162)@35
vCount_uid163_countZ_uid54_fpLogETest_a <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
vCount_uid163_countZ_uid54_fpLogETest_b <= zs_uid161_countZ_uid54_fpLogETest_q;
vCount_uid163_countZ_uid54_fpLogETest_q <= "1" when vCount_uid163_countZ_uid54_fpLogETest_a = vCount_uid163_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a(DELAY,875)@35
ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid163_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4(REG,420)@36
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid167_countZ_uid54_fpLogETest(CONSTANT,166)
zs_uid167_countZ_uid54_fpLogETest_q <= "00000000";
--vStage_uid164_countZ_uid54_fpLogETest(BITSELECT,163)@34
vStage_uid164_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid164_countZ_uid54_fpLogETest_b <= vStage_uid164_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3(REG,414)@34
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= vStage_uid164_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid166_countZ_uid54_fpLogETest(MUX,165)@35
vStagei_uid166_countZ_uid54_fpLogETest_s <= vCount_uid163_countZ_uid54_fpLogETest_q;
vStagei_uid166_countZ_uid54_fpLogETest: PROCESS (vStagei_uid166_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q, reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid166_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid166_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid168_countZ_uid54_fpLogETest(BITSELECT,167)@35
rVStage_uid168_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q;
rVStage_uid168_countZ_uid54_fpLogETest_b <= rVStage_uid168_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid169_countZ_uid54_fpLogETest(LOGICAL,168)@35
vCount_uid169_countZ_uid54_fpLogETest_a <= rVStage_uid168_countZ_uid54_fpLogETest_b;
vCount_uid169_countZ_uid54_fpLogETest_b <= zs_uid167_countZ_uid54_fpLogETest_q;
vCount_uid169_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid169_countZ_uid54_fpLogETest_a = vCount_uid169_countZ_uid54_fpLogETest_b else "0";
vCount_uid169_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid169_countZ_uid54_fpLogETest_q, xin => vCount_uid169_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d(DELAY,613)@36
ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid169_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid173_countZ_uid54_fpLogETest(CONSTANT,172)
zs_uid173_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid170_countZ_uid54_fpLogETest(BITSELECT,169)@35
vStage_uid170_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid170_countZ_uid54_fpLogETest_b <= vStage_uid170_countZ_uid54_fpLogETest_in(7 downto 0);
--reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3(REG,416)@35
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= vStage_uid170_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2(REG,415)@35
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= rVStage_uid168_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid172_countZ_uid54_fpLogETest(MUX,171)@36
vStagei_uid172_countZ_uid54_fpLogETest_s <= vCount_uid169_countZ_uid54_fpLogETest_q;
vStagei_uid172_countZ_uid54_fpLogETest: PROCESS (vStagei_uid172_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q, reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid172_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid172_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid174_countZ_uid54_fpLogETest(BITSELECT,173)@36
rVStage_uid174_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q;
rVStage_uid174_countZ_uid54_fpLogETest_b <= rVStage_uid174_countZ_uid54_fpLogETest_in(7 downto 4);
--vCount_uid175_countZ_uid54_fpLogETest(LOGICAL,174)@36
vCount_uid175_countZ_uid54_fpLogETest_a <= rVStage_uid174_countZ_uid54_fpLogETest_b;
vCount_uid175_countZ_uid54_fpLogETest_b <= zs_uid173_countZ_uid54_fpLogETest_q;
vCount_uid175_countZ_uid54_fpLogETest_q <= "1" when vCount_uid175_countZ_uid54_fpLogETest_a = vCount_uid175_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2(REG,419)@36
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= vCount_uid175_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid176_countZ_uid54_fpLogETest(BITSELECT,175)@36
vStage_uid176_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid176_countZ_uid54_fpLogETest_b <= vStage_uid176_countZ_uid54_fpLogETest_in(3 downto 0);
--vStagei_uid178_countZ_uid54_fpLogETest(MUX,177)@36
vStagei_uid178_countZ_uid54_fpLogETest_s <= vCount_uid175_countZ_uid54_fpLogETest_q;
vStagei_uid178_countZ_uid54_fpLogETest: PROCESS (vStagei_uid178_countZ_uid54_fpLogETest_s, en, rVStage_uid174_countZ_uid54_fpLogETest_b, vStage_uid176_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid178_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid178_countZ_uid54_fpLogETest_q <= rVStage_uid174_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid178_countZ_uid54_fpLogETest_q <= vStage_uid176_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid178_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid180_countZ_uid54_fpLogETest(BITSELECT,179)@36
rVStage_uid180_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q;
rVStage_uid180_countZ_uid54_fpLogETest_b <= rVStage_uid180_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid181_countZ_uid54_fpLogETest(LOGICAL,180)@36
vCount_uid181_countZ_uid54_fpLogETest_a <= rVStage_uid180_countZ_uid54_fpLogETest_b;
vCount_uid181_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid181_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid181_countZ_uid54_fpLogETest_a = vCount_uid181_countZ_uid54_fpLogETest_b else "0";
vCount_uid181_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid181_countZ_uid54_fpLogETest_q, xin => vCount_uid181_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid182_countZ_uid54_fpLogETest(BITSELECT,181)@36
vStage_uid182_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid182_countZ_uid54_fpLogETest_b <= vStage_uid182_countZ_uid54_fpLogETest_in(1 downto 0);
--reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3(REG,418)@36
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= vStage_uid182_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2(REG,417)@36
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= rVStage_uid180_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid184_countZ_uid54_fpLogETest(MUX,183)@37
vStagei_uid184_countZ_uid54_fpLogETest_s <= vCount_uid181_countZ_uid54_fpLogETest_q;
vStagei_uid184_countZ_uid54_fpLogETest: PROCESS (vStagei_uid184_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q, reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid184_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid184_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_countZ_uid54_fpLogETest(BITSELECT,185)@37
rVStage_uid186_countZ_uid54_fpLogETest_in <= vStagei_uid184_countZ_uid54_fpLogETest_q;
rVStage_uid186_countZ_uid54_fpLogETest_b <= rVStage_uid186_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid187_countZ_uid54_fpLogETest(LOGICAL,186)@37
vCount_uid187_countZ_uid54_fpLogETest_a <= rVStage_uid186_countZ_uid54_fpLogETest_b;
vCount_uid187_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid187_countZ_uid54_fpLogETest_q <= "1" when vCount_uid187_countZ_uid54_fpLogETest_a = vCount_uid187_countZ_uid54_fpLogETest_b else "0";
--r_uid188_countZ_uid54_fpLogETest(BITJOIN,187)@37
r_uid188_countZ_uid54_fpLogETest_q <= ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q & reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q & reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q & ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q & reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q & vCount_uid181_countZ_uid54_fpLogETest_q & vCount_uid187_countZ_uid54_fpLogETest_q;
--ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b(DELAY,482)@37
ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => r_uid188_countZ_uid54_fpLogETest_q, xout => ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010000001100";
--expRExt_uid57_fpLogETest(SUB,56)@38
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("000000" & ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q);
expRExt_uid57_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid57_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
END IF;
END IF;
END PROCESS;
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(12 downto 0);
--LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest(BITSELECT,224)@39
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q(117 downto 0);
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in(117 downto 0);
--leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest(BITJOIN,225)@39
leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b & GND_q;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor(LOGICAL,1114)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a or ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena(REG,1115)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1116)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b;
--X22dto0_uid198_normVal_uid55_fpLogETest(BITSELECT,197)@32
X22dto0_uid198_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(22 downto 0);
X22dto0_uid198_normVal_uid55_fpLogETest_b <= X22dto0_uid198_normVal_uid55_fpLogETest_in(22 downto 0);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg(DELAY,1106)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => X22dto0_uid198_normVal_uid55_fpLogETest_b, xout => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1107)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq(22 downto 0);
--leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest(CONSTANT,196)
leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest(BITJOIN,198)@36
leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5(REG,426)@36
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor(LOGICAL,1103)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q <= not (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a or ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena(REG,1104)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1105)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a and ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1096)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 55,
widthad_a => 1,
numwords_a => 2,
width_b => 55,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq(54 downto 0);
--leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest(BITJOIN,195)@36
leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid147_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4(REG,425)@36
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor(LOGICAL,1092)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a or ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena(REG,1093)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1094)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b;
--X86dto0_uid192_normVal_uid55_fpLogETest(BITSELECT,191)@32
X86dto0_uid192_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(86 downto 0);
X86dto0_uid192_normVal_uid55_fpLogETest_b <= X86dto0_uid192_normVal_uid55_fpLogETest_in(86 downto 0);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg(DELAY,1084)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 87, depth => 1 )
PORT MAP ( xin => X86dto0_uid192_normVal_uid55_fpLogETest_b, xout => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1085)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 87,
widthad_a => 1,
numwords_a => 2,
width_b => 87,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq(86 downto 0);
--leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest(BITJOIN,192)@36
leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid155_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3(REG,424)@36
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor(LOGICAL,1162)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q <= not (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a or ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b);
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena(REG,1163)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q = "1") THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd(LOGICAL,1164)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b <= en;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a and ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg(DELAY,1154)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 119, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem(DUALMEM,1155)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 119,
widthad_a => 1,
numwords_a => 2,
width_b => 119,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq,
address_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa,
data_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia
);
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq(118 downto 0);
--reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2(REG,423)@36
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest(BITSELECT,199)@37
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q;
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in(6 downto 5);
--leftShiftStage0_uid201_normVal_uid55_fpLogETest(MUX,200)@37
leftShiftStage0_uid201_normVal_uid55_fpLogETest_s <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid201_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid201_normVal_uid55_fpLogETest_s, en, reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage0_uid201_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest(BITSELECT,208)@37
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(94 downto 0);
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in(94 downto 0);
--leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest(CONSTANT,207)
leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest(BITJOIN,209)@37
leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5(REG,431)@37
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest(BITSELECT,205)@37
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(102 downto 0);
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in(102 downto 0);
--leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest(BITJOIN,206)@37
leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b & zs_uid161_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4(REG,430)@37
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest(BITSELECT,202)@37
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(110 downto 0);
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in(110 downto 0);
--leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest(BITJOIN,203)@37
leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b & zs_uid167_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3(REG,429)@37
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2(REG,428)@37
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest(BITSELECT,210)@37
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(4 downto 0);
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1(REG,427)@37
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid212_normVal_uid55_fpLogETest(MUX,211)@38
leftShiftStage1_uid212_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid212_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid212_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid212_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest(BITSELECT,219)@38
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(112 downto 0);
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b <= LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in(112 downto 0);
--ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b(DELAY,645)@38
ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 113, depth => 1 )
PORT MAP ( xin => LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest(CONSTANT,218)
leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q <= "000000";
--leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest(BITJOIN,220)@39
leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q & leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q;
--LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest(BITSELECT,216)@38
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(114 downto 0);
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b <= LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in(114 downto 0);
--ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b(DELAY,643)@38
ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 115, depth => 1 )
PORT MAP ( xin => LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest(BITJOIN,217)@39
leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q & zs_uid173_countZ_uid54_fpLogETest_q;
--LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest(BITSELECT,213)@38
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(116 downto 0);
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b <= LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in(116 downto 0);
--ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b(DELAY,641)@38
ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 117, depth => 1 )
PORT MAP ( xin => LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest(BITJOIN,214)@39
leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q & z2_uid40_fpLogETest_q;
--reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2(REG,433)@38
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest(BITSELECT,221)@37
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(2 downto 0);
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1(REG,432)@37
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b(DELAY,647)@38
ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid223_normVal_uid55_fpLogETest(MUX,222)@39
leftShiftStage2_uid223_normVal_uid55_fpLogETest_s <= ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q;
leftShiftStage2_uid223_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid223_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q, leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid223_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest(BITSELECT,226)@37
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(0 downto 0);
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b <= leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b(DELAY,655)@37
ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b, xout => ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid228_normVal_uid55_fpLogETest(MUX,227)@39
leftShiftStage3_uid228_normVal_uid55_fpLogETest_s <= ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q;
leftShiftStage3_uid228_normVal_uid55_fpLogETest: PROCESS (leftShiftStage3_uid228_normVal_uid55_fpLogETest_s, en, leftShiftStage2_uid223_normVal_uid55_fpLogETest_q, leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage3_uid228_normVal_uid55_fpLogETest_s IS
WHEN "0" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q;
WHEN "1" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@39
fracR_uid58_fpLogETest_in <= leftShiftStage3_uid228_normVal_uid55_fpLogETest_q(117 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(117 downto 65);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@39
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,434)@39
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@40
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(66 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@40
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(63 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(63 downto 53);
--reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3(REG,436)@40
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= expR_uid62_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor(LOGICAL,1018)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q <= not (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a or ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b);
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top(CONSTANT,1014)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q <= "0100100";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp(LOGICAL,1015)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q <= "1" when ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a = ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b else "0";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg(REG,1016)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena(REG,1019)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd(LOGICAL,1020)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a and ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,319)@0
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= concExc_uid78_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg(DELAY,1008)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q, xout => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt(COUNTER,1010)
-- every=1, low=0, high=36, step=1, init=1
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i = 35 THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i - 36;
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i,6));
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg(REG,1011)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux(MUX,1012)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux: PROCESS (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem(DUALMEM,1009)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 37,
width_b => 3,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia
);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq(2 downto 0);
--excREnc_uid79_fpLogETest(LOOKUP,78)@40
excREnc_uid79_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid79_fpLogETest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@41
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "0000000000000000000000000000000000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@40
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(52 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(52 downto 1);
--reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3(REG,435)@40
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= fracR_uid61_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid83_fpLogETest(MUX,82)@41
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@41
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@41
q <= RLn_uid88_fpLogETest_q;
end normal;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_divrndpipe.vhd
|
10
|
7102
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVRNDPIPE.VHD ***
--*** ***
--*** Function: Output Stage, Pipelined Round ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 3 ***
--***************************************************
ENTITY hcc_divrndpipe IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divrndpipe;
ARCHITECTURE rtl OF hcc_divrndpipe IS
signal zerovec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundmantissanode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff, exponenttwoff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal manoverflowff : STD_LOGIC;
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzv: FOR k IN 1 TO 53 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "000";
satinff <= "00";
zipinff <= "00";
naninff <= "00";
manoverflowff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
signff(3) <= signff(2);
satinff(1) <= satin;
satinff(2) <= satinff(1);
zipinff(1) <= zipin;
zipinff(2) <= zipinff(1);
naninff(1) <= nanin;
naninff(2) <= naninff(1);
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (roundmantissanode(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(13 DOWNTO 1) <= exponentin;
exponenttwoff(13 DOWNTO 1) <= exponentoneff(13 DOWNTO 1) +
(zerovec(12 DOWNTO 1) & manoverflowff);
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponenttwoff(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
gaa: IF (synthesize = 0) GENERATE
addb: hcc_addpipeb
GENERIC MAP (width=>52,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mantissain(53 DOWNTO 2),bb=>zerovec(52 DOWNTO 1),
carryin=>mantissain(1),
cc=>roundmantissanode);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addb: hcc_addpipes
GENERIC MAP (width=>52,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mantissain(53 DOWNTO 2),bb=>zerovec(52 DOWNTO 1),
carryin=>mantissain(1),
cc=>roundmantissanode);
END GENERATE;
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissain(1);
gmoa: FOR k IN 2 TO 53 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissain(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponenttwoff(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponenttwoff(k);
END GENERATE;
-- 12/05/09 - make sure exponent = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponenttwoff(12)) AND NOT(exponenttwoff(13))) OR
satinff(2) OR (exponenttwoff(12) AND NOT(exponenttwoff(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponenttwoff(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponenttwoff(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipinff(2) OR exponenttwoff(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= naninff(2);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR naninff(2);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(3);
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_cntusgn32_sv.vhd
|
20
|
4321
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_castytod.vhd
|
10
|
18709
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_castytod.vhd
|
10
|
18709
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_hypot_s5.vhd
|
10
|
263346
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_hypot_s5
-- VHDL created on Tue Mar 12 11:24:00 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_hypot_s5 is
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_hypot_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid10_fpHypotTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid11_fpHypotTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpHypotTest_q : std_logic_vector (7 downto 0);
signal oFracXSqr_uid45_fpHypotTest_a : std_logic_vector (23 downto 0);
signal oFracXSqr_uid45_fpHypotTest_b : std_logic_vector (23 downto 0);
signal oFracXSqr_uid45_fpHypotTest_s1 : std_logic_vector (47 downto 0);
signal oFracXSqr_uid45_fpHypotTest_pr : UNSIGNED (47 downto 0);
signal oFracXSqr_uid45_fpHypotTest_q : std_logic_vector (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_a : std_logic_vector (23 downto 0);
signal oFracYSqr_uid46_fpHypotTest_b : std_logic_vector (23 downto 0);
signal oFracYSqr_uid46_fpHypotTest_s1 : std_logic_vector (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_pr : UNSIGNED (47 downto 0);
signal oFracYSqr_uid46_fpHypotTest_q : std_logic_vector (47 downto 0);
signal bias_uid47_fpHypotTest_q : std_logic_vector (6 downto 0);
signal cWFP2_uid66_fpHypotTest_q : std_logic_vector (4 downto 0);
signal oFracA_uid68_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracA_uid68_fpHypotTest_q : std_logic_vector (23 downto 0);
signal z_uid71_fpHypotTest_q : std_logic_vector (4 downto 0);
signal excAZero_uid74_fpHypotTest_s : std_logic_vector (0 downto 0);
signal excAZero_uid74_fpHypotTest_q : std_logic_vector (0 downto 0);
signal excBZero_uid75_fpHypotTest_s : std_logic_vector (0 downto 0);
signal excBZero_uid75_fpHypotTest_q : std_logic_vector (0 downto 0);
signal zerosWFp1_uid77_fpHypotTest_q : std_logic_vector (23 downto 0);
signal oFracAPostExc_uid79_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracAPostExc_uid79_fpHypotTest_q : std_logic_vector (23 downto 0);
signal biasP1Signal_uid99_fpHypotTest_q : std_logic_vector (6 downto 0);
signal expRMux_uid104_fpHypotTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid104_fpHypotTest_q : std_logic_vector (9 downto 0);
signal xRegOrZero_uid121_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xRegOrZero_uid121_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xRegOrZero_uid121_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yRegOrZero_uid123_fpHypotTest_q : std_logic_vector(0 downto 0);
signal NaNFracRPostExc_uid133_fpHypotTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid173_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid173_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid174_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid174_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid175_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid175_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q : std_logic_vector (23 downto 0);
signal reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q : std_logic_vector (23 downto 0);
signal reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q : std_logic_vector (4 downto 0);
signal reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q : std_logic_vector (0 downto 0);
signal reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q : std_logic_vector (23 downto 0);
signal reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q : std_logic_vector (0 downto 0);
signal reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q : std_logic_vector (33 downto 0);
signal reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q : std_logic_vector (24 downto 0);
signal reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q : std_logic_vector (9 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q : std_logic_vector (20 downto 0);
signal reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q : std_logic_vector (28 downto 0);
signal reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q : std_logic_vector (24 downto 0);
signal reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q : std_logic_vector (10 downto 0);
signal reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q : std_logic_vector (7 downto 0);
signal ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q : std_logic_vector (7 downto 0);
signal ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q : std_logic_vector (9 downto 0);
signal ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q : std_logic_vector (0 downto 0);
signal ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q : std_logic_vector (9 downto 0);
signal ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q : std_logic_vector (23 downto 0);
signal ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q : std_logic_vector (23 downto 0);
signal ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q : std_logic_vector (0 downto 0);
signal ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q : std_logic_vector (23 downto 0);
signal ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q : std_logic_vector (23 downto 0);
signal ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q : std_logic_vector (7 downto 0);
signal ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q : std_logic_vector (9 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q : std_logic_vector (9 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq : std_logic;
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq : std_logic;
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q : signal is true;
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq : std_logic;
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q : signal is true;
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q : signal is true;
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q : signal is true;
signal ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal pGTEq_uid60_fpHypotTest_a : std_logic_vector(12 downto 0);
signal pGTEq_uid60_fpHypotTest_b : std_logic_vector(12 downto 0);
signal pGTEq_uid60_fpHypotTest_o : std_logic_vector (12 downto 0);
signal pGTEq_uid60_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal pGTEq_uid60_fpHypotTest_n : std_logic_vector (0 downto 0);
signal shiftedOut_uid67_fpHypotTest_a : std_logic_vector(12 downto 0);
signal shiftedOut_uid67_fpHypotTest_b : std_logic_vector(12 downto 0);
signal shiftedOut_uid67_fpHypotTest_o : std_logic_vector (12 downto 0);
signal shiftedOut_uid67_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal shiftedOut_uid67_fpHypotTest_n : std_logic_vector (0 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_a : std_logic_vector(13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_b : std_logic_vector(13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_o : std_logic_vector (13 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal sqrtUnderflow_uid115_fpHypotTest_n : std_logic_vector (0 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_a : std_logic_vector(13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_b : std_logic_vector(13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_o : std_logic_vector (13 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_cin : std_logic_vector (0 downto 0);
signal sqrtOverflow_uid117_fpHypotTest_n : std_logic_vector (0 downto 0);
signal fracRPostInc_uid111_fpHypotTest_a : std_logic_vector(25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_b : std_logic_vector(25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_o : std_logic_vector (25 downto 0);
signal fracRPostInc_uid111_fpHypotTest_q : std_logic_vector (25 downto 0);
signal expCatRndBit_uid91_uid92_fpHypotTest_q : std_logic_vector (33 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpHypotTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpHypotTest_b : std_logic_vector (7 downto 0);
signal fracX_uid8_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracX_uid8_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expY_uid7_fpHypotTest_in : std_logic_vector (30 downto 0);
signal expY_uid7_fpHypotTest_b : std_logic_vector (7 downto 0);
signal fracY_uid9_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracY_uid9_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid14_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid14_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid14_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid16_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid16_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid16_fpHypotTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid18_fpHypotTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid18_fpHypotTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid18_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid19_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid30_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid30_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid30_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid32_fpHypotTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid32_fpHypotTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid32_fpHypotTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid34_fpHypotTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid34_fpHypotTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid34_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid35_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_a : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_b : std_logic_vector(0 downto 0);
signal expCmpGtePQ_uid61_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiffPQ_uid62_fpHypotTest_a : std_logic_vector(10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_b : std_logic_vector(10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_o : std_logic_vector (10 downto 0);
signal expDiffPQ_uid62_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expDiffQP_uid63_fpHypotTest_a : std_logic_vector(10 downto 0);
signal expDiffQP_uid63_fpHypotTest_b : std_logic_vector(10 downto 0);
signal expDiffQP_uid63_fpHypotTest_o : std_logic_vector (10 downto 0);
signal expDiffQP_uid63_fpHypotTest_q : std_logic_vector (10 downto 0);
signal mux_uid64_fpHypotTest_s : std_logic_vector (0 downto 0);
signal mux_uid64_fpHypotTest_q : std_logic_vector (10 downto 0);
signal oFracB_uid69_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracB_uid69_fpHypotTest_q : std_logic_vector (23 downto 0);
signal expA_uid70_fpHypotTest_s : std_logic_vector (0 downto 0);
signal expA_uid70_fpHypotTest_q : std_logic_vector (9 downto 0);
signal shiftValue_uid73_fpHypotTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid73_fpHypotTest_q : std_logic_vector (4 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_a : std_logic_vector(0 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_b : std_logic_vector(0 downto 0);
signal oFracBFlushToZero_uid76_fpHypotTest_q : std_logic_vector(0 downto 0);
signal oFracBPostExc_uid78_fpHypotTest_s : std_logic_vector (0 downto 0);
signal oFracBPostExc_uid78_fpHypotTest_q : std_logic_vector (23 downto 0);
signal sumAHighB_uid84_fpHypotTest_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid84_fpHypotTest_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid84_fpHypotTest_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid84_fpHypotTest_q : std_logic_vector (24 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_a : std_logic_vector(35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_b : std_logic_vector(35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_o : std_logic_vector (35 downto 0);
signal expFracPostNorm_uid94_fpHypotTest_q : std_logic_vector (34 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expSumOfSquaresUnbiased_uid97_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expOddSig_uid100_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid100_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid100_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid100_fpHypotTest_q : std_logic_vector (10 downto 0);
signal expRPostInc_uid114_fpHypotTest_a : std_logic_vector(11 downto 0);
signal expRPostInc_uid114_fpHypotTest_b : std_logic_vector(11 downto 0);
signal expRPostInc_uid114_fpHypotTest_o : std_logic_vector (11 downto 0);
signal expRPostInc_uid114_fpHypotTest_q : std_logic_vector (10 downto 0);
signal excXYZ_uid118_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excXYZ_uid118_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excXYZ_uid118_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_c : std_logic_vector(0 downto 0);
signal excXYRUdf_uid119_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid120_fpHypotTest_q : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_c : std_logic_vector(0 downto 0);
signal xRegOrZeroYRegOvf_uid122_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_c : std_logic_vector(0 downto 0);
signal yRegOrZeroXRegOvf_uid124_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid125_fpHypotTest_q : std_logic_vector(0 downto 0);
signal outMuxSelEnc_uid132_fpHypotTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid136_fpHypotTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid136_fpHypotTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid141_fpHypotTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid141_fpHypotTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal normBitXSqr_uid48_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normBitXSqr_uid48_fpHypotTest_b : std_logic_vector (0 downto 0);
signal normFracXSqrHigh_uid54_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normFracXSqrHigh_uid54_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normFracXSqrLow_uid55_fpHypotTest_in : std_logic_vector (46 downto 0);
signal normFracXSqrLow_uid55_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normBitYSqr_uid49_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normBitYSqr_uid49_fpHypotTest_b : std_logic_vector (0 downto 0);
signal normFracYSqrHigh_uid57_fpHypotTest_in : std_logic_vector (47 downto 0);
signal normFracYSqrHigh_uid57_fpHypotTest_b : std_logic_vector (23 downto 0);
signal normFracYSqrLow_uid58_fpHypotTest_in : std_logic_vector (46 downto 0);
signal normFracYSqrLow_uid58_fpHypotTest_b : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal soSPreNorm_uid82_uid85_fpHypotTest_q : std_logic_vector (25 downto 0);
signal expXTimes2_uid50_fpHypotTest_q : std_logic_vector (8 downto 0);
signal expYTimes2_uid51_fpHypotTest_q : std_logic_vector (8 downto 0);
signal FracRPreSqrt15dto0_uid108_fpHypotTest_in : std_logic_vector (15 downto 0);
signal FracRPreSqrt15dto0_uid108_fpHypotTest_b : std_logic_vector (15 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q : std_logic_vector(0 downto 0);
signal excSelBits_uid131_fpHypotTest_q : std_logic_vector (2 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid112_fpHypotTest_in : std_logic_vector (23 downto 0);
signal fracR_uid112_fpHypotTest_b : std_logic_vector (22 downto 0);
signal fracRPostIncMSBU_uid113_fpHypotTest_in : std_logic_vector (25 downto 0);
signal fracRPostIncMSBU_uid113_fpHypotTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid43_uid43_fpHypotTest_q : std_logic_vector (23 downto 0);
signal oFracY_uid44_uid44_fpHypotTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid24_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid24_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid20_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid20_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid23_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid23_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid40_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid40_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid36_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid36_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid39_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid39_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiff_uid65_fpHypotTest_in : std_logic_vector (9 downto 0);
signal expDiff_uid65_fpHypotTest_b : std_logic_vector (9 downto 0);
signal rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b : std_logic_vector (0 downto 0);
signal oFracBPostExcG_uid80_fpHypotTest_q : std_logic_vector (24 downto 0);
signal fracRPreSqrt_uid95_fpHypotTest_in : std_logic_vector (23 downto 0);
signal fracRPreSqrt_uid95_fpHypotTest_b : std_logic_vector (22 downto 0);
signal expRPreSqrt_uid96_fpHypotTest_in : std_logic_vector (33 downto 0);
signal expRPreSqrt_uid96_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expREven_uid98_fpHypotTest_in : std_logic_vector (10 downto 0);
signal expREven_uid98_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expROdd_uid101_fpHypotTest_in : std_logic_vector (10 downto 0);
signal expROdd_uid101_fpHypotTest_b : std_logic_vector (9 downto 0);
signal expRPreExc_uid139_fpHypotTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid139_fpHypotTest_b : std_logic_vector (7 downto 0);
signal RHypot_uid142_fpHypotTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b : std_logic_vector (18 downto 0);
signal ofracP_uid56_fpHypotTest_s : std_logic_vector (0 downto 0);
signal ofracP_uid56_fpHypotTest_q : std_logic_vector (23 downto 0);
signal ofracQ_uid59_fpHypotTest_s : std_logic_vector (0 downto 0);
signal ofracQ_uid59_fpHypotTest_q : std_logic_vector (23 downto 0);
signal lowRangeB_uid178_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid178_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid179_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid179_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid184_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid184_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid185_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid185_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b : std_logic_vector (23 downto 0);
signal FullSumAB25_uid86_fpHypotTest_in : std_logic_vector (25 downto 0);
signal FullSumAB25_uid86_fpHypotTest_b : std_logic_vector (0 downto 0);
signal soSRangeHigh_uid87_fpHypotTest_in : std_logic_vector (24 downto 0);
signal soSRangeHigh_uid87_fpHypotTest_b : std_logic_vector (23 downto 0);
signal soSRangeLow_uid88_fpHypotTest_in : std_logic_vector (23 downto 0);
signal soSRangeLow_uid88_fpHypotTest_b : std_logic_vector (23 downto 0);
signal expP_uid52_fpHypotTest_a : std_logic_vector(9 downto 0);
signal expP_uid52_fpHypotTest_b : std_logic_vector(9 downto 0);
signal expP_uid52_fpHypotTest_o : std_logic_vector (9 downto 0);
signal expP_uid52_fpHypotTest_q : std_logic_vector (9 downto 0);
signal expQ_uid53_fpHypotTest_a : std_logic_vector(9 downto 0);
signal expQ_uid53_fpHypotTest_b : std_logic_vector(9 downto 0);
signal expQ_uid53_fpHypotTest_o : std_logic_vector (9 downto 0);
signal expQ_uid53_fpHypotTest_q : std_logic_vector (9 downto 0);
signal yT1_uid176_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid176_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal exc_N_uid21_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid21_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid21_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid37_fpHypotTest_q : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_a : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_b : std_logic_vector(0 downto 0);
signal xNaNyNonInf_uid129_fpHypotTest_q : std_logic_vector(0 downto 0);
signal expDiffShiftRange_uid72_fpHypotTest_in : std_logic_vector (4 downto 0);
signal expDiffShiftRange_uid72_fpHypotTest_b : std_logic_vector (4 downto 0);
signal X24dto8_uid145_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid145_alignShift_uid81_fpHypotTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid148_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid148_alignShift_uid81_fpHypotTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid151_alignShift_uid81_fpHypotTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid151_alignShift_uid81_fpHypotTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid106_fpHypotTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid106_fpHypotTest_b : std_logic_vector (6 downto 0);
signal ExpRPreSqrt0_uid102_fpHypotTest_in : std_logic_vector (0 downto 0);
signal ExpRPreSqrt0_uid102_fpHypotTest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid180_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid186_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal resFracNorm_uid89_fpHypotTest_s : std_logic_vector (0 downto 0);
signal resFracNorm_uid89_fpHypotTest_q : std_logic_vector (23 downto 0);
signal normCatFracSoS_uid93_uid93_fpHypotTest_q : std_logic_vector (24 downto 0);
signal InvExc_N_uid22_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid22_fpHypotTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid38_fpHypotTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid38_fpHypotTest_q : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_a : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_b : std_logic_vector(0 downto 0);
signal yNaNxNonInf_uid127_fpHypotTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid130_fpHypotTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal expOddSelect_uid103_fpHypotTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid103_fpHypotTest_q : std_logic_vector(0 downto 0);
signal s1_uid178_uid181_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid184_uid187_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q : std_logic_vector (24 downto 0);
signal exc_R_uid25_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid25_fpHypotTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid41_fpHypotTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid107_fpHypotTest_q : std_logic_vector (7 downto 0);
signal fracRPreInc_uid110_fpHypotTest_in : std_logic_vector (29 downto 0);
signal fracRPreInc_uid110_fpHypotTest_b : std_logic_vector (24 downto 0);
signal lowRangeB_uid82_fpHypotTest_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid82_fpHypotTest_b : std_logic_vector (0 downto 0);
signal highBBits_uid83_fpHypotTest_in : std_logic_vector (24 downto 0);
signal highBBits_uid83_fpHypotTest_b : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid10_fpHypotTest(CONSTANT,9)
cstAllOWE_uid10_fpHypotTest_q <= "11111111";
--VCC(CONSTANT,1)
VCC_q <= "1";
--RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest(BITSELECT,166)@8
RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in <= rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q;
RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b <= RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_in(24 downto 1);
--rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest(BITJOIN,168)@8
rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q <= GND_q & RightShiftStage124dto1_uid167_alignShift_uid81_fpHypotTest_b;
--rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest(CONSTANT,162)
rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q <= "000000";
--zerosWFp1_uid77_fpHypotTest(CONSTANT,76)
zerosWFp1_uid77_fpHypotTest_q <= "000000000000000000000000";
--fracY_uid9_fpHypotTest(BITSELECT,8)@0
fracY_uid9_fpHypotTest_in <= b(22 downto 0);
fracY_uid9_fpHypotTest_b <= fracY_uid9_fpHypotTest_in(22 downto 0);
--oFracY_uid44_uid44_fpHypotTest(BITJOIN,43)@0
oFracY_uid44_uid44_fpHypotTest_q <= VCC_q & fracY_uid9_fpHypotTest_b;
--reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0(REG,199)@0
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q <= oFracY_uid44_uid44_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--oFracYSqr_uid46_fpHypotTest(MULT,45)@1
oFracYSqr_uid46_fpHypotTest_pr <= UNSIGNED(oFracYSqr_uid46_fpHypotTest_a) * UNSIGNED(oFracYSqr_uid46_fpHypotTest_b);
oFracYSqr_uid46_fpHypotTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracYSqr_uid46_fpHypotTest_a <= (others => '0');
oFracYSqr_uid46_fpHypotTest_b <= (others => '0');
oFracYSqr_uid46_fpHypotTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracYSqr_uid46_fpHypotTest_a <= reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q;
oFracYSqr_uid46_fpHypotTest_b <= reg_oFracY_uid44_uid44_fpHypotTest_0_to_oFracYSqr_uid46_fpHypotTest_0_q;
oFracYSqr_uid46_fpHypotTest_s1 <= STD_LOGIC_VECTOR(oFracYSqr_uid46_fpHypotTest_pr);
END IF;
END IF;
END PROCESS;
oFracYSqr_uid46_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracYSqr_uid46_fpHypotTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracYSqr_uid46_fpHypotTest_q <= oFracYSqr_uid46_fpHypotTest_s1;
END IF;
END IF;
END PROCESS;
--normFracYSqrHigh_uid57_fpHypotTest(BITSELECT,56)@4
normFracYSqrHigh_uid57_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q;
normFracYSqrHigh_uid57_fpHypotTest_b <= normFracYSqrHigh_uid57_fpHypotTest_in(47 downto 24);
--normFracYSqrLow_uid58_fpHypotTest(BITSELECT,57)@4
normFracYSqrLow_uid58_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q(46 downto 0);
normFracYSqrLow_uid58_fpHypotTest_b <= normFracYSqrLow_uid58_fpHypotTest_in(46 downto 23);
--normBitYSqr_uid49_fpHypotTest(BITSELECT,48)@4
normBitYSqr_uid49_fpHypotTest_in <= oFracYSqr_uid46_fpHypotTest_q;
normBitYSqr_uid49_fpHypotTest_b <= normBitYSqr_uid49_fpHypotTest_in(47 downto 47);
--ofracQ_uid59_fpHypotTest(MUX,58)@4
ofracQ_uid59_fpHypotTest_s <= normBitYSqr_uid49_fpHypotTest_b;
ofracQ_uid59_fpHypotTest: PROCESS (ofracQ_uid59_fpHypotTest_s, en, normFracYSqrLow_uid58_fpHypotTest_b, normFracYSqrHigh_uid57_fpHypotTest_b)
BEGIN
CASE ofracQ_uid59_fpHypotTest_s IS
WHEN "0" => ofracQ_uid59_fpHypotTest_q <= normFracYSqrLow_uid58_fpHypotTest_b;
WHEN "1" => ofracQ_uid59_fpHypotTest_q <= normFracYSqrHigh_uid57_fpHypotTest_b;
WHEN OTHERS => ofracQ_uid59_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c(DELAY,305)@4
ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ofracQ_uid59_fpHypotTest_q, xout => ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q, ena => en(0), clk => clk, aclr => areset );
--fracX_uid8_fpHypotTest(BITSELECT,7)@0
fracX_uid8_fpHypotTest_in <= a(22 downto 0);
fracX_uid8_fpHypotTest_b <= fracX_uid8_fpHypotTest_in(22 downto 0);
--oFracX_uid43_uid43_fpHypotTest(BITJOIN,42)@0
oFracX_uid43_uid43_fpHypotTest_q <= VCC_q & fracX_uid8_fpHypotTest_b;
--reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0(REG,197)@0
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q <= oFracX_uid43_uid43_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--oFracXSqr_uid45_fpHypotTest(MULT,44)@1
oFracXSqr_uid45_fpHypotTest_pr <= UNSIGNED(oFracXSqr_uid45_fpHypotTest_a) * UNSIGNED(oFracXSqr_uid45_fpHypotTest_b);
oFracXSqr_uid45_fpHypotTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracXSqr_uid45_fpHypotTest_a <= (others => '0');
oFracXSqr_uid45_fpHypotTest_b <= (others => '0');
oFracXSqr_uid45_fpHypotTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracXSqr_uid45_fpHypotTest_a <= reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q;
oFracXSqr_uid45_fpHypotTest_b <= reg_oFracX_uid43_uid43_fpHypotTest_0_to_oFracXSqr_uid45_fpHypotTest_0_q;
oFracXSqr_uid45_fpHypotTest_s1 <= STD_LOGIC_VECTOR(oFracXSqr_uid45_fpHypotTest_pr);
END IF;
END IF;
END PROCESS;
oFracXSqr_uid45_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracXSqr_uid45_fpHypotTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oFracXSqr_uid45_fpHypotTest_q <= oFracXSqr_uid45_fpHypotTest_s1;
END IF;
END IF;
END PROCESS;
--normFracXSqrHigh_uid54_fpHypotTest(BITSELECT,53)@4
normFracXSqrHigh_uid54_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q;
normFracXSqrHigh_uid54_fpHypotTest_b <= normFracXSqrHigh_uid54_fpHypotTest_in(47 downto 24);
--normFracXSqrLow_uid55_fpHypotTest(BITSELECT,54)@4
normFracXSqrLow_uid55_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q(46 downto 0);
normFracXSqrLow_uid55_fpHypotTest_b <= normFracXSqrLow_uid55_fpHypotTest_in(46 downto 23);
--normBitXSqr_uid48_fpHypotTest(BITSELECT,47)@4
normBitXSqr_uid48_fpHypotTest_in <= oFracXSqr_uid45_fpHypotTest_q;
normBitXSqr_uid48_fpHypotTest_b <= normBitXSqr_uid48_fpHypotTest_in(47 downto 47);
--ofracP_uid56_fpHypotTest(MUX,55)@4
ofracP_uid56_fpHypotTest_s <= normBitXSqr_uid48_fpHypotTest_b;
ofracP_uid56_fpHypotTest: PROCESS (ofracP_uid56_fpHypotTest_s, en, normFracXSqrLow_uid55_fpHypotTest_b, normFracXSqrHigh_uid54_fpHypotTest_b)
BEGIN
CASE ofracP_uid56_fpHypotTest_s IS
WHEN "0" => ofracP_uid56_fpHypotTest_q <= normFracXSqrLow_uid55_fpHypotTest_b;
WHEN "1" => ofracP_uid56_fpHypotTest_q <= normFracXSqrHigh_uid54_fpHypotTest_b;
WHEN OTHERS => ofracP_uid56_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d(DELAY,306)@4
ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ofracP_uid56_fpHypotTest_q, xout => ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--expY_uid7_fpHypotTest(BITSELECT,6)@0
expY_uid7_fpHypotTest_in <= b(30 downto 0);
expY_uid7_fpHypotTest_b <= expY_uid7_fpHypotTest_in(30 downto 23);
--expXIsZero_uid30_fpHypotTest(LOGICAL,29)@0
expXIsZero_uid30_fpHypotTest_a <= expY_uid7_fpHypotTest_b;
expXIsZero_uid30_fpHypotTest_b <= cstAllZWE_uid12_fpHypotTest_q;
expXIsZero_uid30_fpHypotTest_q <= "1" when expXIsZero_uid30_fpHypotTest_a = expXIsZero_uid30_fpHypotTest_b else "0";
--ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b(DELAY,294)@0
ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => expXIsZero_uid30_fpHypotTest_q, xout => ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--bias_uid47_fpHypotTest(CONSTANT,46)
bias_uid47_fpHypotTest_q <= "1111111";
--ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg(DELAY,497)
ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid7_fpHypotTest_b, xout => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b(DELAY,278)@0
ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_inputreg_q, xout => ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expYTimes2_uid51_fpHypotTest(BITJOIN,50)@4
expYTimes2_uid51_fpHypotTest_q <= ld_expY_uid7_fpHypotTest_b_to_expYTimes2_uid51_fpHypotTest_b_q & normBitYSqr_uid49_fpHypotTest_b;
--expQ_uid53_fpHypotTest(SUB,52)@4
expQ_uid53_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & expYTimes2_uid51_fpHypotTest_q);
expQ_uid53_fpHypotTest_b <= STD_LOGIC_VECTOR("000" & bias_uid47_fpHypotTest_q);
expQ_uid53_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expQ_uid53_fpHypotTest_a) - UNSIGNED(expQ_uid53_fpHypotTest_b));
expQ_uid53_fpHypotTest_q <= expQ_uid53_fpHypotTest_o(9 downto 0);
--ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b(DELAY,292)@4
ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expQ_uid53_fpHypotTest_q, xout => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expX_uid6_fpHypotTest(BITSELECT,5)@0
expX_uid6_fpHypotTest_in <= a(30 downto 0);
expX_uid6_fpHypotTest_b <= expX_uid6_fpHypotTest_in(30 downto 23);
--ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg(DELAY,496)
ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpHypotTest_b, xout => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b(DELAY,276)@0
ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_inputreg_q, xout => ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXTimes2_uid50_fpHypotTest(BITJOIN,49)@4
expXTimes2_uid50_fpHypotTest_q <= ld_expX_uid6_fpHypotTest_b_to_expXTimes2_uid50_fpHypotTest_b_q & normBitXSqr_uid48_fpHypotTest_b;
--expP_uid52_fpHypotTest(SUB,51)@4
expP_uid52_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & expXTimes2_uid50_fpHypotTest_q);
expP_uid52_fpHypotTest_b <= STD_LOGIC_VECTOR("000" & bias_uid47_fpHypotTest_q);
expP_uid52_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expP_uid52_fpHypotTest_a) - UNSIGNED(expP_uid52_fpHypotTest_b));
expP_uid52_fpHypotTest_q <= expP_uid52_fpHypotTest_o(9 downto 0);
--reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0(REG,201)@4
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q <= expP_uid52_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--pGTEq_uid60_fpHypotTest(COMPARE,59)@5
pGTEq_uid60_fpHypotTest_cin <= GND_q;
pGTEq_uid60_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q(9)) & reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q) & '0';
pGTEq_uid60_fpHypotTest_b <= STD_LOGIC_VECTOR((11 downto 10 => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q(9)) & ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q) & pGTEq_uid60_fpHypotTest_cin(0);
pGTEq_uid60_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(pGTEq_uid60_fpHypotTest_a) - SIGNED(pGTEq_uid60_fpHypotTest_b));
pGTEq_uid60_fpHypotTest_n(0) <= not pGTEq_uid60_fpHypotTest_o(12);
--expCmpGtePQ_uid61_fpHypotTest(LOGICAL,60)@5
expCmpGtePQ_uid61_fpHypotTest_a <= pGTEq_uid60_fpHypotTest_n;
expCmpGtePQ_uid61_fpHypotTest_b <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
expCmpGtePQ_uid61_fpHypotTest_q <= expCmpGtePQ_uid61_fpHypotTest_a or expCmpGtePQ_uid61_fpHypotTest_b;
--oFracB_uid69_fpHypotTest(MUX,68)@5
oFracB_uid69_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
oFracB_uid69_fpHypotTest: PROCESS (oFracB_uid69_fpHypotTest_s, en, ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q, ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q)
BEGIN
CASE oFracB_uid69_fpHypotTest_s IS
WHEN "0" => oFracB_uid69_fpHypotTest_q <= ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q;
WHEN "1" => oFracB_uid69_fpHypotTest_q <= ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q;
WHEN OTHERS => oFracB_uid69_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c(DELAY,325)@5
ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracB_uid69_fpHypotTest_q, xout => ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cWFP2_uid66_fpHypotTest(CONSTANT,65)
cWFP2_uid66_fpHypotTest_q <= "11001";
--expDiffPQ_uid62_fpHypotTest(SUB,61)@5
expDiffPQ_uid62_fpHypotTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q(9)) & reg_expP_uid52_fpHypotTest_0_to_pGTEq_uid60_fpHypotTest_0_q);
expDiffPQ_uid62_fpHypotTest_b <= STD_LOGIC_VECTOR((10 downto 10 => ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q(9)) & ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q);
expDiffPQ_uid62_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expDiffPQ_uid62_fpHypotTest_a) - SIGNED(expDiffPQ_uid62_fpHypotTest_b));
expDiffPQ_uid62_fpHypotTest_q <= expDiffPQ_uid62_fpHypotTest_o(10 downto 0);
--ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b(DELAY,298)@4
ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expP_uid52_fpHypotTest_q, xout => ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0(REG,202)@4
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q <= expQ_uid53_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--expDiffQP_uid63_fpHypotTest(SUB,62)@5
expDiffQP_uid63_fpHypotTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q(9)) & reg_expQ_uid53_fpHypotTest_0_to_expDiffQP_uid63_fpHypotTest_0_q);
expDiffQP_uid63_fpHypotTest_b <= STD_LOGIC_VECTOR((10 downto 10 => ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q(9)) & ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q);
expDiffQP_uid63_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expDiffQP_uid63_fpHypotTest_a) - SIGNED(expDiffQP_uid63_fpHypotTest_b));
expDiffQP_uid63_fpHypotTest_q <= expDiffQP_uid63_fpHypotTest_o(10 downto 0);
--mux_uid64_fpHypotTest(MUX,63)@5
mux_uid64_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
mux_uid64_fpHypotTest: PROCESS (mux_uid64_fpHypotTest_s, en, expDiffQP_uid63_fpHypotTest_q, expDiffPQ_uid62_fpHypotTest_q)
BEGIN
CASE mux_uid64_fpHypotTest_s IS
WHEN "0" => mux_uid64_fpHypotTest_q <= expDiffQP_uid63_fpHypotTest_q;
WHEN "1" => mux_uid64_fpHypotTest_q <= expDiffPQ_uid62_fpHypotTest_q;
WHEN OTHERS => mux_uid64_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--expDiff_uid65_fpHypotTest(BITSELECT,64)@5
expDiff_uid65_fpHypotTest_in <= mux_uid64_fpHypotTest_q(9 downto 0);
expDiff_uid65_fpHypotTest_b <= expDiff_uid65_fpHypotTest_in(9 downto 0);
--reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0(REG,204)@5
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q <= expDiff_uid65_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--shiftedOut_uid67_fpHypotTest(COMPARE,66)@6
shiftedOut_uid67_fpHypotTest_cin <= GND_q;
shiftedOut_uid67_fpHypotTest_a <= STD_LOGIC_VECTOR("00" & reg_expDiff_uid65_fpHypotTest_0_to_shiftedOut_uid67_fpHypotTest_0_q) & '0';
shiftedOut_uid67_fpHypotTest_b <= STD_LOGIC_VECTOR("0000000" & cWFP2_uid66_fpHypotTest_q) & shiftedOut_uid67_fpHypotTest_cin(0);
shiftedOut_uid67_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid67_fpHypotTest_a) - UNSIGNED(shiftedOut_uid67_fpHypotTest_b));
shiftedOut_uid67_fpHypotTest_n(0) <= not shiftedOut_uid67_fpHypotTest_o(12);
--expXIsZero_uid14_fpHypotTest(LOGICAL,13)@0
expXIsZero_uid14_fpHypotTest_a <= expX_uid6_fpHypotTest_b;
expXIsZero_uid14_fpHypotTest_b <= cstAllZWE_uid12_fpHypotTest_q;
expXIsZero_uid14_fpHypotTest_q <= "1" when expXIsZero_uid14_fpHypotTest_a = expXIsZero_uid14_fpHypotTest_b else "0";
--ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d(DELAY,318)@0
ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => expXIsZero_uid14_fpHypotTest_q, xout => ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--excBZero_uid75_fpHypotTest(MUX,74)@5
excBZero_uid75_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
excBZero_uid75_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excBZero_uid75_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE excBZero_uid75_fpHypotTest_s IS
WHEN "0" => excBZero_uid75_fpHypotTest_q <= ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q;
WHEN "1" => excBZero_uid75_fpHypotTest_q <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
WHEN OTHERS => excBZero_uid75_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--oFracBFlushToZero_uid76_fpHypotTest(LOGICAL,75)@6
oFracBFlushToZero_uid76_fpHypotTest_a <= excBZero_uid75_fpHypotTest_q;
oFracBFlushToZero_uid76_fpHypotTest_b <= shiftedOut_uid67_fpHypotTest_n;
oFracBFlushToZero_uid76_fpHypotTest_q <= oFracBFlushToZero_uid76_fpHypotTest_a or oFracBFlushToZero_uid76_fpHypotTest_b;
--oFracBPostExc_uid78_fpHypotTest(MUX,77)@6
oFracBPostExc_uid78_fpHypotTest_s <= oFracBFlushToZero_uid76_fpHypotTest_q;
oFracBPostExc_uid78_fpHypotTest: PROCESS (oFracBPostExc_uid78_fpHypotTest_s, en, ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q, zerosWFp1_uid77_fpHypotTest_q)
BEGIN
CASE oFracBPostExc_uid78_fpHypotTest_s IS
WHEN "0" => oFracBPostExc_uid78_fpHypotTest_q <= ld_oFracB_uid69_fpHypotTest_q_to_oFracBPostExc_uid78_fpHypotTest_c_q;
WHEN "1" => oFracBPostExc_uid78_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q;
WHEN OTHERS => oFracBPostExc_uid78_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--oFracBPostExcG_uid80_fpHypotTest(BITJOIN,79)@6
oFracBPostExcG_uid80_fpHypotTest_q <= oFracBPostExc_uid78_fpHypotTest_q & GND_q;
--X24dto24_uid151_alignShift_uid81_fpHypotTest(BITSELECT,150)@6
X24dto24_uid151_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto24_uid151_alignShift_uid81_fpHypotTest_b <= X24dto24_uid151_alignShift_uid81_fpHypotTest_in(24 downto 24);
--rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest(BITJOIN,152)@6
rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q & X24dto24_uid151_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5(REG,210)@6
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q <= rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest(CONSTANT,148)
rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q <= "0000000000000000";
--X24dto16_uid148_alignShift_uid81_fpHypotTest(BITSELECT,147)@6
X24dto16_uid148_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto16_uid148_alignShift_uid81_fpHypotTest_b <= X24dto16_uid148_alignShift_uid81_fpHypotTest_in(24 downto 16);
--rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest(BITJOIN,149)@6
rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q <= rightShiftStage0Idx2Pad16_uid149_alignShift_uid81_fpHypotTest_q & X24dto16_uid148_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4(REG,209)@6
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q <= rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--X24dto8_uid145_alignShift_uid81_fpHypotTest(BITSELECT,144)@6
X24dto8_uid145_alignShift_uid81_fpHypotTest_in <= oFracBPostExcG_uid80_fpHypotTest_q;
X24dto8_uid145_alignShift_uid81_fpHypotTest_b <= X24dto8_uid145_alignShift_uid81_fpHypotTest_in(24 downto 8);
--rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest(BITJOIN,146)@6
rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q <= cstAllZWE_uid12_fpHypotTest_q & X24dto8_uid145_alignShift_uid81_fpHypotTest_b;
--reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3(REG,208)@6
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q <= rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2(REG,207)@6
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q <= oFracBPostExcG_uid80_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--z_uid71_fpHypotTest(CONSTANT,70)
z_uid71_fpHypotTest_q <= "00000";
--expDiffShiftRange_uid72_fpHypotTest(BITSELECT,71)@5
expDiffShiftRange_uid72_fpHypotTest_in <= expDiff_uid65_fpHypotTest_b(4 downto 0);
expDiffShiftRange_uid72_fpHypotTest_b <= expDiffShiftRange_uid72_fpHypotTest_in(4 downto 0);
--reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2(REG,205)@5
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q <= expDiffShiftRange_uid72_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid73_fpHypotTest(MUX,72)@6
shiftValue_uid73_fpHypotTest_s <= shiftedOut_uid67_fpHypotTest_n;
shiftValue_uid73_fpHypotTest: PROCESS (shiftValue_uid73_fpHypotTest_s, en, reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q, z_uid71_fpHypotTest_q)
BEGIN
CASE shiftValue_uid73_fpHypotTest_s IS
WHEN "0" => shiftValue_uid73_fpHypotTest_q <= reg_expDiffShiftRange_uid72_fpHypotTest_0_to_shiftValue_uid73_fpHypotTest_2_q;
WHEN "1" => shiftValue_uid73_fpHypotTest_q <= z_uid71_fpHypotTest_q;
WHEN OTHERS => shiftValue_uid73_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest(BITSELECT,153)@6
rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q;
rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1(REG,206)@6
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q <= rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid155_alignShift_uid81_fpHypotTest(MUX,154)@7
rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s <= reg_rightShiftStageSel4Dto3_uid154_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_1_q;
rightShiftStage0_uid155_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s, en, reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q, reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q, reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q, reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q)
BEGIN
CASE rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_s IS
WHEN "00" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_oFracBPostExcG_uid80_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_2_q;
WHEN "01" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx1_uid147_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_3_q;
WHEN "10" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx2_uid150_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_4_q;
WHEN "11" => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0Idx3_uid153_alignShift_uid81_fpHypotTest_0_to_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_5_q;
WHEN OTHERS => rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest(BITSELECT,161)@7
RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a(DELAY,424)@7
ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest(BITJOIN,163)@8
rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx3Pad6_uid163_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto6_uid162_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_a_q;
--rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest(CONSTANT,159)
rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q <= "0000";
--RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest(BITSELECT,158)@7
RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a(DELAY,422)@7
ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest(BITJOIN,160)@8
rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx2Pad4_uid160_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto4_uid159_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_a_q;
--rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest(CONSTANT,156)
rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q <= "00";
--RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest(BITSELECT,155)@7
RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b <= RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a(DELAY,420)@7
ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b, xout => ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest(BITJOIN,157)@8
rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx1Pad2_uid157_alignShift_uid81_fpHypotTest_q & ld_RightShiftStage024dto2_uid156_alignShift_uid81_fpHypotTest_b_to_rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_a_q;
--reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2(REG,212)@7
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q <= rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest(BITSELECT,164)@6
rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q(2 downto 0);
rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1(REG,211)@6
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q <= rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b(DELAY,426)@7
ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid166_alignShift_uid81_fpHypotTest(MUX,165)@8
rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s <= ld_reg_rightShiftStageSel2Dto1_uid165_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_1_q_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_b_q;
rightShiftStage1_uid166_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s, en, reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q, rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q, rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q, rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q)
BEGIN
CASE rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_s IS
WHEN "00" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= reg_rightShiftStage0_uid155_alignShift_uid81_fpHypotTest_0_to_rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_2_q;
WHEN "01" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx1_uid158_alignShift_uid81_fpHypotTest_q;
WHEN "10" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx2_uid161_alignShift_uid81_fpHypotTest_q;
WHEN "11" => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= rightShiftStage1Idx3_uid164_alignShift_uid81_fpHypotTest_q;
WHEN OTHERS => rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest(BITSELECT,169)@6
rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in <= shiftValue_uid73_fpHypotTest_q(0 downto 0);
rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b <= rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a(DELAY,475)@6
ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b, xout => ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1(REG,213)@7
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q <= ld_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_b_to_reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid171_alignShift_uid81_fpHypotTest(MUX,170)@8
rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s <= reg_rightShiftStageSel0Dto0_uid170_alignShift_uid81_fpHypotTest_0_to_rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_1_q;
rightShiftStage2_uid171_alignShift_uid81_fpHypotTest: PROCESS (rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s, en, rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q, rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q)
BEGIN
CASE rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_s IS
WHEN "0" => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= rightShiftStage1_uid166_alignShift_uid81_fpHypotTest_q;
WHEN "1" => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= rightShiftStage2Idx1_uid169_alignShift_uid81_fpHypotTest_q;
WHEN OTHERS => rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--highBBits_uid83_fpHypotTest(BITSELECT,82)@8
highBBits_uid83_fpHypotTest_in <= rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q;
highBBits_uid83_fpHypotTest_b <= highBBits_uid83_fpHypotTest_in(24 downto 1);
--reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1(REG,214)@8
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q <= highBBits_uid83_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--oFracA_uid68_fpHypotTest(MUX,67)@5
oFracA_uid68_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
oFracA_uid68_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracA_uid68_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oFracA_uid68_fpHypotTest_s IS
WHEN "0" => oFracA_uid68_fpHypotTest_q <= ld_ofracQ_uid59_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_c_q;
WHEN "1" => oFracA_uid68_fpHypotTest_q <= ld_ofracP_uid56_fpHypotTest_q_to_oFracA_uid68_fpHypotTest_d_q;
WHEN OTHERS => oFracA_uid68_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--excAZero_uid74_fpHypotTest(MUX,73)@5
excAZero_uid74_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
excAZero_uid74_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excAZero_uid74_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE excAZero_uid74_fpHypotTest_s IS
WHEN "0" => excAZero_uid74_fpHypotTest_q <= ld_expXIsZero_uid30_fpHypotTest_q_to_expCmpGtePQ_uid61_fpHypotTest_b_q;
WHEN "1" => excAZero_uid74_fpHypotTest_q <= ld_expXIsZero_uid14_fpHypotTest_q_to_excAZero_uid74_fpHypotTest_d_q;
WHEN OTHERS => excAZero_uid74_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--oFracAPostExc_uid79_fpHypotTest(MUX,78)@6
oFracAPostExc_uid79_fpHypotTest_s <= excAZero_uid74_fpHypotTest_q;
oFracAPostExc_uid79_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oFracAPostExc_uid79_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oFracAPostExc_uid79_fpHypotTest_s IS
WHEN "0" => oFracAPostExc_uid79_fpHypotTest_q <= oFracA_uid68_fpHypotTest_q;
WHEN "1" => oFracAPostExc_uid79_fpHypotTest_q <= zerosWFp1_uid77_fpHypotTest_q;
WHEN OTHERS => oFracAPostExc_uid79_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a(DELAY,331)@7
ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => oFracAPostExc_uid79_fpHypotTest_q, xout => ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid84_fpHypotTest(ADD,83)@9
sumAHighB_uid84_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & ld_oFracAPostExc_uid79_fpHypotTest_q_to_sumAHighB_uid84_fpHypotTest_a_q);
sumAHighB_uid84_fpHypotTest_b <= STD_LOGIC_VECTOR("0" & reg_highBBits_uid83_fpHypotTest_0_to_sumAHighB_uid84_fpHypotTest_1_q);
sumAHighB_uid84_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sumAHighB_uid84_fpHypotTest_a) + UNSIGNED(sumAHighB_uid84_fpHypotTest_b));
sumAHighB_uid84_fpHypotTest_q <= sumAHighB_uid84_fpHypotTest_o(24 downto 0);
--lowRangeB_uid82_fpHypotTest(BITSELECT,81)@8
lowRangeB_uid82_fpHypotTest_in <= rightShiftStage2_uid171_alignShift_uid81_fpHypotTest_q(0 downto 0);
lowRangeB_uid82_fpHypotTest_b <= lowRangeB_uid82_fpHypotTest_in(0 downto 0);
--reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0(REG,215)@8
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q <= lowRangeB_uid82_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--soSPreNorm_uid82_uid85_fpHypotTest(BITJOIN,84)@9
soSPreNorm_uid82_uid85_fpHypotTest_q <= sumAHighB_uid84_fpHypotTest_q & reg_lowRangeB_uid82_fpHypotTest_0_to_soSPreNorm_uid82_uid85_fpHypotTest_0_q;
--FullSumAB25_uid86_fpHypotTest(BITSELECT,85)@9
FullSumAB25_uid86_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q;
FullSumAB25_uid86_fpHypotTest_b <= FullSumAB25_uid86_fpHypotTest_in(25 downto 25);
--soSRangeHigh_uid87_fpHypotTest(BITSELECT,86)@9
soSRangeHigh_uid87_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q(24 downto 0);
soSRangeHigh_uid87_fpHypotTest_b <= soSRangeHigh_uid87_fpHypotTest_in(24 downto 1);
--soSRangeLow_uid88_fpHypotTest(BITSELECT,87)@9
soSRangeLow_uid88_fpHypotTest_in <= soSPreNorm_uid82_uid85_fpHypotTest_q(23 downto 0);
soSRangeLow_uid88_fpHypotTest_b <= soSRangeLow_uid88_fpHypotTest_in(23 downto 0);
--resFracNorm_uid89_fpHypotTest(MUX,88)@9
resFracNorm_uid89_fpHypotTest_s <= FullSumAB25_uid86_fpHypotTest_b;
resFracNorm_uid89_fpHypotTest: PROCESS (resFracNorm_uid89_fpHypotTest_s, en, soSRangeLow_uid88_fpHypotTest_b, soSRangeHigh_uid87_fpHypotTest_b)
BEGIN
CASE resFracNorm_uid89_fpHypotTest_s IS
WHEN "0" => resFracNorm_uid89_fpHypotTest_q <= soSRangeLow_uid88_fpHypotTest_b;
WHEN "1" => resFracNorm_uid89_fpHypotTest_q <= soSRangeHigh_uid87_fpHypotTest_b;
WHEN OTHERS => resFracNorm_uid89_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--normCatFracSoS_uid93_uid93_fpHypotTest(BITJOIN,92)@9
normCatFracSoS_uid93_uid93_fpHypotTest_q <= FullSumAB25_uid86_fpHypotTest_b & resFracNorm_uid89_fpHypotTest_q;
--reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1(REG,217)@9
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q <= normCatFracSoS_uid93_uid93_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable(LOGICAL,505)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q <= not ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_a;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor(LOGICAL,506)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q <= not (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_a or ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_b);
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg(REG,504)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena(REG,507)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_nor_q = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd(LOGICAL,508)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_sticky_ena_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_a and ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_b;
--expA_uid70_fpHypotTest(MUX,69)@5
expA_uid70_fpHypotTest_s <= expCmpGtePQ_uid61_fpHypotTest_q;
expA_uid70_fpHypotTest: PROCESS (expA_uid70_fpHypotTest_s, en, ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q, ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q)
BEGIN
CASE expA_uid70_fpHypotTest_s IS
WHEN "0" => expA_uid70_fpHypotTest_q <= ld_expQ_uid53_fpHypotTest_q_to_pGTEq_uid60_fpHypotTest_b_q;
WHEN "1" => expA_uid70_fpHypotTest_q <= ld_expP_uid52_fpHypotTest_q_to_expDiffQP_uid63_fpHypotTest_b_q;
WHEN OTHERS => expA_uid70_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg(DELAY,498)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expA_uid70_fpHypotTest_q, xout => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt(COUNTER,500)
-- every=1, low=0, high=1, step=1, init=1
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_i,1));
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg(REG,501)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux(MUX,502)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s <= en;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux: PROCESS (ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s, ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q, ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q)
BEGIN
CASE ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_s IS
WHEN "0" => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
WHEN "1" => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem(DUALMEM,499)
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_inputreg_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 1,
numwords_a => 2,
width_b => 10,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq,
address_a => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_aa,
data_a => ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_ia
);
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_iq(9 downto 0);
--cstAllZWF_uid11_fpHypotTest(CONSTANT,10)
cstAllZWF_uid11_fpHypotTest_q <= "00000000000000000000000";
--expCatRndBit_uid91_uid92_fpHypotTest(BITJOIN,91)@9
expCatRndBit_uid91_uid92_fpHypotTest_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_mem_q & cstAllZWF_uid11_fpHypotTest_q & VCC_q;
--reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0(REG,216)@9
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q <= expCatRndBit_uid91_uid92_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostNorm_uid94_fpHypotTest(ADD,93)@10
expFracPostNorm_uid94_fpHypotTest_a <= STD_LOGIC_VECTOR((35 downto 34 => reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q(33)) & reg_expCatRndBit_uid91_uid92_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_0_q);
expFracPostNorm_uid94_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_normCatFracSoS_uid93_uid93_fpHypotTest_0_to_expFracPostNorm_uid94_fpHypotTest_1_q);
expFracPostNorm_uid94_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostNorm_uid94_fpHypotTest_a) + SIGNED(expFracPostNorm_uid94_fpHypotTest_b));
expFracPostNorm_uid94_fpHypotTest_q <= expFracPostNorm_uid94_fpHypotTest_o(34 downto 0);
--expRPreSqrt_uid96_fpHypotTest(BITSELECT,95)@10
expRPreSqrt_uid96_fpHypotTest_in <= expFracPostNorm_uid94_fpHypotTest_q(33 downto 0);
expRPreSqrt_uid96_fpHypotTest_b <= expRPreSqrt_uid96_fpHypotTest_in(33 downto 24);
--ExpRPreSqrt0_uid102_fpHypotTest(BITSELECT,101)@10
ExpRPreSqrt0_uid102_fpHypotTest_in <= expRPreSqrt_uid96_fpHypotTest_b(0 downto 0);
ExpRPreSqrt0_uid102_fpHypotTest_b <= ExpRPreSqrt0_uid102_fpHypotTest_in(0 downto 0);
--expOddSelect_uid103_fpHypotTest(LOGICAL,102)@10
expOddSelect_uid103_fpHypotTest_a <= ExpRPreSqrt0_uid102_fpHypotTest_b;
expOddSelect_uid103_fpHypotTest_q <= not expOddSelect_uid103_fpHypotTest_a;
--fracRPreSqrt_uid95_fpHypotTest(BITSELECT,94)@10
fracRPreSqrt_uid95_fpHypotTest_in <= expFracPostNorm_uid94_fpHypotTest_q(23 downto 0);
fracRPreSqrt_uid95_fpHypotTest_b <= fracRPreSqrt_uid95_fpHypotTest_in(23 downto 1);
--fracXAddr_uid106_fpHypotTest(BITSELECT,105)@10
fracXAddr_uid106_fpHypotTest_in <= fracRPreSqrt_uid95_fpHypotTest_b;
fracXAddr_uid106_fpHypotTest_b <= fracXAddr_uid106_fpHypotTest_in(22 downto 16);
--addrTable_uid107_fpHypotTest(BITJOIN,106)@10
addrTable_uid107_fpHypotTest_q <= expOddSelect_uid103_fpHypotTest_q & fracXAddr_uid106_fpHypotTest_b;
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0(REG,220)@10
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q <= addrTable_uid107_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid175_sqrtTableGenerator_lutmem(DUALMEM,196)@11
memoryC2_uid175_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid175_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid175_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC2_uid175_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid175_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC2_uid175_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid175_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid175_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid175_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid175_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid175_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid175_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid175_sqrtTableGenerator_lutmem_q <= memoryC2_uid175_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1(REG,222)@13
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q <= memoryC2_uid175_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg(DELAY,509)
ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRPreSqrt_uid95_fpHypotTest_b, xout => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a(DELAY,360)@10
ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_inputreg_q, xout => ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracRPreSqrt15dto0_uid108_fpHypotTest(BITSELECT,107)@13
FracRPreSqrt15dto0_uid108_fpHypotTest_in <= ld_fracRPreSqrt_uid95_fpHypotTest_b_to_FracRPreSqrt15dto0_uid108_fpHypotTest_a_q(15 downto 0);
FracRPreSqrt15dto0_uid108_fpHypotTest_b <= FracRPreSqrt15dto0_uid108_fpHypotTest_in(15 downto 0);
--yT1_uid176_sqrtPolynomialEvaluator(BITSELECT,175)@13
yT1_uid176_sqrtPolynomialEvaluator_in <= FracRPreSqrt15dto0_uid108_fpHypotTest_b;
yT1_uid176_sqrtPolynomialEvaluator_b <= yT1_uid176_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0(REG,221)@13
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q <= yT1_uid176_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator(MULT,188)@14
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b);
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_a <= reg_yT1_uid176_sqrtPolynomialEvaluator_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_0_q;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid175_sqrtTableGenerator_lutmem_0_to_prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_1_q;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q <= prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator(BITSELECT,189)@17
prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in <= prodXY_uid189_pT1_uid177_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid179_sqrtPolynomialEvaluator(BITSELECT,178)@17
highBBits_uid179_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b;
highBBits_uid179_sqrtPolynomialEvaluator_b <= highBBits_uid179_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a(DELAY,485)@10
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid107_fpHypotTest_q, xout => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0(REG,223)@13
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid174_sqrtTableGenerator_lutmem(DUALMEM,195)@14
memoryC1_uid174_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid174_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid174_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC1_uid174_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid174_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC1_uid174_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid174_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid174_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid174_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid174_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid174_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid174_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid174_sqrtTableGenerator_lutmem_q <= memoryC1_uid174_sqrtTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0(REG,224)@16
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q <= memoryC1_uid174_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid180_sqrtPolynomialEvaluator(ADD,179)@17
sumAHighB_uid180_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q(20)) & reg_memoryC1_uid174_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid180_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid180_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid179_sqrtPolynomialEvaluator_b(11)) & highBBits_uid179_sqrtPolynomialEvaluator_b);
sumAHighB_uid180_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid180_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid180_sqrtPolynomialEvaluator_b));
sumAHighB_uid180_sqrtPolynomialEvaluator_q <= sumAHighB_uid180_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid178_sqrtPolynomialEvaluator(BITSELECT,177)@17
lowRangeB_uid178_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid190_pT1_uid177_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid178_sqrtPolynomialEvaluator_b <= lowRangeB_uid178_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid178_uid181_sqrtPolynomialEvaluator(BITJOIN,180)@17
s1_uid178_uid181_sqrtPolynomialEvaluator_q <= sumAHighB_uid180_sqrtPolynomialEvaluator_q & lowRangeB_uid178_sqrtPolynomialEvaluator_b;
--reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1(REG,226)@17
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q <= s1_uid178_uid181_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor(LOGICAL,636)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_b);
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena(REG,637)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,638)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0(REG,225)@13
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q <= FracRPreSqrt15dto0_uid108_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg(DELAY,628)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q, xout => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,629)
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_inputreg_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdreg_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_replace_rdmux_q;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator(MULT,191)@18
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b);
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a <= ld_reg_FracRPreSqrt15dto0_uid108_fpHypotTest_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_0_q_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_b <= reg_s1_uid178_uid181_sqrtPolynomialEvaluator_0_to_prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_1_q;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q <= prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator(BITSELECT,192)@21
prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in <= prodXY_uid192_pT2_uid183_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid185_sqrtPolynomialEvaluator(BITSELECT,184)@21
highBBits_uid185_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b;
highBBits_uid185_sqrtPolynomialEvaluator_b <= highBBits_uid185_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,649)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,645)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "0100";
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,646)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,647)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,650)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,651)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,639)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid107_fpHypotTest_q, xout => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=4, step=1, init=1
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 3 THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 4;
ELSE
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,3));
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,642)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,643)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,640)
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0(REG,227)@17
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid107_fpHypotTest_q_to_reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid173_sqrtTableGenerator_lutmem(DUALMEM,194)@18
memoryC0_uid173_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid173_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid173_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid107_fpHypotTest_0_to_memoryC0_uid173_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid173_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_hypot_s5_memoryC0_uid173_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid173_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid173_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid173_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid173_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid173_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid173_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid173_sqrtTableGenerator_lutmem_q <= memoryC0_uid173_sqrtTableGenerator_lutmem_iq(28 downto 0);
--reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0(REG,228)@20
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q <= memoryC0_uid173_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid186_sqrtPolynomialEvaluator(ADD,185)@21
sumAHighB_uid186_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q(28)) & reg_memoryC0_uid173_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid186_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid186_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid185_sqrtPolynomialEvaluator_b(21)) & highBBits_uid185_sqrtPolynomialEvaluator_b);
sumAHighB_uid186_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid186_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid186_sqrtPolynomialEvaluator_b));
sumAHighB_uid186_sqrtPolynomialEvaluator_q <= sumAHighB_uid186_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid184_sqrtPolynomialEvaluator(BITSELECT,183)@21
lowRangeB_uid184_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid193_pT2_uid183_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid184_sqrtPolynomialEvaluator_b <= lowRangeB_uid184_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid184_uid187_sqrtPolynomialEvaluator(BITJOIN,186)@21
s2_uid184_uid187_sqrtPolynomialEvaluator_q <= sumAHighB_uid186_sqrtPolynomialEvaluator_q & lowRangeB_uid184_sqrtPolynomialEvaluator_b;
--fracRPreInc_uid110_fpHypotTest(BITSELECT,109)@21
fracRPreInc_uid110_fpHypotTest_in <= s2_uid184_uid187_sqrtPolynomialEvaluator_q(29 downto 0);
fracRPreInc_uid110_fpHypotTest_b <= fracRPreInc_uid110_fpHypotTest_in(29 downto 5);
--reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0(REG,229)@21
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q <= fracRPreInc_uid110_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostInc_uid111_fpHypotTest(ADD,110)@22
fracRPostInc_uid111_fpHypotTest_a <= STD_LOGIC_VECTOR("0" & reg_fracRPreInc_uid110_fpHypotTest_0_to_fracRPostInc_uid111_fpHypotTest_0_q);
fracRPostInc_uid111_fpHypotTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000" & VCC_q);
fracRPostInc_uid111_fpHypotTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracRPostInc_uid111_fpHypotTest_a) + UNSIGNED(fracRPostInc_uid111_fpHypotTest_b));
fracRPostInc_uid111_fpHypotTest_q <= fracRPostInc_uid111_fpHypotTest_o(25 downto 0);
--fracRPostIncMSBU_uid113_fpHypotTest(BITSELECT,112)@22
fracRPostIncMSBU_uid113_fpHypotTest_in <= fracRPostInc_uid111_fpHypotTest_q;
fracRPostIncMSBU_uid113_fpHypotTest_b <= fracRPostIncMSBU_uid113_fpHypotTest_in(25 downto 25);
--reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1(REG,230)@22
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q <= fracRPostIncMSBU_uid113_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor(LOGICAL,520)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q <= not (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_a or ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_b);
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top(CONSTANT,516)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q <= "01000";
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp(LOGICAL,517)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_mem_top_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q <= "1" when ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_a = ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_b else "0";
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg(REG,518)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena(REG,521)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_nor_q = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd(LOGICAL,522)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_sticky_ena_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b <= en;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_a and ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_b;
--biasP1Signal_uid99_fpHypotTest(CONSTANT,98)
biasP1Signal_uid99_fpHypotTest_q <= "1111110";
--reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0(REG,218)@10
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q <= expRPreSqrt_uid96_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid100_fpHypotTest(ADD,99)@11
expOddSig_uid100_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q(9)) & reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q);
expOddSig_uid100_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & biasP1Signal_uid99_fpHypotTest_q);
expOddSig_uid100_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expOddSig_uid100_fpHypotTest_a) + SIGNED(expOddSig_uid100_fpHypotTest_b));
expOddSig_uid100_fpHypotTest_q <= expOddSig_uid100_fpHypotTest_o(10 downto 0);
--expROdd_uid101_fpHypotTest(BITSELECT,100)@11
expROdd_uid101_fpHypotTest_in <= expOddSig_uid100_fpHypotTest_q;
expROdd_uid101_fpHypotTest_b <= expROdd_uid101_fpHypotTest_in(10 downto 1);
--expSumOfSquaresUnbiased_uid97_fpHypotTest(ADD,96)@11
expSumOfSquaresUnbiased_uid97_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q(9)) & reg_expRPreSqrt_uid96_fpHypotTest_0_to_expSumOfSquaresUnbiased_uid97_fpHypotTest_0_q);
expSumOfSquaresUnbiased_uid97_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & bias_uid47_fpHypotTest_q);
expSumOfSquaresUnbiased_uid97_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumOfSquaresUnbiased_uid97_fpHypotTest_a) + SIGNED(expSumOfSquaresUnbiased_uid97_fpHypotTest_b));
expSumOfSquaresUnbiased_uid97_fpHypotTest_q <= expSumOfSquaresUnbiased_uid97_fpHypotTest_o(10 downto 0);
--expREven_uid98_fpHypotTest(BITSELECT,97)@11
expREven_uid98_fpHypotTest_in <= expSumOfSquaresUnbiased_uid97_fpHypotTest_q;
expREven_uid98_fpHypotTest_b <= expREven_uid98_fpHypotTest_in(10 downto 1);
--ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b(DELAY,354)@10
ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid103_fpHypotTest_q, xout => ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid104_fpHypotTest(MUX,103)@11
expRMux_uid104_fpHypotTest_s <= ld_expOddSelect_uid103_fpHypotTest_q_to_expRMux_uid104_fpHypotTest_b_q;
expRMux_uid104_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid104_fpHypotTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid104_fpHypotTest_s IS
WHEN "0" => expRMux_uid104_fpHypotTest_q <= expREven_uid98_fpHypotTest_b;
WHEN "1" => expRMux_uid104_fpHypotTest_q <= expROdd_uid101_fpHypotTest_b;
WHEN OTHERS => expRMux_uid104_fpHypotTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg(DELAY,510)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expRMux_uid104_fpHypotTest_q, xout => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt(COUNTER,512)
-- every=1, low=0, high=8, step=1, init=1
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i = 7 THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_eq = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i - 8;
ELSE
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_i,4));
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg(REG,513)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux(MUX,514)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s <= en;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux: PROCESS (ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s, ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q, ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_s IS
WHEN "0" => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q;
WHEN "1" => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem(DUALMEM,511)
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_inputreg_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdreg_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_rdmux_q;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 4,
numwords_a => 9,
width_b => 10,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq,
address_a => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_aa,
data_a => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_ia
);
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q <= ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_iq(9 downto 0);
--expRPostInc_uid114_fpHypotTest(ADD,113)@23
expRPostInc_uid114_fpHypotTest_a <= STD_LOGIC_VECTOR((11 downto 10 => ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q(9)) & ld_expRMux_uid104_fpHypotTest_q_to_expRPostInc_uid114_fpHypotTest_a_replace_mem_q);
expRPostInc_uid114_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_fracRPostIncMSBU_uid113_fpHypotTest_0_to_expRPostInc_uid114_fpHypotTest_1_q);
expRPostInc_uid114_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostInc_uid114_fpHypotTest_a) + SIGNED(expRPostInc_uid114_fpHypotTest_b));
expRPostInc_uid114_fpHypotTest_q <= expRPostInc_uid114_fpHypotTest_o(10 downto 0);
--expRPreExc_uid139_fpHypotTest(BITSELECT,138)@23
expRPreExc_uid139_fpHypotTest_in <= expRPostInc_uid114_fpHypotTest_q(7 downto 0);
expRPreExc_uid139_fpHypotTest_b <= expRPreExc_uid139_fpHypotTest_in(7 downto 0);
--ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d(DELAY,404)@23
ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid139_fpHypotTest_b, xout => ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid12_fpHypotTest(CONSTANT,11)
cstAllZWE_uid12_fpHypotTest_q <= "00000000";
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor(LOGICAL,624)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q <= not (ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_a or ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_b);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top(CONSTANT,529)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q <= "010101";
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp(LOGICAL,530)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_mem_top_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q <= "1" when ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_a = ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_b else "0";
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg(REG,531)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena(REG,625)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_nor_q = "1") THEN
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd(LOGICAL,626)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_sticky_ena_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b <= en;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_a and ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_b;
--fracXIsZero_uid18_fpHypotTest(LOGICAL,17)@0
fracXIsZero_uid18_fpHypotTest_a <= fracX_uid8_fpHypotTest_b;
fracXIsZero_uid18_fpHypotTest_b <= cstAllZWF_uid11_fpHypotTest_q;
fracXIsZero_uid18_fpHypotTest_q <= "1" when fracXIsZero_uid18_fpHypotTest_a = fracXIsZero_uid18_fpHypotTest_b else "0";
--expXIsMax_uid16_fpHypotTest(LOGICAL,15)@0
expXIsMax_uid16_fpHypotTest_a <= expX_uid6_fpHypotTest_b;
expXIsMax_uid16_fpHypotTest_b <= cstAllOWE_uid10_fpHypotTest_q;
expXIsMax_uid16_fpHypotTest_q <= "1" when expXIsMax_uid16_fpHypotTest_a = expXIsMax_uid16_fpHypotTest_b else "0";
--exc_I_uid19_fpHypotTest(LOGICAL,18)@0
exc_I_uid19_fpHypotTest_a <= expXIsMax_uid16_fpHypotTest_q;
exc_I_uid19_fpHypotTest_b <= fracXIsZero_uid18_fpHypotTest_q;
exc_I_uid19_fpHypotTest_q <= exc_I_uid19_fpHypotTest_a and exc_I_uid19_fpHypotTest_b;
--InvExc_I_uid23_fpHypotTest(LOGICAL,22)@0
InvExc_I_uid23_fpHypotTest_a <= exc_I_uid19_fpHypotTest_q;
InvExc_I_uid23_fpHypotTest_q <= not InvExc_I_uid23_fpHypotTest_a;
--fracXIsZero_uid34_fpHypotTest(LOGICAL,33)@0
fracXIsZero_uid34_fpHypotTest_a <= fracY_uid9_fpHypotTest_b;
fracXIsZero_uid34_fpHypotTest_b <= cstAllZWF_uid11_fpHypotTest_q;
fracXIsZero_uid34_fpHypotTest_q <= "1" when fracXIsZero_uid34_fpHypotTest_a = fracXIsZero_uid34_fpHypotTest_b else "0";
--InvFracXIsZero_uid36_fpHypotTest(LOGICAL,35)@0
InvFracXIsZero_uid36_fpHypotTest_a <= fracXIsZero_uid34_fpHypotTest_q;
InvFracXIsZero_uid36_fpHypotTest_q <= not InvFracXIsZero_uid36_fpHypotTest_a;
--expXIsMax_uid32_fpHypotTest(LOGICAL,31)@0
expXIsMax_uid32_fpHypotTest_a <= expY_uid7_fpHypotTest_b;
expXIsMax_uid32_fpHypotTest_b <= cstAllOWE_uid10_fpHypotTest_q;
expXIsMax_uid32_fpHypotTest_q <= "1" when expXIsMax_uid32_fpHypotTest_a = expXIsMax_uid32_fpHypotTest_b else "0";
--exc_N_uid37_fpHypotTest(LOGICAL,36)@0
exc_N_uid37_fpHypotTest_a <= expXIsMax_uid32_fpHypotTest_q;
exc_N_uid37_fpHypotTest_b <= InvFracXIsZero_uid36_fpHypotTest_q;
exc_N_uid37_fpHypotTest_q <= exc_N_uid37_fpHypotTest_a and exc_N_uid37_fpHypotTest_b;
--yNaNxNonInf_uid127_fpHypotTest(LOGICAL,126)@0
yNaNxNonInf_uid127_fpHypotTest_a <= exc_N_uid37_fpHypotTest_q;
yNaNxNonInf_uid127_fpHypotTest_b <= InvExc_I_uid23_fpHypotTest_q;
yNaNxNonInf_uid127_fpHypotTest_q <= yNaNxNonInf_uid127_fpHypotTest_a and yNaNxNonInf_uid127_fpHypotTest_b;
--exc_I_uid35_fpHypotTest(LOGICAL,34)@0
exc_I_uid35_fpHypotTest_a <= expXIsMax_uid32_fpHypotTest_q;
exc_I_uid35_fpHypotTest_b <= fracXIsZero_uid34_fpHypotTest_q;
exc_I_uid35_fpHypotTest_q <= exc_I_uid35_fpHypotTest_a and exc_I_uid35_fpHypotTest_b;
--InvExc_I_uid39_fpHypotTest(LOGICAL,38)@0
InvExc_I_uid39_fpHypotTest_a <= exc_I_uid35_fpHypotTest_q;
InvExc_I_uid39_fpHypotTest_q <= not InvExc_I_uid39_fpHypotTest_a;
--InvFracXIsZero_uid20_fpHypotTest(LOGICAL,19)@0
InvFracXIsZero_uid20_fpHypotTest_a <= fracXIsZero_uid18_fpHypotTest_q;
InvFracXIsZero_uid20_fpHypotTest_q <= not InvFracXIsZero_uid20_fpHypotTest_a;
--exc_N_uid21_fpHypotTest(LOGICAL,20)@0
exc_N_uid21_fpHypotTest_a <= expXIsMax_uid16_fpHypotTest_q;
exc_N_uid21_fpHypotTest_b <= InvFracXIsZero_uid20_fpHypotTest_q;
exc_N_uid21_fpHypotTest_q <= exc_N_uid21_fpHypotTest_a and exc_N_uid21_fpHypotTest_b;
--xNaNyNonInf_uid129_fpHypotTest(LOGICAL,128)@0
xNaNyNonInf_uid129_fpHypotTest_a <= exc_N_uid21_fpHypotTest_q;
xNaNyNonInf_uid129_fpHypotTest_b <= InvExc_I_uid39_fpHypotTest_q;
xNaNyNonInf_uid129_fpHypotTest_q <= xNaNyNonInf_uid129_fpHypotTest_a and xNaNyNonInf_uid129_fpHypotTest_b;
--excRNaN_uid130_fpHypotTest(LOGICAL,129)@0
excRNaN_uid130_fpHypotTest_a <= xNaNyNonInf_uid129_fpHypotTest_q;
excRNaN_uid130_fpHypotTest_b <= yNaNxNonInf_uid127_fpHypotTest_q;
excRNaN_uid130_fpHypotTest_q <= excRNaN_uid130_fpHypotTest_a or excRNaN_uid130_fpHypotTest_b;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg(DELAY,614)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid130_fpHypotTest_q, xout => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt(COUNTER,525)
-- every=1, low=0, high=21, step=1, init=1
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i = 20 THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_eq = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i - 21;
ELSE
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_i,5));
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg(REG,526)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux(MUX,527)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s <= en;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux: PROCESS (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s, ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q, ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem(DUALMEM,615)
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_inputreg_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_ia
);
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_iq(0 downto 0);
--reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1(REG,231)@23
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q <= expRPostInc_uid114_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--sqrtOverflow_uid117_fpHypotTest(COMPARE,116)@24
sqrtOverflow_uid117_fpHypotTest_cin <= GND_q;
sqrtOverflow_uid117_fpHypotTest_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q(10)) & reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q) & '0';
sqrtOverflow_uid117_fpHypotTest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid10_fpHypotTest_q) & sqrtOverflow_uid117_fpHypotTest_cin(0);
sqrtOverflow_uid117_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(sqrtOverflow_uid117_fpHypotTest_a) - SIGNED(sqrtOverflow_uid117_fpHypotTest_b));
sqrtOverflow_uid117_fpHypotTest_n(0) <= not sqrtOverflow_uid117_fpHypotTest_o(13);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor(LOGICAL,533)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q <= not (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_a or ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_b);
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena(REG,534)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_nor_q = "1") THEN
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd(LOGICAL,535)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_sticky_ena_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b <= en;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_a and ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_b;
--InvExc_N_uid22_fpHypotTest(LOGICAL,21)@0
InvExc_N_uid22_fpHypotTest_a <= exc_N_uid21_fpHypotTest_q;
InvExc_N_uid22_fpHypotTest_q <= not InvExc_N_uid22_fpHypotTest_a;
--InvExpXIsZero_uid24_fpHypotTest(LOGICAL,23)@0
InvExpXIsZero_uid24_fpHypotTest_a <= expXIsZero_uid14_fpHypotTest_q;
InvExpXIsZero_uid24_fpHypotTest_q <= not InvExpXIsZero_uid24_fpHypotTest_a;
--exc_R_uid25_fpHypotTest(LOGICAL,24)@0
exc_R_uid25_fpHypotTest_a <= InvExpXIsZero_uid24_fpHypotTest_q;
exc_R_uid25_fpHypotTest_b <= InvExc_I_uid23_fpHypotTest_q;
exc_R_uid25_fpHypotTest_c <= InvExc_N_uid22_fpHypotTest_q;
exc_R_uid25_fpHypotTest_q <= exc_R_uid25_fpHypotTest_a and exc_R_uid25_fpHypotTest_b and exc_R_uid25_fpHypotTest_c;
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg(DELAY,523)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid25_fpHypotTest_q, xout => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem(DUALMEM,524)
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_inputreg_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq,
address_a => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_aa,
data_a => ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_ia
);
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_reset0 <= areset;
ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_iq(0 downto 0);
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor(LOGICAL,585)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q <= not (ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_a or ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_b);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top(CONSTANT,568)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q <= "010100";
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp(LOGICAL,569)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_mem_top_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q <= "1" when ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_a = ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_b else "0";
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg(REG,570)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena(REG,586)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_nor_q = "1") THEN
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd(LOGICAL,587)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_sticky_ena_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b <= en;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_a and ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_b;
--InvExc_N_uid38_fpHypotTest(LOGICAL,37)@0
InvExc_N_uid38_fpHypotTest_a <= exc_N_uid37_fpHypotTest_q;
InvExc_N_uid38_fpHypotTest_q <= not InvExc_N_uid38_fpHypotTest_a;
--InvExpXIsZero_uid40_fpHypotTest(LOGICAL,39)@0
InvExpXIsZero_uid40_fpHypotTest_a <= expXIsZero_uid30_fpHypotTest_q;
InvExpXIsZero_uid40_fpHypotTest_q <= not InvExpXIsZero_uid40_fpHypotTest_a;
--exc_R_uid41_fpHypotTest(LOGICAL,40)@0
exc_R_uid41_fpHypotTest_a <= InvExpXIsZero_uid40_fpHypotTest_q;
exc_R_uid41_fpHypotTest_b <= InvExc_I_uid39_fpHypotTest_q;
exc_R_uid41_fpHypotTest_c <= InvExc_N_uid38_fpHypotTest_q;
exc_R_uid41_fpHypotTest_q <= exc_R_uid41_fpHypotTest_a and exc_R_uid41_fpHypotTest_b and exc_R_uid41_fpHypotTest_c;
--yRegOrZero_uid123_fpHypotTest(LOGICAL,122)@0
yRegOrZero_uid123_fpHypotTest_a <= exc_R_uid41_fpHypotTest_q;
yRegOrZero_uid123_fpHypotTest_b <= expXIsZero_uid30_fpHypotTest_q;
yRegOrZero_uid123_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
yRegOrZero_uid123_fpHypotTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
yRegOrZero_uid123_fpHypotTest_q <= yRegOrZero_uid123_fpHypotTest_a or yRegOrZero_uid123_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg(DELAY,575)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yRegOrZero_uid123_fpHypotTest_q, xout => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt(COUNTER,564)
-- every=1, low=0, high=20, step=1, init=1
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i = 19 THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_eq = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i - 20;
ELSE
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_i,5));
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg(REG,565)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux(MUX,566)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s <= en;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux: PROCESS (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s, ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q, ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q)
BEGIN
CASE ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_s IS
WHEN "0" => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
WHEN "1" => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem(DUALMEM,576)
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_inputreg_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq,
address_a => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_aa,
data_a => ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_ia
);
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_iq(0 downto 0);
--yRegOrZeroXRegOvf_uid124_fpHypotTest(LOGICAL,123)@24
yRegOrZeroXRegOvf_uid124_fpHypotTest_a <= ld_yRegOrZero_uid123_fpHypotTest_q_to_yRegOrZeroXRegOvf_uid124_fpHypotTest_a_replace_mem_q;
yRegOrZeroXRegOvf_uid124_fpHypotTest_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q;
yRegOrZeroXRegOvf_uid124_fpHypotTest_c <= sqrtOverflow_uid117_fpHypotTest_n;
yRegOrZeroXRegOvf_uid124_fpHypotTest_q <= yRegOrZeroXRegOvf_uid124_fpHypotTest_a and yRegOrZeroXRegOvf_uid124_fpHypotTest_b and yRegOrZeroXRegOvf_uid124_fpHypotTest_c;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor(LOGICAL,546)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q <= not (ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_a or ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_b);
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena(REG,547)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_nor_q = "1") THEN
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd(LOGICAL,548)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_sticky_ena_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b <= en;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_a and ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_b;
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg(DELAY,536)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid41_fpHypotTest_q, xout => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem(DUALMEM,537)
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_inputreg_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq,
address_a => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_aa,
data_a => ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_ia
);
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_reset0 <= areset;
ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_iq(0 downto 0);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor(LOGICAL,572)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q <= not (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_a or ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_b);
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena(REG,573)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_nor_q = "1") THEN
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd(LOGICAL,574)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_sticky_ena_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b <= en;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_a and ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_b;
--xRegOrZero_uid121_fpHypotTest(LOGICAL,120)@0
xRegOrZero_uid121_fpHypotTest_a <= exc_R_uid25_fpHypotTest_q;
xRegOrZero_uid121_fpHypotTest_b <= expXIsZero_uid14_fpHypotTest_q;
xRegOrZero_uid121_fpHypotTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xRegOrZero_uid121_fpHypotTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xRegOrZero_uid121_fpHypotTest_q <= xRegOrZero_uid121_fpHypotTest_a or xRegOrZero_uid121_fpHypotTest_b;
END IF;
END IF;
END PROCESS;
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg(DELAY,562)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xRegOrZero_uid121_fpHypotTest_q, xout => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem(DUALMEM,563)
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_inputreg_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdreg_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_rdmux_q;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq,
address_a => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_aa,
data_a => ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_ia
);
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_iq(0 downto 0);
--xRegOrZeroYRegOvf_uid122_fpHypotTest(LOGICAL,121)@24
xRegOrZeroYRegOvf_uid122_fpHypotTest_a <= ld_xRegOrZero_uid121_fpHypotTest_q_to_xRegOrZeroYRegOvf_uid122_fpHypotTest_a_replace_mem_q;
xRegOrZeroYRegOvf_uid122_fpHypotTest_b <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q;
xRegOrZeroYRegOvf_uid122_fpHypotTest_c <= sqrtOverflow_uid117_fpHypotTest_n;
xRegOrZeroYRegOvf_uid122_fpHypotTest_q <= xRegOrZeroYRegOvf_uid122_fpHypotTest_a and xRegOrZeroYRegOvf_uid122_fpHypotTest_b and xRegOrZeroYRegOvf_uid122_fpHypotTest_c;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor(LOGICAL,611)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q <= not (ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_a or ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_b);
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena(REG,612)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_nor_q = "1") THEN
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd(LOGICAL,613)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_sticky_ena_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b <= en;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_a and ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_b;
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg(DELAY,601)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid35_fpHypotTest_q, xout => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem(DUALMEM,602)
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_inputreg_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq,
address_a => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_aa,
data_a => ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_ia
);
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_iq(0 downto 0);
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor(LOGICAL,598)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q <= not (ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_a or ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_b);
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena(REG,599)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_nor_q = "1") THEN
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd(LOGICAL,600)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_sticky_ena_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b <= en;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_a and ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_b;
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg(DELAY,588)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid19_fpHypotTest_q, xout => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem(DUALMEM,589)
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_inputreg_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq,
address_a => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_aa,
data_a => ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_ia
);
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_iq(0 downto 0);
--excRInf_uid125_fpHypotTest(LOGICAL,124)@24
excRInf_uid125_fpHypotTest_a <= ld_exc_I_uid19_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_a_replace_mem_q;
excRInf_uid125_fpHypotTest_b <= ld_exc_I_uid35_fpHypotTest_q_to_excRInf_uid125_fpHypotTest_b_replace_mem_q;
excRInf_uid125_fpHypotTest_c <= xRegOrZeroYRegOvf_uid122_fpHypotTest_q;
excRInf_uid125_fpHypotTest_d <= yRegOrZeroXRegOvf_uid124_fpHypotTest_q;
excRInf_uid125_fpHypotTest_q <= excRInf_uid125_fpHypotTest_a or excRInf_uid125_fpHypotTest_b or excRInf_uid125_fpHypotTest_c or excRInf_uid125_fpHypotTest_d;
--sqrtUnderflow_uid115_fpHypotTest(COMPARE,114)@24
sqrtUnderflow_uid115_fpHypotTest_cin <= GND_q;
sqrtUnderflow_uid115_fpHypotTest_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
sqrtUnderflow_uid115_fpHypotTest_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q(10)) & reg_expRPostInc_uid114_fpHypotTest_0_to_sqrtUnderflow_uid115_fpHypotTest_1_q) & sqrtUnderflow_uid115_fpHypotTest_cin(0);
sqrtUnderflow_uid115_fpHypotTest_o <= STD_LOGIC_VECTOR(SIGNED(sqrtUnderflow_uid115_fpHypotTest_a) - SIGNED(sqrtUnderflow_uid115_fpHypotTest_b));
sqrtUnderflow_uid115_fpHypotTest_n(0) <= not sqrtUnderflow_uid115_fpHypotTest_o(13);
--excXYRUdf_uid119_fpHypotTest(LOGICAL,118)@24
excXYRUdf_uid119_fpHypotTest_a <= sqrtUnderflow_uid115_fpHypotTest_n;
excXYRUdf_uid119_fpHypotTest_b <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_mem_q;
excXYRUdf_uid119_fpHypotTest_c <= ld_exc_R_uid41_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_c_replace_mem_q;
excXYRUdf_uid119_fpHypotTest_q <= excXYRUdf_uid119_fpHypotTest_a and excXYRUdf_uid119_fpHypotTest_b and excXYRUdf_uid119_fpHypotTest_c;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor(LOGICAL,559)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a <= ld_expA_uid70_fpHypotTest_q_to_expCatRndBit_uid91_uid92_fpHypotTest_c_notEnable_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q <= not (ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_a or ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_b);
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena(REG,560)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_nor_q = "1") THEN
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd(LOGICAL,561)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_sticky_ena_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b <= en;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_a and ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_b;
--excXYZ_uid118_fpHypotTest(LOGICAL,117)@0
excXYZ_uid118_fpHypotTest_a <= expXIsZero_uid14_fpHypotTest_q;
excXYZ_uid118_fpHypotTest_b <= expXIsZero_uid30_fpHypotTest_q;
excXYZ_uid118_fpHypotTest_q <= excXYZ_uid118_fpHypotTest_a and excXYZ_uid118_fpHypotTest_b;
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg(DELAY,549)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excXYZ_uid118_fpHypotTest_q, xout => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem(DUALMEM,550)
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_inputreg_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdreg_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab <= ld_exc_R_uid25_fpHypotTest_q_to_excXYRUdf_uid119_fpHypotTest_b_replace_rdmux_q;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq,
address_a => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_aa,
data_a => ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_ia
);
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_reset0 <= areset;
ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_iq(0 downto 0);
--excRZero_uid120_fpHypotTest(LOGICAL,119)@24
excRZero_uid120_fpHypotTest_a <= ld_excXYZ_uid118_fpHypotTest_q_to_excRZero_uid120_fpHypotTest_a_replace_mem_q;
excRZero_uid120_fpHypotTest_b <= excXYRUdf_uid119_fpHypotTest_q;
excRZero_uid120_fpHypotTest_q <= excRZero_uid120_fpHypotTest_a or excRZero_uid120_fpHypotTest_b;
--excSelBits_uid131_fpHypotTest(BITJOIN,130)@24
excSelBits_uid131_fpHypotTest_q <= ld_excRNaN_uid130_fpHypotTest_q_to_excSelBits_uid131_fpHypotTest_c_replace_mem_q & excRInf_uid125_fpHypotTest_q & excRZero_uid120_fpHypotTest_q;
--reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0(REG,233)@24
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q <= excSelBits_uid131_fpHypotTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid132_fpHypotTest(LOOKUP,131)@25
outMuxSelEnc_uid132_fpHypotTest: PROCESS (reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid131_fpHypotTest_0_to_outMuxSelEnc_uid132_fpHypotTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid132_fpHypotTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid132_fpHypotTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid132_fpHypotTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid132_fpHypotTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid132_fpHypotTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid141_fpHypotTest(MUX,140)@25
expRPostExc_uid141_fpHypotTest_s <= outMuxSelEnc_uid132_fpHypotTest_q;
expRPostExc_uid141_fpHypotTest: PROCESS (expRPostExc_uid141_fpHypotTest_s, en, cstAllZWE_uid12_fpHypotTest_q, ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q, cstAllOWE_uid10_fpHypotTest_q, cstAllOWE_uid10_fpHypotTest_q)
BEGIN
CASE expRPostExc_uid141_fpHypotTest_s IS
WHEN "00" => expRPostExc_uid141_fpHypotTest_q <= cstAllZWE_uid12_fpHypotTest_q;
WHEN "01" => expRPostExc_uid141_fpHypotTest_q <= ld_expRPreExc_uid139_fpHypotTest_b_to_expRPostExc_uid141_fpHypotTest_d_q;
WHEN "10" => expRPostExc_uid141_fpHypotTest_q <= cstAllOWE_uid10_fpHypotTest_q;
WHEN "11" => expRPostExc_uid141_fpHypotTest_q <= cstAllOWE_uid10_fpHypotTest_q;
WHEN OTHERS => expRPostExc_uid141_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--NaNFracRPostExc_uid133_fpHypotTest(CONSTANT,132)
NaNFracRPostExc_uid133_fpHypotTest_q <= "00000000000000000000001";
--fracR_uid112_fpHypotTest(BITSELECT,111)@22
fracR_uid112_fpHypotTest_in <= fracRPostInc_uid111_fpHypotTest_q(23 downto 0);
fracR_uid112_fpHypotTest_b <= fracR_uid112_fpHypotTest_in(23 downto 1);
--ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg(DELAY,627)
ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracR_uid112_fpHypotTest_b, xout => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d(DELAY,401)@22
ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_inputreg_q, xout => ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid136_fpHypotTest(MUX,135)@25
fracRPostExc_uid136_fpHypotTest_s <= outMuxSelEnc_uid132_fpHypotTest_q;
fracRPostExc_uid136_fpHypotTest: PROCESS (fracRPostExc_uid136_fpHypotTest_s, en, cstAllZWF_uid11_fpHypotTest_q, ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q, cstAllZWF_uid11_fpHypotTest_q, NaNFracRPostExc_uid133_fpHypotTest_q)
BEGIN
CASE fracRPostExc_uid136_fpHypotTest_s IS
WHEN "00" => fracRPostExc_uid136_fpHypotTest_q <= cstAllZWF_uid11_fpHypotTest_q;
WHEN "01" => fracRPostExc_uid136_fpHypotTest_q <= ld_fracR_uid112_fpHypotTest_b_to_fracRPostExc_uid136_fpHypotTest_d_q;
WHEN "10" => fracRPostExc_uid136_fpHypotTest_q <= cstAllZWF_uid11_fpHypotTest_q;
WHEN "11" => fracRPostExc_uid136_fpHypotTest_q <= NaNFracRPostExc_uid133_fpHypotTest_q;
WHEN OTHERS => fracRPostExc_uid136_fpHypotTest_q <= (others => '0');
END CASE;
END PROCESS;
--RHypot_uid142_fpHypotTest(BITJOIN,141)@25
RHypot_uid142_fpHypotTest_q <= GND_q & expRPostExc_uid141_fpHypotTest_q & fracRPostExc_uid136_fpHypotTest_q;
--xOut(GPOUT,4)@25
q <= RHypot_uid142_fpHypotTest_q;
end normal;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_range_table1.vhd
|
10
|
66434
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_rsftcomb32.vhd
|
10
|
3786
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftcomb32;
ARCHITECTURE rtl OF hcc_rsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(32) AND shift(5));
END GENERATE;
levthr(32) <= levtwo(32);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_lnlutpow.vhd
|
10
|
19605
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_castftox.vhd
|
10
|
6574
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - divider mantissa aa to aaff ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftox IS
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castftox;
ARCHITECTURE rtl OF hcc_castftox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
BEGIN
-- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1)
-- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1)
-- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x)
gza: IF (roundconvert = 1) GENERATE
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gro: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fractional & exponent;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
gexpa: FOR k IN 1 TO 8 GENERATE
expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(9) <= satnode;
expnode(10) <= '0';
--*** internal format ***
gxa: IF (target = 0) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= aaff(32);
fracnode(mantissa-2) <= aaff(32);
fracnode(mantissa-3) <= aaff(32);
fracnode(mantissa-4) <= aaff(32);
--fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign
gxb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gxc: FOR k IN 1 TO mantissa-29 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gxd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gxe: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
exponent <= expnode;
END GENERATE;
--*** direct to multiplier ***
gma: IF (target = 1) GENERATE
fracnode(mantissa) <= aaff(32);
--fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode);
gmb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gmc: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gmd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gme: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
-- never register output
--*** direct to divider ***
gda: IF (target = 2) GENERATE
fracnode(mantissa) <= aaff(32);
-- 13/07/09
fracnode(mantissa-1) <= '1' AND NOT(zipnode);
fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1);
gfb: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= '0';
END GENERATE;
fractional <= fracnode;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
--*** OUTPUTS ***
goa: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gob: IF ((target = 0 AND outputpipe = 0) OR
(target = 1 AND outputpipe = 0) OR
(target = 2)) GENERATE
cc <= fractional & exponent;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_del.vhd
|
10
|
3579
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Generic Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del;
ARCHITECTURE rtl OF fp_del IS
component fp_del_one IS
GENERIC (width : positive := 64);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
genone: IF (pipes = 1) GENERATE
delone: fp_del_one
GENERIC MAP (width=>width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
genvar: IF (pipes > 1) GENERATE
delvar: fp_del_var
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/hcc_normfp1x_sv.vhd
|
10
|
12224
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** 16/04/09 - add NAN support ***
--*** 08/11/10 - +0,-0 mantissa case ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : ***
--***************************************************
--***************************************************
--*** NOTES: ***
--*** normalize signed numbers (x input format) ***
--*** for 1x multipliers ***
--*** format signed32/36 bit mantissa and 10 bit ***
--*** exponent ***
--*** unsigned numbers for divider (S,1,23 bit ***
--*** mantissa for divider) divider packed into ***
--*** 32/36bit mantissa + exponent ***
--***************************************************
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff, aananff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal maximumnumberff : STD_LOGIC;
signal zeroexponent, zeroexponentff : STD_LOGIC;
signal exponentmiddle : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatdelff, aazipdelff, aanandelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
aananff <= aanan;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
ccnan <= aananff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
maximumnumberff <= '0';
zeroexponentff <= '0';
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
aanandelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exponentmiddle;
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
-- 08/11/09
maximumnumberff <= aaff(mantissa+10) XOR aaff(mantissa+9);
zeroexponentff <= zeroexponent;
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
aanandelff(1) <= aanan;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
aanandelff(k) <= aanandelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
-- 08/11/10 - also where exponentmiddle is used
-- '1' if true : if countsign 0, then "111...111" (-0) or "000...000" (+0) case, zero exponent output
zeroexponent <= NOT(countsign(6) OR countsign(5) OR countsign(4) OR
countsign(3) OR countsign(2) OR countsign(1) OR maximumnumberff);
gen_exp_mid: FOR k IN 1 TO 10 GENERATE
exponentmiddle(k) <= exptopff(2)(k) AND NOT(zeroexponentff);
END GENERATE;
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
ccnan <= aanandelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
ccnan <= aanandelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exponentmiddle;
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
ccnan <= aanandelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_delbit_one.vhd
|
10
|
1709
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DELBIT_ONE.VHD ***
--*** ***
--*** Function: Single Bit Delay ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_delbit_one IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
END fp_delbit_one ;
ARCHITECTURE rtl OF fp_delbit_one IS
signal delff : STD_LOGIC;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
delff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delff;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_div_lut0.vhd
|
10
|
37328
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_cordic_start1.vhd
|
10
|
3284
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
mit
|
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