repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
boztalay/OZ-3
|
FPGA/OZ-3/ID.vhd
|
2
|
13633
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:55:38 10/26/2009
-- Design Name:
-- Module Name: ID - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The instruction decoder of the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Ports written in
-- Revision 0.15 - Main process outlines written
-- Revision 0.30 - Control and Arithmetic/Logic decoding sections first draft done
-- Revision 0.31 - Memory and I/O decoding sections first draft complete, need to include the register file
-- and output process to handle forwarding
-- Revision 0.32 - Output/forward logic process done, need to do all of the ORing of data lines, add
-- the register file, and OR all of its address lines
-- Revision 0.33 - Register file component instantiated, ports mapped; need to OR all the signals and such
-- Revision 0.40 - First draft of module complete, syntax errors corrected; need to simulate
-- Revision 0.50 - Simulation and testing of all instruction complete, need to test forwarding
-- Revision 0.55 - Forwarding logic tested
-- Revision 0.56 - Added forwarding logic for the third address port of the register file
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ID is
Port ( --Inputs--
--Main inputs
clock : in STD_LOGIC;
reset : in STD_LOGIC;
instruction_from_IF : in STD_LOGIC_VECTOR(31 downto 0);
--Register file inputs
rfile_read_addr3_from_MEMIO : in STD_LOGIC_VECTOR(4 downto 0); --AKA RAM reg addr
rfile_write_addr_from_WB : in STD_LOGIC_VECTOR(4 downto 0);
rfile_write_data_from_WB : in STD_LOGIC_VECTOR(31 downto 0);
rfile_write_e_from_WB : in STD_LOGIC;
--Forwarding logic inptus
forward_addr_EX : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_EX : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_MEMIO : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_MEMIO : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_WB : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_WB : in STD_LOGIC_VECTOR(31 downto 0);
--Outputs--
--EX Control
ALU_A_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
ALU_B_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
EX_control : out STD_LOGIC_VECTOR(11 downto 0);
--MEMIO Control
RAM_reg_data_to_MEMIO : out STD_LOGIC_VECTOR(31 downto 0);
MEMIO_control : out STD_LOGIC_VECTOR(20 downto 0);
--WB Control
WB_control : out STD_LOGIC_VECTOR(5 downto 0));
end ID;
architecture Behavioral of ID is
--//Components\\--
component RegFile is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
write_e : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
r_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr2 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr3 : in STD_LOGIC_VECTOR(4 downto 0);
w_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
data_out_1 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_2 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_3 : out STD_LOGIC_VECTOR(31 downto 0));
end component;
component GenReg is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal rfile_read_addr1_cntl : STD_LOGIC_VECTOR(4 downto 0); --These will get ORed before going to
signal rfile_read_addr1_arith_logic : STD_LOGIC_VECTOR(4 downto 0); --the register file
signal rfile_read_addr1_MEMIO : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr1 : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr2 : STD_LOGIC_VECTOR(4 downto 0); --This goes straight to the register file
--and forwarding logic
signal RAM_reg_data_from_rfile : STD_LOGIC_VECTOR(31 downto 0); --This signal carries the rfile's
--third output to the output logic
signal WB_WE_arith_logic : STD_LOGIC; --These will get ORed before going to WB
signal WB_WE_MEMIO : STD_LOGIC;
signal result_reg_arith_logic : STD_LOGIC_VECTOR(4 downto 0); --These will get ORed before going out
signal result_reg_MEMIO : STD_LOGIC_VECTOR(4 downto 0); --to the stages as a single result_reg
signal result_reg : STD_LOGIC_VECTOR(4 downto 0);
signal instruction : STD_LOGIC_VECTOR(31 downto 0);
--All of this has to do with the output to the ALU.
--It'll mostly get handled by tricky ORing, due to the
--fact that the "do nothing" state for the drivers of these signals
--is all zeros, so I can OR them to allow the only used value through
signal rfile_out_1 : STD_LOGIC_VECTOR(31 downto 0);
signal rfile_out_2 : STD_LOGIC_VECTOR(31 downto 0);
signal arith_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal MEMIO_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal displacement : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_B : STD_LOGIC_VECTOR(31 downto 0);
--\\Signals//--
begin
--This process takes care of control instructions
control: process (instruction) is
begin
--Signals to initialize to zero
EX_control(6 downto 4) <= b"000";
rfile_read_addr1_cntl <= b"00000";
displacement <= x"00000000";
if instruction(31) = '1' then
EX_control(6 downto 4) <= instruction(28 downto 26);
rfile_read_addr1_cntl <= instruction(25 downto 21);
if (instruction(20) = '0') then --Sign extension of the displacement value
displacement <= b"00000000000" & instruction(20 downto 0);
else
displacement <= b"11111111111" & instruction(20 downto 0);
end if;
end if;
end process;
--This process decodes memory and I/O instructions
MEMIO: process (instruction) is
begin
--Signals to initialize as zero
MEMIO_immediate <= x"00000000";
MEMIO_control(20 downto 18) <= b"000";
MEMIO_control(12 downto 0) <= b"0000000000000";
rfile_read_addr1_MEMIO <= b"00000";
result_reg_MEMIO <= b"00000";
WB_WE_MEMIO <= '0';
if instruction(30) = '1' then --Need to finish this section, don't forget section cntl
--The immediate value from MEMIO sign extension
if instruction(15) = '0' then
MEMIO_immediate <= (x"0000" & instruction(15 downto 0));
else
MEMIO_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
--If it's a store/load instruction
if instruction(29) = '1' then
--Control signal for the RAM section
MEMIO_control(2) <= '1';
--Detect load or store
if instruction(27) = '0' then
--Load
result_reg_MEMIO <= instruction(25 downto 21); --result register
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --the register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(19 downto 18) <= b"10"; --MUX control
WB_WE_MEMIO <= '1'; --write enable
else
--Store
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(7) <= '1'; --change the dRAM write/read signal
end if;
--Upper/lower control signal
MEMIO_control(20) <= instruction(26);
end if;
--If it's a port instruction
if instruction(29 downto 27) = b"001" then
--Control signal for the port section
MEMIO_control(1) <= '1';
--Detect input/output with the ports
if instruction(26) = '0' then --Input
result_reg_MEMIO <= instruction(25 downto 21); --result register
WB_WE_MEMIO <= '1'; --write enable
MEMIO_control(19 downto 18) <= b"01"; --set select for MUX to iprt data
else --Output
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --data register
MEMIO_control(6) <= '1'; --enable the oprt register clock
end if;
end if;
--If it's a pin instruction
if instruction(29 downto 28) = b"01" then
--Control signal for the pin section
MEMIO_control(0) <= '1';
--Detect if it's an output or inpupt pin instruction
if instruction(27) = '0' then --Output
MEMIO_control(5) <= instruction(26); --Opin 1/0 select
MEMIO_control(4) <= '1'; --Opin register clock enable
else --Input
MEMIO_control(3) <= '1'; --pin check enable
end if;
end if;
end if;
end process;
--This process decodes arithmetic and logic instructions
arith_logic: process (instruction) is --I think this is done, but recheck
begin
--Signals to initialize as zero
EX_control(3 downto 0) <= b"0000";
arith_immediate <= x"00000000";
result_reg_arith_logic <= b"00000";
rfile_read_addr1_arith_logic <= b"00000";
rfile_read_addr2 <= b"00000";
WB_WE_arith_logic <= '0';
if instruction(30 downto 29) = b"01" then
result_reg_arith_logic <= instruction(25 downto 21);
rfile_read_addr1_arith_logic <= instruction(20 downto 16);
WB_WE_arith_logic <= '1'; --write enable
--Detecting a register verus immediate addressing mode instruction
if instruction(28 downto 26) = b"111" then
--This is getting the ALU select value
EX_control(3 downto 0) <= instruction(3 downto 0);
--Register file source 2 address
rfile_read_addr2 <= instruction(15 downto 11);
else
--ALU select value if the instruction is in the immediate addressing mode
EX_control(3 downto 0) <= ('0' & instruction(28 downto 26));
--Immediate value sign extension
if instruction(15) = '0' then
arith_immediate <= (x"0000" & instruction(15 downto 0));
else
arith_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
end if;
end if;
end process;
--This process handles the main outputs, along with
--forwarding logic (ALU A and B already ORed n such)
output: process (rfile_out_1, ALU_B, forward_data_EX, forward_data_MEMIO, forward_data_WB,
forward_addr_EX, forward_addr_MEMIO, forward_addr_WB, rfile_read_addr1,
rfile_read_addr2, rfile_read_addr3_from_MEMIO, RAM_reg_data_from_rfile) is
begin
--Logic for ALU_A/src1
if rfile_read_addr1 /= b"00000" then
--if the source register is EX's result register
if rfile_read_addr1 = forward_addr_EX then
ALU_A_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr1 = forward_addr_MEMIO then
ALU_A_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr1 = forward_addr_WB then
ALU_A_to_EX <= forward_data_WB;
else
ALU_A_to_EX <= rfile_out_1;
end if;
else
ALU_A_to_EX <= rfile_out_1;
end if;
--Logic for ALU_B/src2
--if the source register is EX's result register
if rfile_read_addr2 /= b"00000" then
if rfile_read_addr2 = forward_addr_EX then
ALU_B_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr2 = forward_addr_MEMIO then
ALU_B_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr2 = forward_addr_WB then
ALU_B_to_EX <= forward_data_WB;
else
ALU_B_to_EX <= ALU_B;
end if;
else
ALU_B_to_EX <= ALU_B;
end if;
--Logic for the RAM register
--if the source register is EX's RAM register
if rfile_read_addr3_from_MEMIO /= b"00000" then
if rfile_read_addr3_from_MEMIO = forward_addr_EX then
RAM_reg_data_to_MEMIO <= forward_data_EX;
--if the source register is MEMIO's result register
-- elsif rfile_read_addr3_from_MEMIO = forward_addr_MEMIO then
-- RAM_reg_data_to_MEMIO <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr3_from_MEMIO = forward_addr_WB then
RAM_reg_data_to_MEMIO <= forward_data_WB;
else
RAM_reg_data_to_MEMIO <= (others => '0');
end if;
else
RAM_reg_data_to_MEMIO <= RAM_reg_data_from_rfile; --new sig like above
end if;
end process;
--Signals getting combined (I know this adds a lot of excess logic, will optimize later)
rfile_read_addr1 <= (rfile_read_addr1_cntl or rfile_read_addr1_MEMIO or rfile_read_addr1_arith_logic);
result_reg <= (result_reg_MEMIO or result_reg_arith_logic);
WB_control(0) <= (WB_WE_MEMIO or WB_WE_arith_logic);
ALU_B <= (rfile_out_2 or arith_immediate or MEMIO_immediate or displacement);
--Finishing up the control signals
MEMIO_control(17 downto 13) <= result_reg;
EX_control(11 downto 7) <= result_reg;
WB_control(5 downto 1) <= result_reg;
--Register file
rfile: RegFile port map (clock, reset, rfile_write_e_from_WB, rfile_write_data_from_WB, rfile_read_addr1,
rfile_read_addr2, rfile_read_addr3_from_MEMIO, rfile_write_addr_from_WB, rfile_out_1,
rfile_out_2, RAM_reg_data_from_rfile);
--Input register
inst_reg : GenReg generic map (32)
port map (clock, '1', reset, instruction_from_IF, instruction);
end Behavioral;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/fp_fabs.vhd
|
10
|
3173
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_fabs;
ARCHITECTURE rtl OF fp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 8 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(8));
expmax <= expmaxchk(8);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(23));
mannonzero <= manzerochk(23);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
mit
|
LorhanSohaky/UFSCar
|
2018/lab-arq1/aula_03-26/Lorhan740951/work/gray_counter/_primary.vhd
|
1
|
404
|
library verilog;
use verilog.vl_types.all;
entity gray_counter is
generic(
WIDTH : integer := 8
);
port(
clk : in vl_logic;
reset : in vl_logic;
gray_count : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of WIDTH : constant is 1;
end gray_counter;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_explutneg.vhd
|
10
|
14862
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explutneg IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explutneg;
ARCHITECTURE rtl OF fp_explutneg IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "0000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "0000001" =>
mantissa <= conv_std_logic_vector(3955378,23);
exponent <= conv_std_logic_vector(125,8);
WHEN "0000010" =>
mantissa <= conv_std_logic_vector(693589,23);
exponent <= conv_std_logic_vector(124,8);
WHEN "0000011" =>
mantissa <= conv_std_logic_vector(4976006,23);
exponent <= conv_std_logic_vector(122,8);
WHEN "0000100" =>
mantissa <= conv_std_logic_vector(1444526,23);
exponent <= conv_std_logic_vector(121,8);
WHEN "0000101" =>
mantissa <= conv_std_logic_vector(6081023,23);
exponent <= conv_std_logic_vector(119,8);
WHEN "0000110" =>
mantissa <= conv_std_logic_vector(2257552,23);
exponent <= conv_std_logic_vector(118,8);
WHEN "0000111" =>
mantissa <= conv_std_logic_vector(7277405,23);
exponent <= conv_std_logic_vector(116,8);
WHEN "0001000" =>
mantissa <= conv_std_logic_vector(3137800,23);
exponent <= conv_std_logic_vector(115,8);
WHEN "0001001" =>
mantissa <= conv_std_logic_vector(92049,23);
exponent <= conv_std_logic_vector(114,8);
WHEN "0001010" =>
mantissa <= conv_std_logic_vector(4090830,23);
exponent <= conv_std_logic_vector(112,8);
WHEN "0001011" =>
mantissa <= conv_std_logic_vector(793249,23);
exponent <= conv_std_logic_vector(111,8);
WHEN "0001100" =>
mantissa <= conv_std_logic_vector(5122658,23);
exponent <= conv_std_logic_vector(109,8);
WHEN "0001101" =>
mantissa <= conv_std_logic_vector(1552426,23);
exponent <= conv_std_logic_vector(108,8);
WHEN "0001110" =>
mantissa <= conv_std_logic_vector(6239800,23);
exponent <= conv_std_logic_vector(106,8);
WHEN "0001111" =>
mantissa <= conv_std_logic_vector(2374373,23);
exponent <= conv_std_logic_vector(105,8);
WHEN "0010000" =>
mantissa <= conv_std_logic_vector(7449310,23);
exponent <= conv_std_logic_vector(103,8);
WHEN "0010001" =>
mantissa <= conv_std_logic_vector(3264281,23);
exponent <= conv_std_logic_vector(102,8);
WHEN "0010010" =>
mantissa <= conv_std_logic_vector(185108,23);
exponent <= conv_std_logic_vector(101,8);
WHEN "0010011" =>
mantissa <= conv_std_logic_vector(4227768,23);
exponent <= conv_std_logic_vector(99,8);
WHEN "0010100" =>
mantissa <= conv_std_logic_vector(894003,23);
exponent <= conv_std_logic_vector(98,8);
WHEN "0010101" =>
mantissa <= conv_std_logic_vector(5270919,23);
exponent <= conv_std_logic_vector(96,8);
WHEN "0010110" =>
mantissa <= conv_std_logic_vector(1661510,23);
exponent <= conv_std_logic_vector(95,8);
WHEN "0010111" =>
mantissa <= conv_std_logic_vector(6400319,23);
exponent <= conv_std_logic_vector(93,8);
WHEN "0011000" =>
mantissa <= conv_std_logic_vector(2492476,23);
exponent <= conv_std_logic_vector(92,8);
WHEN "0011001" =>
mantissa <= conv_std_logic_vector(7623101,23);
exponent <= conv_std_logic_vector(90,8);
WHEN "0011010" =>
mantissa <= conv_std_logic_vector(3392149,23);
exponent <= conv_std_logic_vector(89,8);
WHEN "0011011" =>
mantissa <= conv_std_logic_vector(279189,23);
exponent <= conv_std_logic_vector(88,8);
WHEN "0011100" =>
mantissa <= conv_std_logic_vector(4366209,23);
exponent <= conv_std_logic_vector(86,8);
WHEN "0011101" =>
mantissa <= conv_std_logic_vector(995862,23);
exponent <= conv_std_logic_vector(85,8);
WHEN "0011110" =>
mantissa <= conv_std_logic_vector(5420806,23);
exponent <= conv_std_logic_vector(83,8);
WHEN "0011111" =>
mantissa <= conv_std_logic_vector(1771791,23);
exponent <= conv_std_logic_vector(82,8);
WHEN "0100000" =>
mantissa <= conv_std_logic_vector(6562600,23);
exponent <= conv_std_logic_vector(80,8);
WHEN "0100001" =>
mantissa <= conv_std_logic_vector(2611876,23);
exponent <= conv_std_logic_vector(79,8);
WHEN "0100010" =>
mantissa <= conv_std_logic_vector(7798799,23);
exponent <= conv_std_logic_vector(77,8);
WHEN "0100011" =>
mantissa <= conv_std_logic_vector(3521421,23);
exponent <= conv_std_logic_vector(76,8);
WHEN "0100100" =>
mantissa <= conv_std_logic_vector(374301,23);
exponent <= conv_std_logic_vector(75,8);
WHEN "0100101" =>
mantissa <= conv_std_logic_vector(4506169,23);
exponent <= conv_std_logic_vector(73,8);
WHEN "0100110" =>
mantissa <= conv_std_logic_vector(1098839,23);
exponent <= conv_std_logic_vector(72,8);
WHEN "0100111" =>
mantissa <= conv_std_logic_vector(5572338,23);
exponent <= conv_std_logic_vector(70,8);
WHEN "0101000" =>
mantissa <= conv_std_logic_vector(1883282,23);
exponent <= conv_std_logic_vector(69,8);
WHEN "0101001" =>
mantissa <= conv_std_logic_vector(6726661,23);
exponent <= conv_std_logic_vector(67,8);
WHEN "0101010" =>
mantissa <= conv_std_logic_vector(2732585,23);
exponent <= conv_std_logic_vector(66,8);
WHEN "0101011" =>
mantissa <= conv_std_logic_vector(7976426,23);
exponent <= conv_std_logic_vector(64,8);
WHEN "0101100" =>
mantissa <= conv_std_logic_vector(3652111,23);
exponent <= conv_std_logic_vector(63,8);
WHEN "0101101" =>
mantissa <= conv_std_logic_vector(470458,23);
exponent <= conv_std_logic_vector(62,8);
WHEN "0101110" =>
mantissa <= conv_std_logic_vector(4647665,23);
exponent <= conv_std_logic_vector(60,8);
WHEN "0101111" =>
mantissa <= conv_std_logic_vector(1202946,23);
exponent <= conv_std_logic_vector(59,8);
WHEN "0110000" =>
mantissa <= conv_std_logic_vector(5725533,23);
exponent <= conv_std_logic_vector(57,8);
WHEN "0110001" =>
mantissa <= conv_std_logic_vector(1995997,23);
exponent <= conv_std_logic_vector(56,8);
WHEN "0110010" =>
mantissa <= conv_std_logic_vector(6892523,23);
exponent <= conv_std_logic_vector(54,8);
WHEN "0110011" =>
mantissa <= conv_std_logic_vector(2854620,23);
exponent <= conv_std_logic_vector(53,8);
WHEN "0110100" =>
mantissa <= conv_std_logic_vector(8156001,23);
exponent <= conv_std_logic_vector(51,8);
WHEN "0110101" =>
mantissa <= conv_std_logic_vector(3784235,23);
exponent <= conv_std_logic_vector(50,8);
WHEN "0110110" =>
mantissa <= conv_std_logic_vector(567669,23);
exponent <= conv_std_logic_vector(49,8);
WHEN "0110111" =>
mantissa <= conv_std_logic_vector(4790713,23);
exponent <= conv_std_logic_vector(47,8);
WHEN "0111000" =>
mantissa <= conv_std_logic_vector(1308195,23);
exponent <= conv_std_logic_vector(46,8);
WHEN "0111001" =>
mantissa <= conv_std_logic_vector(5880410,23);
exponent <= conv_std_logic_vector(44,8);
WHEN "0111010" =>
mantissa <= conv_std_logic_vector(2109948,23);
exponent <= conv_std_logic_vector(43,8);
WHEN "0111011" =>
mantissa <= conv_std_logic_vector(7060204,23);
exponent <= conv_std_logic_vector(41,8);
WHEN "0111100" =>
mantissa <= conv_std_logic_vector(2977993,23);
exponent <= conv_std_logic_vector(40,8);
WHEN "0111101" =>
mantissa <= conv_std_logic_vector(8337547,23);
exponent <= conv_std_logic_vector(38,8);
WHEN "0111110" =>
mantissa <= conv_std_logic_vector(3917809,23);
exponent <= conv_std_logic_vector(37,8);
WHEN "0111111" =>
mantissa <= conv_std_logic_vector(665948,23);
exponent <= conv_std_logic_vector(36,8);
WHEN "1000000" =>
mantissa <= conv_std_logic_vector(4935332,23);
exponent <= conv_std_logic_vector(34,8);
WHEN "1000001" =>
mantissa <= conv_std_logic_vector(1414599,23);
exponent <= conv_std_logic_vector(33,8);
WHEN "1000010" =>
mantissa <= conv_std_logic_vector(6036985,23);
exponent <= conv_std_logic_vector(31,8);
WHEN "1000011" =>
mantissa <= conv_std_logic_vector(2225150,23);
exponent <= conv_std_logic_vector(30,8);
WHEN "1000100" =>
mantissa <= conv_std_logic_vector(7229726,23);
exponent <= conv_std_logic_vector(28,8);
WHEN "1000101" =>
mantissa <= conv_std_logic_vector(3102720,23);
exponent <= conv_std_logic_vector(27,8);
WHEN "1000110" =>
mantissa <= conv_std_logic_vector(66239,23);
exponent <= conv_std_logic_vector(26,8);
WHEN "1000111" =>
mantissa <= conv_std_logic_vector(4052849,23);
exponent <= conv_std_logic_vector(24,8);
WHEN "1001000" =>
mantissa <= conv_std_logic_vector(765304,23);
exponent <= conv_std_logic_vector(23,8);
WHEN "1001001" =>
mantissa <= conv_std_logic_vector(5081537,23);
exponent <= conv_std_logic_vector(21,8);
WHEN "1001010" =>
mantissa <= conv_std_logic_vector(1522171,23);
exponent <= conv_std_logic_vector(20,8);
WHEN "1001011" =>
mantissa <= conv_std_logic_vector(6195279,23);
exponent <= conv_std_logic_vector(18,8);
WHEN "1001100" =>
mantissa <= conv_std_logic_vector(2341616,23);
exponent <= conv_std_logic_vector(17,8);
WHEN "1001101" =>
mantissa <= conv_std_logic_vector(7401108,23);
exponent <= conv_std_logic_vector(15,8);
WHEN "1001110" =>
mantissa <= conv_std_logic_vector(3228816,23);
exponent <= conv_std_logic_vector(14,8);
WHEN "1001111" =>
mantissa <= conv_std_logic_vector(159015,23);
exponent <= conv_std_logic_vector(13,8);
WHEN "1010000" =>
mantissa <= conv_std_logic_vector(4189370,23);
exponent <= conv_std_logic_vector(11,8);
WHEN "1010001" =>
mantissa <= conv_std_logic_vector(865751,23);
exponent <= conv_std_logic_vector(10,8);
WHEN "1010010" =>
mantissa <= conv_std_logic_vector(5229346,23);
exponent <= conv_std_logic_vector(8,8);
WHEN "1010011" =>
mantissa <= conv_std_logic_vector(1630923,23);
exponent <= conv_std_logic_vector(7,8);
WHEN "1010100" =>
mantissa <= conv_std_logic_vector(6355309,23);
exponent <= conv_std_logic_vector(5,8);
WHEN "1010101" =>
mantissa <= conv_std_logic_vector(2459360,23);
exponent <= conv_std_logic_vector(4,8);
WHEN "1010110" =>
mantissa <= conv_std_logic_vector(7574370,23);
exponent <= conv_std_logic_vector(2,8);
WHEN "1010111" =>
mantissa <= conv_std_logic_vector(3356295,23);
exponent <= conv_std_logic_vector(1,8);
WHEN "1011000" =>
mantissa <= conv_std_logic_vector(252809,23);
exponent <= conv_std_logic_vector(0,8);
WHEN "1011001" =>
mantissa <= conv_std_logic_vector(4327390,23);
exponent <= conv_std_logic_vector(-2,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dp_clzpipe64.vhd
|
10
|
7360
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_CLZPIPE64.VHD ***
--*** ***
--*** Function: Pipelined, Count Leading Zeroes ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_clzpipe64;
ARCHITECTURE rtl of dp_clzpipe64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroupff, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastman : STD_LOGIC_VECTOR (6 DOWNTO 1);
component dp_pos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
zerogroupff(k) <= '0';
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zerogroupff(1) <= mantissa(64) OR mantissa(63) OR mantissa(62) OR mantissa(61) OR mantissa(60) OR mantissa(59);
zerogroupff(2) <= mantissa(58) OR mantissa(57) OR mantissa(56) OR mantissa(55) OR mantissa(54) OR mantissa(53);
zerogroupff(3) <= mantissa(52) OR mantissa(51) OR mantissa(50) OR mantissa(49) OR mantissa(48) OR mantissa(47);
zerogroupff(4) <= mantissa(46) OR mantissa(45) OR mantissa(44) OR mantissa(43) OR mantissa(42) OR mantissa(41);
zerogroupff(5) <= mantissa(40) OR mantissa(39) OR mantissa(38) OR mantissa(37) OR mantissa(36) OR mantissa(35);
zerogroupff(6) <= mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31) OR mantissa(30) OR mantissa(29);
zerogroupff(7) <= mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25) OR mantissa(24) OR mantissa(23);
zerogroupff(8) <= mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18) OR mantissa(17);
zerogroupff(9) <= mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12) OR mantissa(11);
zerogroupff(10) <= mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6) OR mantissa(5);
zerogroupff(11) <= mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
lastman <= mantissa(4 DOWNTO 1) & "00";
pone: dp_pos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastman,position=>position(11)(6 DOWNTO 1));
ptwo: dp_pos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>mantissa(10 DOWNTO 5),position=>position(10)(6 DOWNTO 1));
pthr: dp_pos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>mantissa(16 DOWNTO 11),position=>position(9)(6 DOWNTO 1));
pfor: dp_pos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>mantissa(22 DOWNTO 17),position=>position(8)(6 DOWNTO 1));
pfiv: dp_pos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>mantissa(28 DOWNTO 23),position=>position(7)(6 DOWNTO 1));
psix: dp_pos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(34 DOWNTO 29),position=>position(6)(6 DOWNTO 1));
psev: dp_pos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(40 DOWNTO 35),position=>position(5)(6 DOWNTO 1));
pegt: dp_pos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(46 DOWNTO 41),position=>position(4)(6 DOWNTO 1));
pnin: dp_pos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(52 DOWNTO 47),position=>position(3)(6 DOWNTO 1));
pten: dp_pos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(58 DOWNTO 53),position=>position(2)(6 DOWNTO 1));
pelv: dp_pos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(64 DOWNTO 59),position=>position(1)(6 DOWNTO 1));
firstzero(1) <= zerogroupff(1);
firstzero(2) <= NOT(zerogroupff(1)) AND zerogroupff(2);
firstzero(3) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND zerogroupff(3);
firstzero(4) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND zerogroupff(4);
firstzero(5) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND zerogroupff(5);
firstzero(6) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND zerogroupff(6);
firstzero(7) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND zerogroupff(7);
firstzero(8) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND NOT(zerogroupff(7)) AND zerogroupff(8);
firstzero(9) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND NOT(zerogroupff(7)) AND NOT(zerogroupff(8))
AND zerogroupff(9);
firstzero(10) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND NOT(zerogroupff(7)) AND NOT(zerogroupff(8))
AND NOT(zerogroupff(9)) AND zerogroupff(10);
firstzero(11) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND NOT(zerogroupff(4))
AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND NOT(zerogroupff(7)) AND NOT(zerogroupff(8))
AND NOT(zerogroupff(9)) AND NOT(zerogroupff(10)) AND zerogroupff(11);
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(11)(6 DOWNTO 1);
END rtl;
|
mit
|
boztalay/OZ-3
|
FPGA/OZ-3_System/OZ3_System.vhd
|
2
|
14329
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: OZ3_System
--Module Description:
-- This is the module that brings all of the pieces together; the OZ-3, the
-- clock generator, and the memory bus controller. Other pieces of hardware
-- can be added to expand the system, such as a 7-segment decoder or VGA
-- controller.
--
--Notes:
-- Nomenclature for signals: OZ3_dRAM_data_to_MC
-- |^| |---^---| |-^-|
-- | | |
-- sending module | receiving module
-- signal name/content
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OZ3_System is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
--For the keyboard interface
key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
--Pushbuttons
button_0 : in STD_LOGIC;
button_1 : in STD_LOGIC;
button_2 : in STD_LOGIC;
--Switches
switches : in STD_LOGIC_VECTOR(7 downto 0);
--Control signals for the 4-digit, 7-segment display
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
--Outputs for the LCD
LCD_data_bus_out : out STD_LOGIC_VECTOR(7 downto 0);
LCD_RW : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_E : out STD_LOGIC;
--Output to the LEDs
LEDs : out STD_LOGIC_VECTOR(7 downto 0);
--Memory data and address buses
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
--Data RAM control signals
dRAM_ce : out STD_LOGIC;
dRAM_lb : out STD_LOGIC;
dRAM_ub : out STD_LOGIC;
dRAM_adv : out STD_LOGIC;
dRAM_cre : out STD_LOGIC;
dRAM_clk : out STD_LOGIC;
--Instruction Flash control signals
flash_ce : out STD_LOGIC;
flash_rp : out STD_LOGIC;
--Shared memory signals
mem_oe : out STD_LOGIC;
mem_we : out STD_LOGIC);
end OZ3_System;
architecture Behavioral of OZ3_System is
--//Components\\--
--The OZ-3
component OZ3 is
Port ( main_clock : in STD_LOGIC;
dbl_clock : in STD_LOGIC;
inv_clock : in STD_LOGIC;
reset : in STD_LOGIC;
input_pins : in STD_LOGIC_VECTOR(15 downto 0);
input_port : in STD_LOGIC_VECTOR(31 downto 0);
instruction_from_iROM : in STD_LOGIC_VECTOR(15 downto 0);
data_from_dRAM : in STD_LOGIC_VECTOR(15 downto 0);
output_pins : out STD_LOGIC_VECTOR(15 downto 0);
output_port : out STD_LOGIC_VECTOR(31 downto 0);
output_port_enable : out STD_LOGIC;
addr_to_iROM : out STD_LOGIC_VECTOR(22 downto 0);
data_to_dRAM : out STD_LOGIC_VECTOR(15 downto 0);
addr_to_dRAM : out STD_LOGIC_VECTOR(22 downto 0);
WR_to_dRAM : out STD_LOGIC);
end component;
--The memory bus controller
component Mem_Ctrl is
Port ( flash_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dbl_clk_from_OZ3 : in STD_LOGIC;
dRAM_WR_from_OZ3 : in STD_LOGIC;
dRAM_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_from_OZ3 : in STD_LOGIC_VECTOR(15 downto 0);
data_bus : in STD_LOGIC_VECTOR(15 downto 0);
dRAM_ce : out STD_LOGIC;
dRAM_lb : out STD_LOGIC;
dRAM_ub : out STD_LOGIC;
dRAM_adv : out STD_LOGIC;
dRAM_cre : out STD_LOGIC;
dRAM_clk : out STD_LOGIC;
flash_ce : out STD_LOGIC;
flash_rp : out STD_LOGIC;
mem_oe : out STD_LOGIC;
mem_we : out STD_LOGIC;
address_bus : out STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0);
instruction_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0));
end component;
--The clock manager/generator
component Clock_Mgt is
Port ( board_clock : in STD_LOGIC;
clock1_out : out STD_LOGIC;
clock2_out : out STD_LOGIC;
clock3_out : out STD_LOGIC;
clock4_out : out STD_LOGIC);
end component;
--The 4-digit, 7-segment decoder
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
--An input port extender for the OZ-3
component Input_Port_MUX is
Port ( input0 : in STD_LOGIC_VECTOR (31 downto 0);
input1 : in STD_LOGIC_VECTOR (31 downto 0);
input2 : in STD_LOGIC_VECTOR (31 downto 0);
input3 : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (31 downto 0));
end component;
--An output port extender for the OZ-3
component Output_Port_MUX is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output0 : out STD_LOGIC_VECTOR (31 downto 0);
output1 : out STD_LOGIC_VECTOR (31 downto 0);
output2 : out STD_LOGIC_VECTOR (31 downto 0);
output3 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
--A simple debouncer for inputs
component Debouncer is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end component;
--A keyboard interface controller
component Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (0 to 7);
code_ready : out STD_LOGIC);
end component;
--\\Components//--
--//Signals\\--
--These signals cary the four clock signals from the clock manager
--to other parts of the system
signal clock_1 : STD_LOGIC;
signal clock_2 : STD_LOGIC;
signal clock_3 : STD_LOGIC;
signal clock_4 : STD_LOGIC;
----Signals between the MC and OZ3
signal OZ3_instruction_addr_to_MC : STD_LOGIC_VECTOR(22 downto 0); --Signals used to send data from OZ-3 to the
signal OZ3_dRAM_data_to_MC : STD_LOGIC_VECTOR(15 downto 0); --memory controller
signal OZ3_dRAM_addr_to_MC : STD_LOGIC_VECTOR(22 downto 0);
signal OZ3_dRAM_WR_to_MC : STD_LOGIC;
signal MC_instruction_to_OZ3 : STD_LOGIC_VECTOR(15 downto 0); --Signals used to send data from the memory
signal MC_dRAM_data_to_OZ3 : STD_LOGIC_VECTOR(15 downto 0); --controller to the OZ-3
--OZ3 I/O bus signals
--These are the signals that the OZ-3 directly takes input from and outputs to.
--Simply use them to connect to peripheral hardware
signal OZ3_input_pins_sig : STD_LOGIC_VECTOR(15 downto 0);
signal OZ3_input_port_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_output_pins_sig : STD_LOGIC_VECTOR(15 downto 0);
signal OZ3_output_port_sig : STD_LOGIC_VECTOR(31 downto 0);
--Port extension signals
signal OZ3_ex_oport_0_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_1_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_2_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_3_sig : STD_LOGIC_VECTOR(31 downto 0);
signal output_port_MUX_sel : STD_LOGIC_VECTOR(1 downto 0);
signal output_port_MUX_data : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_output_port_enable : STD_LOGIC;
signal OZ3_ex_iport_0_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_1_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_2_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_3_sig : STD_LOGIC_VECTOR(31 downto 0);
signal input_port_MUX_sel : STD_LOGIC_VECTOR(1 downto 0);
signal input_port_MUX_out : STD_LOGIC_VECTOR(31 downto 0);
--Keyboard signals
signal key_scan_code_sig : STD_LOGIC_VECTOR(7 downto 0); --The code ready signal from the keyboard interface
signal key_acknowledge : STD_LOGIC; --Carries the acknowledgment signal to the keyboard module
signal key_code_ready : STD_LOGIC; --Carries the code ready signal to the OZ-3
--Debounced buttons
signal button_0_debnc : STD_LOGIC;
signal button_1_debnc : STD_LOGIC;
signal button_2_debnc : STD_LOGIC;
--Other signals
signal display_data : STD_LOGIC_VECTOR(15 downto 0); --Carries display data to the 7-segment display decoder
--\\Signals//--
begin
--OZ-3 instantiation
OZ3_inst : OZ3 port map (main_clock => clock_1,
dbl_clock => clock_2,
inv_clock => clock_3,
reset => reset,
input_pins => OZ3_input_pins_sig,
input_port => OZ3_input_port_sig,
instruction_from_iROM => MC_instruction_to_OZ3,
data_from_dRAM => MC_dRAM_data_to_OZ3,
output_pins => OZ3_output_pins_sig,
output_port => OZ3_output_port_sig,
output_port_enable => OZ3_output_port_enable,
addr_to_iROM => OZ3_instruction_addr_to_MC,
data_to_dRAM => OZ3_dRAM_data_to_MC,
addr_to_dRAM => OZ3_dRAM_addr_to_MC,
WR_to_dRAM => OZ3_dRAM_WR_to_MC);
--Memory bus controller instantiation
mem_ctrl_inst : Mem_Ctrl port map (flash_address_from_OZ3 => OZ3_instruction_addr_to_MC,
dbl_clk_from_OZ3 => clock_4,
dRAM_WR_from_OZ3 => OZ3_dRAM_WR_to_MC,
dRAM_address_from_OZ3 => OZ3_dRAM_addr_to_MC,
dRAM_data_from_OZ3 => OZ3_dRAM_data_to_MC,
data_bus => memory_data_bus,
dRAM_ce => dRAM_ce,
dRAM_lb => dRAM_lb,
dRAM_ub => dRAM_ub,
dRAM_adv => dRAM_adv,
dRAM_cre => dRAM_cre,
dRAM_clk => dRAM_clk,
flash_ce => flash_ce,
flash_rp => flash_rp,
mem_oe => mem_oe,
mem_we => mem_we,
address_bus => memory_address_bus,
dRAM_data_to_OZ3 => MC_dRAM_data_to_OZ3,
instruction_to_OZ3 => MC_instruction_to_OZ3);
--Clock manager instantiation
clk_mgt : Clock_Mgt port map (clock,
clock_1,
clock_2,
clock_3,
clock_4);
--7-segment display decoder instantiation
--This is an example of peripheral hardware that can be added to the system
Decoder: four_dig_7seg port map (clock => clock,
display_data => display_data,
anodes => anodes,
to_display => decoder_out);
Input_Extender: Input_Port_MUX port map (input0 => OZ3_ex_iport_0_sig,
input1 => OZ3_ex_iport_1_sig,
input2 => OZ3_ex_iport_2_sig,
input3 => OZ3_ex_iport_3_sig,
sel => input_port_MUX_sel,
output => input_port_MUX_out);
Output_Extender: Output_Port_MUX port map (clock => clock_1,
reset => reset,
enable => OZ3_output_port_enable,
data => output_port_MUX_data,
sel => output_port_MUX_sel,
output0 => OZ3_ex_oport_0_sig,
output1 => OZ3_ex_oport_1_sig,
output2 => OZ3_ex_oport_2_sig,
output3 => OZ3_ex_oport_3_sig);
--The debouncers for the pushbuttons
Debounce1: Debouncer port map (clock => clock,
reset => reset,
input => button_0,
output => button_0_debnc);
Debounce2: Debouncer port map (clock => clock,
reset => reset,
input => button_1,
output => button_1_debnc);
Debounce3: Debouncer port map (clock => clock,
reset => reset,
input => button_2,
output => button_2_debnc);
--The keyboard controller
keyboard_cntl : Keyboard port map (key_clock => key_clock,
key_data => key_data,
acknowledge => key_acknowledge,
scan_code => key_scan_code_sig,
code_ready => key_code_ready);
--Assigning the OZ-3 I/O
--Main input and output ports
OZ3_input_port_sig <= input_port_MUX_out;
output_port_MUX_data <= OZ3_output_port_sig;
--The input pins
OZ3_input_pins_sig(0) <= button_2_debnc;
OZ3_input_pins_sig(1) <= button_1_debnc;
OZ3_input_pins_sig(2) <= button_0_debnc;
OZ3_input_pins_sig(3) <= '0';
OZ3_input_pins_sig(4) <= '0';
OZ3_input_pins_sig(5) <= '0';
OZ3_input_pins_sig(6) <= '0';
OZ3_input_pins_sig(7) <= '0';
OZ3_input_pins_sig(8) <= '0';
OZ3_input_pins_sig(9) <= '0';
OZ3_input_pins_sig(10) <= '0';
OZ3_input_pins_sig(11) <= '0';
OZ3_input_pins_sig(12) <= '0';
OZ3_input_pins_sig(13) <= '0';
OZ3_input_pins_sig(14) <= '0';
OZ3_input_pins_sig(15) <= key_code_ready;
-- --The output pins
-- ? <= OZ3_output_pins_sig(0);
-- ? <= OZ3_output_pins_sig(1);
-- ? <= OZ3_output_pins_sig(2);
-- ? <= OZ3_output_pins_sig(3);
-- ? <= OZ3_output_pins_sig(4);
-- ? <= OZ3_output_pins_sig(5);
-- ? <= OZ3_output_pins_sig(6);
-- ? <= OZ3_output_pins_sig(7);
LCD_E <= OZ3_output_pins_sig(8);
LCD_RS <= OZ3_output_pins_sig(9);
LCD_RW <= OZ3_output_pins_sig(10);
key_acknowledge <= OZ3_output_pins_sig(11);
input_port_MUX_sel(0) <= OZ3_output_pins_sig(12);
input_port_MUX_sel(1) <= OZ3_output_pins_sig(13);
output_port_MUX_sel(0) <= OZ3_output_pins_sig(14);
output_port_MUX_sel(1) <= OZ3_output_pins_sig(15);
--The input ports
--Keyboard scan code
OZ3_ex_iport_0_sig <= x"000000" & key_scan_code_sig;
--Switches
OZ3_ex_iport_1_sig <= x"000000" & switches;
--Blank
OZ3_ex_iport_2_sig <= x"00000000";
--Blank
OZ3_ex_iport_3_sig <= x"00000000";
--The output ports
--LCD data bus
LCD_data_bus_out <= OZ3_ex_oport_0_sig(7 downto 0);
--LEDs
LEDs <= OZ3_ex_oport_1_sig(7 downto 0);
--Data to the 7-segment display
display_data <= OZ3_ex_oport_2_sig(15 downto 0);
--Output port 3 is blank
-- ? <= OZ3_ex_oport_3_sig
end Behavioral;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/SinPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for SinPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinPiDPStratixVf400_safe_path;
PACKAGE body SinPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_lsftpipe32.vhd
|
20
|
4030
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_lsftcomb64.vhd
|
10
|
4151
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 64 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_lsftcomb64;
ARCHITECTURE rtl OF hcc_lsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
gcd: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/dotp_core.vhd
|
10
|
11621
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/fp_clz23.vhd
|
10
|
4166
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/hcc_usgnpos.vhd
|
20
|
6063
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_USGNPOS.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small ***
--*** unsigned number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_usgnpos;
ARCHITECTURE rtl of hcc_usgnpos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
|
mit
|
richjyoung/lfsr-package
|
test/JUNIT_TB/junit_pkg_header.vhd
|
1
|
4435
|
library IEEE, STD;
use IEEE.std_logic_1164.all;
use STD.textio.all;
--------------------------------------------------------------------------------
package junit is
----------------------------------------------------------------------------
-- Procedure: JUnit XML Declaration
-- * Outputs the XML declaration header to JUNIT_FILE
----------------------------------------------------------------------------
procedure junit_xml_declaration (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuites
-- * Opening <testsuites> tag
----------------------------------------------------------------------------
procedure junit_start_testsuites (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuites
-- * Closing </testsuites> tag
----------------------------------------------------------------------------
procedure junit_end_testsuites (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuite
-- * Opening <testsuite> tag
----------------------------------------------------------------------------
procedure junit_start_testsuite (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuite
-- * Closing </testsuite> tag
----------------------------------------------------------------------------
procedure junit_end_testsuite (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testcase
-- * Opening <testcase> tag
----------------------------------------------------------------------------
procedure junit_start_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit Testcase
-- * Opening and closing <testcase> tags, with no content
----------------------------------------------------------------------------
procedure junit_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testcase
-- * Closing </testcase> tag
----------------------------------------------------------------------------
procedure junit_end_testcase (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Failure
-- * <failure> tag and body
----------------------------------------------------------------------------
procedure junit_failure (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
);
----------------------------------------------------------------------------
-- Procedure: JUnit Error
-- * <error> tag and body
----------------------------------------------------------------------------
procedure junit_error (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
);
----------------------------------------------------------------------------
-- Procedure: JUnit Skipped
-- * <skipped /> self-closing tag
----------------------------------------------------------------------------
procedure junit_skipped (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Function: JUnit Time
-- * Converts simulation time to real seconds
----------------------------------------------------------------------------
function junit_time (RUNTIME : in time) return real;
end junit;
|
mit
|
18545/FPGA
|
FPGA.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_funcsim.vhdl
|
1
|
2723618
| null |
mit
|
18545/FPGA
|
FPGA.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
41
|
20439
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
S/b+3WZyyE2NN0I2emS78G5gzXg+2HbeNQqzwGLtTu1RKu+fteo7MzjTyI9oicnaXKbXm4TdJtrL
CBdSQSW09g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oaWo0XEQxxtgWP21Pl51U+TGxBlWSne4OYZ7e6qmcKkFCHhELNUyIgcchKHVbgf2g1ekpEKv23up
e9kNBFVP8PaF46NC8zdQhdBiyHY4Fble0m+F7iRrQDFVq53YvvyZi2itfVZuL7dDvQ7rjRV6Giht
d2GSFIryCjqjBh/6DAc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
koGZRj1ONYx4dEkr8kV6F56aDfCqsX6JXZS12blfwpx5PIsZJpmuDMgIo3EW9N+IyQs4IZBMiwKe
dSc2JRW9dzyPk3KGLdehLg3ND67uw233AeitaTQNrr6Khu6xVvrozPCorKIax+/0Qimi7XwzMj7m
Xmf202/pn1cRzzbsuAytg7Rezrh0CchL179vIP4VPBKySnasBil6lSYkJcqS06VlTMjTHfRb3xfi
tafIIN5XblcMv63ip3KW4GQdVYJSfWiROSHkcNAkrJKSj4blZtQgdf2tQRwjIt/Vj1FHmqZ9SrEY
gKl/wx4gLfGe2zBgz58itJ4qyGkNFbYpd43cIQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
PdvDeCuHOT7dB2KRfG/IK54ZEWbz64WrER1IKCkqjLU8eyc+Q5B8d5SeXkSSOrUxYfGW2ZL9SNT7
xRi6Jen90/nlGOGQoHQeH4Hv2tMcpx3JZR4LJSNlvk0Fch0YJ2trGlRRUgy9/5BYSx4fpo3IduPl
cpgr7ySt5TSihkyZPms=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MRPtR4KhdHmz3MWfpDi9vdur+0ZJ64TDHCHLQePx1vP6vpjMfLtPdYmIOUj0hNqhjhWBIqWG7vjJ
Q7u7NBs7PqXQYsEqoR/q+MOp0mJjWU6WKlEmqhrW38BvR5rCZ7u9yJx+xsMmX4wq0YjHXCc6HE8T
522tbLrKEgFXa+OBJ4AkLBo3rExrLkvYOgPupOW3BVqIZkXcv4Eld+HiJjV9reUW6AUqY3TxXDvB
PUv0fi76Uyy32UyQIXDYVqGgJ8fBKKraH7t4aeBG2IN+3c4syZtKiOd1xmPockrVtzFkbkKTsl+N
cC6PvaOYL5JLQTD4kKCcofiKg/q+bQsW64XsQA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
XYR5EDO4OXnfXqXXmJxxpRof2p/bzcBe/0WoxyLop8Qlv4cggmkdAVBslAsEeQtj/RtHKy+8L32k
lZbmTjfjXu8oDn/bN24hzovJaZV4GE1Raa/eskUJ1ghVUbHtu3/hZp19nSNO9crfXNsl4F55SL8U
tNiQsfMfWV5zcMnSdD+Bq6Wat0N7w03HbU9+E7Q45jSweQERqnlQZAzPdjgQ2c/9IvIKwPAXQjk8
4VTYCfSv8QiYqueJHPFdnCx7tFLp+G3Ney1SUrHqYWntiCcvZzPnLrWyuf816/FarCF5mi58XRQP
us3Y0GcgBF7VEh8KIXgGnDAcjP2Qdf1sLWSLkbyNZ94Ov4EBtMP1BuJWtlkNUOUKWnp4TcDyBXPs
jBZRza+f937VGzJ3XeaetrelHgI2V6IEZ7n01QEIpFdiBmah8HwUlN0ofHhXocEVBZZkrk7DaAnz
cPfmSx++0FWAU8D2ygEavfs7F9MLMi1oczH15ZY6BQbDtcKaBXV/ZQwADXsg0/SeQmw9E/nUGVrs
jsVohZ6bE/4CeuZzSdwQjYoEwOgCNChhTvwFTW7mptGm/1MGEYayjw15e8+CQnvwf2jt6iAap8JU
UuD+XCWRMD3QZ3coiNS0Zwlnuc2Ed3uw1US9vKtS+239Nz7qWWPRbxjoLF8Ea5sLNwDuJXbgcZTO
uW+AV7qkalRcZDRMIXMFahusuGxgRFa40YhM20sO+uOESaJjsXbF/N1iP9OTbZ2uaHELjYCj+5fd
8XN4niDQL1XYgYcNvixIZnVfuhJ3oIVb4/Pc08i1DRviYai5NrF4s8GbMQSBVmsnoJOJ0qBAgZ20
Flk9HJcjeRwTWIMY/PaV6S2eEusmj6hWfRgIFGwYoKG4ADKkCT7CllupSQ7HZ3jbjzWbHdLSjrrt
ISoIqt4iMZrKSKG9li4ACbIZuDcPtPBArj55TVsB3cSB4iNodHkc66+pYQsoLGY7E6ORwoYxh42C
Yg8/cTzGCwJgxBHsg4jzxgDgAur1pKidiyIdwwXMK51xb/ijfjO6PsmR/gYPCOu6dpVIvV2cAh5t
HXh3fl/6Dfn0H27BNH5TW1uDSI/umw2r59SsLcQ9ujPpDCBnTjH7qxh7D53CXWBoV2aTqdbdL+Dj
IAw5w6LeZ7ygbkCdQGv02oOvIdtNlQ7vf2NWt92ssen4IvgvC35TeEHqTFg+BbfnTIhwah203+Rt
ENWHDo7mrJUyjyKzKX4uNwoInLf+M6oQtFW16U/sGlfZJLJwTRUQ5Ddro3bcsfC4tl0tXmiseesj
cNW3shMf6CPcFulfCxAA3gVspVxeV8gfrQL0dOEODwPe6g4qV38mQWXenkwniyWlyEDw8q0ocf2J
aTd2ReA6OlgPkkSroctjVWa8TR9bW7IV8tIySBJSC630iMykNOep5iFCfrxh5rcEjlFXFgsKvf8R
swAyxyyvNToS16/+qd+iDOO29Ey6htPWw9zTmLvD42795302PErW8N70PCGpHjUE4uc1Bd6Jz7Q6
diqGUf6BEVm/GopMQTVlkwA5nL2S5xz2E9dozGxSCf677XzzMVwRkbt83+wGp7JG4Xv2iuct7re3
BKUVJrtwYh1+akp+nO3hgVYEn+2UApxWi0HpJyBjAZOhG97+xLmmjxN3dMSljnj1pa1UpaPooglq
2psTnc4rxpdNvMaQVdjlLUwWc6HwwbO99GP7E83ZL4RrWPLlVyZw+1KTU8wErAvksAX++noFASc6
a+E7maWcvzZMrEzMtwNJII1IRA/I2Y0552XYUDNrFvIDeCa2DAB3732zOOcj1zyVP40wza3syyKn
vv/EvIp4nS8wPXkhBGZLpB/9307T5oqLdMQ62Ui7FkQOgMCswwWiNS5nYOm8kDQYbGxu2F8S7j1f
sk+BV+XyaseLfyO4H7Y8f+mZdX0MsepeMcs76HN0ZaVnFzChc2tuU5gdtNeUpgvdpUu9ZrzAdOpK
A6Wi/siB5yPhfbqVgsJcxBgWqVsDDmg5wRMgQuUn1kozM/CZ5mlcsTJlAa4dfETazDD6dfRxGXFe
wv1rxC7LcACezRXZapsDKw7z7r0PsFlkcc37Qau1d2YD587OZ3ipMBexXOvc6dWvKoaLbFWREXiU
GbT7knkWqFlumS6UTyXAZCBp+HiNJnzVefp8MNcyg3owh5VaiwLOYHz+tb5rMHlIAj/4IVUcOeEO
l3YMRTRG8vzK9PG8mfTxn9QCTbh5cRkagUpbKYOlMnunrL+YncA7CdZSev3LIVEzvnIz6R2YpG84
JUcw5gM7Nl2dEI06gVeSGW0RhTOPJ/ZJO0bHDdFg6kPnUiRO+F3D2Png0K+V0T2P7IWNMhlLEjkS
C+sdaXFrDJiMKfErhDgVn5eyDLeTyX7B9yFOaUvDOiWNRQdMmnWsaZDXk2fr6XNLjORzJ1y6O4mw
vtVf0xCNSYkDODnU0stPUBiC1n1spV189rwplzCf66nC5tVs2GC88atONAyWQwj1dRAyVyVsaND3
Gf/36o+wZSnYXTRc5lvPVCTsAffENrYPs6DWdicGpl5ZFcr0m83KygJrk18NK7tQuIjGRAAED6Mn
bn1kKLlAFneTLfW/EijF5pgqXzSe977B7kMoSu4LxYROi5O996gux2EHMVr1GdXFW4NLW4oIVGeb
Gao3+1s+xpo4dPXITJ5vBtlr1/JoFvilbxgWj4VsutdClozDhYPpWYZnFujfZkbI+E8iDJ5q/zPb
Wf5A9kt01+ojTOddPhFyKO20YkVMtX+gPv6fSU5J5AK6uui9AVDgsE4N71GpiHkYJuZKzIzBIpro
5hHvNwv6lSZGkH4duPwH2WCQonDRIIz9LlJm3PILdRWAiMXC86EsKhuKVzsmZC8/gbLbiFbcrLBb
gCuNW4gN2XSlwgeWyKofdakFMowjvWpAHDQrpedBU9NnchjhDd8PqnizBKRRsUV0s1UEoEjmZHLA
+8AanZrNRFT0Se57vpiF9mkeCiqywS5I+SOdmUs4vTtgdznsrpAbgQ0N6NLN4rOkvc2JacceP/4D
iCnI9Cm/VEWTytVpA3We3x8M9cDuCFxGawG1tkHmyOqvZygojOj2+jhomjJOxygy6L+owE/h1+ND
5XViOE2s2eu4TzRz403OJQo+czP3dnMh02kJ5c22uf9BX3qUXGMFO3OtSYhzGjwnpSbV+FrseVi5
MT9e/G8Nyc3sMTbvO/oc1kNwfESatzAgXk9eqQWQDEs5tF6hHdjRxJJz3lmQXGGbSMJxTT2NcbsJ
RSHdqB70pkeeXe+ubb10pX6+pmDKwXOMjd2IOo/8kmHsk1525W7A81aRv8MGVooYvFz6B/rN1dUd
Ce6xX6b1zAzFG8sRd9k7CMMdw4qpOqyvxMUCVCnKOiYRatnmx4rMacVn3sBlvglGXspoWhwLkSkb
HVkiyZr/qMUxXT/h6AdS4e+ph2wGye26bZqGzrUwkOXuS20I6wnoLqtSfJJRzhnZ6Mba5WV9j7it
wROgcMVDPUiwfEwgLMrN8txsTF2XwhG6H12H8rgnidOYhI0spH40ztgiIePI9ZZzaJRD2WRzGcOu
AbzHevUCrFvJ/At+cI4uL81Y5++AZgJLJE2xX7R5hm6xWC2lTjZoOMPwT5E3ItVcVRjQZ+pLLmoq
Gt0rBSr5T8GbRr8WDXjez5FZ7A0FE5LRsVhxalqW2OzJ1TS09NXpjOgsA7Fjm8RJliqf0+ovGn2u
3HA3HyL3h76CiOTls0QUk5CFiUut4nZ6y0BiPz1nSXx5qJ/FGYMrzao2B8lXS+HkKSFvick2Z+9l
n+2Kxj94Ex06hSBaE+LmFqrDiIPIUPTpfCeMJQtojuJMz6xLhMP4XkE9/Kpr0Mo68IZuZsFUZAle
dFJl4cQtAgO2EFL/30ieERNuFwjtFjmJ102+WBrFDFohh3W404Ywr9SFQwW+XOhZsCiAMk+lmWpx
TNFCR9b8kiKj3gCSctRouxmoJEcPKLV/2bLRr2q+1WGVoyHftPWNVJmQ2BYLJR7BJ8S+0O5JLerd
tr3BR2WIvtZc7YMa2sp9BdBxXlS82XEyp/Ju2fAwCsGOLOPx5hUsPCRpkEuPGP1LDfpWzi0/kMgI
dlgiWDcBGjSDsP9B8Lf5Uf4Zs8qX4l/wNyWZAiRu9DjeiZnMCiusr25Vb4/wZgYexkcSX8I5DQ+8
ycquwBHNkNCJaD+DmMZc7u3xUZB1cxQv0ThdgPy0Jfb/lKuWnkZGveo03srjUTVkM9iV6a5uakGA
RN+ubnOKjtS+qG+hkL/ligKIugEQAY3HxYpUCpT6JnpT7C4T/sGesr4IOq4x8IQStLG4Eyfugs+u
XbN1Y0oW3Kux+dnJ+xAmh3SyPT44IY8JnADS3zF6P9u6d0Ng7rjgatBLaqIXokTW5XuzOM5N8iz9
sNT9vzSDnRSRCb+ad522MylPIkq+8JrkHchJlXi2sSPFzFbkMRjh5yXz8pHzCcQCiMVBIGZ+ndjr
jub+C4G3LrFYabznIK3ORWRMYxsxdi1inamz+M9jxKVSZ74XTxgKA7OKInpwIlbHpe8IexEJb1md
uvl+r+KPE5ARw53nqba3DLg5gDR/w5QCiA0/jHjW4eLi4mlql5UMKnVZtZe111G/IsWbGUEiZiBU
pCteLakVQkGDETQ2O87RjS9gEQtnMPpgdV5bCvtWQRfutFF+aWfRZH8pWDaZ3eJAQoYwjppTjoCF
1Rr7kS1ZRYU1kRaI3JIq6IGS8aY05Ql1+GhTJ8eFBXeW8Kd3otDqqUP1cf0Tx7kbNPNTplZKTrb2
3QvOvJaRz+KV4WEoyL9dPsD1QpH1I6J0OXhEJcDogWqh3KfyKjdpS/fVVrGWlas9Vb0T3xU5x17B
mStx7DKiD3wpi2D2VNhICP+cRBSgY51VUT5Htu3KkBmi2QbOQPp4eDXdWgL033HYseQC1bNJBiYI
sv2k2eSxnH0D8QsaTg9tkT7elaK4dAaJwyqhG+Ig8z3i1iOYnzkLkJ32EV0j5tOvbkodq6g0elzn
sP/cJSzxcI5ymJLiTYhkEjYk2KfQ3R+UZoPig09qPvBDaaOKciddZCeuJHILe7ZLGG6cHvqvagIv
q2D80XWa1cY9p/bq8wcN5UAvtw327anVMXT6FM+UAqRvdVcLxYGqI/ZDhevJLdzRTeqiwA+hvk1e
EazsnT3OcvqEOLMRcfplVjfmgemAMHzUTj4ngnU4nOCHN7moPR8dgEWP+zjqpv9CmeGU2oBg5eV/
FSWfdEocSLOz0ZipoFU9wWyvHNNZCl6fDsIMeDTv3v1oQeIEJcn6XbVs3Oh3RwvSHPOJiXcQo+7f
s4BvpT3cRX74CgSCzfjJ9LCuVAXsUs+fxv+tLIaOtpkqaqhVVvlfme7TWWU8jCXJRkvFkilPqfre
5Lc4qmfwYxqqJWKF7VrN7zTtdNaehsLlJq/7DCGo2pdXJu7HTbmrGgu4e+Lm8Dj9t+a/FqY8URie
cmL5/gKw/GZ0NdyYrQQ0FGBcFdXDStp8l5/ARbKTYN1B5CEPCDeDNT5LU2TcAKApFbn+Xylx1DgW
oYVfWQ3FOTU2rVxlhv+v7wbcn0Mn2LG2PCfEjEnEunkGIX1UbG9JphDP5Wcw6gvcsOAkrS/FpZDc
fZWlNmWYw8/Tqf047sXflqaFuoPEPcd6vWwhK/8hKGXLR2oQFN6E2LuePpVR5IfmqTBknm0L+LRx
adrUkjkWRzOsSXktTIFWzjjC4E5CC3Zw2Y/qoDlPcqxClCbi9dyneUO/84eDMBDZj3r85Ud1ZL+J
rR8mPNJfgclwLH4plDSf/9Z1FL+V44yEm0YfqRUXAGsw7gNwWB5QF3msqxqIWkOrjiLnLc/Ry9vO
MCEgfqWJJPD5G7BBey5VqhJ4hAhVp+OH6rQ4dXobEY/qFeR2py0T6/9oUFcUT4zrOYpGyyg40LC9
p7EC6uyBf/QHiofDRdfnZ3hMmUuON5DpQF2IsJ2JtCdFUIDTLfMh0z/dWwpsU/KUZuhfuIO2fyvW
Cjk6xRNP7RmExcpi4lhWV10Y6G5OoEg6ARA0T1Q0l5VNOfHDNoKi7z37tIGLza3CWtUbeKT8g/os
r7fehAV73LcDwBwFvt1BTaqAzJ6ESfS3iRRAtJfAUGmzLpJC8YpgHr2jqlikUet8+HpXUVohX7oJ
obmvM1lySLBBsSVRh3oJ78iPjp+Lx5x2cneIIIIcfP6Wp6kKxXjsYIqb3rXhHDCb+cwCnfm6Ha7m
01s8zod7Nk73FokdwSllllg/yb8maAZgIuZeFo6z1LZ7Z9WgvkzWsZhn+bq2WsmW6OWmLvGYMZ03
/5gIz8wQrjbk79jAnR0onPz7OSKQnTGKEpAX3hCh8qLmoVDiBag0z6lPbwVIg4ttIysWfyfpw2RO
g/c6qhp78jQpb49fusLcXI9QnXfOlkt2HWDdEd6blcySGoYZxe4WZxPPth6IByTLpv6HjZ0WzjEv
WwmNjBh98Sp2kc/BrcQn3kUP4aAjDDLn5iXWYVTVaBLqWHKjhfZJtwdk+ouEb70HJqGf/xZov0Gt
EBb/WIPL+CnMyqJ2iHrw8yXn+h5Wz4LQY2OslmHImNztaCAtGaTg6HaiZQ48IfniGDRQJsbLS5DT
NH/2hAsB2n6Nn8i40vMGMBGOROvJ4Kn/O5Ic0++44PUDiUJrgsPKOb2In4s4RYCkh5i8HZEaU1kX
aISH1SiysWGFwRDBoq8KKOi0g1t0QdMg5UCVaEGg+TZ1oCgpzPEezzQjH0hWAVEKjsXdVw5rblUL
AJ4BDTxVo35dekv/6n9IqXoXo55V99OeTKXIuPN7WwqQjdZb1apQXyR1Shx9D6/SeheRczDbk7MK
CfW+c8S3jfef+Ah6LDnEMCTv97LIlU9MC2ImI1KcAj6Jjdgsnv2j/Cu/PhnaTPgy6nqZ0p+T+03s
yiH+Me6dPfcyLkDaiNPYWkJ8+GIRscCTsD1zzo8IM1yEN3KlMWh2X3yUmtC9HmFfmo0pV7/b2GQC
Y2046njGtLDglPhEM2Gd8pjxYWFlNdzqOlAMA+y0sfiU/izWcwSWqWp2UXgJ23av1DATSs2+RzzQ
D+XWvBvD91rak4PwVMDfUXK3rxQayZzm3toRKt3gweOpk6Mxyt8W7NaJDmxdyha19jvTEhn3RJvo
vOL1lDqYPXM7hbcvDnHy551FtQApgKQCihOGlcFx8XMuXDfywOWQ7aKKtqhpJDFAoMiG9piYheTU
NX3+RkTmf0Vp4vtrEVn7iyjKuIfswo+8ObQEOszOUela1odwPiGYcBIMtCPbmfYw3is+vqwpxkxN
3VhkfBM9o9ncCpMVpDyQ6ZG11YS4Pob9LrmUj/Q1cPb++kx4GacgV4zE9PuP+4cN8jnIfJbnNTDg
bnjPrXObCj0O7msOY6v1CHhdAMR5FsxJ/PfBBlNeNG49qeJnt/4ugJVJd9S+W0dB57Nh2G/6WHzV
wXDu0Ugc9455b2uDWw9F4XuEdWjte3pG4kDVJ51nC67FziwRzKyfFrT1sSclI9jIATnc81P6xzkZ
130muSr8YFGjL2NG3mJZYtV4h9f/zB42ou13IMLrjuElDTLHl2F3vn/mq0y3CgpUcxYCbvixwABO
xIBTKFPv18L6CEvTK5OidN9rDeTgo65lGQCDt7twrAiduXsMEYCxlp1P2fxVy3waUOnqoUt9kqkR
Y6S+wtruIKpxA2r7DoDFs/RGEcaJufffxRZzM1tGUYsu+WBzhpIHqbgasZ6eFWm4dMapFOLF4ptc
AP1Kwvp/E0SGSWnNK8CldMnXJk734f9kycAZZ0Uh87rq3440nZSIvCg4/X4woQb6o2pj178STtxZ
q0qNgFrqbCSH6KrIxUrF0iFwfjV1ihhrtMN5XQO3ByFRBiBFqT3aKeD2/zFCOsPzHJULfogYXCmT
HME6uU3mrGtGjSpL5rUrCsi+FPU5MdxfY8/RCScA3CMxcV2F7tQ/relgFtzZ9V68QxyznbDUrYv4
/V+ulQ7bIQwGshiAYfir2hwJoDWtmP2faPiYoxkX4qYoRa5bsn65d+hevAqoUy1x3xB5TE1yVfNX
sg+NI9W/bZfYvjKTD0szBj3zS5sfySYAWDTxyiSVgxPBKNvLP1FmE5GEdXXxn8MiWZbzs4nftJ5U
+xJ9q93lOmnmlBrFLLQvkN89d5xE7vEQvec+aDPlIwtSdG64h1qetKk9NlGae7bxsQtLkDmQoSWx
sisXnRZn1IVNvCrS44vVeRyj2as4hnH+mDPBkIqu8jG3j8VPj75h6A3kXXE2BxZi+Auzy1B4Enbc
QR29J2ZD9pYcyWVlUJLkvzjoJWnaE8iqRPqKsVqgGi07pwp8c1FmyCwQlcCJXh97Wdzl2IDL0ZY9
DJJ5EwJDsFeUC3RcZN5btpjbHKo2Wu3bctFTzOcWKioYPAQCdttKFkL5zknfY8ntHEXy0L81/Hj+
24YuIBXhbn6L4kfWllHnqQnCgmvtGKbrRwRZbsghOMl8WjfvmfX1HiPfbc0wZDZLpRjyM/GVcTbW
bFXXIMap9caD1PldRZgaSXP98xcsKVbQyAiYbwfdcPuMSyURVkiKNIc5XiR1YmDL82pIvlY3ox04
Fi5ner4TjjRNzHnznQ/tse7BNsFbAp2Jkfii7UG0XradZrzBHe7PzN16hIiqRPcQxs+cep+/hUYU
K+9RDBimtHGFRWbuqtx8WOWQ6wg+piMx5qpNI74oV26QmHUqp8NubIbjaM7CT7ImSIbFkvl3su+U
fOjcQwh3tnIjBFP0N7yoqneXqZYR/KcUTuYO8d4b20hUcwrJH0ZnKTYcP0QJfgY5F5VOfE4MWUsV
qBwxUOPBfBeK/62kcKCyG84UUiCgNOLfjGdtRgP+IHRXGZTwlWtQcyeOBjgIcT7ix2rqDo7u85+t
TtgvYALj1/Wlw/0G1x+DNnreJzZ/oJypJOupx0ZQlu2oF0xoNPvxmxGzEz5BUC4cnAnmvhs6ejDK
kuaMzJSGVnOvB43tIQl6/pTX3k2BhCNnE/ZL7heKvfI+oSXSBgpB0JIt/Y8chWdsc06QOXvba9Xt
2E6b630VuaDw0suqT4mNrTwie0dxyrfR/MgZmW92TRhNOVCpKwQJi6+L/vDpyNazMrP72Q1OpawA
cPH6+7T8k4Zxq+3LqDd5eWh6QOGlQUVRsa2mQuIP8aNWXxBpCbQi1Ugp17LwlJ73YW55CTLYRP5o
dyddhuVVsYUqxuOvQ+lvIc1xU0gox48z7XhRlf4oUQWMSmJunQfwKEh56VCejS38RCwandNvE4xZ
NablEwHtjhaLIuk0XA2PKz/2aMu+ILflnfZ1u7ThtNjygE35ntplh0nVNuo97N7SE4Sr+uQxgmmm
bly8gmgEeKsNEqjLcaN0w1o3MLbLQSOVVppD7oeK/hohMd0Zx2kucrwQ+ziEDegdxFPXDPnlWCMq
OccswRWsVEXFGpoIu4AxX+9/9cxRdyW5WEZWj9DBoNAVWh7EFkiZeGAu1+2sIZ2a1vWZIobL99wA
WuCg1J1Krde/qJqsXD7eguB72b+NSh4Ez8ANudpsd2uXlf3iagl146j2yRHrd+FhbKHvirmuSa+4
Th6IqWlNLkfkFKirlEPswDc6rAEfaS4EM5yGr7arOOXnV6IEhzq9PBgVcImQFjLDsuWZ9K/HMIeh
B9AEmwxzNTrhYruhfRA9a8hA0dD2OEYyLa9F/YH9M9qHpZrehmGdS+MJ9Gk19ESRjObDuIs3MTrj
s2UpOej3cWhPjdjar/OildS6v5pnViSKiiIz9Phbi+UbRvViEgrKqz6ILJ/FmpFCfIAIPMSEzhmp
ARJgy5+x/XsT3CG8L9jkYutcRkA0+QpZhQWCNlTsuHKR/bJnh6wmxKqGre6k8S9U2jB1/EqimccH
VoNl7hfLqHx6SOZ6JDmVuIPh0DbljPtBwRGomT3vMrbfsk6aa11p5b9zG/+yG+UhV+ee+EUOxZk+
TdpWkJgJbkr1IwozdE4/Cb7nj11QfB179I62uTCfe1NflCoDg6DZC5YKlEaCMDUUaDmEPflshPgH
1ceG5HsoXRd8UKfDv+i/rREMq6i5+2Uo12VbB+aASfO0is5VoQsX7GJSogDv/5RTrLZ2P3DLj7GG
eD0ihaCE8SZSuacJVK9BgEFGYnOCEbD2KURdTFa4zZf1dzu7m1QdNXGYtoqiJ1AHm+sTXcoKObCC
UPi+uuB4W7KNMKkPnVaWLmE5i1RwOTXicMx0Al0br9vPzsvKncq7z+IDaDer3WLAlhdEOWd/3o1t
tD4mOtyWjBYDoNDpNPPV1wDmofUGaAtJri7pBf9wYQ4Wf8vGF8z7vYryuGqOYfFeQwlE0+6ihpIE
DG4tR7yTYPqj16XzrjRHCt9ovoJmgLn4If5n2UU24wz2wYlLlz58oIK0DqsXoQXB/u0eADKivQcz
UZkxMYsWdwXznLR8HZJmto+xI3bjQ82sc/myOdreShdSxj1EAi/OXqgo4EzzoDPlMpHy+z3bGZQR
iADvGd8hjBFCURmukazHWsSA6Tl8nRn+sVD4RA8TIa3KoRbwy6809+CWj4+wYAOvbQkUCFKHWrcu
aYdvVSyny0Sf8rCRtVF5uk68ZQtHT4C/nO9us2K+qCJL/wRxNHV1c14919R6mK2zG0zyehdz/9RK
/crjcikT/H988FpPhvYmBUXzm9eU2USiBRXOeVKvII660kNtt6MdgmtQyPestA3N3vpmbNQxYGRV
aRYmP1VEW3k/hsewG7mMk0TfGyNW1Zn5tUXqF5Fm447fvGYBaLs0UgWk17Ns2yAvpJNNX1/IgC3y
PYJ0vBsTui20wxdtOayZhzjdSZJGvV/2Pdxaevp6vHxS2f2Yu5shVrdSq5s1fPPQZZVSEXtntRU3
xCqEw/aKXhO4qYFhLb4m/Opf3hnj9iUhrmVIL0taxUcFPqqD/c3V4F4AbptFsriohaD1iTDDDioe
AJzvixVES5eZ7j7zUTQivg70PHlwjggcCEtTTnmfbKW1MmGkI5Ptel2Rofll0AqlIqKnVsh+V9DU
Mr4Y0TetdleHRfcR5plMhNzXKvE9Pa8DYaXXFdDOJKVEedCagzdDg4TSOcKc4y3V+W20TgicWJDa
jqDWWMXbj6c/L36rdnBkyV2ziawsa22Izt5RRyro67rZju/ifpfgEwaYUlxdMb+shj47An0uYJM3
tVnRo94TeyV3EPARAiGgIWyvyf19cdMkYbdATAIdZAdn87mfQtKxq7oPM2il5OYkpQ/Mb4Z+pdBv
AnQGOHPun7RZhzsM9dY73E+51uDAI34J8U204dsam7fC+cuTTVV9/FHXWsSK9qdeQ01zBYLojw22
mXL9tDFxywrzOHC471kK1WoDpdtbipHHeLmZ964le+485EQy+iFPE1v9kmJFF8Eysw9uBh3WRYhm
xcmS/Ap6Q9ngE5XKDDoUgWeSMSTD6jRJ4hqLPULBJiUjJnkeQoFfalRMfMKtOnOF5Mz25KEKxTMh
Y6BmCa84/rp+6jnontD2gYTwTrBE93OupwUlvYKAOho9NO5CQeenHRPlUOzJiDzfFIoAM2C+Ekbp
nTSIkIa5fIirtcuLIDPOfC5EbELU6LwXuzg3rlm1qnLlK0HjUbqIMNMtOBsAfZIlQlMT9qDH4cwj
kfQZi24RZQ225GLXjJKcoTExPPAIre5+Ip/j7Ic76jKNBpLJA0m1NYy2CZ39qYIOqFqMi/15jHNU
C2G+ijG67YLUbJoebwMxtWhNB+L0jiig9qBx0vQb6yfXzLAAyjMaYHXs6uoFn+0I9DCXb/ZS0Ddy
LQpshGBu4hs+paF3ymVerxg8G1tozF7Z9QCNfd5P9Sm53URH9u701saxdIJI7RWr2Se5JcMlz0B0
y0xL77exLvaaj0BW3/kR99tcKXtqAMZWgsVlX8+sR897pyexpcKPz8Z2qD23ukhVO3C11GrtOVM7
1/DOG9QaH8pR8tO5cyrT9BQGrzz61gq+wEckO0OqTqcllC4p7Ws6AhhWGc/n0p5IS6p9lNBiQ+DW
2i9zs2Xj/rCaKaf/6kLDcu24EeWDqsxqpuehZVOG87TJJ8dz4yG5t3L4MZFrGHWekF/kvm45wBdg
+VsWC+GCAoOLY1oNU8ANyzur2fWl8t8zw6zD4W5fkxKXpokUMliYSJYgs9QJFDsS+P8bM13Gwwe9
7qenYSaTvsqXx0LvAnlYFatK2if0/GJe1b45L3rmwmHiz4He0JBUg5+veK1TJZyADwJv/Fyt/TzM
IMlE9HtPS8BDIzGYVmVWHHWKIHUiRN0oNEsGvNDawKZFLU5eFiTvflOtTjFdHjKoexES+TbdpjG1
bfAaXGR7oyItZo2I8eu8gY4sc0VNsfaCq1TNoxchAsQUQThMHXUwkKZP7XZJ+aKSMgbpyADQLkwl
H97dRYew9QQc9NyDJyLnqBw8YaWnCnInORx1/AeeEjBPOcctR2SJR/3CD1GYLmb0mKDhv+oxB5ep
XEfs6IYhZE6WZExRegGY8SSWKH1d4lK1ht9okICDoFcD6aFQdghONEZpjnXwKS0S3MtEy81gib/b
jlBnGnAiWA73Z9It3N1sTfWZGI2atthgBVpy9AGvNxpZEHPjQTAOqcn/VBvaNA1HlQJvMnWAyAsU
GRJBjAbGS0pGzPo5d6qkX4slprdgV8s+VtN2iXBwsh2uOn84U9Fd5vQ5QMQKK46YeScergKqPpy1
gBis4FvgcaiUdoNlFreIFvKj1WeYwbiBl3b5RJVqqrSPv+Z9gDwMx+0WqUqGNtJFBFE43CG/6KkJ
AcA3RCI8JYSfjNyL39UEl37KuvXtK3Blc7M9/H0JJdKnONu7q7yOFfu9fNFBBzIT+XNerX0r1lTA
NZRh/mtB0TwjidZrDrw/iMj1mcgKQXiQ46EpMkH7oRrUW9UIAuI/TpQvEGD0u4YvMNQ2+Qu8uyJt
FXTIcMg/Mp7NNu/DxAQI1WfiE9bnOq0DNwDGKeT1XT7SxUGQqxuGUSVZ4p6/70OL6tQljc0y5xmC
ttxX69CXoixVf/VuoEqTrXhirPM3+TgqbJ/Y9if+CL1P9Z/rWQju47tIbPlZMj5Xpc+/1J8z83ih
rZVU3kQoJ4OEoFg/+7MYX/MrrURAA7uWBmYf5cr4Bi0Xx3CBIhKr/AvwcakzbCmbrgjsoJCGeFAO
aZW4P+HdAuhyjLcnGuac8x107TNBmX8QGeoN/d4+mEvTKObQaokkb0TlHb/b2FEk7tt/oSBJQMWa
814f0jFIJYWkWSqoSzM6HdrFPXs7D1SMHvplFlO1ktexYNqnfogwX8/rSCX+VqZkhTKuHPFeSPgl
PkfNQxP3+C2fvTXVF7tT5UJKd7HVY1bI0MNVzF9sOHQuYPBh9rHQ5quM/bZRxac6CisTvcuwQU9M
LNe8gCpZ4VWvzWHAnJP6j+1SqwKLBP+DM1Q4jUZZQe0u5qLERe1FMuffgm5I+FS6hVmPOqAg9uNr
OMfQyTmlfYPOR66ohLCBaYTgHnLwu8mdBIuF1sa3XbRbKvetIRmfWN/MXZLrkz+OltmQMyW2xvdK
TrFnsY75xhsyLtYjUMBNxqNXWpzkPkNJvW75fVijaZLnAiEybCrBvWQgnFcXFufICd5VQ/Op4sG5
MEBkIrH979hhj6GBL8JIq4SR8kkyTWCogCT4DjocJhGEXAsweTbY6kYFZAooNqosPa5a1ZasrPJ9
KR8iLccWQx85ujsURiiht8mqheFyNr3In7FuPPhFgt0xHP2A1f9Hdlr+3LBd7l+ptfQpjnXaPwYD
adUapAatBx1cpdXqAW76vrB2/i1YP6kXhGNrNmRjTfYwv3hVUBblH3vgr6SqFSxHqW7alHP4zHIC
bQQXuby9fmrWIghdBEBetGrU1YAfF9oxyXtBjblxsCewgW5rBI94PO2mapwzHPIy3FfXaQvIUpht
Xc2jYHhMoQAXZDQASMQ4fMF9S1SapZh374yQTLj7G+m2PfF+Gw5ltdqr6a3p9f8FhxOb07Atbxkr
Zm172W5Z62SSQa9Pgqm1XtZvEgncfESkN9jou9jywi0RbMMFZziuui082KsIYpSdRIB2G31js2lM
veMyoPp4CHDK+WBv4UricxKqrOPJLVcuUTQQO13PPm/bN1BdpfjxtdauMuWbhv1ri58+FwP6KCUg
EjUyaCu5x/pj9qOmn0+5j9iRUp2Cuq5bdcSiCyVT5SLidcyPnY9DNb3Tb/kwh2lqAC9nmGNrzasz
TzC5Se94fHNqyNtU9Mm68fqXIl+eQNMugBu7s9JF8nxS2xzA349fgvFDJzp3m2uNmvWAXfg5dGme
7p69zyVvcxWIeivVGO5jsCk3ok1NN0lKLx2vLHkeiigDou7rG0IuUzHqNgyY9nxbB+nwJHUrTOL4
cGCppD/Nk90K2+B+vuoFsRW45G5CEPRdtchUyTP8ZjCz0EUa/QSBBVWPiLVofBihAEOS/00jl/GZ
jruO7YGhhn16UlKvJdACa7rWqerLpkTXHG0pNnVwwynuBmw6yzffx92tbNs8bXjHnm2XBUItGTH4
Nrp/bSt2H4vMPl5ghpzb0FWN748bW/fw95tILnesbogBQqrwp8K1nktbq5Kk4GVQFHIVsIXJmEyc
N6vXWUeK5d12KDf5VJbsWBpwYVaT6JrSlFsKERTEqKo6D4Lb8YWbwIRjMXuOtnH/CP+d8bMeOcoe
1NHawKvaTIVQbHvusIStSSLX6Tv/aI2jsFSLz3OQI1liod+GjwP35mTrhVTtOyMzy1wKOIXbiuNU
WfP7xPBhb2HdJy9vqxhKl2sSMvG6nM7VjByE2Az5TjskhxTk9h7N6e/2Bar3hUCIritgOcvQWQAY
ugDYlK9LJRNCZvHj7PySQLnQNXlKr5YM6NnxfqUdXbqJL7NZn1iXFCJRxwVqKr46zXULWFz1ZaIM
pYcUPZDJUWls0TFJr2sLYF/oxRV8AC/j/8xu+gcKHxnYdWzJTERiRcX7E5miL2mCAkKoFV3ChPhr
gWsFkY6ez3tKgmDPGbNiGMaSninwVtZ41EikOVeM3bDF+59tSnBzlNO+h1tZcReDQSAmXQktpySx
AuTcEDpiM1MjCTUQPPiJmyvDBUR0xJ4TpSI9QTg5yZhb10FootnsTWx/40JzCfrdS4AOcTZmfJnI
gGIfmcBUOiqwF5VNan0xOA3+fY3lQw3yMFCwG+erYWpFdDI605xWlRxjllFM7dBMonW/Zo8N2Dfh
vKMm+7aDsUSvA59SSNBrcyT3BhAqJ6s8BSKnfyFFmBRhs3hz4mS5c2Rf0jwwRHQjoJdYY8i2ofOE
u47sQDFKnfcjo9gqw5QP1TL3ead6G4LSBDSaWreSh+aQP9NYYpVs8v1GSUqNLqBXFSerq4fP/Krk
e4Sx0GvT7lL5eT9pledKyJXxljztybUkrhtZvf8ub9AXBy0lxiWEWNxXmFb4fc+ZRVLiv3Wdj1xA
j7/NqMhQruR06auKMqZ9wSUPMyQmFonOXYeo2S/yyszqc1AT3nRj6lKI0jOTPIg8yphWaqxib7e7
gEqHmM14pg1u4oOKLb1tTjhmCrySeLqJ2pR3ilqhe/03sPdCeAK3cG0vzWFdO2Ela0dczUPH3wZy
RX0XwFjNXb/f1K46M2S1EqQx4C4I9Qy4CK0hOq+IljjLIScQ916eQEEYe4kTUGpO8rzuLxQ1SRYk
8HcohvEJ3ixdOzvIgfr4ZkSlGvnGxW0TeBq63bXgnsEUqR7a7MN2HBV6rksnU+0ErP2GOeHtSq1G
Wp+nMSnSKl/dzMpPmZstI2UtZ6GCjhvhtNDS1MNcjxtprGCa3A5ecnpuA6ab5kbVwrYNcMV1EFlU
HrYobMyxlR5VVyFtr1U6SEoBQsSYvGSa9/74IDZvxCzUtQOUVmzv6vnEvYWUuY6jVkBGeTv8THIV
3TSY9ZArsgY+IyNZhf6MYjTP7WFFgQS/mRd618mpfxZiS4DaJFQRsOpYCf6rJzKgBCOkZZSOe4j8
QwrAxGnctyefhGO10gTiC8AS7K/1gDnfiCdF/aSumqFB40asOthXfWJtg62QhcW/c1h8UlkJsSvD
5z3L64HuGMrFx435y++L0cUqQrMF+peMLrWxa2YbqNTopsV+9s0WJLxxl99EBceEQdlVtH/Uf7c+
xijZhjhHUun2JICEgS5BvG3Id8B2y1VCB8F8lM+hegi3TP7oycN/3oVyIoyFJy1avikIhfXEK5nQ
PBfTTnKAIPCNVby5rmLaOtiDFZpqJtjaj8odtvEC3z1jnHIiqwN4CU27DtEEmN1rDbSpf1D0o0Lv
z6K7PrLZPH7ZzXrb8gF03Qv0oN0tVz9w60uvdSj4qXOoI7PeHVjZ8aXHhLEF8Ub/jKRU7DovG6UJ
oyXp2yYUcifhKSJn6l3OKW/9vQtzjdl70DCtaaS0jGh1E9wJqiH6YRmsG4DBo2Dx8o6liAtmS9aN
MUOyBN6O+FxxxJxKBkU3XiXRvtldFBX1hC/TQNX0LDegXGYEFZWPEwNTPSdLS/ncDpb1d+A60O9C
TZ1oGBNoIwiDVUcj8rfaLu4QOwSjUEQtvzFzDcWm40DUoMX4JlojsbLDzyp/X700okaEEPo6ywPy
UZpEgOg1pev7Q7tjBbeaCuSVGSksZDar7L3en7euWcV0TGFCVJYL8yl6Fz3+0zt5gQoJQneD0pyj
/q+79I+rmxb+RoYJzWqL8Z63Ydd21ULUb6PflVigStqpP1veDapVgO51I89N+sbtZlD8O2Aqm+wD
fM98LVLNc0+etrADc1zXX+y87zEoWUE88OgLiJoU9WmNxSK3QqefjOzpCQiyuMcKZM6xAbM/X/r3
m2pkrY52hZ2NWjeMF8Y1iOyopCbX0bR0XbulH0hB8z1FzlSlo6MILooCp/15ePTRXi2Ulf6oqr/Q
NYcO31ORyEpNNq0jvKcn7sGKJZ6FH/4hshsxscivHw3DCyZlgIeAR9xK1UmCpoWWRs58JOKzwIbX
AZRE9XGoJLGiZ5hagIi9i0bBTj3PdANVW9Fxb2seq0ZkDGioO3JK/HQ2waTiiUuHSYFTT2f8CyMz
XuTqL4G1Iv6aQWrGWiGHk5T9uvifA8KHVx5SxCD2WQtPLlt1wUZwYmIAzlYAM/E2jziBnfpPU0lL
mxukfK9CbjIaMOtpmuF+fDh9iqKNWPQ+jwe6ouCR2Mo+goJ2jtREXNncr0Qi41O+EyryGyMnZobx
FgssBy0LmyZvJEOv6dPsZbZnyPWALDjAbYt70Tp3WKwyFs4JZrtk3a6NusOIo++gbAT5Y7v9zLBE
wl7pIRbKYuBBwEnfKmeQrtecnqlZ9YvmvDa/VX2ItDPder6FnkII/ERAM/J+KL1JFIfTOV50saaM
YRj70hsRpMYB55q9/n5eYuJ5zcAqsTNmELioahjFEZ1Jb7WrjdN0DvtDRBCYiILPOs7rXGNBPJqE
1QsZ+WmO2z7tZetfGQuEne78g4mbfynugV6iR/67TquQwAox+o3lLH7KijOIcotwWZbe/LrceZIC
QXM9Pqol9Vla9W/tHepEmDqQNh6MyQFpTf4V6aGP8dw0p6FWSv1VXjSmyeGP/UEhvOZe295SzJX5
LMMVeSTgCD8Mpz5fWobJakWt7EyMUZSaI7OY7IlvhSB6jewfxWa6bUCYkMQvFrewHJz8HaiS4GeQ
hk9sn0mOL3vHaOVueiqojhqTVASbdjDIfsBvnFMg7TuWXD67ovxUDYHMQn5UALKpnb+IcO67doNw
/NidH8BKKHOXn0NE7jvNLymFz1sG3D55gsTy113+45e7abbWq3FJ8dFnXuPhmWtCwfFxcJIbd0+C
U/PLOIKnF6yQY7cKqdneBBDNf2LXyutUFCl+Ec0xnRHxtWLGGuMkvedZhyar3coUpUDN0GJ0
`protect end_protected
|
mit
|
18545/FPGA
|
project_1.srcs/sources_1/ip/ila_0/ila_0_funcsim.vhdl
|
2
|
3297046
| null |
mit
|
Gizeta/bjuedc
|
uart-fpga/uart.vhd
|
1
|
5248
|
--------------------------------------------
-- 串口收发实验
-- Filename: uart
-- PIN_89--->P1.2
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uart is -- 定义uart实体
port(
clkin, resetin : in std_logic; -- clkin 为50M
rxd : in std_logic; -- 串行输入数据
txd : out std_logic; -- 串行输出数据
wei : out std_logic_vector(3 downto 0); -- S0 ~ S3
duan : out std_logic_vector(7 downto 0)
);
end uart;
architecture arch of uart is
component gen_div is -- 分频元件调用声明
-- 326分频, 326 * 16 * (9600) = 50M
-- 波特率为9600
generic(div_param : integer := 163);
port(
clk_in : in std_logic;
clk_out : out std_logic;
reset : in std_logic
);
end component;
component uart_send is -- 串口发送元件调用声明
port(
bclk_t, reset_t, xmit_cmd_p : in std_logic;
tbuf : in std_logic_vector(7 downto 0);
txd : out std_logic;
t_done : out std_logic
);
end component;
component uart_recv is -- 串口接受元件调用声明
port(
bclk_r, reset_r, rxd : in std_logic;
r_ready : out std_logic;
rbuf : out std_logic_vector(7 downto 0)
);
end component;
component narr_sig is -- 信号窄化元件声明调用
port(
sig_in : in std_logic;
clk : in std_logic;
reset : in std_logic;
narr_prd : in std_logic_vector(7 downto 0);
narr_sig_out : out std_logic
);
end component;
signal clk_b : std_logic; -- 波特率时钟
signal clk1 : std_logic; -- 数码管时钟
signal xmit_p : std_logic; -- 新一轮发送启动信号
signal xbuf : std_logic_vector(7 downto 0); -- 待发送数据缓冲区
signal txd_done_iner : std_logic; -- 帧数据发送完标志
signal rev_buf : std_logic_vector(7 downto 0); -- 接收数据缓冲区
signal rev_ready : std_logic; -- 帧数据接受完标志
begin
---------------------------------
-- 分频模块例化
---------------------------------
uart_baud: gen_div
generic map(163)
port map(
clk_in => clkin,
reset => not resetin,
clk_out => clk_b
);
---------------------------------
-- 分频模块例化
---------------------------------
seg_clk: gen_div
generic map(10) -- 20分频
port map(
clk_in => clkin,
reset => not resetin,
clk_out => clk1
);
---------------------------------
-- 串口发送模块例化
---------------------------------
uart_transfer: uart_send
port map(
bclk_t => clk_b,
reset_t => not resetin,
xmit_cmd_p => xmit_p,
tbuf => xbuf,
txd => txd,
t_done => txd_done_iner
);
---------------------------------
-- 串口接收元件例化
---------------------------------
uart_receive: uart_recv
port map(
bclk_r => clk_b,
reset_r => not resetin,
rxd => rxd,
r_ready => rev_ready,
rbuf => rev_buf
);
---------------------------------
-- 信号窄化模块例化
---------------------------------
narr_rev_ready: narr_sig -- 窄化rev_ready信号后给xmit_p
port map(
sig_in => rev_ready, -- 输入需窄化信号
clk => clk_b,
reset => not resetin,
narr_prd => X"03", -- narr信号高电平持续的周期数(以clk为周期)
narr_sig_out => xmit_p -- 输出窄化后信号
);
process(rev_ready, resetin, rev_buf, clk_b)
begin
if rising_edge(rev_ready) then -- 接收完毕
xbuf <= rev_buf; -- 装载数据
end if;
end process;
display: process(clk1, rev_ready, rev_buf)
begin
if rising_edge(rev_ready) then -- 接收完毕
case rev_buf(7 downto 4) is -- 前四位为位选信息
when "0001" => wei <= "1000"; -- 1
when "0010" => wei <= "0100"; -- 2
when "0011" => wei <= "0010"; -- 3
when "0100" => wei <= "0001"; -- 4
when "1001" => wei <= "1000"; -- 1.
when "1010" => wei <= "0100"; -- 2.
when "1011" => wei <= "0010"; -- 3.
when "1100" => wei <= "0001"; -- 4.
when others => wei <= "0000";
end case;
case rev_buf(3 downto 0) is -- 后四位为位选信息
when "0000" => duan <= x"3f"; -- 0
when "0001" => duan <= x"06"; -- 1
when "0010" => duan <= x"5b"; -- 2
when "0011" => duan <= x"4f"; -- 3
when "0100" => duan <= x"66"; -- 4
when "0101" => duan <= x"6d"; -- 5
when "0110" => duan <= x"7d"; -- 6
when "0111" => duan <= x"07"; -- 7
when "1000" => duan <= x"7f"; -- 8
when "1001" => duan <= x"6f"; -- 9
when others => duan <= x"00";
end case;
if rev_buf(7) = '1' then
duan(7) <= '1';
end if;
end if;
end process;
end arch;
|
mit
|
18545/FPGA
|
src/ov7670_capture.vhd
|
1
|
2501
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Captures the pixels coming from the OV7670 camera and
-- Stores them in block RAM
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_capture is
Port ( pclk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (7 downto 0);
addr : out STD_LOGIC_VECTOR (18 downto 0);
dout : out STD_LOGIC_VECTOR (11 downto 0);
we : out STD_LOGIC);
end ov7670_capture;
architecture Behavioral of ov7670_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal address_next : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal wr_hold : std_logic_vector(1 downto 0) := (others => '0');
begin
addr <= address;
process(pclk)
begin
if rising_edge(pclk) then
-- This is a bit tricky href starts a pixel transfer that takes 3 cycles
-- Input | state after clock tick
-- href | wr_hold d_latch d we address address_next
-- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx x xxxx xxxx
-- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxxxxxx x xxxx addr
-- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxRRRRRGGG x addr addr
-- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRRGGGGGGBBBBB 1 addr addr+1
if vsync = '1' then
address <= (others => '0');
address_next <= (others => '0');
wr_hold <= (others => '0');
else
dout <= d_latch(10 downto 7) & d_latch(15 downto 12) & d_latch(4 downto 1);
address <= address_next;
we <= wr_hold(1);
wr_hold <= wr_hold(0) & (href and not wr_hold(0));
d_latch <= d_latch( 7 downto 0) & d;
if wr_hold(1) = '1' then
address_next <= std_logic_vector(unsigned(address_next)+1);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
peteg944/music-fpga
|
Enlightened Main Project/fpga_tb.vhd
|
4
|
3174
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:21 09/05/2013
-- Design Name:
-- Module Name: C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga/fpga_tb.vhd
-- Project Name: fpga
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fpga_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fpga_tb IS
END fpga_tb;
ARCHITECTURE behavior OF fpga_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fpga_top
PORT(
clk : IN std_logic;
led : OUT std_logic;
bluetooth_rxd : OUT std_logic;
bluetooth_txd : IN std_logic;
display_rgb1 : OUT std_logic_vector(2 downto 0);
display_rgb2 : OUT std_logic_vector(2 downto 0);
display_addr : OUT std_logic_vector(3 downto 0);
display_clk : OUT std_logic;
display_oe : OUT std_logic;
display_lat : OUT std_logic;
usb_rxd : OUT std_logic;
usb_txd : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal bluetooth_txd : std_logic := '1';
signal usb_txd : std_logic := '1';
--Outputs
signal led : std_logic;
signal bluetooth_rxd : std_logic;
signal display_rgb1 : std_logic_vector(2 downto 0);
signal display_rgb2 : std_logic_vector(2 downto 0);
signal display_addr : std_logic_vector(3 downto 0);
signal display_clk : std_logic;
signal display_oe : std_logic;
signal display_lat : std_logic;
signal usb_rxd : std_logic;
-- Clock period definitions
constant clk_period : time := 31250 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fpga_top PORT MAP (
clk => clk,
led => led,
bluetooth_rxd => bluetooth_rxd,
bluetooth_txd => bluetooth_txd,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat,
usb_rxd => usb_rxd,
usb_txd => usb_txd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
|
mit
|
peteg944/music-fpga
|
LED_Matrix_FPGA_Nexys 3/fpga_tb.vhd
|
4
|
3174
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:21 09/05/2013
-- Design Name:
-- Module Name: C:/Users/Shahriar Shahramian/Desktop/32x32LEDMatrix/fpga/fpga_tb.vhd
-- Project Name: fpga
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fpga_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fpga_tb IS
END fpga_tb;
ARCHITECTURE behavior OF fpga_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fpga_top
PORT(
clk : IN std_logic;
led : OUT std_logic;
bluetooth_rxd : OUT std_logic;
bluetooth_txd : IN std_logic;
display_rgb1 : OUT std_logic_vector(2 downto 0);
display_rgb2 : OUT std_logic_vector(2 downto 0);
display_addr : OUT std_logic_vector(3 downto 0);
display_clk : OUT std_logic;
display_oe : OUT std_logic;
display_lat : OUT std_logic;
usb_rxd : OUT std_logic;
usb_txd : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal bluetooth_txd : std_logic := '1';
signal usb_txd : std_logic := '1';
--Outputs
signal led : std_logic;
signal bluetooth_rxd : std_logic;
signal display_rgb1 : std_logic_vector(2 downto 0);
signal display_rgb2 : std_logic_vector(2 downto 0);
signal display_addr : std_logic_vector(3 downto 0);
signal display_clk : std_logic;
signal display_oe : std_logic;
signal display_lat : std_logic;
signal usb_rxd : std_logic;
-- Clock period definitions
constant clk_period : time := 31250 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fpga_top PORT MAP (
clk => clk,
led => led,
bluetooth_rxd => bluetooth_rxd,
bluetooth_txd => bluetooth_txd,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat,
usb_rxd => usb_rxd,
usb_txd => usb_txd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
|
mit
|
Saucyz/explode
|
Hardware/Mod2/Mod2.vhd
|
1
|
5472
|
-- Inputs: SW7°0 are parallel port inputs to the Nios II system.
-- CLOCK_50 is the system clock.
-- KEY0 is the active-low system reset.
-- Outputs: LEDG7°0 are parallel port outputs from the Nios II system.
-- SDRAM ports correspond to the signals in Figure 2; their names are those
-- used in the DE2 User Manual.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY Mod2 IS
PORT (
SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
UART_RXD : in std_logic; -- RXD
UART_TXD : out std_logic; -- TXD
DRAM_CLK, DRAM_CKE : OUT STD_LOGIC;
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
DRAM_BA_0, DRAM_BA_1 : BUFFER STD_LOGIC;
DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
DRAM_UDQM, DRAM_LDQM : BUFFER STD_LOGIC;
LCD_DATA : inout STD_LOGIC_VECTOR(7 downto 0);
LCD_ON, LCD_BLON, LCD_EN, LCD_RS, LCD_RW : out STD_LOGIC;
SD_CMD, SD_DAT, SD_DAT3 : INOUT STD_LOGIC;
SD_CLK : OUT STD_LOGIC;
AUD_ADCDAT : in std_logic; -- ADCDAT
AUD_ADCLRCK : in std_logic; -- ADCLRCK
AUD_BCLK : in std_logic; -- BCLK
AUD_DACDAT : out std_logic; -- DACDAT
AUD_DACLRCK : in std_logic; -- DACLRCK
I2C_SDAT : inout std_logic;
I2C_SCLK : out std_logic;
CLOCK_27 : IN STD_LOGIC;
AUD_XCK : OUT STD_LOGIC;
TD_RESET : OUT STD_LOGIC
);
END Mod2;
ARCHITECTURE Structure OF Mod2 IS
COMPONENT nios_system
PORT (
clk_clk : IN STD_LOGIC;
reset_reset_n : IN STD_LOGIC;
sdram_clk_clk : OUT STD_LOGIC;
leds_export : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switches_export : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
serial_RXD : in std_logic := 'X'; -- RXD
serial_TXD : out std_logic; -- TXD
sdram_wire_addr : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sdram_wire_ba : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
sdram_wire_cas_n : OUT STD_LOGIC;
sdram_wire_cke : OUT STD_LOGIC;
sdram_wire_cs_n : OUT STD_LOGIC;
sdram_wire_dq : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sdram_wire_dqm : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
sdram_wire_ras_n : OUT STD_LOGIC;
sdram_wire_we_n : OUT STD_LOGIC;
lcd_data_DATA : INOUT STD_LOGIC_VECTOR(7 downto 0);
lcd_data_ON : OUT STD_LOGIC;
lcd_data_BLON : OUT STD_LOGIC;
lcd_data_EN : OUT STD_LOGIC;
lcd_data_RS : OUT STD_LOGIC;
lcd_data_RW : OUT STD_LOGIC;
keys_export : IN STD_LOGIC_VECTOR(3 downto 0);
sd_wire_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd
sd_wire_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat
sd_wire_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3
sd_wire_o_SD_clock : out std_logic; -- o_SD_clock
audio_ADCDAT : in std_logic := 'X'; -- ADCDAT
audio_ADCLRCK : in std_logic := 'X'; -- ADCLRCK
audio_BCLK : in std_logic := 'X'; -- BCLK
audio_DACDAT : out std_logic; -- DACDAT
audio_DACLRCK : in std_logic := 'X'; -- DACLRCK
audio_config_SDAT : inout std_logic := 'X'; -- SDAT
audio_config_SCLK : out std_logic; -- SCLK
audio_clk_clk : OUT STD_LOGIC;
clk_in_secondary_clk : IN STD_LOGIC
);
END COMPONENT;
SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
DRAM_BA_0 <= BA(0);
DRAM_BA_1 <= BA(1);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
TD_RESET <= '1';
-- Instantiate the Nios II system entity generated by the Qsys tool.
NiosII: nios_system
PORT MAP (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_clk_clk => DRAM_CLK,
leds_export => LEDG,
switches_export => SW,
serial_RXD => UART_RXD,
serial_TXD => UART_TXD,
sdram_wire_addr => DRAM_ADDR,
sdram_wire_ba => BA,
sdram_wire_cas_n => DRAM_CAS_N,
sdram_wire_cke => DRAM_CKE,
sdram_wire_cs_n => DRAM_CS_N,
sdram_wire_dq => DRAM_DQ,
sdram_wire_dqm => DQM,
sdram_wire_ras_n => DRAM_RAS_N,
sdram_wire_we_n => DRAM_WE_N,
lcd_data_DATA => LCD_DATA,
lcd_data_ON => LCD_ON,
lcd_data_BLON => LCD_BLON,
lcd_data_EN => LCD_EN,
lcd_data_RS => LCD_RS,
lcd_data_RW => LCD_RW,
keys_export => KEY,
sd_wire_b_SD_cmd => SD_CMD, -- sd_wire.b_SD_cmd
sd_wire_b_SD_dat => SD_DAT, -- .b_SD_dat
sd_wire_b_SD_dat3 => SD_DAT3, -- .b_SD_dat3
sd_wire_o_SD_clock => SD_CLK, -- .o_SD_clock
audio_ADCDAT => AUD_ADCDAT,
audio_ADCLRCK => AUD_ADCLRCK,
audio_BCLK => AUD_BCLK,
audio_DACDAT => AUD_DACDAT,
audio_DACLRCK => AUD_DACLRCK,
audio_config_SDAT => I2C_SDAT, -- audio_config.SDAT
audio_config_SCLK => I2C_SCLK, -- .SCLK
clk_in_secondary_clk => CLOCK_27,
audio_clk_clk => AUD_XCK
);
--DRAM_CLK <= CLOCK_50;
END Structure;
|
mit
|
amerc/TCP3
|
ipcore_dir/RxTstFIFO2K/simulation/RxTstFIFO2K_pkg.vhd
|
2
|
11384
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE RxTstFIFO2K_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT RxTstFIFO2K_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RxTstFIFO2K_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RxTstFIFO2K_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT RxTstFIFO2K_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RxTstFIFO2K_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RxTstFIFO2K_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END RxTstFIFO2K_pkg;
PACKAGE BODY RxTstFIFO2K_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END RxTstFIFO2K_pkg;
|
mit
|
peteg944/music-fpga
|
Experimental/Zedboard UART/ipcore_dir/pll.vhd
|
3
|
8140
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______102.845_____87.180
-- CLK_OUT2___100.000______0.000______50.0______115.831_____87.180
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 12,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
mit
|
huljar/klein-vhdl
|
src/util.vhd
|
1
|
618
|
library ieee;
use ieee.std_logic_1164.all;
package util is
type key_enum is (K_64, K_80, K_96);
type key_lookup is array(key_enum) of natural;
constant key_bits: key_lookup := (
K_64 => 64,
K_80 => 80,
K_96 => 96
);
type rc_lookup is array(key_enum) of std_logic_vector(4 downto 0);
constant final_rc: rc_lookup := (
K_64 => "01101",
K_80 => "10001",
K_96 => "10101"
);
type round_lookup is array(key_enum) of natural;
constant rounds: round_lookup := (
K_64 => 12,
K_80 => 16,
K_96 => 20
);
end package;
|
mit
|
amerc/TCP3
|
ipcore_dir/genclks/example_design/genclks_exdes.vhd
|
2
|
7067
|
-- file: genclks_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity genclks_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end genclks_exdes;
architecture xilinx of genclks_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 3;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component genclks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : genclks
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2),
CLK_OUT3 => clk_int(3),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
clk(3) <= clk_int(3);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
|
mit
|
huljar/klein-vhdl
|
src/klein_top.vhd
|
1
|
2572
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity klein_top is
generic(k: key_enum);
port(plaintext: in std_logic_vector(63 downto 0);
key: in std_logic_vector(key_bits(k)-1 downto 0);
clk: in std_logic;
reset: in std_logic;
ciphertext: out std_logic_vector(63 downto 0)
);
end klein_top;
architecture behavioral of klein_top is
signal data_state,
data_key_added,
data_nibbles_subbed,
data_nibbles_mixed: std_logic_vector(63 downto 0);
signal key_state,
key_updated: std_logic_vector(key_bits(k)-1 downto 0);
signal round_counter: std_logic_vector(4 downto 0);
component sub_nibbles
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component rotate_mix_nibbles
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component key_schedule
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
rc: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end component;
begin
SN: sub_nibbles port map(
data_in => data_key_added,
data_out => data_nibbles_subbed
);
RMN: rotate_mix_nibbles port map(
data_in => data_nibbles_subbed,
data_out => data_nibbles_mixed
);
KS: key_schedule generic map(
k => k
) port map(
data_in => key_state,
rc => round_counter,
data_out => key_updated
);
data_key_added <= data_state xor key_state(key_bits(k)-1 downto key_bits(k)-64);
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
data_state <= plaintext;
key_state <= key;
round_counter <= "00001";
ciphertext <= (others => '0');
else
data_state <= data_nibbles_mixed;
key_state <= key_updated;
round_counter <= std_logic_vector(unsigned(round_counter) + 1);
case round_counter is
when final_rc(k) => ciphertext <= data_key_added;
when others => ciphertext <= (others => '0');
end case;
end if;
end if;
end process;
end architecture;
|
mit
|
peteg944/music-fpga
|
Enlightened Main Project/display_control.vhd
|
4
|
7028
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
entity display_control is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
display_ena : in STD_LOGIC;
ram_data : in STD_LOGIC_VECTOR (47 downto 0);
ram_address : out STD_LOGIC_VECTOR ( 8 downto 0);
display_rgb1 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_addr : out STD_LOGIC_VECTOR ( 3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC);
end display_control;
architecture rtl of display_control is
constant gamma : real := 2.8;
constant wait_max : integer := 3;
constant wait_res : integer := integer(ceil(log2(real(2*wait_max+1))));
signal pwm_ctr : std_logic_vector(8 downto 0);
signal pwm_inc : std_logic;
signal row_inc : std_logic;
signal col_inc : std_logic;
signal red1 : std_logic_vector(7 downto 0);
signal red2 : std_logic_vector(7 downto 0);
signal green1 : std_logic_vector(7 downto 0);
signal green2 : std_logic_vector(7 downto 0);
signal blue1 : std_logic_vector(7 downto 0);
signal blue2 : std_logic_vector(7 downto 0);
signal wait_ctr : std_logic_vector(wait_res-1 downto 0);
signal wait_ena : std_logic;
--signal address_inc : std_logic;
signal address_ctr : std_logic_vector(8 downto 0);
signal next_oe : std_logic;
signal disp_oe : std_logic;
signal disp_lat : std_logic;
signal disp_clk : std_logic;
type fsm_type is (st0_idle, st1_clock_high, st2_clk_low, st3_inc_ctr, st4_latch, st5_oe_high, st6_oe_low);
signal state, next_state : fsm_type;
begin
red1_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(7 downto 0),
val_out => red1);
green1_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(15 downto 8),
val_out => green1);
blue1_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(23 downto 16),
val_out => blue1);
red2_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(31 downto 24),
val_out => red2);
green2_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(39 downto 32),
val_out => green2);
blue2_i : entity work.gamma_table
generic map (
color_res => 8,
gamma => gamma)
port map (
CLK => clk,
val_in => ram_data(47 downto 40),
val_out => blue2);
pwm_proc : process (rst, clk)
begin
if rst = '1' then
pwm_ctr <= (others => '0');
elsif rising_edge(clk) then
if pwm_inc = '1' then
if pwm_ctr = 256 then
pwm_ctr <= (others => '0');
else
pwm_ctr <= pwm_ctr + 1;
end if;
end if;
end if;
end process pwm_proc;
wait_proc : process (clk)
begin
if rising_edge(clk) then
if wait_ena = '0' then
wait_ctr <= (others => '0');
else
wait_ctr <= wait_ctr + 1;
end if;
end if;
end process wait_proc;
addr_proc : process (rst, clk)
begin
if rst = '1' then
address_ctr <= (others => '0');
elsif rising_edge(clk) then
if col_inc = '1' then
if (pwm_inc = '1') and (row_inc = '0') then
address_ctr <= address_ctr(8 downto 5) & "00000";
else
address_ctr <= address_ctr + 1;
end if;
end if;
end if;
end process addr_proc;
-- Display outputs
display_rgb1(0) <= '1' when (pwm_ctr < ('0' & red1)) else '0';
display_rgb1(1) <= '1' when (pwm_ctr < ('0' & green1)) else '0';
display_rgb1(2) <= '1' when (pwm_ctr < ('0' & blue1)) else '0';
display_rgb2(0) <= '1' when (pwm_ctr < ('0' & red2)) else '0';
display_rgb2(1) <= '1' when (pwm_ctr < ('0' & green2)) else '0';
display_rgb2(2) <= '1' when (pwm_ctr < ('0' & blue2)) else '0';
ram_address <= address_ctr;
-- Display latch
disp_proc : process (clk)
begin
if rising_edge(clk) then
display_oe <= disp_oe;
display_lat <= disp_lat;
display_clk <= disp_clk;
if (disp_oe = '1') and (disp_lat = '1') then
display_addr <= address_ctr(8 downto 5);
end if;
end if;
end process disp_proc;
fsm_proc : process (rst, clk)
begin
if rst = '1' then
state <= st0_idle;
disp_oe <= '0';
elsif rising_edge(clk) then
state <= next_state;
disp_oe <= next_oe;
end if;
end process fsm_proc;
next_proc : process (state, display_ena, wait_ctr, address_ctr, pwm_ctr, disp_oe)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
next_oe <= disp_oe;
row_inc <= '0';
col_inc <= '0';
pwm_inc <= '0';
wait_ena <= '0';
disp_clk <= '1';
disp_lat <= '0';
--insert statements to decode next_state
--below is a simple example
case (state) is
when st0_idle =>
if display_ena = '1' then
next_state <= st1_clock_high;
end if;
when st1_clock_high =>
if wait_ctr = wait_max then
next_state <= st2_clk_low;
else
wait_ena <= '1';
end if;
when st2_clk_low =>
disp_clk <= '0';
if wait_ctr = wait_max then
if address_ctr(4 downto 0) = 31 then
if pwm_ctr = 0 then
next_state <= st5_oe_high;
else
next_state <= st4_latch;
end if;
else
next_state <= st3_inc_ctr;
end if;
else
wait_ena <= '1';
end if;
when st3_inc_ctr =>
wait_ena <= '1';
col_inc <= '1';
if address_ctr(4 downto 0) = 31 then
pwm_inc <= '1';
end if;
if pwm_ctr = 256 then
row_inc <= '1';
end if;
if disp_oe = '1' then
next_state <= st6_oe_low;
else
next_state <= st1_clock_high;
end if;
when st4_latch =>
disp_lat <= '1';
if wait_ctr = 2*wait_max then
next_state <= st3_inc_ctr;
else
wait_ena <= '1';
end if;
when st5_oe_high =>
next_oe <= '1';
if wait_ctr = 2*wait_max then
next_state <= st4_latch;
else
wait_ena <= '1';
end if;
when st6_oe_low =>
if wait_ctr = 2*wait_max then
next_oe <= '0';
next_state <= st1_clock_high;
else
wait_ena <= '1';
end if;
end case;
end process next_proc;
end rtl;
|
mit
|
Saucyz/explode
|
Hardware/Mod2/nios_system/synthesis/submodules/Altera_UP_SD_CRC16_Generator.vhd
|
2
|
1938
|
----------------------------------------------------------------------------------------
-- This generates the necessary 16-CRC for Command and Response
-- Implementation: serial input/parallel output
-- When input stream ends, the crcout output is the CRC checksum for them
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC16_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC16_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(15 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_sync_reset = '1') then
shift_register <= (OTHERS => '0');
elsif (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(15);
shift_register(4 downto 1) <= shift_register(3 downto 0);
shift_register(5) <= shift_register(4) XOR i_datain XOR shift_register(15);
shift_register(11 downto 6) <= shift_register(10 downto 5);
shift_register(12) <= shift_register(11) XOR i_datain XOR shift_register(15);
shift_register(15 downto 13) <= shift_register(14 downto 12);
else -- shift CRC out (no more calculation now)
shift_register(15 downto 1) <= shift_register(14 downto 0);
shift_register(0) <= '0';
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(15);
o_crcout <= shift_register;
end rtl;
|
mit
|
peteg944/music-fpga
|
Experimental/Zedboard UART/uart_top.vhd
|
4
|
7380
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:00 07/31/2011
-- Design Name:
-- Module Name: uart_top - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_top is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
CLK200P : in std_logic;
CLK200N : in std_logic;
RXD : in std_logic;
CTS : in std_logic;
LED : out std_logic_vector(7 downto 0);
TXD : out std_logic;
RTS : out std_logic);
end uart_top;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_top is
----------------------------------------------------------------------------------
-- Component Declaration
----------------------------------------------------------------------------------
-- Clock manager
component mmcm200
port (
-- Clock in ports
CLK200_P : in std_logic;
CLK200_N : in std_logic;
-- Clock out ports
CLK100 : out std_logic;
CLKOSX : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic);
end component;
-- Integrated controller
component icon_cs
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
-- Virtual input/output
component vio_cs
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
SYNC_IN : in std_logic_vector(54 downto 0);
ASYNC_OUT : out std_logic_vector( 1 downto 0);
SYNC_OUT : out std_logic_vector(12 downto 0));
end component;
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal VIO_CONTROL : std_logic_vector(35 downto 0);
signal VIO_ASYNC_OUT : std_logic_vector( 1 downto 0);
signal VIO_SYNC_OUT : std_logic_vector(12 downto 0);
signal VIO_SYNC_IN : std_logic_vector(54 downto 0);
signal CLK : std_logic;
signal CLKOSX : std_logic;
signal MMCM_LOCKED : std_logic;
signal MMCM_RST : std_logic;
signal UART_RST : std_logic;
signal WREN : std_logic;
signal RDEN : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
signal RDDATA : std_logic_vector(7 downto 0);
signal WRRDY : std_logic;
signal RDRDY : std_logic;
signal TX_WRCOUNT : std_logic_vector(10 downto 0);
signal TX_RDCOUNT : std_logic_vector(10 downto 0);
signal RX_WRCOUNT : std_logic_vector(10 downto 0);
signal RX_RDCOUNT : std_logic_vector(10 downto 0);
signal RTS_INT : std_logic;
signal CTS_INT : std_logic;
signal RDEN_SWITCH : std_logic;
signal RDEN_PULSE : std_logic;
signal WREN_SWITCH : std_logic;
signal WREN_PULSE : std_logic;
signal WRSEL : std_logic;
signal WRDATA_VIO : std_logic_vector(7 downto 0);
----------------------------------------------------------------------------------
-- Attributes
----------------------------------------------------------------------------------
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of icon_cs : component is true;
attribute syn_black_box of vio_cs : component is true;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- ChipScope integrated controller
icon_inst : icon_cs
port map (
CONTROL0 => VIO_CONTROL);
-- ChipScope virtual input/output
vio_inst : vio_cs
port map (
CONTROL => VIO_CONTROL,
CLK => CLK,
SYNC_IN => VIO_SYNC_IN,
ASYNC_OUT => VIO_ASYNC_OUT,
SYNC_OUT => VIO_SYNC_OUT);
-- Clock manager
mmcm_i : mmcm200
port map (
-- Clock in ports
CLK200_P => CLK200P,
CLK200_N => CLK200N,
-- Clock out ports
CLK100 => CLK,
CLKOSX => CLKOSX,
-- Status and control signals
RESET => MMCM_RST,
LOCKED => MMCM_LOCKED);
-- Universal asynchonous transmitter
tx_inst : entity work.uart_tx
generic map (
use_handshake => use_handshake,
log2_oversampling => log2_oversampling)
port map (
RST => UART_RST,
WRCLK => CLK,
CLKOSX => CLKOSX,
WREN => WREN,
CTS => CTS_INT,
WRCOUNT => TX_WRCOUNT,
RDCOUNT => TX_RDCOUNT,
WRDATA => WRDATA,
WRRDY => WRRDY,
TXD => TXD);
-- Universal asynchonous receiver
rx_inst : entity work.uart_rx
generic map (
use_handshake => use_handshake,
log2_oversampling => log2_oversampling)
port map (
RST => UART_RST,
RDCLK => CLK,
CLKOSX => CLKOSX,
RXD => RXD,
RDEN => RDEN,
RTS => RTS_INT,
WRCOUNT => RX_WRCOUNT,
RDCOUNT => RX_RDCOUNT,
RDDATA => RDDATA,
RDRDY => RDRDY);
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Virtual inputs
VIO_SYNC_IN <= (TX_RDCOUNT & TX_WRCOUNT & RX_RDCOUNT & RX_WRCOUNT & WRRDY & RDRDY & RDDATA & MMCM_LOCKED);
-- Virtual outputs
UART_RST <= VIO_ASYNC_OUT(1);
MMCM_RST <= VIO_ASYNC_OUT(0);
RDEN_SWITCH <= VIO_SYNC_OUT(12);
RDEN_PULSE <= VIO_SYNC_OUT(11);
WREN_SWITCH <= VIO_SYNC_OUT(10);
WREN_PULSE <= VIO_SYNC_OUT(9);
WRSEL <= VIO_SYNC_OUT(8);
WRDATA_VIO <= VIO_SYNC_OUT(7 downto 0);
-- Request/Clear To Send
RTS <= RTS_INT;
CTS_INT <= CTS;
-- Read/Write enable & selector for tx data
wr_proc : process (CLK)
begin
if rising_edge(CLK) then
RDEN <= RDEN_SWITCH or RDEN_PULSE;
WREN <= WREN_SWITCH or WREN_PULSE;
if WRSEL = '1' then
WRDATA <= WRDATA_VIO;
else
WRDATA <= RDDATA;
end if;
end if;
end process wr_proc;
-- LED outputs
led_proc : process (CLK)
begin
if rising_edge(CLK) then
LED(0) <= MMCM_RST;
LED(1) <= UART_RST;
LED(2) <= RTS_INT;
LED(3) <= CTS_INT;
LED(4) <= RDEN;
LED(5) <= WREN;
LED(6) <= '0';
LED(7) <= '1';
end if;
end process led_proc;
end rtl;
|
mit
|
amerc/TCP3
|
ipcore_dir/RxTstFIFO2K/simulation/RxTstFIFO2K_tb.vhd
|
2
|
6083
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_tb IS
END ENTITY;
ARCHITECTURE RxTstFIFO2K_arch OF RxTstFIFO2K_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from RxTstFIFO2K_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of RxTstFIFO2K_synth
RxTstFIFO2K_synth_inst:RxTstFIFO2K_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
peteg944/music-fpga
|
Experimental/RainbowMatrix and Partial Spectrum/i3c2.vhd
|
5
|
14041
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral;
|
mit
|
fortesit/MIPS-CPU-simulator
|
processor.vhd
|
1
|
3030
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity processor is
port (
clk : in std_logic;
rst : in std_logic;
run : in std_logic;
wen : in std_logic;
addr : in std_logic_vector(31 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
fin : out std_logic;
PCout : out std_logic_vector(31 downto 0);
regaddr : in std_logic_vector(4 downto 0);
regdout : out std_logic_vector(31 downto 0)
);
end processor;
architecture arch_processor of processor is
component memtable
port (
clk : in std_logic;
rst : in std_logic;
instaddr: in std_logic_vector(31 downto 0);
instout : out std_logic_vector(31 downto 0);
wen : in std_logic;
addr : in std_logic_vector(31 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
extwen : in std_logic;
extaddr : in std_logic_vector(31 downto 0);
extdin : in std_logic_vector(31 downto 0);
extdout : out std_logic_vector(31 downto 0)
);
end component;
component processor_core
port (
clk : in std_logic;
rst : in std_logic;
run : in std_logic;
instaddr: out std_logic_vector(31 downto 0);
inst : in std_logic_vector(31 downto 0);
memwen : out std_logic;
memaddr : out std_logic_vector(31 downto 0);
memdw : out std_logic_vector(31 downto 0);
memdr : in std_logic_vector(31 downto 0);
fin : out std_logic;
PCout : out std_logic_vector(31 downto 0);
regaddr : in std_logic_vector(4 downto 0);
regdout : out std_logic_vector(31 downto 0)
);
end component;
signal instaddr : std_logic_vector(31 downto 0);
signal inst : std_logic_vector(31 downto 0);
signal memwen : std_logic;
signal memaddr : std_logic_vector(31 downto 0);
signal memdw : std_logic_vector(31 downto 0);
signal memdr : std_logic_vector(31 downto 0);
begin
MAIN_MEM: memtable
port map (
clk => clk, --clock signal
rst => rst, --Asynchronous active-high reset signal
instaddr => instaddr, --instruction memory read address
instout => inst, --instruction memory data
wen => memwen, --Data memory write enable
addr => memaddr, --Data memory address
din => memdw, --Data memory write data
dout => memdr, --Data memory read data
extwen => wen, --External write Enable (debug use only)
extaddr => addr, --External memory address (debug use only)
extdin => din, --External memory write data (debug use only)
extdout => dout --External memory read data (debug use only)
);
PCORE: processor_core
port map (
clk => clk,
rst => rst,
run => run,
instaddr => instaddr,
inst => inst,
memwen => memwen,
memaddr => memaddr,
memdw => memdw,
memdr => memdr,
fin => fin,
PCout => PCout,
regaddr => regaddr,
regdout => regdout
);
end arch_processor;
|
mit
|
migueljiarr/RV32I
|
src/right_XLEN_barrel_shifter.vhd
|
1
|
1156
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_XLEN_barrel_shifter;
architecture structural of right_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= '0' & i(31 downto 1);
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= "00" & s1(31 downto 2);
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= "0000" & s2(31 downto 4);
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= "00000000" & s3(31 downto 8);
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= "0000000000000000" & s4(31 downto 16);
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
|
mit
|
0x19/jsonstruct.com
|
public/components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/misc/grgpio.in.vhd
|
6
|
208
|
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/maps/ssrctrl_net.vhd
|
2
|
12187
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ssrctrl_net
-- file: ssrctrl_net.vhd
-- Description: Wrapper for SSRAM controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ssrctrl_net is
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end entity ssrctrl_net;
architecture rtl of ssrctrl_net is
component ssrctrl_unisim
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
begin
xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
ssrctrlxil: ssrctrl_unisim
port map(
rst => rst,
clk => clk,
n_ahbsi_hsel => n_ahbsi_hsel,
n_ahbsi_haddr => n_ahbsi_haddr,
n_ahbsi_hwrite => n_ahbsi_hwrite,
n_ahbsi_htrans => n_ahbsi_htrans,
n_ahbsi_hsize => n_ahbsi_hsize,
n_ahbsi_hburst => n_ahbsi_hburst,
n_ahbsi_hwdata => n_ahbsi_hwdata,
n_ahbsi_hprot => n_ahbsi_hprot,
n_ahbsi_hready => n_ahbsi_hready,
n_ahbsi_hmaster => n_ahbsi_hmaster,
n_ahbsi_hmastlock => n_ahbsi_hmastlock,
n_ahbsi_hmbsel => n_ahbsi_hmbsel,
n_ahbsi_hcache => n_ahbsi_hcache,
n_ahbsi_hirq => n_ahbsi_hirq,
n_ahbso_hready => n_ahbso_hready,
n_ahbso_hresp => n_ahbso_hresp,
n_ahbso_hrdata => n_ahbso_hrdata,
n_ahbso_hsplit => n_ahbso_hsplit,
n_ahbso_hcache => n_ahbso_hcache,
n_ahbso_hirq => n_ahbso_hirq,
n_apbi_psel => n_apbi_psel,
n_apbi_penable => n_apbi_penable,
n_apbi_paddr => n_apbi_paddr,
n_apbi_pwrite => n_apbi_pwrite,
n_apbi_pwdata => n_apbi_pwdata,
n_apbi_pirq => n_apbi_pirq,
n_apbo_prdata => n_apbo_prdata,
n_apbo_pirq => n_apbo_pirq,
n_sri_data => n_sri_data,
n_sri_brdyn => n_sri_brdyn,
n_sri_bexcn => n_sri_bexcn,
n_sri_writen => n_sri_writen,
n_sri_wrn => n_sri_wrn,
n_sri_bwidth => n_sri_bwidth,
n_sri_sd => n_sri_sd,
n_sri_cb => n_sri_cb,
n_sri_scb => n_sri_scb,
n_sri_edac => n_sri_edac,
n_sro_address => n_sro_address,
n_sro_data => n_sro_data,
n_sro_sddata => n_sro_sddata,
n_sro_ramsn => n_sro_ramsn,
n_sro_ramoen => n_sro_ramoen,
n_sro_ramn => n_sro_ramn,
n_sro_romn => n_sro_romn,
n_sro_mben => n_sro_mben,
n_sro_iosn => n_sro_iosn,
n_sro_romsn => n_sro_romsn,
n_sro_oen => n_sro_oen,
n_sro_writen => n_sro_writen,
n_sro_wrn => n_sro_wrn,
n_sro_bdrive => n_sro_bdrive,
n_sro_vbdrive => n_sro_vbdrive,
n_sro_svbdrive => n_sro_svbdrive,
n_sro_read => n_sro_read,
n_sro_sa => n_sro_sa,
n_sro_cb => n_sro_cb,
n_sro_scb => n_sro_scb,
n_sro_vcdrive => n_sro_vcdrive,
n_sro_svcdrive => n_sro_svcdrive,
n_sro_ce => n_sro_ce);
end generate;
-- pragma translate_off
nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)))
generate
err : process
begin
assert False report "ERROR : No ssrctrl netlist available for this technology!"
severity Failure;
wait;
end process;
end generate;
nobus16 : if not ( bus16=1 )
generate
err : process
begin
assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
|
mit
|
franz/pocl
|
examples/accel/rtl/platform/tta-accel.vhdl
|
2
|
28539
|
-- Copyright (c) 2016-2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------------
-- Title : AXI interface for AlmaIF wrapper
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : tta-accel-rtl.vhdl
-- Author : Viitanen Timo (Tampere University) <[email protected]>
-- Company :
-- Created : 2016-01-27
-- Last update: 2017-03-27
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-01-27 1.0 viitanet Created
-- 2016-11-18 1.1 tervoa Added full AXI4 interface
-- 2017-03-27 1.2 tervoa Change to axislave interface
-- 2017-04-25 1.3 tervoa Merge entity and architecture, use generics
-- instead of consts from packages
-- 2017-06-01 1.4 tervoa Convert to memory buses with handshaking
-- 2018-07-30 1.5 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.tce_util.all;
entity tta_accel is
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
axi_offset_g : integer := 0;
full_debugger_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_awid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector (8-1 downto 0);
s_axi_awsize : in std_logic_vector (3-1 downto 0);
s_axi_awburst : in std_logic_vector (2-1 downto 0);
s_axi_bid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arid : in std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector (8-1 downto 0);
s_axi_arsize : in std_logic_vector (3-1 downto 0);
s_axi_arburst : in std_logic_vector (2-1 downto 0);
s_axi_rid : out std_logic_vector (axi_id_width_g-1 downto 0);
s_axi_rlast : out std_logic;
-- AXI4-Lite Master for global mem
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(dmem_data_width_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(dmem_data_width_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(dmem_data_width_g-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(0 downto 0);
core_dmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(core_count_g*dmem_addr_width_g-1
downto 0);
core_dmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_astrb_in : in std_logic_vector((dmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_dmem_adata_in : in std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
core_dmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_dmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(core_count_g*dmem_data_width_g-1
downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_a_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(dmem_addr_width_g-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector((dmem_data_width_g+7)/8-1 downto 0);
data_b_adata_out : out std_logic_vector(dmem_data_width_g-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(dmem_data_width_g-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_aready_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(core_count_g*pmem_addr_width_g-1
downto 0);
core_pmem_awren_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_astrb_in : in std_logic_vector((pmem_data_width_g+7)/8*core_count_g-1
downto 0);
core_pmem_adata_in : in std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
core_pmem_rvalid_out : out std_logic_vector(core_count_g-1 downto 0);
core_pmem_rready_in : in std_logic_vector(core_count_g-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(core_count_g*pmem_data_width_g-1
downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_a_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
param_b_adata_out : out std_logic_vector(pmem_data_width_g-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(pmem_data_width_g-1 downto 0);
-- Debug ports
core_db_tta_nreset : out std_logic_vector(core_count_g-1 downto 0);
core_db_lockrq : out std_logic_vector(core_count_g-1 downto 0);
core_db_pc : in std_logic_vector(core_count_g*imem_addr_width_g-1
downto 0);
core_db_lockcnt : in std_logic_vector(core_count_g*64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(core_count_g*64-1 downto 0)
);
end entity tta_accel;
architecture rtl of tta_accel is
constant dataw_c : integer := 32;
constant ctrl_addr_width_c : integer := 8;
constant dbg_core_sel_width_c : integer := bit_width(core_count_g);
constant imem_byte_sel_width_c : integer := bit_width(imem_data_width_g/8);
constant dmem_byte_sel_width_c : integer := bit_width(dmem_data_width_g/8);
constant pmem_byte_sel_width_c : integer := bit_width(pmem_data_width_g/8);
constant pmem_offset_c : integer := axi_offset_g + 2**(axi_addr_width_g-2)*3;
constant enable_dmem : boolean := dmem_data_width_g > 0;
constant enable_pmem : boolean := pmem_data_width_g > 0;
-- AXI slave memory bus
signal axi_avalid : std_logic;
signal axi_aready : std_logic;
signal axi_aaddr : std_logic_vector(axi_addr_width_g-2-1 downto 0);
signal axi_awren : std_logic;
signal axi_astrb : std_logic_vector(dataw_c/8-1 downto 0);
signal axi_adata : std_logic_vector(dataw_c-1 downto 0);
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal axi_rdata : std_logic_vector(dataw_c-1 downto 0);
signal dmem_avalid : std_logic;
signal dmem_aready : std_logic;
signal dmem_rvalid : std_logic;
signal dmem_rready : std_logic;
signal dmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_avalid : std_logic;
signal ctrl_aready : std_logic;
signal ctrl_rvalid : std_logic;
signal ctrl_rready : std_logic;
signal ctrl_rdata : std_logic_vector(core_count_g*dataw_c-1 downto 0);
signal pmem_avalid : std_logic;
signal pmem_aready : std_logic;
signal pmem_rvalid : std_logic;
signal pmem_rready : std_logic;
signal pmem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal imem_avalid : std_logic;
signal imem_aready : std_logic;
signal imem_rvalid : std_logic;
signal imem_rready : std_logic;
signal imem_rdata : std_logic_vector(dataw_c-1 downto 0);
signal core_busy : std_logic_vector(core_count_g-1 downto 0);
signal tta_sync_nreset : std_logic_vector(core_count_g-1 downto 0);
signal ctrl_en : std_logic;
signal ctrl_data : std_logic_vector(dataw_c-1 downto 0);
signal ctrl_core_sel : std_logic_vector(bit_width(core_count_g)-1 downto 0);
signal mc_arb_pmem_avalid : std_logic;
signal mc_arb_pmem_aready : std_logic;
signal mc_arb_pmem_aaddr : std_logic_vector(pmem_addr_width_g-1 downto 0);
signal mc_arb_pmem_awren : std_logic;
signal mc_arb_pmem_astrb : std_logic_vector((pmem_data_width_g+7)/8-1 downto 0);
signal mc_arb_pmem_adata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal mc_arb_pmem_rvalid : std_logic;
signal mc_arb_pmem_rready : std_logic;
signal mc_arb_pmem_rdata : std_logic_vector(pmem_data_width_g-1 downto 0);
signal axi_imem_avalid_out : std_logic;
signal axi_imem_aready_in : std_logic;
signal axi_imem_aaddr_out : std_logic_vector(imem_addr_width_g-1 downto 0);
signal axi_imem_awren_out : std_logic;
signal axi_imem_astrb_out : std_logic_vector((imem_data_width_g+7)/8-1 downto 0);
signal axi_imem_adata_out : std_logic_vector(imem_data_width_g-1 downto 0);
signal axi_imem_rvalid_in : std_logic;
signal axi_imem_rready_out : std_logic;
signal axi_imem_rdata_in : std_logic_vector(imem_data_width_g-1 downto 0);
signal tta_aready : std_logic_vector(core_count_g-1 downto 0);
signal tta_rvalid : std_logic_vector(core_count_g-1 downto 0);
signal aql_read_idx, aql_write_idx : std_logic_vector(64-1 downto 0);
signal aql_read_idx_clear : std_logic_vector(0 downto 0);
signal core_db_pc_start : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_instr : std_logic_vector(core_count_g*imem_data_width_g-1 downto 0);
signal core_db_pc_next : std_logic_vector(core_count_g*imem_addr_width_g-1 downto 0);
signal core_db_bustraces : std_logic_vector(core_count_g*32*bus_count_g-1 downto 0);
begin
-----------------------------------------------------------------------------
-- AXI Controller
-----------------------------------------------------------------------------
tta_axislave_1 : entity work.tta_axislave
generic map (
axi_addrw_g => axi_addr_width_g,
axi_idw_g => axi_id_width_g,
axi_dataw_g => dataw_c,
sync_reset_g => sync_reset_g
)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
avalid_out => axi_avalid,
aready_in => axi_aready,
aaddr_out => axi_aaddr,
awren_out => axi_awren,
astrb_out => axi_astrb,
adata_out => axi_adata,
rvalid_in => axi_rvalid,
rready_out => axi_rready,
rdata_in => axi_rdata
);
bus_splitter : entity work.membus_splitter
generic map (
core_count_g => core_count_g,
axi_addr_width_g => axi_addr_width_g,
axi_data_width_g => dataw_c,
ctrl_addr_width_g => ctrl_addr_width_c,
imem_addr_width_g => imem_addr_width_g + imem_byte_sel_width_c,
dmem_addr_width_g => dmem_addr_width_g + dmem_byte_sel_width_c,
pmem_addr_width_g => pmem_addr_width_g + pmem_byte_sel_width_c
) port map (
-- AXI slave
avalid_in => axi_avalid,
aready_out => axi_aready,
aaddr_in => axi_aaddr,
rvalid_out => axi_rvalid,
rready_in => axi_rready,
rdata_out => axi_rdata,
-- Control signals to arbiters
dmem_avalid_out => dmem_avalid,
dmem_aready_in => dmem_aready,
dmem_rvalid_in => dmem_rvalid,
dmem_rready_out => dmem_rready,
dmem_rdata_in => dmem_rdata,
pmem_avalid_out => pmem_avalid,
pmem_aready_in => pmem_aready,
pmem_rvalid_in => pmem_rvalid,
pmem_rready_out => pmem_rready,
pmem_rdata_in => pmem_rdata,
imem_avalid_out => imem_avalid,
imem_aready_in => imem_aready,
imem_rvalid_in => imem_rvalid,
imem_rready_out => imem_rready,
imem_rdata_in => imem_rdata,
-- Signals to debugger(s)
ctrl_avalid_out => ctrl_avalid,
ctrl_aready_in => ctrl_aready,
ctrl_rvalid_in => ctrl_rvalid,
ctrl_rready_out => ctrl_rready,
ctrl_rdata_in => ctrl_rdata,
ctrl_core_sel_out => ctrl_core_sel
);
------------------------------------------------------------------------------
-- Debugger
------------------------------------------------------------------------------
minidebug : entity work.minidebugger
generic map (
data_width_g => 32,
axi_addr_width_g => axi_addr_width_g,
core_count_g => core_count_g,
core_id_width_g => dbg_core_sel_width_c,
imem_data_width_g => imem_data_width_g,
imem_addr_width_g => imem_addr_width_g,
dmem_data_width_g => dmem_data_width_g,
dmem_addr_width_g => dmem_addr_width_g,
pmem_data_width_g => pmem_data_width_g,
pmem_addr_width_g => local_mem_addrw_g
) port map (
clk => clk,
rstx => rstx,
avalid_in => ctrl_avalid,
aready_out => ctrl_aready,
aaddr_in => axi_aaddr,
awren_in => axi_awren,
astrb_in => axi_astrb,
adata_in => axi_adata,
rvalid_out => ctrl_rvalid,
rready_in => ctrl_rready,
rdata_out => ctrl_rdata(dataw_c-1 downto 0),
core_sel_in => ctrl_core_sel,
tta_locked_in => core_busy,
tta_lockrq_out => core_db_lockrq,
tta_nreset_out => core_db_tta_nreset,
tta_pc_in => core_db_pc,
tta_lockcnt_in => core_db_lockcnt,
tta_cyclecnt_in => core_db_cyclecnt,
tta_read_idx_in => aql_read_idx,
tta_read_idx_clear_out => aql_read_idx_clear,
tta_write_idx_out => aql_write_idx
);
rdata_broadcast : for I in 1 to core_count_g-1 generate
ctrl_rdata((I+1)*dataw_c-1 downto I*dataw_c)
<= ctrl_rdata(dataw_c-1 downto 0);
end generate rdata_broadcast;
aql_read_idx <= aql_read_idx_in;
aql_read_idx_clear_out <= aql_read_idx_clear;
------------------------------------------------------------------------------
-- Memory arbitration between IO and TTA
------------------------------------------------------------------------------
mc_arbiters : if core_count_g > 1 generate
gen_dmem_arbiter : if enable_dmem generate
mc_arbiter_dmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_dmem_avalid_in,
tta_aready_out => core_dmem_aready_out,
tta_aaddr_in => core_dmem_aaddr_in,
tta_awren_in => core_dmem_awren_in,
tta_astrb_in => core_dmem_astrb_in,
tta_adata_in => core_dmem_adata_in,
tta_rvalid_out => core_dmem_rvalid_out,
tta_rready_in => core_dmem_rready_in,
tta_rdata_out => core_dmem_rdata_out,
-- Bus to memory
mem_avalid_out => data_a_avalid_out(0),
mem_aready_in => data_a_aready_in(0),
mem_aaddr_out => data_a_aaddr_out,
mem_awren_out => data_a_awren_out(0),
mem_astrb_out => data_a_astrb_out,
mem_adata_out => data_a_adata_out,
mem_rvalid_in => data_a_rvalid_in(0),
mem_rready_out => data_a_rready_out(0),
mem_rdata_in => data_a_rdata_in
);
end generate;
gen_pmem_arbiter : if enable_pmem generate
mc_arbiter_pmem : entity work.almaif_mc_arbiter
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => pmem_addr_width_g,
core_count_g => core_count_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
tta_sync_nreset_in => tta_sync_nreset,
-- Buses to cores
tta_avalid_in => core_pmem_avalid_in,
tta_aready_out => core_pmem_aready_out,
tta_aaddr_in => core_pmem_aaddr_in,
tta_awren_in => core_pmem_awren_in,
tta_astrb_in => core_pmem_astrb_in,
tta_adata_in => core_pmem_adata_in,
tta_rvalid_out => core_pmem_rvalid_out,
tta_rready_in => core_pmem_rready_in,
tta_rdata_out => core_pmem_rdata_out,
-- Bus to memory
mem_avalid_out => mc_arb_pmem_avalid,
mem_aready_in => mc_arb_pmem_aready,
mem_aaddr_out => mc_arb_pmem_aaddr,
mem_awren_out => mc_arb_pmem_awren,
mem_astrb_out => mc_arb_pmem_astrb,
mem_adata_out => mc_arb_pmem_adata,
mem_rvalid_in => mc_arb_pmem_rvalid,
mem_rready_out => mc_arb_pmem_rready,
mem_rdata_in => mc_arb_pmem_rdata
);
end generate;
end generate;
no_mc_arbiters : if core_count_g <= 1 generate
data_a_avalid_out <= core_dmem_avalid_in;
core_dmem_aready_out <= data_a_aready_in;
data_a_aaddr_out <= core_dmem_aaddr_in;
data_a_awren_out <= core_dmem_awren_in;
data_a_astrb_out <= core_dmem_astrb_in;
data_a_adata_out <= core_dmem_adata_in;
core_dmem_rvalid_out <= data_a_rvalid_in;
data_a_rready_out <= core_dmem_rready_in;
core_dmem_rdata_out <= data_a_rdata_in;
mc_arb_pmem_avalid <= core_pmem_avalid_in(0);
core_pmem_aready_out(0) <= mc_arb_pmem_aready;
mc_arb_pmem_aaddr <= core_pmem_aaddr_in;
mc_arb_pmem_awren <= core_pmem_awren_in(0);
mc_arb_pmem_astrb <= core_pmem_astrb_in;
mc_arb_pmem_adata <= core_pmem_adata_in;
core_pmem_rvalid_out(0) <= mc_arb_pmem_rvalid;
mc_arb_pmem_rready <= core_pmem_rready_in(0);
core_pmem_rdata_out <= mc_arb_pmem_rdata;
end generate;
gen_decoder : if axi_offset_g /= 0 generate
decoder_pmem : entity work.almaif_decoder
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_addrw_g => 32,
mem_offset_g => pmem_offset_c,
sync_reset_g => sync_reset_g
) port map (
clk => clk,
rstx => rstx,
-- Bus from arbiter
arb_avalid_in => mc_arb_pmem_avalid,
arb_aready_out => mc_arb_pmem_aready,
arb_aaddr_in => mc_arb_pmem_aaddr,
arb_awren_in => mc_arb_pmem_awren,
arb_astrb_in => mc_arb_pmem_astrb,
arb_adata_in => mc_arb_pmem_adata,
--
arb_rvalid_out => mc_arb_pmem_rvalid,
arb_rready_in => mc_arb_pmem_rready,
arb_rdata_out => mc_arb_pmem_rdata,
-- Bus to local memory
mem_avalid_out => param_a_avalid_out(0),
mem_aready_in => param_a_aready_in(0),
mem_aaddr_out => param_a_aaddr_out,
mem_awren_out => param_a_awren_out(0),
mem_astrb_out => param_a_astrb_out,
mem_adata_out => param_a_adata_out,
--
mem_rvalid_in => param_a_rvalid_in(0),
mem_rready_out => param_a_rready_out(0),
mem_rdata_in => param_a_rdata_in,
-- AXI lite master
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awprot => m_axi_awprot,
--
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
--
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
--
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
--
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
m_axi_rdata => m_axi_rdata
);
end generate;
no_decoder : if axi_offset_g = 0 generate
param_a_avalid_out(0) <= mc_arb_pmem_avalid;
mc_arb_pmem_aready <= param_a_aready_in(0);
param_a_aaddr_out <= mc_arb_pmem_aaddr;
param_a_awren_out(0) <= mc_arb_pmem_awren;
param_a_astrb_out <= mc_arb_pmem_astrb;
param_a_adata_out <= mc_arb_pmem_adata;
mc_arb_pmem_rvalid <= param_a_rvalid_in(0);
param_a_rready_out(0) <= mc_arb_pmem_rready;
mc_arb_pmem_rdata <= param_a_rdata_in;
end generate;
gen_dmem_expander : if enable_dmem generate
dmem_expander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => dmem_data_width_g,
mem_addrw_g => dmem_addr_width_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => dmem_avalid,
axi_aready_out => dmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => dmem_rvalid,
axi_rready_in => dmem_rready,
axi_rdata_out => dmem_rdata,
-- Bus to memory
mem_avalid_out => data_b_avalid_out(0),
mem_aready_in => data_b_aready_in(0),
mem_aaddr_out => data_b_aaddr_out,
mem_awren_out => data_b_awren_out(0),
mem_astrb_out => data_b_astrb_out,
mem_adata_out => data_b_adata_out,
mem_rvalid_in => data_b_rvalid_in(0),
mem_rready_out => data_b_rready_out(0),
mem_rdata_in => data_b_rdata_in
);
end generate;
no_dmem_expander : if not enable_dmem generate
dmem_aready <= '1';
dmem_rvalid <= '1';
dmem_rdata <= (others => '0');
end generate;
gen_pmem_expander : if enable_pmem generate
pmem_epander : entity work.almaif_axi_expander
generic map (
mem_dataw_g => pmem_data_width_g,
mem_addrw_g => local_mem_addrw_g,
axi_dataw_g => dataw_c,
axi_addrw_g => axi_addr_width_g,
sync_reset_g => sync_reset_g
) port map (
clk => clk, rstx => rstx,
-- Bus to AXI if
axi_avalid_in => pmem_avalid,
axi_aready_out => pmem_aready,
axi_aaddr_in => axi_aaddr,
axi_awren_in => axi_awren,
axi_astrb_in => axi_astrb,
axi_adata_in => axi_adata,
axi_rvalid_out => pmem_rvalid,
axi_rready_in => pmem_rready,
axi_rdata_out => pmem_rdata,
-- Bus to memory
mem_avalid_out => param_b_avalid_out(0),
mem_aready_in => param_b_aready_in(0),
mem_aaddr_out => param_b_aaddr_out,
mem_awren_out => param_b_awren_out(0),
mem_astrb_out => param_b_astrb_out,
mem_adata_out => param_b_adata_out,
mem_rvalid_in => param_b_rvalid_in(0),
mem_rready_out => param_b_rready_out(0),
mem_rdata_in => param_b_rdata_in
);
end generate;
no_pmem_expander : if not enable_pmem generate
pmem_aready <= '1';
pmem_rvalid <= '1';
pmem_rdata <= (others => '0');
end generate;
end architecture rtl;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/eth/core/greth_rx.vhd
|
2
|
10381
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
constant maxsize : integer := 1518;
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0';
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if (dv and r.rxen(1)) = '1' then
v.rx_state := wait_sfd;
elsif dv = '1' then v.rx_state := discard_packet; end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when wait_sfd =>
if act = '0' then v.rx_state := idle;
elsif (rxd = "1101") and (dv = '1') and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsize then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if rxi.writeack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
if rmii = 1 then
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
end if;
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
end process;
rxregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
mit
|
lxp32/lxp32-cpu
|
verify/common_pkg/common_pkg_body.vhd
|
1
|
1776
|
---------------------------------------------------------------------
-- Common package for LXP32 testbenches
--
-- Part of the LXP32 verification environment
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package body common_pkg is
procedure rand(variable st: inout rng_state_type; a,b: integer; variable x: out integer) is
variable r: real;
begin
assert a<=b report "Invalid range" severity failure;
uniform(st.seed1,st.seed2,r);
r:=r*real(b-a+1);
x:=a+integer(floor(r));
end procedure;
function hex_string(x: std_logic_vector) return string is
variable xx: std_logic_vector(x'length-1 downto 0);
variable i: integer:=0;
variable ii: integer;
variable c: integer;
variable high_index: integer;
variable s: string(x'length downto 1);
begin
xx:=x;
loop
ii:=i*4;
exit when ii>xx'high;
if ii+3<=xx'high then
high_index:=ii+3;
else
high_index:=xx'high;
end if;
if is_x(xx(high_index downto ii)) then
c:=-1;
else
c:=to_integer(unsigned(xx(high_index downto ii)));
end if;
case c is
when 0 => s(i+1):='0';
when 1 => s(i+1):='1';
when 2 => s(i+1):='2';
when 3 => s(i+1):='3';
when 4 => s(i+1):='4';
when 5 => s(i+1):='5';
when 6 => s(i+1):='6';
when 7 => s(i+1):='7';
when 8 => s(i+1):='8';
when 9 => s(i+1):='9';
when 10 => s(i+1):='A';
when 11 => s(i+1):='B';
when 12 => s(i+1):='C';
when 13 => s(i+1):='D';
when 14 => s(i+1):='E';
when 15 => s(i+1):='F';
when others => s(i+1):='X';
end case;
i:=i+1;
end loop;
return s(i downto 1);
end function;
end package body;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram_2p.vhd
|
2
|
6732
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2p
-- File: syncram_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
entity syncram_2p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram_2p is
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal diagin : std_logic_vector(3 downto 0);
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
diagin <= (others => '0');
inf : if tech = inferred generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech =virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram_2p generic map (abits, dbits, sepclk, wrfst)
port map (rclk, renable, raddress, dataout, wclk,
write, waddress, datain);
end generate;
vir : if tech = memvirage generate
d39 : if dbits = 39 generate
x0 : virage_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
d32 : if dbits <= 32 generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain, testin);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
ihp : if tech = ihp25 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (rclk, raddress, vgnd, dataout, renable, gnd,
wclk, waddress, datain, open, write, write);
end generate;
rh_lib18t0 : if tech = rhlib18t generate
x0 : rh_lib18t_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout, write, waddress, datain, diagin);
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
ecl : if tech = eclipse generate
x0 : eclipse_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/misc/spictrl.vhd
|
2
|
24377
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl
-- File: spictrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.misc.all;
entity spictrl is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- SPI controller configuration
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0); -- Output enable polarity
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl;
architecture rtl of spictrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SPICTRL_REV : integer := 0;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant CAP_ADDR : std_logic_vector(7 downto 2) := "000000"; -- 0x00
constant MODE_ADDR : std_logic_vector(7 downto 2) := "001000"; -- 0x20
constant EVENT_ADDR : std_logic_vector(7 downto 2) := "001001"; -- 0x24
constant MASK_ADDR : std_logic_vector(7 downto 2) := "001010"; -- 0x28
constant COM_ADDR : std_logic_vector(7 downto 2) := "001011"; -- 0x2C
constant TD_ADDR : std_logic_vector(7 downto 2) := "001100"; -- 0x30
constant RD_ADDR : std_logic_vector(7 downto 2) := "001101"; -- 0x34
constant SLVSEL_ADDR : std_logic_vector(7 downto 2) := "001110"; -- 0x38
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ,8) & conv_std_logic_vector(SLVSEL_EN,8) &
conv_std_logic_vector(FIFO_DEPTH,8) & conv_std_logic_vector(SPICTRL_REV,8);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
cg : std_logic_vector(4 downto 0); -- Clock gap
end record;
type spi_em_rec is record -- SPI Event and Mask registers
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
end record;
type spi_fifo is array (0 to (FIFO_DEPTH-1)) of std_logic_vector(31 downto 0);
-- Two stage synchronizers on each input coming from off-chip
type spi_in_array is array (1 downto 0) of spi_in_type;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
toggle : std_ulogic; -- SCK has toggled
sc : std_ulogic; -- Sample/Change
psck : std_ulogic; -- Previous value of SC
running : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : integer range 0 to (FIFO_DEPTH-1); -- First tx queue element
rdfi : integer range 0 to (FIFO_DEPTH-1); -- First rx queue element
tdli : integer range 0 to (FIFO_DEPTH-1); -- Last tx queue element
rdli : integer range 0 to (FIFO_DEPTH-1); -- Last rx queue element
bitcnt : integer range 0 to 31; -- Current bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
--
irq : std_ulogic;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_type;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns an integer containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0);
rev : std_ulogic)
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
case length is
when 31 => rdata := data;
when 30 => rdata(30 downto 0) := data(30 downto 0);
when 29 => rdata(29 downto 0) := data(29 downto 0);
when 28 => rdata(28 downto 0) := data(28 downto 0);
when 27 => rdata(27 downto 0) := data(27 downto 0);
when 26 => rdata(26 downto 0) := data(26 downto 0);
when 25 => rdata(25 downto 0) := data(25 downto 0);
when 24 => rdata(24 downto 0) := data(24 downto 0);
when 23 => rdata(23 downto 0) := data(23 downto 0);
when 22 => rdata(22 downto 0) := data(22 downto 0);
when 21 => rdata(21 downto 0) := data(21 downto 0);
when 20 => rdata(20 downto 0) := data(20 downto 0);
when 19 => rdata(19 downto 0) := data(19 downto 0);
when 18 => rdata(18 downto 0) := data(18 downto 0);
when 17 => rdata(17 downto 0) := data(17 downto 0);
when 16 => rdata(16 downto 0) := data(16 downto 0);
when 15 => rdata(15 downto 0) := data(15 downto 0);
when 14 => rdata(14 downto 0) := data(14 downto 0);
when 13 => rdata(13 downto 0) := data(13 downto 0);
when 12 => rdata(12 downto 0) := data(12 downto 0);
when 11 => rdata(11 downto 0) := data(11 downto 0);
when 10 => rdata(10 downto 0) := data(10 downto 0);
when 9 => rdata(9 downto 0) := data(9 downto 0);
when 8 => rdata(8 downto 0) := data(8 downto 0);
when 7 => rdata(7 downto 0) := data(7 downto 0);
when 6 => rdata(6 downto 0) := data(6 downto 0);
when 5 => rdata(5 downto 0) := data(5 downto 0);
when 4 => rdata(4 downto 0) := data(4 downto 0);
when 3 => rdata(3 downto 0) := data(3 downto 0);
when 2 => rdata(2 downto 0) := data(2 downto 0);
when 1 => rdata(1 downto 0) := data(1 downto 0);
when others => rdata(0) := data(0);
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
signal spisel : std_ulogic;
signal cpol : std_ulogic;
signal sck : std_ulogic;
signal prevsck : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if (sck xor prevsck) = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
begin
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi, spii)
variable v : spi_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable sample, change : std_ulogic;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
len := spilen(r.mode.len);
indata := '0'; sample := '0'; change := '0'; v.toggle := '0';
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CAP_ADDR =>
apbout := SPICTRLCAPREG;
when MODE_ADDR =>
apbout := zero32(31) & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & zero32(15 downto 12) &
r.mode.cg & zero32(6 downto 0);
when EVENT_ADDR =>
apbout := zero32(31 downto 15) & r.event.lt & zero32(13) &
r.event.ov & r.event.un & r.event.mme & r.event.ne &
r.event.nf & zero32(7 downto 0);
when MASK_ADDR =>
apbout := zero32(31 downto 15) & r.mask.lt & zero32(13) &
r.mask.ov & r.mask.un & r.mask.mme & r.mask.ne &
r.mask.nf & zero32(7 downto 0);
when RD_ADDR =>
apbout := condhwordswap(r.rd, len, r.mode.rev);
v.rd_free := '1';
when SLVSEL_ADDR =>
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when MODE_ADDR =>
v.mode.loopb := apbi.pwdata(30);
v.mode.cpol := apbi.pwdata(29);
v.mode.cpha := apbi.pwdata(28);
v.mode.div16 := apbi.pwdata(27);
v.mode.rev := apbi.pwdata(26);
v.mode.ms := apbi.pwdata(25);
v.mode.en := apbi.pwdata(24);
v.mode.len := apbi.pwdata(23 downto 20);
v.mode.pm := apbi.pwdata(19 downto 16);
v.mode.cg := apbi.pwdata(11 downto 7);
when EVENT_ADDR =>
wc(v.event.lt, r.event.lt, apbi.pwdata(14));
wc(v.event.ov, r.event.ov, apbi.pwdata(12));
wc(v.event.un, r.event.un, apbi.pwdata(11));
wc(v.event.mme, r.event.mme, apbi.pwdata(10));
when MASK_ADDR =>
v.mask.lt := apbi.pwdata(14);
v.mask.ov := apbi.pwdata(12);
v.mask.un := apbi.pwdata(11);
v.mask.mme := apbi.pwdata(10);
v.mask.ne := apbi.pwdata(9);
v.mask.nf := apbi.pwdata(8);
when COM_ADDR =>
v.lst := apbi.pwdata(22);
when TD_ADDR =>
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi.pwdata;
v.td_occ := '1';
end if;
when SLVSEL_ADDR =>
if SLVSEL_EN /= 0 then v.slvsel := apbi.pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
when others => null;
end case;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if r.mode.rev = '0' then
v.txfifo(r.tdli) := r.td;
else
v.txfifo(r.tdli) := reverse(r.td);
end if;
v.tdli := (r.tdli + 1) mod FIFO_DEPTH;
v.tfreecnt := r.tfreecnt - 1;
-- Safe since APB has one wait state between writes
v.td_occ := '0';
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(r.rdfi), len));
else
v.rd := select_data(r.rxfifo(r.rdfi), len);
end if;
v.rdfi := (r.rdfi + 1) mod FIFO_DEPTH;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1' then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if (r.mode.ms and r.running) = '1' then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the div16 and pm inputs. They have the same meaning as in
-- the MPC83xx register interface. The clock is divided by 4*([PM]+1) and
-- if div16 is set the clock is divided by 16*(4*([PM]+1)). The duty cycle
-- is 50%.
if r.divcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if r.cgcnt = 0 or r.spio.sck /= r.mode.cpol then
v.spio.sck := not r.spio.sck;
v.toggle := '1';
end if;
if r.cgcnt /= 0 then
v.cgcnt := r.cgcnt - 1;
end if;
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
v.divcnt := r.divcnt - 1;
end if;
else
v.divcnt := (others => '0');
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' then
if r.mode.ms = '1' then
v.spio.sck := r.mode.cpol;
v.spio.misooen := INPUT;
v.spio.mosioen := r.mode.loopb xor OEPOL_LEVEL;
v.spio.sckoen := r.mode.loopb xor OEPOL_LEVEL;
else
if r.spii(1).spisel = '0' then
v.spio.misooen := r.mode.loopb xor OEPOL_LEVEL;
else
v.spio.misooen := INPUT;
end if;
v.spio.mosioen := INPUT;
v.spio.sckoen := INPUT;
end if;
if ((r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH) or
slv_start(r.spii(1).spisel, r.mode.cpol, r.spii(1).sck, r.psck)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
end if;
v.bitcnt := 0;
v.cgcnt := (others => '0');
change := not r.mode.cpha;
-- sc should not be changed on b2b
if r.spii(1).spisel /= '0' then
v.sc := not r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- The sc bit determines if the core should read or change the data on
-- the upcoming flank.
if r.toggle = '1' then
v.sc := not r.sc;
end if;
-- Sample data
if (r.toggle and r.sc) = '1' then
sample := '1';
end if;
-- Change data on the clock flank...
if (v.toggle and not r.sc) = '1' then
change := '1';
end if;
-- Detect multiple-master errors (mode-fault)
if r.spii(1).spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
end if;
indata := spii.miso;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if r.spii(1).spisel = '0' then
v.psck := r.spii(1).sck;
if (r.psck xor r.spii(1).sck) = '1' then
if r.sc = '1' then
sample := '1';
else
change := '1';
end if;
v.sc := not r.sc;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if (r.rfreecnt = 0 and r.rd_free = '0') or r.ov = '1' then
v.ov := '1';
-- Overflow event and IRQ
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
else
if r.mode.loopb = '1' then
v.rxfifo(r.rdli)(0) := r.spio.mosi;
else
v.rxfifo(r.rdli)(0) := indata;
end if;
v.rxfifo(r.rdli)(31 downto 1) := r.rxfifo(r.rdli)(30 downto 0);
end if;
if r.bitcnt = conv_integer(len) then
if r.ov = '0' then
v.rdli := (r.rdli + 1) mod FIFO_DEPTH;
v.rfreecnt := v.rfreecnt - 1;
end if;
v.ov := '0'; -- Clear overflow condition
v.bitcnt := 0;
v.cgcnt := unsigned(r.mode.cg & '0');
if r.uf = '0' then
v.tfreecnt := v.tfreecnt + 1;
v.tdfi := (v.tdfi + 1) mod FIFO_DEPTH;
v.txfifo(r.tdfi)(0) := '1';
end if;
if v.tfreecnt /= FIFO_DEPTH then
v.running := r.mode.ms;
else
v.running := '0';
-- LST detection
if r.lst = '1' then
v.event.lt := '1';
if (r.mask.lt and not r.event.lt) = '1' then
v.irq := '1';
end if;
end if;
v.lst := '0';
end if;
v.uf := '0';
else
v.bitcnt := r.bitcnt + 1;
end if;
end if;
if change = '1' then
if v.uf = '0' then
v.spio.miso := r.txfifo(r.tdfi)(r.bitcnt);
v.spio.mosi := r.txfifo(r.tdfi)(r.bitcnt);
else
v.spio.miso := '1';
v.spio.mosi := '1';
end if;
end if;
if r.mode.en = '0' then -- Core is disabled
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := 0; v.rdfi := 0;
v.tdli := 0; v.rdli := 0;
v.rd_free := '1';
v.td_occ := '0';
v.lst := '0';
v.uf := '0';
v.ov := '0';
v.running := '0';
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
v.spio.sckoen := INPUT;
-- Need to assign sc and psck here if spisel is low when the core is
-- enabled
v.sc := not r.mode.cpha;
v.psck := r.mode.cpol;
-- Set all first bits in txfifo to idle value
for i in 0 to (FIFO_DEPTH-1) loop
v.txfifo(i)(0) := '1';
end loop; -- i
end if;
if rstn = '0' then
v.mode := ('0','0','0','0','0','0','0',"0000","0000", "00000");
v.event := ('0','0','0','0','0','0');
v.mask := ('0','0','0','0','0','0');
v.lst := '0';
v.slvsel := (others => '1');
end if;
-- Synchronize inputs
v.spii(0) := spii;
v.spii(1) := r.spii(0);
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
slvsel <= r.slvsel;
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spictrl" & tost(pindex) & ": SPI controller rev " &
tost(0) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/spacewire/spacewire.in.vhd
|
2
|
608
|
-- Spacewire interface
constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/designs/myDemo/config.vhd
|
2
|
5778
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 2;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := (0) + 0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#00007A#;
constant CFG_ETH_ENL : integer := 16#CC0809#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (256);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (1);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
mit
|
franz/pocl
|
examples/accel/rtl/platform/ffaccel_toplevel_params_pkg.vhdl
|
2
|
207
|
package ffaccel_toplevel_params is
constant fu_DATA_LSU_addrw_g : integer := 12;
constant fu_PARAM_LSU_addrw_g : integer := 32;
constant fu_SP_LSU_addrw_g : integer := 10;
end ffaccel_toplevel_params;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/grlib/amba/ahbctrl.vhd
|
2
|
26677
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0 --master with highest priority
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
end record;
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
for i in 0 to nahbmx-1 loop
if (rsplit(i) = '0') or (split = 0) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
nmst(3) := r.hmaster; nvalid(3) := true;
if (mprio /= 0) and ((rsplit(mprio) = '0') or (split = 0)) then
if msto(mprio).hbusreq = '1' then nmst(1) := mprio; nvalid(1) := true; end if;
end if;
end if;
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen)
variable v : reg_type;
variable nhmaster, hmaster : integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hcache : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
arb := '0';
if r.hmasterlock = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i);
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
if (arb = '1') then selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then defmst := r.defmst; end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error respons on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
hrdata := slvo(r.hslave).hrdata;
if cfgmask /= 0 then
-- v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
-- if r.haddr(11 downto MIMAX+6) /= zero32(11 downto MIMAX+6) then v.hrdatam := (others => '0'); end if;
-- if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (r.haddr(4 downto 2) = "000")
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
-- if r.haddr(11 downto SIMAX+6) /= ('1' & zero32(10 downto SIMAX+6)) then v.hrdatas := (others => '0'); end if;
--if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
if r.haddr(10 downto 4) = "1111111" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := r.hrdatam;
else hrdata := r.hrdatas; end if;
end if;
end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hmasterlock := msto(nhmaster).hlock; v.hslave := nslave; v.defslv := defslv;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
if r.cfgsel = '1' then hcache := '1'; else hcache := slvo(v.hslave).hcache; end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hwdata := msto(r.hmasterd).hwdata;
vslvi.hprot := msto(r.hmaster).hprot;
vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hcache := hcache;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hwdata := msto(r.hmasterd).hwdata;
vslvi.hirq := hirq;
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
-- reset operation
if (rst = '0') then
v.hmaster := 0; v.hmasterlock := '0'; vsplit := (others => '0');
v.htrans := HTRANS_IDLE; v.defslv := '0'; -- v.beat := "0001";
v.hslave := 0; v.cfgsel := '0'; v.defmst := '0';
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hcache <= hcache;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hcache <= hcache;
lmsti.hirq <= hirq;
-- pragma translate_on
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin if rising_edge(clk) then rsplit <= rsplitin; end if; end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
-- diag : process
-- variable k : integer;
-- variable mask : std_logic_vector(11 downto 0);
-- variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
-- variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
-- begin
-- wait for 2 ns;
-- k := 0; mask := IOMSK;
-- while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
-- print("ahbctrl: AHB arbiter/multiplexer rev 1");
-- if ioen /= 0 then
-- print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
-- else
-- print("ahbctrl: Common I/O area disabled");
-- end if;
-- if cfgmask /= 0 then
-- print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
-- else
-- print("ahbctrl: Configuration area disabled");
-- end if;
-- wait;
-- end process;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
begin
wait for 2 ns;
if debug = 0 then wait; end if;
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
if debug = 1 then wait; end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) severity failure;
end if;
end loop;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
if (mask /= "000000000000") then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
std.textio.write(L1, "ahbctrl: memory at " & tost( slvo(i).hconfig(j)(31 downto 20))&
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
when "11" =>
if ioen /= 0 then
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost( iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) severity failure;
end if;
end loop;
wait;
end process;
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/ec/orca/orcacomp.vhd
|
5
|
74888
|
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A.
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 1-408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
--
-- Simulation Library File for EC/XP
--
-- $Header: G:\\CVS_REPOSITORY\\CVS_MACROS/LEON3SDE/ALTERA/grlib-eval-1.0.4/lib/tech/ec/ec/ORCACOMP.vhd,v 1.1 2005/12/06 13:00:22 tame Exp $
--
---
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE components IS
function str2std(L: string) return std_logic_vector;
function Str2int( L : string) return integer;
function Str2real( L : string) return REAL;
-----functions for Multipliers (for ECP)----------
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR;
function VEC2INT(v: std_logic_vector) return integer;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
function BITX (VECT: std_logic) return boolean;
function VECX (VECT: std_logic_vector) return boolean;
--
COMPONENT ageb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ge: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aleb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
le: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT aneb2
PORT(
a0, a1: IN std_logic := 'X';
b0, b1: IN std_logic := 'X';
ci: IN std_logic := 'X';
ne: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT and5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cd2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cu2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT cb2
PORT(
ci : IN std_logic := 'X';
pc0, pc1 : IN std_logic := 'X';
con: IN std_logic := 'X';
co : OUT std_logic := 'X';
nc0, nc1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lb4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
con: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu2p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ld4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT lu4p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d0, d1, d2, d3 : IN std_logic := 'X';
ci: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
co: OUT std_logic := 'X';
q0, q1, q2, q3 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadd2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
ci: IN std_logic := 'X';
cout0, cout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fsub2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bi: IN std_logic := 'X';
bout0, bout1 : OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fadsu2
PORT(
a0, a1 : IN std_logic := 'X';
b0, b1 : IN std_logic := 'X';
bci: IN std_logic := 'X';
con: IN std_logic := 'X';
bco: OUT std_logic := 'X';
s0, s1 : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d: IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fd1s3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
ck: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3az
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3iy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1p3jy
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sp: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1a
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ax
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT fl1s3ay
GENERIC (gsr : String := "ENABLED");
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
ck: IN std_logic := 'X';
sd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT gsr
PORT(
gsr: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT inv
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1b
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1d
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1i
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ifs1s1j
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd : IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT l6mux21
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
sd: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux41
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux81
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux161
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT mux321
PORT(
d0: IN std_logic := 'X';
d1: IN std_logic := 'X';
d2: IN std_logic := 'X';
d3: IN std_logic := 'X';
d4: IN std_logic := 'X';
d5: IN std_logic := 'X';
d6: IN std_logic := 'X';
d7: IN std_logic := 'X';
d8: IN std_logic := 'X';
d9: IN std_logic := 'X';
d10: IN std_logic := 'X';
d11: IN std_logic := 'X';
d12: IN std_logic := 'X';
d13: IN std_logic := 'X';
d14: IN std_logic := 'X';
d15: IN std_logic := 'X';
d16: IN std_logic := 'X';
d17: IN std_logic := 'X';
d18: IN std_logic := 'X';
d19: IN std_logic := 'X';
d20: IN std_logic := 'X';
d21: IN std_logic := 'X';
d22: IN std_logic := 'X';
d23: IN std_logic := 'X';
d24: IN std_logic := 'X';
d25: IN std_logic := 'X';
d26: IN std_logic := 'X';
d27: IN std_logic := 'X';
d28: IN std_logic := 'X';
d29: IN std_logic := 'X';
d30: IN std_logic := 'X';
d31: IN std_logic := 'X';
sd1: IN std_logic := 'X';
sd2: IN std_logic := 'X';
sd3: IN std_logic := 'X';
sd4: IN std_logic := 'X';
sd5: IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nd5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT nr5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofe1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
eclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3bx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3dx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3ix
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
cd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT ofs1p3jx
GENERIC (gsr : String := "ENABLED");
PORT(
d : IN std_logic := 'X';
sp: IN std_logic := 'X';
sclk: IN std_logic := 'X';
pd: IN std_logic := 'X';
q : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT or5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pfumx
PORT(
alut: IN std_logic := 'X';
blut: IN std_logic := 'X';
c0 : IN std_logic := 'X';
z : OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pur
PORT(
pur: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom32x1
GENERIC(
initval : string := "0x00000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom16x1
GENERIC(
initval : string := "0x0000"
);
PORT(
ad0, ad1, ad2, ad3: IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom64x1
GENERIC(
initval : string := "0x0000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom128x1
GENERIC(
initval : string := "0x00000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT rom256x1
GENERIC(
initval : string := "0x0000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7 : IN std_logic := 'X';
do0: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT strtup
PORT(
uclk : IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT tsall
PORT(
tsall: IN std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vhi
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT vlo
PORT(
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor11
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xor21
PORT(
a, b, c, d, e, f, g, h, i, j, k: IN std_logic := 'X';
l, m, n, o, p, q, r, s, t, u: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor2
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor3
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor4
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT xnor5
PORT(
a: IN std_logic := 'X';
b: IN std_logic := 'X';
c: IN std_logic := 'X';
d: IN std_logic := 'X';
e: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bufba
PORT(
a: IN std_logic := 'X';
z: OUT std_logic := 'X'
);
END COMPONENT;
--
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT pdp8ka
GENERIC(
DATA_WIDTH_W : in Integer := 18;
DATA_WIDTH_R : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
--
COMPONENT bbw
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obw
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ilvds
PORT(
a : IN std_logic := 'X';
an: IN std_logic := 'X';
z : OUT std_logic
);
END COMPONENT;
--
COMPONENT olvds
PORT(
a : IN std_logic := 'X';
z : OUT std_logic ;
zn : OUT std_logic
);
END COMPONENT;
--
COMPONENT bb
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpd
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT bbpu
PORT(
b: INOUT std_logic := 'X';
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ib
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpd
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ibpu
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT ob
PORT(
i: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obz
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpd
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT obzpu
PORT(
i: IN std_logic := 'X';
t: IN std_logic := 'X';
o: OUT std_logic);
END COMPONENT;
--
COMPONENT dcs
GENERIC(
DCSMODE : String := "POS");
PORT(
clk0 : IN std_logic;
clk1 : IN std_logic;
sel : IN std_logic;
dcsout : OUT std_logic);
END COMPONENT;
--
component EPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "8";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
WAKE_ON_LOCK : string := "off");
port(
CLKI : in STD_ULOGIC;
RST : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
LOCK : out STD_ULOGIC
);
end component;
--
component EHXPLLB
generic(
FIN : string := "100.0";
CLKI_DIV : string := "1";
CLKOP_DIV : string := "1";
CLKFB_DIV : string := "1";
FDEL : string := "1";
FB_MODE : string := "CLOCKTREE";
CLKOK_DIV : string := "2";
WAKE_ON_LOCK : string := "off";
DELAY_CNTL : string := "STATIC";
PHASEADJ : string := "0";
DUTY : string := "4");
port(
CLKI : in STD_ULOGIC;
CLKFB : in STD_ULOGIC;
RST : in STD_ULOGIC := '0';
DDAMODE : in STD_ULOGIC;
DDAIZR : in STD_ULOGIC;
DDAILAG : in STD_ULOGIC;
DDAIDEL0 : in STD_ULOGIC;
DDAIDEL1 : in STD_ULOGIC;
DDAIDEL2 : in STD_ULOGIC;
CLKOP : out STD_ULOGIC;
CLKOS : out STD_ULOGIC;
CLKOK : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
DDAOZR : out STD_ULOGIC;
DDAOLAG : out STD_ULOGIC;
DDAODEL0 : out STD_ULOGIC;
DDAODEL1 : out STD_ULOGIC;
DDAODEL2 : out STD_ULOGIC
);
end component;
--
------Component ORCALUT4------
component ORCALUT4
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT5------
component ORCALUT5
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT6------
component ORCALUT6
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT7------
component ORCALUT7
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
------Component ORCALUT8------
component ORCALUT8
generic( INIT : bit_vector);
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
F : in STD_ULOGIC;
G : in STD_ULOGIC;
H : in STD_ULOGIC;
Z : out STD_ULOGIC
);
end component;
--
component MULT2
port(
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
CI : in STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
--
component IDDRXB
generic( REGSET : string := "RESET");
port(
D : in STD_LOGIC;
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
LSR : in STD_LOGIC;
CE : in STD_LOGIC;
DDRCLKPOL : in STD_LOGIC;
QA : out STD_LOGIC;
QB : out STD_LOGIC
);
end component;
--
component ODDRXB
generic( REGSET : string := "RESET");
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
--
component CCU2
generic (
inject1_0 : string := "YES";
inject1_1 : string := "YES";
init0: string := "0x0000";
init1: string := "0x0000"
);
port (
A0,A1 : in std_ulogic;
B0,B1 : in std_ulogic;
C0,C1 : in std_ulogic;
D0,D1 : in std_ulogic;
CIN : in std_ulogic;
S0,S1 : out std_ulogic;
COUT0,COUT1 : out std_ulogic
);
end component;
--
component DQSBUFB
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0");
port(
DQSI : in STD_LOGIC;
CLK : in STD_LOGIC;
READ : in STD_LOGIC;
DQSDEL : in STD_LOGIC;
DQSO : out STD_LOGIC;
DDRCLKPOL : out STD_LOGIC;
DQSC : out STD_LOGIC;
PRMBDET : out STD_LOGIC
);
end component;
--
component DQSDLL
generic(DEL_ADJ : string := "PLUS";
DEL_VAL : string := "0";
LOCK_SENSITIVITY : string := "LOW");
port(
CLK : in STD_ULOGIC;
RST : in STD_ULOGIC;
UDDCNTL : in STD_ULOGIC;
LOCK : out STD_ULOGIC;
DQSDEL : out STD_ULOGIC
);
end component;
--
-- 18x18 MULT for ECP
component MULT18X18
generic(
REG_INPUTA_CLK : string := "NONE";
REG_INPUTA_CE : string := "CE0";
REG_INPUTA_RST : string := "RST0";
REG_INPUTB_CLK : string := "NONE";
REG_INPUTB_CE : string := "CE0";
REG_INPUTB_RST : string := "RST0";
REG_PIPELINE_CLK : string := "NONE";
REG_PIPELINE_CE : string := "CE0";
REG_PIPELINE_RST : string := "RST0";
REG_OUTPUT_CLK : string := "NONE";
REG_OUTPUT_CE : string := "CE0";
REG_OUTPUT_RST : string := "RST0";
REG_SIGNEDAB_0_CLK : string := "NONE";
REG_SIGNEDAB_0_CE : string := "CE0";
REG_SIGNEDAB_0_RST : string := "RST0";
REG_SIGNEDAB_1_CLK : string := "NONE";
REG_SIGNEDAB_1_CE : string := "CE0";
REG_SIGNEDAB_1_RST : string := "RST0";
SHIFT_IN_A : string := "FALSE";
SHIFT_IN_B : string := "FALSE";
GSR : string := "ENABLED");
port (
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
A5 : in STD_ULOGIC;
A6 : in STD_ULOGIC;
A7 : in STD_ULOGIC;
A8 : in STD_ULOGIC;
A9 : in STD_ULOGIC;
A10 : in STD_ULOGIC;
A11 : in STD_ULOGIC;
A12 : in STD_ULOGIC;
A13 : in STD_ULOGIC;
A14 : in STD_ULOGIC;
A15 : in STD_ULOGIC;
A16 : in STD_ULOGIC;
A17 : in STD_ULOGIC;
SRIA0 : in STD_ULOGIC;
SRIA1 : in STD_ULOGIC;
SRIA2 : in STD_ULOGIC;
SRIA3 : in STD_ULOGIC;
SRIA4 : in STD_ULOGIC;
SRIA5 : in STD_ULOGIC;
SRIA6 : in STD_ULOGIC;
SRIA7 : in STD_ULOGIC;
SRIA8 : in STD_ULOGIC;
SRIA9 : in STD_ULOGIC;
SRIA10 : in STD_ULOGIC;
SRIA11 : in STD_ULOGIC;
SRIA12 : in STD_ULOGIC;
SRIA13 : in STD_ULOGIC;
SRIA14 : in STD_ULOGIC;
SRIA15 : in STD_ULOGIC;
SRIA16 : in STD_ULOGIC;
SRIA17 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
B2 : in STD_ULOGIC;
B3 : in STD_ULOGIC;
B4 : in STD_ULOGIC;
B5 : in STD_ULOGIC;
B6 : in STD_ULOGIC;
B7 : in STD_ULOGIC;
B8 : in STD_ULOGIC;
B9 : in STD_ULOGIC;
B10 : in STD_ULOGIC;
B11 : in STD_ULOGIC;
B12 : in STD_ULOGIC;
B13 : in STD_ULOGIC;
B14 : in STD_ULOGIC;
B15 : in STD_ULOGIC;
B16 : in STD_ULOGIC;
B17 : in STD_ULOGIC;
SRIB0 : in STD_ULOGIC;
SRIB1 : in STD_ULOGIC;
SRIB2 : in STD_ULOGIC;
SRIB3 : in STD_ULOGIC;
SRIB4 : in STD_ULOGIC;
SRIB5 : in STD_ULOGIC;
SRIB6 : in STD_ULOGIC;
SRIB7 : in STD_ULOGIC;
SRIB8 : in STD_ULOGIC;
SRIB9 : in STD_ULOGIC;
SRIB10 : in STD_ULOGIC;
SRIB11 : in STD_ULOGIC;
SRIB12 : in STD_ULOGIC;
SRIB13 : in STD_ULOGIC;
SRIB14 : in STD_ULOGIC;
SRIB15 : in STD_ULOGIC;
SRIB16 : in STD_ULOGIC;
SRIB17 : in STD_ULOGIC;
SIGNEDAB : in STD_ULOGIC;
CE0 : in STD_ULOGIC;
CE1 : in STD_ULOGIC;
CE2 : in STD_ULOGIC;
CE3 : in STD_ULOGIC;
CLK0 : in STD_ULOGIC;
CLK1 : in STD_ULOGIC;
CLK2 : in STD_ULOGIC;
CLK3 : in STD_ULOGIC;
RST0 : in STD_ULOGIC;
RST1 : in STD_ULOGIC;
RST2 : in STD_ULOGIC;
RST3 : in STD_ULOGIC;
SROA0 : out STD_ULOGIC;
SROA1 : out STD_ULOGIC;
SROA2 : out STD_ULOGIC;
SROA3 : out STD_ULOGIC;
SROA4 : out STD_ULOGIC;
SROA5 : out STD_ULOGIC;
SROA6 : out STD_ULOGIC;
SROA7 : out STD_ULOGIC;
SROA8 : out STD_ULOGIC;
SROA9 : out STD_ULOGIC;
SROA10 : out STD_ULOGIC;
SROA11 : out STD_ULOGIC;
SROA12 : out STD_ULOGIC;
SROA13 : out STD_ULOGIC;
SROA14 : out STD_ULOGIC;
SROA15 : out STD_ULOGIC;
SROA16 : out STD_ULOGIC;
SROA17 : out STD_ULOGIC;
SROB0 : out STD_ULOGIC;
SROB1 : out STD_ULOGIC;
SROB2 : out STD_ULOGIC;
SROB3 : out STD_ULOGIC;
SROB4 : out STD_ULOGIC;
SROB5 : out STD_ULOGIC;
SROB6 : out STD_ULOGIC;
SROB7 : out STD_ULOGIC;
SROB8 : out STD_ULOGIC;
SROB9 : out STD_ULOGIC;
SROB10 : out STD_ULOGIC;
SROB11 : out STD_ULOGIC;
SROB12 : out STD_ULOGIC;
SROB13 : out STD_ULOGIC;
SROB14 : out STD_ULOGIC;
SROB15 : out STD_ULOGIC;
SROB16 : out STD_ULOGIC;
SROB17 : out STD_ULOGIC;
P0 : out STD_ULOGIC;
P1 : out STD_ULOGIC;
P2 : out STD_ULOGIC;
P3 : out STD_ULOGIC;
P4 : out STD_ULOGIC;
P5 : out STD_ULOGIC;
P6 : out STD_ULOGIC;
P7 : out STD_ULOGIC;
P8 : out STD_ULOGIC;
P9 : out STD_ULOGIC;
P10 : out STD_ULOGIC;
P11 : out STD_ULOGIC;
P12 : out STD_ULOGIC;
P13 : out STD_ULOGIC;
P14 : out STD_ULOGIC;
P15 : out STD_ULOGIC;
P16 : out STD_ULOGIC;
P17 : out STD_ULOGIC;
P18 : out STD_ULOGIC;
P19 : out STD_ULOGIC;
P20 : out STD_ULOGIC;
P21 : out STD_ULOGIC;
P22 : out STD_ULOGIC;
P23 : out STD_ULOGIC;
P24 : out STD_ULOGIC;
P25 : out STD_ULOGIC;
P26 : out STD_ULOGIC;
P27 : out STD_ULOGIC;
P28 : out STD_ULOGIC;
P29 : out STD_ULOGIC;
P30 : out STD_ULOGIC;
P31 : out STD_ULOGIC;
P32 : out STD_ULOGIC;
P33 : out STD_ULOGIC;
P34 : out STD_ULOGIC;
P35 : out STD_ULOGIC
);
end component;
end Components;
package body Components is
function str2std(L: string) return std_logic_vector is
variable vpos : integer := 0; -- Index of last valid bit in val.
variable lpos : integer; -- Index of next unused char in L.
variable val : std_logic_vector(1 to L'right); -- lenth of the vector.
begin
lpos := L'left;
while lpos <= L'right and vpos < VAL'length loop
if L(lpos) = '0' then
vpos := vpos + 1;
val(vpos) := '0';
elsif L(lpos) = '1' then
vpos := vpos + 1;
val(vpos) := '1';
else
exit; -- Bit values must be '0' or '1'.
end if;
lpos := lpos + 1;
end loop;
return val;
end str2std;
function str2int( L : string) return integer is
variable ok: boolean;
variable pos: integer:=1;
variable sign: integer := 1;
variable rval: integer := 0;
variable value: integer := 0;
begin
ok := FALSE;
if pos < L'right and (L(pos) = '-' or L(pos) = '+') then
if L(pos) = '-' then
sign := -1;
end if;
pos := pos + 1;
end if;
-- Once the optional leading sign is removed, an integer can
-- contain only the digits '0' through '9' and the '_'
-- (underscore) character. VHDL disallows two successive
-- underscores, and leading or trailing underscores.
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval * 10
+ character'pos(L(pos)) - character'pos('0');
ok := TRUE;
elsif L(pos) = '_' then
if pos = L'right
or L(pos + 1) < '0'
or L(pos + 1) > '9' then
ok := FALSE;
exit;
end if;
else
exit;
end if;
pos := pos + 1;
end loop;
end if;
value := sign * rval;
RETURN(value);
end str2int;
function str2real( L: string) return real is
variable pos: integer;
variable value: real;
variable ok: boolean;
variable sign: real := 1.0;
variable rval: real := 0.0;
variable powerten: real := 0.1;
begin
pos := L'left;
if (pos <= L'right) and (L(pos) = '-') then
sign := -1.0;
pos := pos + 1;
end if;
ok := FALSE;
rval := 0.0;
if pos <= L'right and L(pos) >= '0' and L(pos) <= '9' then
while pos <= L'right and L(pos) /= '.' and L(pos) /= ' ' and L(pos) /= HT
loop
if L(pos) >= '0' and L(pos) <= '9' then
rval := rval*10.0 + real(character'pos(L(pos)) - character'pos('0'));
pos := pos+1;
ok := true;
else
ok := false;
exit;
end if;
end loop;
end if;
if ok and pos <= L'right and L(pos) = '.' then
pos := pos + 1;
end if;
if pos <= L'right then
while pos <= L'right and ((L(pos) >= '0' and L(pos) <= '9') or L(pos) = '_') loop
rval := rval + (real(character'pos(L(pos))-character'pos('0'))*powerten);
powerten := powerten*0.1;
pos := pos+1;
ok := true;
end loop;
end if;
if ok then
value := rval * sign;
end if;
return (value);
end str2real;
function INT2VEC(INT: INTEGER; BWIDTH: INTEGER) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (BWIDTH-1 downto 0);
variable tmp : integer := INT;
begin
tmp := INT;
for i in 0 to BWIDTH-1 loop
if (tmp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if tmp > 0 then
tmp := tmp /2 ;
elsif (tmp > integer'low) then
tmp := (tmp-1) / 2;
else
tmp := tmp / 2;
end if;
end loop;
return result;
end;
function VEC2INT(v: std_logic_vector) return integer is
variable result: integer := 0;
variable addition: integer := 1;
begin
for b in v'reverse_range loop
if v(b) = '1' then
result := result + addition;
end if;
addition := addition * 2;
end loop;
return result;
end VEC2INT;
function VECX (VECT: std_logic_vector) return boolean is
begin
for b in VECT'range loop
if bitX (VECT (b)) then
return true;
end if;
end loop;
return false;
end VECX;
function TSCOMP(VECT: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (VECT'left downto 0);
variable is1 : std_ulogic := '0';
begin
for i in 0 to VECT'left loop
if (is1 = '0') then
result(i) := VECT(i);
if (VECT(i) = '1' ) then
is1 := '1';
end if;
else
result(i) := NOT VECT(i);
end if;
end loop;
return result;
end;
function ADDVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable BVect, result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '0';
BVEct := B;
for i in 0 to A'left loop
result(i) := A(i) xor BVect(i) xor cout;
cout := (A(i) and BVect(i)) or
(A(i) and cout) or
(cout and BVect(i));
end loop;
return result;
end;
function SUBVECT(A, B: STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR is
variable cout: STD_ULOGIC;
variable result: STD_LOGIC_VECTOR(A'left downto 0);
begin
for i in 0 to A'left loop
if (A(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
for i in 0 to B'left loop
if (B(i) = 'X') then
result := (others => 'X');
return(result);
end if;
end loop;
cout := '1';
for i in 0 to A'left loop
result(i) := A(i) xor not B(i) xor cout;
cout := (A(i) and not B(i)) or
(A(i) and cout) or
(cout and not B(i));
end loop;
return result;
end;
function BITX (VECT: std_logic) return boolean is
begin
case VECT is
when 'X' => return true;
when others => return false;
end case;
end BITX;
END components;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/maps/techbuf.vhd
|
2
|
2814
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity techbuf is
generic(
buftype : integer range 0 to 4 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
begin
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
pa3 : if (tech = apa3) generate
axc : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) generate
axc : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or
(tech = spartan3e) or (tech = virtex5) generate
xil : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
axc : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/pci/pci.vhd
|
2
|
12537
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pci is
type pci_in_type is record
rst : std_ulogic;
gnt : std_ulogic;
idsel : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
lock : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
host : std_ulogic;
pci66 : std_ulogic;
pme_status : std_ulogic;
int : std_logic_vector(3 downto 0); -- D downto A
end record;
type pci_out_type is record
aden : std_ulogic;
vaden : std_logic_vector(31 downto 0);
cbeen : std_logic_vector(3 downto 0);
frameen : std_ulogic;
irdyen : std_ulogic;
trdyen : std_ulogic;
devselen : std_ulogic;
stopen : std_ulogic;
ctrlen : std_ulogic;
perren : std_ulogic;
paren : std_ulogic;
reqen : std_ulogic;
locken : std_ulogic;
serren : std_ulogic;
inten : std_ulogic;
req : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
lock : std_ulogic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_ulogic;
pme_clear : std_ulogic;
int : std_ulogic;
end record;
component pci_target
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pci_mt
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component dmactrl
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
blength : integer := 4);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type);
end component;
component pci_mtf
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0;
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcitrace
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcipads
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0)
);
end component;
component pcidma
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
scanen : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pciahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
component pcif
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
aaddr_width : integer := 28;
maddr_width : integer := 28;
pcibars : integer := 1;
ahbmasters : integer := 8;
fifo_depth : integer := 3;
ft : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#);
port(
rst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
--debug : out std_logic_vector(233 downto 0));
end component;
component pcif_async
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
bar1 : integer := 20;
bar2 : integer := 24;
bar3 : integer := 0;
bar4 : integer := 0;
ahbmasters : integer := 28;
fifo_depth : integer := 1;
ft : integer := 0;
nsync : integer := 2;
irqctrl : integer := 0;
host : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
pirq : integer := 0;
netlist : integer := 0;
debugen : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pcirst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type--;
--debug : out std_logic_vector(255 downto 0)
);
end component;
constant PCI_VENDOR_ESA : integer := 16#16E3#;
constant PCI_VENDOR_GAISLER : integer := 16#1AC8#;
constant PCI_VENDOR_AEROFLEX : integer := 16#1AD0#;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci.vhd
|
2
|
12537
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pci is
type pci_in_type is record
rst : std_ulogic;
gnt : std_ulogic;
idsel : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
lock : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
host : std_ulogic;
pci66 : std_ulogic;
pme_status : std_ulogic;
int : std_logic_vector(3 downto 0); -- D downto A
end record;
type pci_out_type is record
aden : std_ulogic;
vaden : std_logic_vector(31 downto 0);
cbeen : std_logic_vector(3 downto 0);
frameen : std_ulogic;
irdyen : std_ulogic;
trdyen : std_ulogic;
devselen : std_ulogic;
stopen : std_ulogic;
ctrlen : std_ulogic;
perren : std_ulogic;
paren : std_ulogic;
reqen : std_ulogic;
locken : std_ulogic;
serren : std_ulogic;
inten : std_ulogic;
req : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
lock : std_ulogic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_ulogic;
pme_clear : std_ulogic;
int : std_ulogic;
end record;
component pci_target
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pci_mt
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component dmactrl
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
blength : integer := 4);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type);
end component;
component pci_mtf
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0;
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcitrace
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcipads
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0)
);
end component;
component pcidma
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
scanen : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pciahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
component pcif
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
aaddr_width : integer := 28;
maddr_width : integer := 28;
pcibars : integer := 1;
ahbmasters : integer := 8;
fifo_depth : integer := 3;
ft : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#);
port(
rst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
--debug : out std_logic_vector(233 downto 0));
end component;
component pcif_async
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
bar1 : integer := 20;
bar2 : integer := 24;
bar3 : integer := 0;
bar4 : integer := 0;
ahbmasters : integer := 28;
fifo_depth : integer := 1;
ft : integer := 0;
nsync : integer := 2;
irqctrl : integer := 0;
host : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
pirq : integer := 0;
netlist : integer := 0;
debugen : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pcirst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type--;
--debug : out std_logic_vector(255 downto 0)
);
end component;
constant PCI_VENDOR_ESA : integer := 16#16E3#;
constant PCI_VENDOR_GAISLER : integer := 16#1AC8#;
constant PCI_VENDOR_AEROFLEX : integer := 16#1AD0#;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/leon3/libproc3.vhd
|
1
|
6202
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libproc3
-- File: libproc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 proc3 component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libcache.all;
use gaisler.libiu.all;
--library fpu;
--use fpu.libfpu.all;
package libproc3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic;
hackVector : out std_logic_vector(7 downto 0)
);
end component;
component grfpwx
generic (fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/eth/comp/ethcomp.vhd
|
2
|
15187
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ethcomp is
component grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000"
);
end component;
component greth_gbitc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(8 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(8 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(8 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(8 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
component greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
component greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic
);
end component;
end package;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrctrl.vhd
|
2
|
33891
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrctrl
-- File: ddrctrl.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller with AMBA interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
use gaisler.ddrrec.all;
entity ddrctrl is
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 2; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 16; -- Allowed: 4, 8, 16
chipsize : integer := 256; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := virtex2;
clkperiod : integer := 10); -- (ns)
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end ddrctrl;
architecture rtl of ddrctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant DELAY_15600NS : integer := (15600 / clkperiod);
constant DELAY_7800NS : integer := (7800 / clkperiod);
constant DELAY_7_15600NS : integer := (7*(15600 / clkperiod));
constant DELAY_7_7800NS : integer := (7*(7800 / clkperiod));
constant DELAY_200US : integer := (200000 / clkperiod);
constant REVISION : integer := 0;
constant pmask : integer := 16#fff#;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant dqsize : integer := numchips*chipbits;
constant dmsize : integer := (dqsize/8);
constant strobesize : integer := (dqsize/8) * dmvector(chipbits);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal toAHB : two_ahb_ctrl_in_type;
signal fromAHB : two_ahb_ctrl_out_type;
signal fromAHB2Main : two_ahb_ctrl_out_type;
signal apbr : apb_reg_type;
signal apbri : apb_reg_type;
signal fromAPB : apb_ctrl_out_type;
signal fromAPB2Main : apb_ctrl_out_type;
signal mainr : main_reg_type;
signal mainri : main_reg_type;
signal fromMain : main_ctrl_out_type;
signal fromMain2APB : apb_ctrl_in_type;
signal fromMain2AHB : two_ahb_ctrl_in_type;
signal fromMain2HS : hs_in_type;
signal toHS : hs_in_type;
signal fromHS : hs_out_type;
begin -- achitecture rtl
-------------------------------------------------------------------------------
-- Error reports
assert (tech = virtex2 or tech = virtex4 or tech = lattice) report "Unsupported technology by DDR controller (generic tech)" severity failure;
assert (modbanks=1 or modbanks=2) report "Only 1 or 2 module banks is supported (generic modbanks)" severity failure;
assert (chipbits=4 or chipbits=8 or chipbits=16) report "DDR chips either have 4, 8 or 16 bits output (generic chipbits)" severity failure;
assert (chipsize=64 or chipsize=128 or chipsize=256 or chipsize=512 or chipsize=1024) report "DDR chips either have 64, 128, 256, 512 or 1024 Mbit size" severity failure;
assert (buffersize>=2) report "Buffer must have room for at least 2 bursts (generic buffersize)" severity failure;
assert (plldelay=0 or plldelay=1) report "Invalid setting for DDRRAM PLL delay (generic plldelay)" severity failure;
assert (numahb=1 or numahb=2) report "Only one or two AHB interfaces can be used (generic numahb)" severity failure;
-------------------------------------------------------------------------------
-- APB control
-- Controls APB bus. Contains the DDRCFG register. Clear memcmd
-- bits when a memory command requested on APB is complete.
apbcomb : process(apbr, apbsi, fromMain2APB, rst)
variable v : apb_reg_type;
begin
v:= apbr;
if rst = '0' then -- Reset
v.ddrcfg_reg := ddrcfg_reset;
elsif fromMain2APB.apb_cmd_done = '1' then -- Clear memcmd bits
v.ddrcfg_reg(28 downto 27) := "00";
elsif (apbsi.psel(pindex) and apbsi.penable and apbsi.pwrite) = '1' then -- Write
v.ddrcfg_reg := apbsi.pwdata(31 downto 1) & fromMain2APB.ready;
else
v.ddrcfg_reg(0) := fromMain2APB.ready;
end if;
apbri <= v;
fromAPB.ddrcfg_reg <= v.ddrcfg_reg;
end process apbcomb;
apbclk : process(pclk)
begin
if rising_edge(pclk) then apbr <= apbri; end if;
end process;
apbso.prdata <= fromAPB.ddrcfg_reg; apbso.pirq <= (others => '0');
apbso.pindex <= pindex; apbso.pconfig <= pconfig;
-------------------------------------------------------------------------------
-- Main controller
-------------------------------------------------------------------------------
maincomb : process(mainr, fromAHB, fromAHB2Main, fromAPB2Main, rst, fromHS)
variable v : main_reg_type;
begin
v := mainr; v.loadcmdbuffer := '0'; -- Clear Cmd loading bit
-------------------------------------------------------------------------------
-- DDRCFG control
-- Reads DDRCFG from APB controller. Handles refresh command from refresh
-- timer and memoory comand requested on APB.
case v.apbstate is
when idle =>
v.apb_cmd_done := '0';
-- Refresh timer signals refresh
if v.doRefresh = '1' and v.ddrcfg.refresh = '1' then
v.apbstate := refresh;
-- LMR cmd on APB bus
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) = "11" then
v.lockAHB := "11";
v.apbstate := wait_lmr1;
-- Refresh or Precharge cmd on APB BUS
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) > "00" then
v.apbstate := cmd;
-- Nothing to be done
else
v.ddrcfg.memcmd := "00";
end if;
-- Refresh from Timer
when refresh =>
if v.mainstate = idle then v.ddrcfg.memcmd := "10"; end if;
if v.dorefresh = '0' then v.ddrcfg.memcmd := "00"; v.apbstate := idle; end if;
-- Refresh or Precharge from APB BUS
when cmd =>
if v.mainstate = idle then v.ddrcfg.memcmd := fromAPB2Main.ddrcfg_reg(28 downto 27); end if;
v.apbstate := cmdDone;
-- Wait until no more cmd can arrive from AHB ctrl
when wait_lmr1 => v.apbstate := wait_lmr2;
when wait_lmr2 => v.apbstate := cmdlmr;
when cmdlmr =>
-- Check that no new R/W cmd is to be performed
if fromAHB2Main(0).rw_cmd_valid = v.rw_cmd_done(0) and
fromAHB2Main(1).rw_cmd_valid = v.rw_cmd_done(1) and v.mainstate = idle then
v.ddrcfg.memcmd := "11";
v.ddrcfg.cas := fromAPB2Main.ddrcfg_reg(30 downto 29);
v.ddrcfg.bl := fromAPB2Main.ddrcfg_reg(26 downto 25);
v.apbstate := cmdDone;
end if;
when cmdDone =>
v.lockAHB := "00";
if v.memCmdDone = '1' then
v.ddrcfg.memcmd := "00"; v.apb_cmd_done := '1'; v.apbstate := cmdDone2;
end if;
when cmdDone2 =>
if fromAPB2Main.ddrcfg_reg(28 downto 27) = "00" then
v.apb_cmd_done := '0'; v.apbstate := idle;
end if;
end case;
if v.mainstate = idle then
v.ddrcfg.refresh := fromAPB2Main.ddrcfg_reg(31);
v.ddrcfg.autopre := fromAPB2Main.ddrcfg_reg(24);
v.ddrcfg.r_predict := fromAPB2Main.ddrcfg_reg(23 downto 22);
v.ddrcfg.w_prot := fromAPB2Main.ddrcfg_reg(21 downto 20);
v.ddrcfg.ready := fromAPB2Main.ddrcfg_reg(0);
end if;
-------------------------------------------------------------------------------
-- Calcualtes burst length
case v.ddrcfg.bl is
when "00" => v.burstlength := 2;
when "01" => v.burstlength := 4;
when "10" => v.burstlength := 8;
when others => v.burstlength := 8;
end case;
-------------------------------------------------------------------------------
-- Calculates row and column address
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.coladdress := (others => (others => '0'));
v.tmpcolbits := 0; v.colbits := 0; v.rowbits := 0;
-- Based on the size of the chip its organization can be calculated
case chipsize is
when 64 => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 64Mbit
when 128 => v.tmpcolbits := 11; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 128Mbit
when 256 => v.tmpcolbits := 11; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 256Mbit
when 512 => v.tmpcolbits := 12; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 512Mbit
when 1024 => v.tmpcolbits := 12; v.rowbits := 14; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 1Gbit
when others => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- Others 64Mbit
end case;
case chipbits is
when 4 => v.colbits := v.tmpcolbits; -- x4 bits
when 8 => v.colbits := (v.tmpcolbits-1); -- x8 bits
when 16 => v.colbits := (v.tmpcolbits-2); -- x16 bits
when others => null;
end case;
v.addressrange := v.colbits + v.rowbits;
-- AHB controller 1 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(0)(i) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(0)(i-v.colbits) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(0)(i - v.addressrange) := fromAHB(0).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(0)(adrbits-1 downto 0) := v.intbankbits(0) &
v.tmpcoladdress(0)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(0)(9 downto 0); --Bit 9 to 0
v.rowaddress(0)(adrbits-1 downto (adrbits-2)) := v.intbankbits(0);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(0).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(0) := BANK0;
else
v.bankselect(0) := BANK1;
end if;
else
v.bankselect(0) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(0):= conv_integer(v.bankselect(0)(0) & v.rowaddress(0)(adrbits-1 downto (adrbits-2)));
-- AHB Controller 2 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(1)(i) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(1)(i-v.colbits) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(1)(i - v.addressrange) := fromAHB(1).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(1)(adrbits-1 downto 0) := v.intbankbits(1) &
v.tmpcoladdress(1)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(1)(9 downto 0); --Bit 9 to 0
v.rowaddress(1)(adrbits-1 downto (adrbits-2)) := v.intbankbits(1);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(1).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(1) := BANK0;
else
v.bankselect(1) := BANK1;
end if;
else
v.bankselect(1) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(1):= conv_integer(v.bankselect(1)(0) & v.rowaddress(1)(adrbits-1 downto (adrbits-2)));
-- ((1bit(Lower/upper half if 32 bit mode))) + 1bit(module bank select) +
-- 2bits(Chip bank selekt) + Xbits(address, depending on chip size)
-------------------------------------------------------------------------------
-- Calculate LMR command address
v.lmradr(adrbits-1 downto 7) := (others => '0');
-- CAS value
case v.ddrcfg.cas is
when "00" => v.lmradr(6 downto 4) := "010";
when "01" => v.lmradr(6 downto 4) := "110";
when "10" => v.lmradr(6 downto 4) := "011";
when others => v.lmradr(6 downto 4) := "010";
end case;
-- Burst type, seqencial or interleaved (fixed att seqencial)
v.lmradr(3) := '0';
-- Burst length
case v.ddrcfg.bl is
when "00" => v.lmradr(2 downto 0) := "001";
when "01" => v.lmradr(2 downto 0) := "010";
when "10" => v.lmradr(2 downto 0) := "011";
when others => v.lmradr(2 downto 0) := "010";
end case;
-------------------------------------------------------------------------------
-- Auto refresh timer
case v.timerstate is
when t1 =>
v.doRefresh := '0'; v.refreshcnt := v.refreshTime; v.timerstate := t2;
when t2 =>
v.doRefresh := '0'; v.refreshcnt := mainr.refreshcnt -1;
if v.refreshcnt < 50 then v.timerstate := t3; end if;
when t3 =>
if mainr.refreshcnt > 1 then v.refreshcnt := mainr.refreshcnt -1; end if;
v.doRefresh := '1';
if v.refreshDone = '1' then
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
v.timerstate := t4;
end if;
when t4 =>
v.doRefresh := '0'; v.timerstate := t2; when others => null;
end case;
-------------------------------------------------------------------------------
-- Init statemachine
case v.initstate is
when idle =>
v.memInitDone := '0';
if v.doMemInit = '1' then
if plldelay = 1 then
-- Using refrshtimer for initial wait
v.refreshcnt := DELAY_200US +50; v.timerstate := t2; v.initstate := i1;
else v.initstate := i2; end if;
end if;
when i1 =>
if v.doRefresh = '1' then v.initstate := i2; end if;
when i2 =>
v.cs := "00";
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_NOP; v.loadcmdbuffer := '1'; v.initstate := i3;
end if;
when i3 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i4;
end if;
when i4 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1';
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := "01";
v.adrbufferdata((adrbits -3) downto 0) := (others => '0');
v.initstate := i5;
end if;
when i5 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.refreshcnt := 250; v.timerstate := t2; --200 cycle count
v.adrbufferdata(8) := '1'; v.initstate := i6;
end if;
when i6 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i7;
end if;
when i7 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i8;
end if;
when i8 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i9;
end if;
when i9 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.initstate := i10;
end if;
when i10 =>
if v.doRefresh = '1' then v.initstate := i11; end if;
when i11 =>
v.memInitDone := '1';
if v.doMemInit = '0' then v.initstate := idle; end if;
when others => null;
end case;
-------------------------------------------------------------------------------
-- Main controller statemachine
case v.mainstate is
-- Initialize memory
when init =>
v.doMemInit := '1';
v.ready := '0';
if v.memInitDone = '1' then
v.mainstate := idle;
end if;
-- Await command
when idle =>
v.doMemInit := '0';
v.RefreshDone := '0';
v.memCmdDone := '0';
v.ready := '1';
v.use_bl := mainr.burstlength;
v.use_cas := mainr.ddrcfg.cas;
if v.ddrcfg.memcmd /= "00" then
v.mainstate := c1;
elsif fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) or
fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) then
-- This code is to add read priority between the ahb controllers
-- if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) and
-- fromAHB(0).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 0;
-- v.use_buf := v.rw_cmd_done(0)+1;
-- elsif fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) and
-- fromAHB(1).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 1;
-- v.use_buf := v.rw_cmd_done(1)+1;
if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) then
v.use_ahb := 0;
v.use_buf := v.rw_cmd_done(0)+1;
else
v.use_ahb := 1;
v.use_buf := v.rw_cmd_done(1)+1;
end if;
-- Check if the chip bank which is to be R/W has a row open
if mainr.pre_chg(v.pre_bankadr(v.use_ahb)) = '1' then
-- Check if the row which is open is the same that will be R/W
if mainr.pre_row(v.pre_bankadr(v.use_ahb)) = v.rowaddress(v.use_ahb) then
v.mainstate := rw;
-- R/W to a different row then the one open, has to precharge and
-- activate new row
else
v.mainstate := pre1;
end if;
-- No row open, has to activate row
else
v.mainstate := act1;
end if;
end if;
-- Nothing to do, if 10 idle cycles, run Refreash (if needed)
if v.idlecnt = 10 and v.refreshcnt < v.maxRefreshTime then
v.doRefresh := '1';
v.idlecnt := 0;
v.timerstate := t3;
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
elsif v.idlecnt = 10 then
v.idlecnt := 0;
else
v.idlecnt := mainr.idlecnt + 1;
end if;
-- Precharge memory
when pre1 =>
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
-- Select chip bank to precharge
v.adrbufferdata := (others => '0');
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := v.rowaddress(mainr.use_ahb)(adrbits-1 downto (adrbits-2));
v.cmdbufferdata := CMD_PRE;
-- Clear bit in register for active rows
v.pre_chg(v.pre_bankadr(mainr.use_ahb)):= '0';
v.loadcmdbuffer := '1';
v.mainstate := act1;
end if;
-- Activate row in memory
when act1 => -- Get adr and cmd from AHB, set to HS
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
v.cmdbufferdata := CMD_ACTIVE;
v.adrbufferdata := v.rowaddress(mainr.use_ahb);
v.loadcmdbuffer := '1';
-- Set bit in register for active row if auto-precharge is disabled
if v.ddrcfg.autopre = '0' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '1';
v.pre_row(v.pre_bankadr(mainr.use_ahb)) := v.rowaddress(mainr.use_ahb);
end if;
v.mainstate := rw;
end if;
-- Issu read or write to HS part
when rw =>
if fromAHB(mainr.use_ahb).asramso.dataout(ahbadr) = '1' then
v.cmdbufferdata := CMD_WRITE;
else
v.cmdbufferdata := CMD_READ;
end if;
if v.ddrcfg.autopre = '1' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '0';
end if;
v.adrbufferdata := v.coladdress(mainr.use_ahb);
v.cs := v.bankselect(mainr.use_ahb);
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
if fromAHB2Main(mainr.use_ahb).w_data_valid /= v.rw_cmd_done(mainr.use_ahb) then
v.loadcmdbuffer := '1';
v.rw_cmd_done(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.sync2_adr(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.mainstate := idle;
end if;
end if;
-- Issue prechare, auto refresh or LMR to HS part
when c1 =>
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
v.cs := BANK01;
case v.ddrcfg.memCmd is
when "01" => -- Precharge all
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.memCmdDone := '1';
v.mainstate := c2;
when "10" => -- AutoRefresh
-- All banks have to be precharged before AR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_AR;
v.memCmdDone := '1';
v.mainstate := c2;
v.refreshDone := '1';
else -- Run Precharge, and let AR begin when finished
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when "11" => -- LMR
-- All banks have to be precharged before LMR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_LMR;
v.adrbufferdata := v.lmradr;
v.memCmdDone := '1';
v.mainstate := c2;
else
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when others => null;
end case;
v.loadcmdbuffer := '1';
end if;
when c2 =>
if v.ddrcfg.memCmd = "00" then
v.refreshDone := '0';
v.mainstate := idle;
end if;
when others =>
v.mainstate := init;
end case;
-- Reset
if rst = '0' then
-- Main controller
v.mainstate := init;
v.loadcmdbuffer := '0';
v.cmdbufferdata := CMD_NOP;
v.adrbufferdata := (others => '0');
v.use_ahb := 0;
v.use_bl := 4;
v.use_cas := "00";
v.use_buf := (others => '1');
v.burstlength := 8;
v.rw_cmd_done := (others => (others => '1'));
v.lmradr := (others => '0');
v.memCmdDone := '0';
v.lockAHB := "00";
v.pre_row := (others => (others => '0'));
v.pre_chg := (others => '0');
v.pre_bankadr := (0,0);
v.sync2_adr := (others =>(others => '0'));
-- For init statemachine
v.initstate := idle;
v.doMemInit := '0';
v.memInitDone := '0';
v.initDelay := 0;
v.cs := "11";
-- For address calculator
v.coladdress := (others => (others => '0'));
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.addressrange := 0;
v.tmpcolbits := 0;
v.colbits := 0;
v.rowbits := 0;
v.bankselect := ("11","11");
v.intbankbits := ("00","00");
-- For refresh timer statemachine
v.timerstate := t2;
v.doRefresh := '0';
v.refreshDone := '0';
v.refreshTime := 0;
v.maxRefreshTime := 0;
v.idlecnt := 0;
v.refreshcnt := DELAY_200us;
-- For DDRCFG register
v.apbstate := idle;
v.apb_cmd_done := '0';
v.ready := '0';
v.ddrcfg := (ddrcfg_reset(31),ddrcfg_reset(30 downto 29),ddrcfg_reset(28 downto 27),
ddrcfg_reset(26 downto 25),ddrcfg_reset(24),ddrcfg_reset(23 downto 22),
ddrcfg_reset(21 downto 20),'0');
end if;
-- Set output signals
mainri <= v;
fromMain.hssi.bl <= v.use_bl;
fromMain.hssi.ml <= fromAHB(mainr.use_ahb).burst_dm(conv_integer(mainr.use_buf));
fromMain.hssi.cas <= v.use_cas;
fromMain.hssi.buf <= v.use_buf;
fromMain.hssi.ahb <= v.use_ahb;
fromMain.hssi.cs <= v.cs;
fromMain.hssi.cmd <= v.cmdbufferdata;
fromMain.hssi.cmd_valid <= v.loadcmdbuffer;
fromMain.hssi.adr <= v.adrbufferdata;
fromMain.ahbctrlsi(0).burstlength <= v.burstlength;
fromMain.ahbctrlsi(1).burstlength <= v.burstlength;
fromMain.ahbctrlsi(0).r_predict <= v.ddrcfg.r_predict(0);
fromMain.ahbctrlsi(1).r_predict <= v.ddrcfg.r_predict(1);
fromMain.ahbctrlsi(0).w_prot <= v.ddrcfg.w_prot(0);
fromMain.ahbctrlsi(1).w_prot <= v.ddrcfg.w_prot(1);
fromMain.ahbctrlsi(0).locked <= v.lockAHB(0);
fromMain.ahbctrlsi(1).locked <= v.lockAHB(1);
fromMain.ahbctrlsi(0).asramsi.raddress <= v.sync2_adr(0);
fromMain.ahbctrlsi(1).asramsi.raddress <= v.sync2_adr(1);
fromMain.apbctrlsi.apb_cmd_done <= v.apb_cmd_done;
fromMain.apbctrlsi.ready <= v.ready;
end process;
--Main clocked register
mainclk : process(clk0)
begin
if rising_edge(clk0) then
mainr <= mainri;
-- Register to sync between different clock domains
fromAPB2Main.ddrcfg_reg <= fromAPB.ddrcfg_reg;
-- Makes signals from main to AHB, ABP, HS registerd
fromMain2AHB <= fromMain.ahbctrlsi;
fromMain2APB <= fromMain.apbctrlsi;
fromMain2HS <= fromMain.hssi;
end if;
end process;
-- Sync of incoming data valid signals from AHB
-- Either if separate clock domains or if syncram_2p
-- doesn't support write through (write first)
a1rt : if ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip1 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end if;
end process;
end generate;
arf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end generate;
a2rt : if ahb2sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip2 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end if;
end process;
end generate;
a2rf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end generate;
-------------------------------------------------------------------------------
-- High speed interface (Physical layer towards memory)
-------------------------------------------------------------------------------
D0 : hs
generic map(
tech => tech,
dqsize => dqsize,
dmsize => dmsize,
strobesize => strobesize,
clkperiod => clkperiod)
port map(
rst => rst,
clk0 => clk0,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
hclk => pclk,
hssi => toHS,
hsso => fromHS);
A0 : ahb_slv
generic map(
hindex => hindex1,
haddr => haddr1,
hmask => hmask1,
sepclk => ahb1sepclk,
dqsize => dqsize,
dmsize => dmsize,
tech => tech)
port map (
rst => rst,
hclk => hclk1,
clk0 => clk0,
csi => toAHB(0),
cso => fromAHB(0));
B1: if numahb = 2 generate
A1 : ahb_slv
generic map(
hindex => hindex2,
haddr => haddr2,
hmask => hmask2,
sepclk => ahb2sepclk,
dqsize => dqsize,
dmsize => dmsize)
port map (
rst => rst,
hclk => hclk2,
clk0 => clk0,
csi => toAHB(1),
cso => fromAHB(1));
end generate;
B2 : if numahb /= 2 generate
fromAHB(1).rw_cmd_valid <= (others => '1');
end generate;
-------------------------------------------------------------------------------
-- Mapping signals
-- Signals to HS
toHS.bl <= fromMain.hssi.bl;
toHS.ml <= fromMain.hssi.ml;
toHS.cas <= fromMain.hssi.cas;
toHS.buf <= fromMain.hssi.buf;
toHS.ahb <= fromMain.hssi.ahb;
toHS.cs <= fromMain.hssi.cs;
toHS.adr <= fromMain.hssi.adr;
toHS.cmd <= fromMain.hssi.cmd;
toHS.cmd_valid <= fromMain.hssi.cmd_valid;
toHS.dsramso(0) <= fromAHB(0).dsramso;
toHS.dsramso(1) <= fromAHB(1).dsramso;
toHS.ddso <= ddso;
-- Signals to AHB ctrl 1
toAHB(0).ahbsi <= ahb1si;
toAHB(0).asramsi <= fromMain.ahbctrlsi(0).asramsi;
toAHB(0).dsramsi <= fromHS.dsramsi(0);
toAHB(0).burstlength <= fromMain2AHB(0).burstlength;
toAHB(0).r_predict <= fromMain2AHB(0).r_predict;
toAHB(0).w_prot <= fromMain2AHB(0).w_prot;
toAHB(0).locked <= fromMain2AHB(0).locked;
toAHB(0).rw_cmd_done <= fromHS.cmdDone(0);
-- Signals to AHB ctrl 2
toAHB(1).ahbsi <= ahb2si;
toAHB(1).asramsi <= fromMain.ahbctrlsi(1).asramsi;
toAHB(1).dsramsi <= fromHS.dsramsi(1);
toAHB(1).burstlength <= fromMain2AHB(1).burstlength;
toAHB(1).r_predict <= fromMain2AHB(1).r_predict;
toAHB(1).w_prot <= fromMain2AHB(1).w_prot;
toAHB(1).locked <= fromMain2AHB(1).locked;
toAHB(1).rw_cmd_done <= fromHS.cmdDone(1);
-- Ouput signals
ahb1so <= fromAHB(0).ahbso;
ahb2so <= fromAHB(1).ahbso;
ddsi <= fromHS.ddsi;
end rtl;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/memctrl/ssrctrl.in.vhd
|
6
|
134
|
-- SSRAM controller
constant CFG_SSCTRL : integer := CONFIG_SSCTRL;
constant CFG_SSCTRLP16 : integer := CONFIG_SSCTRL_PROM16;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitrace.vhd
|
2
|
7635
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
|
mit
|
lxp32/lxp32-cpu
|
verify/lxp32/src/platform/scrambler.vhd
|
2
|
1187
|
---------------------------------------------------------------------
-- Scrambler
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Generates a pseudo-random binary sequence using a Linear-Feedback
-- Shift Register (LFSR).
--
-- In order to generate a maximum-length sequence, 1+x^TAP1+x^TAP2
-- must be a primitive polynomial. Typical polynomials include:
-- (6,7), (9,11), (14,15).
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity scrambler is
generic(
TAP1: integer;
TAP2: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
d_o: out std_logic
);
end entity;
architecture rtl of scrambler is
signal reg: std_logic_vector(TAP2 downto 1):=(others=>'1');
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
reg<=(others=>'1');
elsif ce_i='1' then
reg<=reg(TAP2-1 downto 1)&(reg(TAP2) xor reg(TAP1));
end if;
end if;
end process;
d_o<=reg(1);
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gleichmann/spi/spi_oc.vhd
|
2
|
4968
|
--------------------------------------------------------------------
-- Entity: SPI_OC
-- File: spi_oc.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
--
-- Description: VHDL wrapper for the Opencores SPI core with APB
-- interface
--------------------------------------------------------------------
-- CVS Entries:
-- $Date: 2006/12/04 14:44:05 $
-- $Author: tame $
-- $Log: spi_oc.vhd,v $
-- Revision 1.3 2006/12/04 14:44:05 tame
-- Changed interrupt output to LEON from a level (that is active until it is reset) to
-- a short pulse.
--
-- Revision 1.1 2006/11/17 12:28:56 tame
-- Added SPI files: Simple SPI package and a wrapper for the (modified)
-- OpenCores Simple SPI Core with APB interface.
--
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
library gleichmann;
use gleichmann.ocrcomp.all;
use gleichmann.sspi.all;
library opencores;
use opencores.occomp.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity spi_oc is
generic (
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0 -- Leon-IRQ
);
port (
rstn : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
spi_in : in spi_in_type; -- MultIO-Inputs
spi_out : out spi_out_type -- Spi-Outputs
);
end entity spi_oc;
architecture implementation of spi_oc is
constant data_width : integer := 8;
constant address_width : integer := 3;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_SPIOC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
signal irq : std_ulogic;
signal irq_1t : std_ulogic;
signal irq_adapt : std_ulogic; -- registered and converted to rising edge activity
begin
simple_spi_top_1 : simple_spi_top
port map (
prdata_o => apbo.prdata(data_width-1 downto 0),
pirq_o => irq,
sck_o => spi_out.sck,
mosi_o => spi_out.mosi,
ssn_o => spi_out.ssn,
pclk_i => clk,
prst_i => rstn,
psel_i => apbi.psel(pindex),
penable_i => apbi.penable,
paddr_i => apbi.paddr(address_width+1 downto 2), -- 32-bit addresses
pwrite_i => apbi.pwrite,
pwdata_i => apbi.pwdata(data_width-1 downto 0),
miso_i => spi_in.miso);
-- drive selected interrupt, remaining bits with zeroes
apbo.pirq(NAHBIRQ-1 downto pirq+1) <= (others => '0');
-- apbo.pirq(pirq) <= irq; -- corrected by MH, 28.11.2006
apbo.pirq(pirq) <= irq_adapt;
apbo.pirq(pirq-1 downto 0) <= (others => '0');
-- drive unused data bits with don't cares
apbo.prdata(31 downto data_width) <= (others => '0');
-- drive index for diagnostic use
apbo.pindex <= pindex;
-- drive slave configuration
apbo.pconfig <= pconfig;
---------------------------------------------------------------------------------------
-- Synchronous process to convert the high level interrupt from the core to
-- to an rising edge triggered interrupt to be suitable for the Leon IRQCTL
-- asynchronous low active reset like the open core simple SPI module !!!
---------------------------------------------------------------------------------------
irq_adaption: process (clk, rstn) -- added by MH, 28.11.2006
begin -- process irq_adaption)
if rstn = '0' then
irq_adapt <= '0';
irq_1t <= '0';
elsif clk'event and clk = '1' then
irq_1t <= irq;
irq_adapt <= irq and not irq_1t;
end if;
end process irq_adaption;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
assert (pirq < 15 and pirq > 0 ) report
"Simple SPI Controller interrupt warning: " &
"0 does not exist, 15 is unmaskable, 16 to 31 are unused"
severity warning;
bootmsg : report_version
generic map ("SPI_OC: Simple SPI Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq) &
", APB slave " & tost(pindex));
-- pragma translate_on
end architecture implementation;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/unisim/usbhc_unisim.vhd
|
1
|
19559
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_unisim
-- File: usbhc_unisim.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for unisim/xilinx usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.all;
library techmap;
use techmap.usbhc_unisimpkg.all;
entity usbhc_unisim is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_unisim;
architecture rtl of usbhc_unisim is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_unisimpkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_unisimpkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_unisim_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_unisim_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_unisim_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_unisim_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination " &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_dma_fifo.vhd
|
2
|
5537
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atahost_dma_fifo
-- File: atahost_dma_fifo.vhd
-- Author: Erik Jagre - Gaisler Research
-- Description: Generic FIFO, based on syncram in grlib
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity atahost_dma_fifo is
generic(tech : integer:=0; abits : integer:=3;
dbits : integer:=32; depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0');
end;
architecture rtl of atahost_dma_fifo is
type state_type is (full_state, empty_state, idle_state);
type reg_type is record
state : state_type;
level : integer range 0 to depth;
aw : integer range 0 to depth;
ar : integer range 0 to depth;
data_o : std_logic_vector(dbits-1 downto 0);
rd : std_logic;
wr : std_logic;
erd : std_logic;
ewr : std_logic;
reset : std_logic;
adr : std_logic_vector(abits-1 downto 0);
end record;
constant zerod : std_logic_vector(dbits-1 downto 0) := (others => '0');
constant zeroa : std_logic_vector(abits-1 downto 0) := (others => '0');
constant RESET_VECTOR : reg_type := (empty_state,0,0,0,
zerod,'0','0','0','0','0', zeroa);
signal r,ri : reg_type;
signal s_ram_adr : std_logic_vector(abits-1 downto 0);
begin
-- comb:process(write_enable, read_enable, data_in,reset, r) Erik 2007-02-08
comb:process(write_enable, read_enable, reset, r)
variable v : reg_type;
variable vfull, vempty : std_logic;
begin
v:=r;
v.wr:=write_enable; v.rd:=read_enable; v.reset:=reset;
case r.state is
when full_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.ewr:='1'; v.state:=full_state;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if r.aw=v.ar then v.state:=empty_state;
else v.state:=idle_state; end if;
v.ewr:='0';
end if;
when empty_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.aw=r.ar then v.state:=full_state;
else v.state:=idle_state; end if;
v.erd:='0';
elsif write_enable='0' and read_enable='1' and reset='0' then
v.erd:='1'; v.state:=empty_state;
end if;
when idle_state=>
if write_enable='1' and read_enable='0' and reset='0' then
v.adr:=conv_std_logic_vector(r.aw,abits);
if r.aw=depth-1 then v.aw:=0; else v.aw:=r.aw+1; end if;
v.level:=r.level+1;
if v.level=depth then v.state:=full_state;
else v.state:=idle_state; end if;
elsif write_enable='0' and read_enable='1' and reset='0' then
v.adr:=conv_std_logic_vector(r.ar,abits);
if r.ar=depth-1 then v.ar:=0; else v.ar:=r.ar+1; end if;
v.level:=r.level-1;
if v.level=0 then v.state:=empty_state;
else v.state:=idle_state; end if;
end if;
end case;
if r.level=0 then vempty:='1'; vfull:='0';
elsif r.level=depth then vempty:='0'; vfull:='1';
else vempty:='0'; vfull:='0'; end if;
--reset logic
if (reset='1') then v:=RESET_VECTOR; end if;
ri<=v;
s_ram_adr<=v.adr;
--assigning outport
write_error<=v.ewr; read_error<=v.erd; level<=v.level;
empty<=vempty; full<=vfull;
end process;
ram : syncram
generic map(tech=>tech, abits=>abits, dbits=>dbits)
port map (
clk => clk,
address => s_ram_adr,
datain => data_in,
dataout => data_out,
enable => read_enable,
write => write_enable
);
sync:process(clk) --Activate on clock & reset
begin
if clk'event and clk='1' then r<=ri; end if;
end process;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/leon3/cachemem.vhd
|
2
|
18464
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of cachemem is
constant DSNOOPMMU : boolean := (dsnoop > 3);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+--------+-----+-------+
-- | LRR | LOCK_BIT | MMUCTX | TAG | VALID |
-- +-----+----------+--------+-----+-------+
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + isetlock + MMUCTX_BITS;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + dsetlock + MMUCTX_BITS;
constant IDWIDTH : natural := 32;
constant DDWIDTH : natural := 32;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH-1 downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH-1 downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : cdatatype;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(crami, dtdataout2, dtdataout3)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : cdatatype;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)((DTWIDTH - (DLRR_BIT+dsetlock+1)) downto (DTWIDTH - (DLRR_BIT+dsetlock+M_CTX_SZ))) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTWIDTH-(DCLOCK_BIT + dsetlock)) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
vdtdatain(i)(DTWIDTH-DLRR_BIT) := crami.dcramin.tag(i)(CTAG_LRRPOS);
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (DSETS > 1) and (crami.dcramin.flush = '1') then
vdtdatain(i)(dlinesize+1 downto dlinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
vdtdatain2 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
if (DSETS > 1) then
vdtdatain2(i)(dlinesize+1 downto dlinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
vdddatain := crami.dcramin.data;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)((ITWIDTH - (ILRR_BIT+isetlock+1)) downto (ITWIDTH - (ILRR_BIT+isetlock+M_CTX_SZ))) := crami.icramin.ctx;
end if;
vitdatain(i)(ITWIDTH-(ICLOCK_BIT + isetlock)) := crami.icramin.tag(i)(CTAG_LOCKPOS);
vitdatain(i)(ITWIDTH-ILRR_BIT) := crami.icramin.tag(i)(CTAG_LRRPOS);
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW) & crami.icramin.tag(i)(ilinesize-1 downto 0);
if (ISETS > 1) and (crami.icramin.flush = '1') then
vitdatain(i)(ilinesize+1 downto ilinesize) := conv_std_logic_vector(i,2);
end if;
end loop;
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dtdatain3 <= vdtdatain3; dtdatainu <= vdtdatainu; dddatain <= vdddatain;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i));
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i));
end generate;
ind0 : for i in ISETS to MAXSETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i));
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if ((MMUEN = 0) or not DSNOOPMMU) generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i));
end generate;
end generate;
mdt1 : if not ((MMUEN = 0) or not DSNOOPMMU) generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i));
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_BITS) port map (
clk, dtaddr, dtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i));
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
dtdataout3(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i));
end generate;
dnd0 : for i in DSETS to MAXSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dtdataout3(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dtdataout3(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITWIDTH - (1+ICLOCK_BIT));
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITWIDTH-1);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)((ITWIDTH - (ILRR_BIT+ICLOCK_BIT+1)) downto (ITWIDTH - (ILRR_BIT+ICLOCK_BIT+M_CTX_SZ)));
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
--(DTWIDTH-1-(DLRR_BIT+DCLOCK_BIT) downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-(DLRR_BIT+DCLOCK_BIT)-1);
--cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTWIDTH-1-(DLRR_BIT+DCLOCK_BIT) downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-(DLRR_BIT+DCLOCK_BIT)-1);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTWIDTH - (1+DCLOCK_BIT));
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTWIDTH-1);
ictx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)((DTWIDTH - (DLRR_BIT+DCLOCK_BIT+1)) downto (DTWIDTH - (DLRR_BIT+DCLOCK_BIT+M_CTX_SZ)));
end generate;
stagv : if not ((MMUEN = 0) or not DSNOOPMMU) generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
end generate;
stagp : if ((MMUEN = 0) or not DSNOOPMMU) generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
end generate;
-- cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTWIDTH-1 downto DTWIDTH-(TAG_HIGH-DTAG_LOW)-1);
cramo.dcramo.stag(i)(dlinesize-1 downto 0) <= dtdataout2(i)(dlinesize-1 downto 0);
cramo.dcramo.stag(i)(CTAG_LRRPOS) <= dtdataout2(i)(DTWIDTH - (1+DCLOCK_BIT));
cramo.dcramo.stag(i)(CTAG_LOCKPOS) <= dtdataout2(i)(DTWIDTH-1);
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
cramo.dcramo.stag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
cramo.dcramo.stag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
end generate;
nodrv : for i in 0 to MAXSETS-1 generate
cramo.dcramo.tpar(i) <= (others => '0');
cramo.dcramo.dpar(i) <= (others => '0');
cramo.dcramo.spar(i) <= '0';
cramo.icramo.tpar(i) <= (others => '0');
cramo.icramo.dpar(i) <= (others => '0');
nommu : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
end generate;
end ;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/altera_mf/simprims/altera_mf_components.vhd
|
2
|
90634
|
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
----------------------------------------------------------------------------
-- ALtera Megafunction Component Declaration File
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package altera_mf_components is
-- pragma translate_off
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component altcam
generic (
width : natural := 1;
widthad : natural := 1;
numwords : natural := 1;
lpm_file : string := "UNUSED";
lpm_filex : string := "UNUSED";
match_mode : string := "MULTIPLE";
output_reg : string := "UNREGISTERED";
output_aclr : string := "ON";
pattern_reg : string := "INCLOCK";
pattern_aclr : string := "ON";
wraddress_aclr : string := "ON";
wrx_reg : string := "INCLOCK";
wrx_aclr : string := "ON";
wrcontrol_aclr : string := "ON";
use_eab : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcam" );
port (
pattern : in std_logic_vector(width-1 downto 0);
wrx : in std_logic_vector(width-1 downto 0) := (others => 'Z');
wrxused : in std_logic := '1';
wrdelete : in std_logic := '0';
wraddress : in std_logic_vector(widthad-1 downto 0);
wren : in std_logic;
inclock : in std_logic;
inclocken : in std_logic := '1';
inaclr : in std_logic := '0';
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
outaclr : in std_logic := '0';
mstart : in std_logic := 'X';
mnext : in std_logic := '0';
maddress : out std_logic_vector(widthad-1 downto 0);
mbits : out std_logic_vector(numwords-1 downto 0);
mfound : out std_logic;
mcount : out std_logic_vector(widthad-1 downto 0);
rdbusy : out std_logic;
wrbusy : out std_logic );
end component;
component altclklock
generic (
inclock_period : natural := 10000; -- units in ps
inclock_settings : string := "UNUSED";
valid_lock_cycles : natural := 5;
invalid_lock_cycles : natural := 5;
valid_lock_multiplier : natural := 5;
invalid_lock_multiplier : natural := 5;
operation_mode : string := "NORMAL";
clock0_boost : natural := 1;
clock0_divide : natural := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay : string := "0";
clock1_boost : natural := 1;
clock1_divide : natural := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay : string := "0";
clock2_boost : natural := 1;
clock2_divide : natural := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay : string := "0";
clock_ext_boost : natural := 1;
clock_ext_divide : natural := 1;
clock_ext_settings : string := "UNUSED";
clock_ext_time_delay : string := "0";
outclock_phase_shift : natural := 0; -- units in ps
intended_device_family : string := "APEX20KE" ;
lpm_hint : string := "UNUSED";
lpm_type : string := "altclklock" );
port(
inclock : in std_logic; -- required port, input reference clock
inclocken : in std_logic := '1'; -- PLL enable signal
fbin : in std_logic := '1'; -- feedback input for the PLL
clock0 : out std_logic; -- clock0 output
clock1 : out std_logic; -- clock1 output
clock2 : out std_logic; -- clock2 output, for Mercury only
clock_ext : out std_logic; -- external clock output, for Mercury only
locked : out std_logic ); -- PLL lock signal
end component;
component altlvds_rx
generic (
number_of_channels : natural;
deserialization_factor : natural;
inclock_boost : natural:= 0;
registered_output : string := "ON";
inclock_period : natural;
cds_mode : string := "UNUSED";
intended_device_family : string := "APEX20KE";
input_data_rate : natural:= 0;
inclock_data_alignment : string := "EDGE_ALIGNED";
registered_data_align_input : string :="ON";
common_rx_tx_pll : string :="ON";
enable_dpa_mode : string := "OFF";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror : string := "OFF";
use_coreclock_input : string := "OFF";
dpll_lock_count : natural:= 0;
dpll_lock_window : natural:= 0;
outclock_resource : string := "AUTO";
data_align_rollover : natural := 10;
lose_lock_on_one_change : string := "OFF";
reset_fifo_at_first_lock : string := "ON";
use_external_pll : string := "OFF";
implement_in_les : string := "OFF";
buffer_implementation : string := "RAM";
port_rx_data_align : string := "PORT_CONNECTIVITY";
pll_operation_mode : string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift : string := "ON";
rx_align_data_reg : string := "RISING_EDGE";
inclock_phase_shift : integer := 0;
enable_soft_cdr_mode : string := "OFF";
sim_dpa_output_clock_phase_shift : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
clk_src_is_pll : string := "off" );
port (
rx_in : in std_logic_vector(number_of_channels-1 downto 0);
rx_inclock : in std_logic := '0';
rx_syncclock : in std_logic := '0';
rx_readclock : in std_logic := '0';
rx_enable : in std_logic := '1';
rx_deskew : in std_logic := '0';
rx_pll_enable : in std_logic := '1';
rx_data_align : in std_logic := '0';
rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
pll_areset : in std_logic := '0';
rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
rx_outclock : out std_logic;
rx_locked : out std_logic;
rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altlvds_tx
generic (
number_of_channels : natural;
deserialization_factor : natural:= 4;
inclock_boost : natural := 0;
outclock_divide_by : positive:= 1;
registered_input : string := "ON";
multi_clock : string := "OFF";
inclock_period : natural;
center_align_msb : string := "UNUSED";
intended_device_family : string := "APEX20KE";
output_data_rate : natural:= 0;
outclock_resource : string := "AUTO";
common_rx_tx_pll : string := "ON";
inclock_data_alignment : string := "EDGE_ALIGNED";
outclock_alignment : string := "EDGE_ALIGNED";
use_external_pll : string := "OFF";
implement_in_les : STRING := "OFF";
preemphasis_setting : natural := 0;
vod_setting : natural := 0;
differential_drive : natural := 0;
outclock_multiply_by : natural := 1;
coreclock_divide_by : natural := 2;
outclock_duty_cycle : natural := 50;
inclock_phase_shift : integer := 0;
outclock_phase_shift : integer := 0;
use_no_phase_shift : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_tx";
clk_src_is_pll : string := "off" );
port (
tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
tx_inclock : in std_logic := '0';
tx_syncclock : in std_logic := '0';
tx_enable : in std_logic := '1';
sync_inclock : in std_logic := '0';
tx_pll_enable : in std_logic := '1';
pll_areset : in std_logic := '0';
tx_out : out std_logic_vector(number_of_channels-1 downto 0);
tx_outclock : out std_logic;
tx_coreclock : out std_logic;
tx_locked : out std_logic );
end component;
component altdpram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
ram_block_type : string := "AUTO";
width_byteena : natural := 1;
byte_size : natural := 5;
read_during_write_mode_mixed_ports : string := "DONT_CARE";
intended_device_family : string := "APEX20KE";
lpm_type : string := "altdpram" );
port(
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0) );
end component;
component alt3pram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "OFF";
write_reg : string := "UNREGISTERED";
write_aclr : string := "OFF";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a : string := "OFF";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b : string := "OFF";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a : string := "OFF";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b : string := "OFF";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OFF";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OFF";
intended_device_family : string := "APEX20KE";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram" );
port (
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad-1 downto 0);
rdaddress_b : in std_logic_vector(widthad-1 downto 0);
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
qa : out std_logic_vector(width-1 downto 0);
qb : out std_logic_vector(width-1 downto 0) );
end component;
component altqpram
generic (
operation_mode : string := "QUAD_PORT";
width_write_a : natural := 1;
widthad_write_a : natural := 1;
numwords_write_a : natural := 0; -- default = 2^widthad_write_a
indata_reg_a : string := "INCLOCK_A";
indata_aclr_a : string := "INACLR_A";
wrcontrol_wraddress_reg_a : string := "INCLOCK_A";
wrcontrol_aclr_a : string := "INACLR_A";
wraddress_aclr_a : string := "INACLR_A";
width_write_b : natural := 1; -- default = width_write_a
widthad_write_b : natural := 1; -- default = widthad_write_a
numwords_write_b : natural := 0; -- default = 2^widthad_write_b
indata_reg_b : string := "INCLOCK_B";
indata_aclr_b : string := "INACLR_B";
wrcontrol_wraddress_reg_b : string := "INCLOCK_B";
wrcontrol_aclr_b : string := "INACLR_B";
wraddress_aclr_b : string := "INACLR_B";
width_read_a : natural := 1;
widthad_read_a : natural := 1;
numwords_read_a : natural := 0; -- default = 2^widthad_read_a
rdcontrol_reg_a : string := "OUTCLOCK_A";
rdcontrol_aclr_a : string := "OUTACLR_A";
rdaddress_reg_a : string := "OUTCLOCK_A";
rdaddress_aclr_a : string := "OUTACLR_A";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OUTACLR_A";
width_read_b : natural := 1; -- default = width_read_a
widthad_read_b : natural := 1; -- default = widthad_read_a
numwords_read_b : natural := 0; -- default = 2^widthad_read_b
rdcontrol_reg_b : string := "OUTCLOCK_B";
rdcontrol_aclr_b : string := "OUTACLR_B";
rdaddress_reg_b : string := "OUTCLOCK_B";
rdaddress_aclr_b : string := "OUTACLR_B";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OUTACLR_B";
init_file : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altqpram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
data_a : in std_logic_vector(width_write_a-1 downto 0) := (OTHERS => '0');
data_b : in std_logic_vector(width_write_b-1 downto 0) := (OTHERS => '0');
wraddress_a : in std_logic_vector(widthad_write_a-1 downto 0) := (OTHERS => '0');
wraddress_b : in std_logic_vector(widthad_write_b-1 downto 0) := (OTHERS => '0');
inclock_a : in std_logic := '0';
inclock_b : in std_logic := '0';
inclocken_a : in std_logic := '1';
inclocken_b : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad_read_a-1 downto 0) := (OTHERS => '0');
rdaddress_b : in std_logic_vector(widthad_read_b-1 downto 0) := (OTHERS => '0');
outclock_a : in std_logic := '0';
outclock_b : in std_logic := '0';
outclocken_a : in std_logic := '1';
outclocken_b : in std_logic := '1';
inaclr_a : in std_logic := '0';
inaclr_b : in std_logic := '0';
outaclr_a : in std_logic := '0';
outaclr_b : in std_logic := '0';
q_a : out std_logic_vector(width_read_a-1 downto 0);
q_b : out std_logic_vector(width_read_b-1 downto 0) );
end component;
component scfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
intended_device_family : string := "NON_STRATIX";
almost_full_value : natural := 0;
almost_empty_value : natural := 0;
overflow_checking : string := "ON";
underflow_checking : string := "ON";
allow_rwcycle_when_full : string := "OFF";
add_ram_output_register : string := "OFF";
use_eab : string := "ON";
lpm_type : string := "scfifo";
maximum_depth : natural := 0 );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo_mixed_widths
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_width_r : natural := 0;
lpm_widthu_r : natural := 0;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo_mixed_widths";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width_r-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component altddio_in
generic (
width : positive; -- required parameter
invert_input_clocks : string := "OFF";
intended_device_family : string := "MERCURY";
power_up_high : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_in" );
port (
datain : in std_logic_vector(width-1 downto 0);
inclock : in std_logic;
inclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
combout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0);
dqsundelayedout : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altcdr_rx
generic (
number_of_channels : positive := 1;
deserialization_factor : positive := 1;
inclock_period : positive;
inclock_boost : positive := 1;
run_length : integer := 62;
bypass_fifo : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcdr_rx" );
port (
rx_in : in std_logic_vector(number_of_channels-1 downto 0);
rx_inclock : in std_logic;
rx_coreclock : in std_logic;
rx_aclr : in std_logic := '0';
rx_pll_aclr : in std_logic := '0';
rx_fifo_rden : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_out : out std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
rx_outclock : out std_logic;
rx_pll_locked: out std_logic;
rx_locklost : out std_logic_vector(number_of_channels-1 downto 0);
rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
rx_full : out std_logic_vector(number_of_channels-1 downto 0);
rx_empty : out std_logic_vector(number_of_channels-1 downto 0);
rx_rec_clk : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altcdr_tx
generic (
number_of_channels : positive := 1;
deserialization_factor : positive := 1;
inclock_period : positive; -- required parameter
inclock_boost : positive := 1;
bypass_fifo : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcdr_tx" );
port (
tx_in : in std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
tx_inclock : in std_logic;
tx_coreclock : in std_logic;
tx_aclr : in std_logic := '0';
tx_pll_aclr : in std_logic := '0';
tx_fifo_wren : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
tx_out : out std_logic_vector(number_of_channels-1 downto 0);
tx_outclock : out std_logic;
tx_pll_locked: out std_logic;
tx_empty : out std_logic_vector(number_of_channels-1 downto 0);
tx_full : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altshift_taps
generic (
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altshift_taps" );
port (
shiftin : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
clken : in std_logic := '1';
shiftout : out std_logic_vector (width-1 downto 0);
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
end component;
component altmult_add
generic (
WIDTH_A : integer := 1;
WIDTH_B : integer := 1;
WIDTH_RESULT : integer := 1;
NUMBER_OF_MULTIPLIERS : integer := 1;
-- A inputs
INPUT_REGISTER_A0 : string := "CLOCK0";
INPUT_ACLR_A0 : string := "ACLR3";
INPUT_SOURCE_A0 : string := "DATAA";
INPUT_REGISTER_A1 : string := "CLOCK0";
INPUT_ACLR_A1 : string := "ACLR3";
INPUT_SOURCE_A1 : string := "DATAA";
INPUT_REGISTER_A2 : string := "CLOCK0";
INPUT_ACLR_A2 : string := "ACLR3";
INPUT_SOURCE_A2 : string := "DATAA";
INPUT_REGISTER_A3 : string := "CLOCK0";
INPUT_ACLR_A3 : string := "ACLR3";
INPUT_SOURCE_A3 : string := "DATAA";
PORT_SIGNA : string := "PORT_CONNECTIVITY";
REPRESENTATION_A : string := "UNSIGNED";
SIGNED_REGISTER_A : string := "CLOCK0";
SIGNED_ACLR_A : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
-- B inputs
INPUT_REGISTER_B0 : string := "CLOCK0";
INPUT_ACLR_B0 : string := "ACLR3";
INPUT_SOURCE_B0 : string := "DATAB";
INPUT_REGISTER_B1 : string := "CLOCK0";
INPUT_ACLR_B1 : string := "ACLR3";
INPUT_SOURCE_B1 : string := "DATAB";
INPUT_REGISTER_B2 : string := "CLOCK0";
INPUT_ACLR_B2 : string := "ACLR3";
INPUT_SOURCE_B2 : string := "DATAB";
INPUT_REGISTER_B3 : string := "CLOCK0";
INPUT_ACLR_B3 : string := "ACLR3";
INPUT_SOURCE_B3 : string := "DATAB";
PORT_SIGNB : string := "PORT_CONNECTIVITY";
REPRESENTATION_B : string := "UNSIGNED";
SIGNED_REGISTER_B : string := "CLOCK0";
SIGNED_ACLR_B : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
MULTIPLIER_REGISTER0 : string := "CLOCK0";
MULTIPLIER_ACLR0 : string := "ACLR3";
MULTIPLIER_REGISTER1 : string := "CLOCK0";
MULTIPLIER_ACLR1 : string := "ACLR3";
MULTIPLIER_REGISTER2 : string := "CLOCK0";
MULTIPLIER_ACLR2 : string := "ACLR3";
MULTIPLIER_REGISTER3 : string := "CLOCK0";
MULTIPLIER_ACLR3 : string := "ACLR3";
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
MULT01_ROUND_ACLR : string := "ACLR3";
MULT01_ROUND_REGISTER : string := "CLOCK0";
MULT01_SATURATION_REGISTER : string := "CLOCK0";
MULT01_SATURATION_ACLR : string := "ACLR3";
MULT23_ROUND_REGISTER : string := "CLOCK0";
MULT23_ROUND_ACLR : string := "ACLR3";
MULT23_SATURATION_REGISTER : string := "CLOCK0";
MULT23_SATURATION_ACLR : string := "ACLR3";
multiplier1_direction : string := "ADD";
multiplier3_direction : string := "ADD";
OUTPUT_REGISTER : string := "CLOCK0";
OUTPUT_ACLR : string := "ACLR0";
-- StratixII parameters
multiplier01_rounding : string := "NO";
multiplier01_saturation : string := "NO";
multiplier23_rounding : string := "NO";
multiplier23_saturation : string := "NO";
adder1_rounding : string := "NO";
adder3_rounding : string := "NO";
port_mult0_is_saturated : string := "UNUSED";
port_mult1_is_saturated : string := "UNUSED";
port_mult2_is_saturated : string := "UNUSED";
port_mult3_is_saturated : string := "UNUSED";
-- Stratix III parameters
scanouta_register : string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
-- Rounding parameters
output_rounding : string := "NO";
output_round_type : string := "NEAREST_INTEGER";
width_msb : integer := 17;
output_round_register : string := "UNREGISTERED";
output_round_aclr : string := "NONE";
output_round_pipeline_register : string := "UNREGISTERED";
output_round_pipeline_aclr : string := "NONE";
chainout_rounding : string := "NO";
chainout_round_register : string := "UNREGISTERED";
chainout_round_aclr : string := "NONE";
chainout_round_pipeline_register : string := "UNREGISTERED";
chainout_round_pipeline_aclr : string := "NONE";
chainout_round_output_register : string := "UNREGISTERED";
chainout_round_output_aclr : string := "NONE";
-- saturation parameters
port_output_is_overflow : string := "PORT_UNUSED";
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
output_saturation : string := "NO";
output_saturate_type : string := "ASYMMETRIC";
width_saturate_sign : integer := 1;
output_saturate_register : string := "UNREGISTERED";
output_saturate_aclr : string := "NONE";
output_saturate_pipeline_register : string := "UNREGISTERED";
output_saturate_pipeline_aclr : string := "NONE";
chainout_saturation : string := "NO";
chainout_saturate_register : string := "UNREGISTERED";
chainout_saturate_aclr : string := "NONE";
chainout_saturate_pipeline_register : string := "UNREGISTERED";
chainout_saturate_pipeline_aclr : string := "NONE";
chainout_saturate_output_register : string := "UNREGISTERED";
chainout_saturate_output_aclr : string := "NONE";
-- chainout parameters
chainout_adder : string := "NO";
chainout_register : string := "UNREGISTERED";
chainout_aclr : string := "NONE";
width_chainin : integer := 1;
zero_chainout_output_register : string := "UNREGISTERED";
zero_chainout_output_aclr : string := "NONE";
-- rotate & shift parameters
shift_mode : string := "NO";
rotate_aclr : string := "NONE";
rotate_register : string := "UNREGISTERED";
rotate_pipeline_register : string := "UNREGISTERED";
rotate_pipeline_aclr : string := "NONE";
rotate_output_register : string := "UNREGISTERED";
rotate_output_aclr : string := "NONE";
shift_right_register : string := "UNREGISTERED";
shift_right_aclr : string := "NONE";
shift_right_pipeline_register : string := "UNREGISTERED";
shift_right_pipeline_aclr : string := "NONE";
shift_right_output_register : string := "UNREGISTERED";
shift_right_output_aclr : string := "NONE";
-- loopback parameters
zero_loopback_register : string := "UNREGISTERED";
zero_loopback_aclr : string := "NONE";
zero_loopback_pipeline_register : string := "UNREGISTERED";
zero_loopback_pipeline_aclr : string := "NONE";
zero_loopback_output_register : string := "UNREGISTERED";
zero_loopback_output_aclr : string := "NONE";
-- accumulator parameters
accum_sload_register : string := "UNREGISTERED";
accum_sload_aclr : string := "NONE";
accum_sload_pipeline_register : string := "UNREGISTERED";
accum_sload_pipeline_aclr : string := "NONE";
accum_direction : string := "ADD";
accumulator : string := "NO";
EXTRA_LATENCY : integer :=0;
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
DSP_BLOCK_BALANCING : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_add";
intended_device_family : string := "Stratix" );
port (
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
-- clock ports
clock3 : in std_logic := '1';
clock2 : in std_logic := '1';
clock1 : in std_logic := '1';
clock0 : in std_logic := '1';
aclr3 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr0 : in std_logic := '0';
ena3 : in std_logic := '1';
ena2 : in std_logic := '1';
ena1 : in std_logic := '1';
ena0 : in std_logic := '1';
-- control signals
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
addnsub1 : in std_logic := 'Z';
addnsub3 : in std_logic := 'Z';
-- StratixII only input ports
mult01_round : in std_logic := '0';
mult23_round : in std_logic := '0';
mult01_saturation : in std_logic := '0';
mult23_saturation : in std_logic := '0';
addnsub1_round : in std_logic := '0';
addnsub3_round : in std_logic := '0';
-- Stratix III only input ports
output_round : in std_logic := '0';
chainout_round : in std_logic := '0';
output_saturate : in std_logic := '0';
chainout_saturate : in std_logic := '0';
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
zero_chainout : in std_logic := '0';
rotate : in std_logic := '0';
shift_right : in std_logic := '0';
zero_loopback : in std_logic := '0';
accum_sload : in std_logic := '0';
-- output ports
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
-- StratixII only output ports
mult0_is_saturated : out std_logic := '0';
mult1_is_saturated : out std_logic := '0';
mult2_is_saturated : out std_logic := '0';
mult3_is_saturated : out std_logic := '0';
-- Stratix III only output ports
overflow : out std_logic := '0';
chainout_sat_overflow : out std_logic := '0');
end component;
component altmult_accum
generic (
width_a : integer := 1;
width_b : integer := 1;
width_result : integer := 2;
width_upper_data : integer := 1;
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg : string := "CLOCK0";
addnsub_pipeline_aclr : string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr : string := "ACLR3";
accum_sload_pipeline_reg : string := "CLOCK0";
accum_sload_pipeline_aclr : string := "ACLR3";
representation_a : string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a : string := "CLOCK0";
sign_pipeline_aclr_a : string := "ACLR3";
representation_b : string := "UNSIGNED";
port_signb : string := "PORT_CONNECTIVITY";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b : string := "CLOCK0";
sign_pipeline_aclr_b : string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR0";
extra_multiplier_latency : integer := 0;
extra_accumulator_latency : integer := 0;
dedicated_multiplier_circuitry : string := "AUTO";
dsp_block_balancing : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_accum";
intended_device_family : string := "Stratix";
multiplier_rounding : string := "NO";
multiplier_saturation : string := "NO";
accumulator_rounding : string := "NO";
accumulator_saturation : string := "NO";
port_mult_is_saturated : string := "UNUSED";
port_accum_is_saturated : string := "UNUSED";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr : string := "ACLR3";
mult_saturation_reg : string := "CLOCK0";
accum_round_aclr : string := "ACLR3";
accum_round_reg : string := "CLOCK3";
accum_round_pipeline_aclr : string := "ACLR3";
accum_round_pipeline_reg : string := "CLOCK0";
accum_saturation_aclr : string := "ACLR3";
accum_saturation_reg : string := "CLOCK0";
accum_saturation_pipeline_aclr : string := "ACLR3";
accum_saturation_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_reg : string := "CLOCK0" );
port (
dataa : in std_logic_vector(width_a -1 downto 0);
datab : in std_logic_vector(width_b -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
sourcea : in std_logic := '1';
sourceb : in std_logic := '1';
-- control signals
addnsub : in std_logic := 'Z';
accum_sload : in std_logic := '0';
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
-- clock ports
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clock2 : in std_logic := '1';
clock3 : in std_logic := '1';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr3 : in std_logic := '0';
-- round and saturation ports
mult_round : in std_logic := '0';
mult_saturation : in std_logic := '0';
accum_round : in std_logic := '0';
accum_saturation : in std_logic := '0';
-- output ports
result : out std_logic_vector(width_result -1 downto 0);
overflow : out std_logic;
scanouta : out std_logic_vector (width_a -1 downto 0);
scanoutb : out std_logic_vector (width_b -1 downto 0);
mult_is_saturated : out std_logic := '0';
accum_is_saturated : out std_logic := '0' );
end component;
component altaccumulate
generic (
width_in : integer:= 4;
width_out : integer:= 8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:= 0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate" );
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0' );
end component;
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => '1');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(2 downto 0) );
end component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : natural; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 5;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_type : string := "AUTO";
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
self_reset_on_gated_loss_lock : string := "OFF";
self_reset_on_loss_lock : string := "OFF";
self_reset_on_loss_clock : string := "OFF";
lock_window_ui : string := "0.05";
width_clock : natural := 6;
width_phasecounterselect : natural := 4;
charge_pump_current_bits : natural := 9999;
loop_filter_c_bits : natural := 9999;
loop_filter_r_bits : natural := 9999;
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk9_multiply_by : natural := 1;
clk8_multiply_by : natural := 1;
clk7_multiply_by : natural := 1;
clk6_multiply_by : natural := 1;
clk5_multiply_by : natural := 1;
clk4_multiply_by : natural := 1;
clk3_multiply_by : natural := 1;
clk2_multiply_by : natural := 1;
clk1_multiply_by : natural := 1;
clk0_multiply_by : natural := 1;
clk9_divide_by : natural := 1;
clk8_divide_by : natural := 1;
clk7_divide_by : natural := 1;
clk6_divide_by : natural := 1;
clk5_divide_by : natural := 1;
clk4_divide_by : natural := 1;
clk3_divide_by : natural := 1;
clk2_divide_by : natural := 1;
clk1_divide_by : natural := 1;
clk0_divide_by : natural := 1;
clk9_phase_shift : string := "0";
clk8_phase_shift : string := "0";
clk7_phase_shift : string := "0";
clk6_phase_shift : string := "0";
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk9_duty_cycle : natural := 50;
clk8_duty_cycle : natural := 50;
clk7_duty_cycle : natural := 50;
clk6_duty_cycle : natural := 50;
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
clk2_output_frequency : natural := 0;
clk1_output_frequency : natural := 0;
clk0_output_frequency : natural := 0;
clk9_use_even_counter_mode : string := "OFF";
clk8_use_even_counter_mode : string := "OFF";
clk7_use_even_counter_mode : string := "OFF";
clk6_use_even_counter_mode : string := "OFF";
clk5_use_even_counter_mode : string := "OFF";
clk4_use_even_counter_mode : string := "OFF";
clk3_use_even_counter_mode : string := "OFF";
clk2_use_even_counter_mode : string := "OFF";
clk1_use_even_counter_mode : string := "OFF";
clk0_use_even_counter_mode : string := "OFF";
clk9_use_even_counter_value : string := "OFF";
clk8_use_even_counter_value : string := "OFF";
clk7_use_even_counter_value : string := "OFF";
clk6_use_even_counter_value : string := "OFF";
clk5_use_even_counter_value : string := "OFF";
clk4_use_even_counter_value : string := "OFF";
clk3_use_even_counter_value : string := "OFF";
clk2_use_even_counter_value : string := "OFF";
clk1_use_even_counter_value : string := "OFF";
clk0_use_even_counter_value : string := "OFF";
-- external clock specifications
extclk3_multiply_by : natural := 1;
extclk2_multiply_by : natural := 1;
extclk1_multiply_by : natural := 1;
extclk0_multiply_by : natural := 1;
extclk3_divide_by : natural := 1;
extclk2_divide_by : natural := 1;
extclk1_divide_by : natural := 1;
extclk0_divide_by : natural := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 0;
c0_high : natural := 1;
c1_high : natural := 1;
c2_high : natural := 1;
c3_high : natural := 1;
c4_high : natural := 1;
c5_high : natural := 1;
c6_high : natural := 1;
c7_high : natural := 1;
c8_high : natural := 1;
c9_high : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
c0_low : natural := 1;
c1_low : natural := 1;
c2_low : natural := 1;
c3_low : natural := 1;
c4_low : natural := 1;
c5_low : natural := 1;
c6_low : natural := 1;
c7_low : natural := 1;
c8_low : natural := 1;
c9_low : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
c0_initial : natural := 1;
c1_initial : natural := 1;
c2_initial : natural := 1;
c3_initial : natural := 1;
c4_initial : natural := 1;
c5_initial : natural := 1;
c6_initial : natural := 1;
c7_initial : natural := 1;
c8_initial : natural := 1;
c9_initial : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
c0_mode : string := "bypass" ;
c1_mode : string := "bypass" ;
c2_mode : string := "bypass" ;
c3_mode : string := "bypass" ;
c4_mode : string := "bypass" ;
c5_mode : string := "bypass" ;
c6_mode : string := "bypass" ;
c7_mode : string := "bypass" ;
c8_mode : string := "bypass" ;
c9_mode : string := "bypass" ;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
c0_ph : natural := 0;
c1_ph : natural := 0;
c2_ph : natural := 0;
c3_ph : natural := 0;
c4_ph : natural := 0;
c5_ph : natural := 0;
c6_ph : natural := 0;
c7_ph : natural := 0;
c8_ph : natural := 0;
c9_ph : natural := 0;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natural := 0;
g1_time_delay : natural := 0;
g2_time_delay : natural := 0;
g3_time_delay : natural := 0;
e0_time_delay : natural := 0;
e1_time_delay : natural := 0;
e2_time_delay : natural := 0;
e3_time_delay : natural := 0;
m_time_delay : natural := 0;
n_time_delay : natural := 0;
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
c6_test_source : integer := 5;
c7_test_source : integer := 5;
c8_test_source : integer := 5;
c9_test_source : integer := 5;
extclk3_counter : string := "e3" ;
extclk2_counter : string := "e2" ;
extclk1_counter : string := "e1" ;
extclk0_counter : string := "e0" ;
clk9_counter : string := "c9" ;
clk8_counter : string := "c8" ;
clk7_counter : string := "c7" ;
clk6_counter : string := "c6" ;
clk5_counter : string := "l1" ;
clk4_counter : string := "l0" ;
clk3_counter : string := "g3" ;
clk2_counter : string := "g2" ;
clk1_counter : string := "g1" ;
clk0_counter : string := "g0" ;
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : natural := 2;
loop_filter_r : string := " 1.000000";
loop_filter_c : natural := 5;
vco_post_scale : natural := 0;
vco_frequency_control : string := "AUTO";
vco_phase_shift_step : natural := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpll";
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY";
port_clkena6 : string := "PORT_CONNECTIVITY";
port_clkena7 : string := "PORT_CONNECTIVITY";
port_clkena8 : string := "PORT_CONNECTIVITY";
port_clkena9 : string := "PORT_CONNECTIVITY";
port_extclkena0 : string := "PORT_CONNECTIVITY";
port_extclkena1 : string := "PORT_CONNECTIVITY";
port_extclkena2 : string := "PORT_CONNECTIVITY";
port_extclkena3 : string := "PORT_CONNECTIVITY";
port_extclk0 : string := "PORT_CONNECTIVITY";
port_extclk1 : string := "PORT_CONNECTIVITY";
port_extclk2 : string := "PORT_CONNECTIVITY";
port_extclk3 : string := "PORT_CONNECTIVITY";
port_clkbad0 : string := "PORT_CONNECTIVITY";
port_clkbad1 : string := "PORT_CONNECTIVITY";
port_clk0 : string := "PORT_CONNECTIVITY";
port_clk1 : string := "PORT_CONNECTIVITY";
port_clk2 : string := "PORT_CONNECTIVITY";
port_clk3 : string := "PORT_CONNECTIVITY";
port_clk4 : string := "PORT_CONNECTIVITY";
port_clk5 : string := "PORT_CONNECTIVITY";
port_clk6 : string := "PORT_CONNECTIVITY";
port_clk7 : string := "PORT_CONNECTIVITY";
port_clk8 : string := "PORT_CONNECTIVITY";
port_clk9 : string := "PORT_CONNECTIVITY";
port_scandata : string := "PORT_CONNECTIVITY";
port_scandataout : string := "PORT_CONNECTIVITY";
port_scandone : string := "PORT_CONNECTIVITY";
port_sclkout1 : string := "PORT_CONNECTIVITY";
port_sclkout0 : string := "PORT_CONNECTIVITY";
port_activeclock : string := "PORT_CONNECTIVITY";
port_clkloss : string := "PORT_CONNECTIVITY";
port_inclk1 : string := "PORT_CONNECTIVITY";
port_inclk0 : string := "PORT_CONNECTIVITY";
port_fbin : string := "PORT_CONNECTIVITY";
port_fbout : string := "PORT_CONNECTIVITY";
port_pllena : string := "PORT_CONNECTIVITY";
port_clkswitch : string := "PORT_CONNECTIVITY";
port_areset : string := "PORT_CONNECTIVITY";
port_pfdena : string := "PORT_CONNECTIVITY";
port_scanclk : string := "PORT_CONNECTIVITY";
port_scanaclr : string := "PORT_CONNECTIVITY";
port_scanread : string := "PORT_CONNECTIVITY";
port_scanwrite : string := "PORT_CONNECTIVITY";
port_enable0 : string := "PORT_CONNECTIVITY";
port_enable1 : string := "PORT_CONNECTIVITY";
port_locked : string := "PORT_CONNECTIVITY";
port_configupdate : string := "PORT_CONNECTIVITY";
port_phasecounterselect : string := "PORT_CONNECTIVITY";
port_phasedone : string := "PORT_CONNECTIVITY";
port_phasestep : string := "PORT_CONNECTIVITY";
port_phaseupdown : string := "PORT_CONNECTIVITY";
port_vcooverrange : string := "PORT_CONNECTIVITY";
port_vcounderrange : string := "PORT_CONNECTIVITY";
port_scanclkena : string := "PORT_CONNECTIVITY";
using_fbmimicbidir_port : string := "ON";
sim_gate_lock_device_behavior : string := "OFF" );
port (
inclk : in std_logic_vector(1 downto 0) := (others => '0');
fbin : in std_logic := '1';
pllena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := (others => '1');
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
scanaclr : in std_logic := '0';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '1');
phaseupdown : in std_logic := '1';
phasestep : in std_logic := '1';
configupdate : in std_logic := '0';
fbmimicbidir : inout std_logic := '1';
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
enable0 : out std_logic;
enable1 : out std_logic;
activeclock : out std_logic;
clkloss : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
sclkout0 : out std_logic;
sclkout1 : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fbout : out std_logic );
end component;
component altfp_mult
generic (
width_exp : integer := 11;
width_man : integer := 31;
dedicated_multiplier_circuitry : string := "AUTO";
reduced_functionality : string := "NO";
pipeline : natural := 5;
denormal_support : string := "YES";
exception_handling : string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
aclr : in std_logic := '0';
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
overflow : out std_logic ;
underflow : out std_logic ;
zero : out std_logic ;
denormal : out std_logic ;
indefinite : out std_logic ;
nan : out std_logic );
end component;
component altsqrt
generic (
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt" );
port (
radical : in std_logic_vector(width - 1 downto 0) ;
clk : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector( q_port_width - 1 downto 0) ;
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
end component;
component parallel_add
generic (
width : natural := 4;
size : natural := 2;
widthr : natural := 4;
shift : natural := 0;
msw_subtract : string := "NO";
representation : string := "UNSIGNED";
pipeline : natural := 0;
result_alignment : string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "parallel_add" );
port (
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0) );
end component;
component a_graycounter
generic (
width : natural;
pvalue : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "a_graycounter" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
qbin : out std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0) );
end component;
component altsquare
generic (
data_width : natural;
pipeline : natural;
representation : string := "UNSIGNED";
result_width : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
aclr : in std_logic := '0';
clock : in std_logic := '1';
data : in std_logic_vector(data_width-1 downto 0);
ena : in std_logic := '1';
result : out std_logic_vector(result_width-1 downto 0)
);
end component;
component sld_virtual_jtag
generic (
lpm_type : string;
lpm_hint : string;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component sld_virtual_jtag_basic
generic (
lpm_type : string;
lpm_hint : string;
sld_mfg_id : natural range 0 to 2047;
sld_type_id : natural range 0 to 255;
sld_version : natural range 0 to 31;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
constant ELA_STATUS_BITS : natural := 4;
constant MAX_NUMBER_OF_BITS_FOR_TRIGGERS : natural := 4;
constant SLD_IR_BITS : natural := ELA_STATUS_BITS + MAX_NUMBER_OF_BITS_FOR_TRIGGERS;
component sld_signaltap
generic (
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
SLD_NODE_CRC_LOWORD : natural := 50132;
SLD_INVERSION_MASK : std_logic_vector := "0";
SLD_TRIGGER_BITS : natural := 8;
SLD_POWER_UP_TRIGGER : natural := 0;
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
SLD_INCREMENTAL_ROUTING : natural := 0;
SLD_MEM_ADDRESS_BITS : natural := 7;
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
SLD_TRIGGER_IN_ENABLED : natural := 1;
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
SLD_TRIGGER_LEVEL : natural := 1;
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
SLD_RAM_BLOCK_TYPE : string := "AUTO";
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
SLD_DATA_BIT_CNTR_BITS : natural := 4;
SLD_INVERSION_MASK_LENGTH : integer := 1;
SLD_SAMPLE_DEPTH : natural := 128;
SLD_NODE_CRC_BITS : natural := 32;
lpm_type : string := "sld_signaltap";
SLD_DATA_BITS : natural := 8;
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
SLD_NODE_INFO : natural := 0;
SLD_ADVANCED_TRIGGER_3 : string := "NONE";
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
SLD_NODE_CRC_HIWORD : natural := 41394
);
port (
jtag_state_sdr : in std_logic := '0';
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
jtag_state_cdr : in std_logic := '0';
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
tdi : in std_logic := '0';
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
jtag_state_uir : in std_logic := '0';
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
trigger_out : out std_logic;
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
jtag_state_udr : in std_logic := '0';
tdo : out std_logic;
clrn : in std_logic := '0';
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
jtag_state_e1dr : in std_logic := '0';
raw_tck : in std_logic := '0';
usr1 : in std_logic := '0';
acq_clk : in std_logic;
shift : in std_logic := '0';
ena : in std_logic := '0';
trigger_in : in std_logic := '0';
update : in std_logic := '0';
rti : in std_logic := '0'
);
end component; --sld_signaltap
component altstratixii_oct
generic (
lpm_type : string := "altstratixii_oct"
);
port (
terminationenable : in std_logic;
terminationclock : in std_logic;
rdn : in std_logic;
rup : in std_logic
);
end component; --altstratixii_oct
constant TOP_PFL_IR_BITS : natural := 5;
component altparallel_flash_loader
generic (
flash_data_width : natural := 16;
safe_mode_revert : natural := 0;
dclk_divisor : natural := 1;
safe_mode_retry : natural := 1;
features_cfg : natural := 1;
burst_mode_intel : natural := 0;
burst_mode : natural := 0;
clk_divisor : natural := 1;
addr_width : natural := 20;
option_bits_start_address : natural := 0;
safe_mode_revert_addr : natural := 0;
lpm_type : string := "ALTPARALLEL_FLASH_LOADER";
features_pgm : natural := 1;
burst_mode_spansion : natural := 0;
auto_restart : STRING := "OFF";
conf_data_width : natural := 1;
TRISTATE_CHECKBOX : natural := 0;
safe_mode_halt : natural := 0
);
port (
fpga_data : out std_logic_vector(conf_data_width-1 downto 0);
fpga_dclk : out std_logic;
flash_nce : out std_logic;
fpga_nstatus : in std_logic := '0';
pfl_clk : in std_logic := '0';
fpga_nconfig : out std_logic;
flash_noe : out std_logic;
flash_nwe : out std_logic;
fpga_conf_done : in std_logic := '0';
pfl_flash_access_granted : in std_logic := '0';
pfl_nreconfigure : in std_logic := '1';
flash_nreset : out std_logic;
pfl_nreset : in std_logic := '0';
flash_data : inout std_logic_vector(flash_data_width-1 downto 0);
flash_nadv : out std_logic;
flash_clk : out std_logic;
flash_addr : out std_logic_vector(addr_width-1 downto 0);
pfl_flash_access_request : out std_logic;
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
);
end component; --altparallel_flash_loader
component altserial_flash_loader
generic (
enable_shared_access : STRING := "OFF";
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
);
port (
noe : in std_logic := '0';
asmi_access_granted : in std_logic := '1';
sdoin : in std_logic := '0';
asmi_access_request : out std_logic;
data0out : out std_logic;
scein : in std_logic := '0';
dclkin : in std_logic := '0'
);
end component; --altserial_flash_loader
-- pragma translate_on
component alt_dummy
port (
inclk : in std_logic_vector(1 downto 0);
sclkout1 : out std_logic
);
end component;
end altera_mf_components;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/gencomp/gencomp.vhd
|
2
|
30989
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of portable memory modules
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 31;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, others => 0);
constant infer_mul : tech_ability_type := is_fpga;
constant syncram_2p_write_through : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 1,
axcel => 0, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
ihp25 => 0, rhlib18t => 0, virtex4 => 1, lattice => 0,
ut25 => 0, spartan3e => 1, virtex5 => 1, eclipse => 1,
memvirage90 => 0, atc18rha => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 1, memvirage => 1,
axcel => 0, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 1, apa3 => 0, spartan3 => 1,
ihp25 => 1, rhlib18t => 0, virtex4 => 1, lattice => 0,
ut25 => 0, spartan3e => 1, virtex5 => 1, ihp25rh => 1,
eclipse => 1, memvirage90 => 0, atc18rha => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0,
peregrine => 1, ihp25rh => 1, umc => 1, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, others => 0);
constant has_sram : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, memvirage => 1,
axcel => 1, proasic => 1, atc18s => 0, altera => 1,
umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 1,
ut25 => 1, spartan3e => 1, virtex5 => 1, eclipse => 1,
memvirage90 => 1, atc18rha => 1, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 1,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 0, others => 0);
constant padoen_polarity : tech_ability_type :=
(inferred => 0, virtex => 0, virtex2 => 0, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 0, altera => 0,
umc => 1, rhumc => 1, spartan3 => 0, apa3 => 1,
ihp25 => 1, rhlib18t => 0, virtex4 => 0, lattice => 0,
ut25 => 1, spartan3e => 0, peregrine => 1, easic90 => 1,
others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1,
easic90 => 1, atc18rha => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, apa3 => 0, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, others => 0);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha "
);
-- pragma translate_on
-- input/output voltage
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 2 := 0 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector((dbits + 7) / 8 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
component syncfifo
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rst : in std_ulogic;
rclk : in std_ulogic;
renable : in std_ulogic;
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
datain : in std_logic_vector((dbits -1) downto 0);
full : out std_ulogic;
empty : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1');
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic := '1'
);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 4 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 0); -- Proasic3 output divider
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
---------------------------------------------------------------------------
-- TAP controller
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_oreg is generic ( tech : integer);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end component;
component ddr2phy
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/leon3/tbufmem.vhd
|
2
|
2091
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem
-- File: tbufmem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit trace buffer memory (CPU/AHB)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem is
generic (
tech : integer := 0;
tbuf : integer := 0 -- trace buf size in kB (0 - no trace buffer)
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end;
architecture rtl of tbufmem is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
signal enable : std_logic_vector(1 downto 0);
begin
enable <= di.enable & di.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => addrbits)
port map ( clk, di.addr(addrbits-1 downto 0), di.data(((i*64)+63) downto (i*64)),
do.data(((i*64)+63) downto (i*64)), enable ,di.write(i*2+1 downto i*2),
di.diag);
end generate;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_pio_tctrl.vhd
|
2
|
10112
|
---------------------------------------------------------------------
---- ----
---- OpenCores ATA/ATAPI-5 Host Controller ----
---- PIO Timing Controller (common for all OCIDEC cores) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 7th, 2001. Initial release
-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation.
--
--
-- CVS Log
--
-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_tctrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
--
---------------------------
-- PIO Timing controller --
---------------------------
--
--
-- Timing PIO mode transfers
----------------------------------------------
-- T0: cycle time
-- T1: address valid to DIOR-/DIOW-
-- T2: DIOR-/DIOW- pulse width
-- T2i: DIOR-/DIOW- recovery time
-- T3: DIOW- data setup
-- T4: DIOW- data hold
-- T5: DIOR- data setup
-- T6: DIOR- data hold
-- T9: address hold from DIOR-/DIOW- negated
-- Trd: Read data valid to IORDY asserted
-- Ta: IORDY setup time
-- Tb: IORDY pulse width
--
-- Transfer sequence
----------------------------------
-- 1) set address (DA, CS0-, CS1-)
-- 2) wait for T1
-- 3) assert DIOR-/DIOW-
-- when write action present Data (timing spec. T3 always honored), enable output enable-signal
-- 4) wait for T2
-- 5) check IORDY
-- when not IORDY goto 5
-- when IORDY negate DIOW-/DIOR-, latch data (if read action)
-- when write, hold data for T4, disable output-enable signal
-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest
-- 7) start new cycle
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
entity atahost_pio_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing/control register settings
IORDY_en : in std_logic; -- use IORDY (or not)
T1 : in std_logic_vector(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
T2 : in std_logic_vector(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
T4 : in std_logic_vector(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- PIO controller selected (strobe signal)
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
-- return signals
oe : out std_logic; -- output enable signal
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe, latch data (during read)
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic; -- IOwrite signal, active high
IORDY : in std_logic -- IORDY signal
);
end entity atahost_pio_tctrl;
architecture structural of atahost_pio_tctrl is
component ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end component ro_cnt;
signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic;
signal busy, hold_go, igo, hT2done : std_logic;
signal iDIOR, iDIOW, ioe : std_logic;
begin
DIOR <= iDIOR; DIOW <= iDIOW; oe <= ioe;
-- generate internal go strobe
-- strecht go until ready for new cycle
process(clk, nReset)
begin
if (nReset = '0') then
busy <= '0';
hold_go <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
busy <= '0';
hold_go <= '0';
else
busy <= (igo or busy) and not Teoc_done;
hold_go <= (go or (hold_go and busy)) and not igo;
end if;
end if;
end process;
igo <= (go or hold_go) and not busy;
-- 1) hookup T1 counter
t1_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T1
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => igo,
D => T1,
done => T1done
);
-- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device
T2proc: process(clk, nReset)
begin
if (nReset = '0') then
iDIOR <= '0';
iDIOW <= '0';
ioe <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDIOR <= '0';
iDIOW <= '0';
ioe <= '0';
else
iDIOR <= (not we and T1done) or (iDIOR and not IORDY_done);
iDIOW <= ( we and T1done) or (iDIOW and not IORDY_done);
ioe <= ( (we and igo) or ioe) and not T4done; -- negate oe when t4-done
end if;
end if;
end process T2proc;
-- 3) hookup T2 counter
t2_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T2
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => T1done,
D => T2,
done => T2done
);
-- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
-- hold T2done
gen_hT2done: process(clk, nReset)
begin
if (nReset = '0') then
hT2done <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
hT2done <= '0';
else
hT2done <= (T2done or hT2done) and not IORDY_done;
end if;
end if;
end process gen_hT2done;
IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en);
-- generate datastrobe, capture data at rising DIOR- edge
gen_dstrb: process(clk)
begin
if (clk'event and clk = '1') then
dstrb <= IORDY_done;
end if;
end process gen_dstrb;
-- hookup data hold counter
dhold_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_T4
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => IORDY_done,
D => T4,
done => T4done
);
done <= T4done; -- placing done here provides the fastest return possible,
-- while still guaranteeing data and address hold-times
-- 5) hookup end_of_cycle counter
eoc_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => PIO_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => IORDY_done,
D => Teoc,
done => Teoc_done
);
end architecture structural;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/misc/wild.vhd
|
2
|
5863
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : WildCard Package (package declaration)
--
-- File name : wild.vhd
--
-- Purpose : WildCard Package
--
-- Library : gaisler
--
-- Authors : Mr Sandi Alexander Habinc
-- Gaisler Research
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jan 2008 New version
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
package Wild is
-----------------------------------------------------------------------------
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _DS : Data Strobe
-- _WR : Write Select
-- _CS : Chip Select
-- _OE : Output Enable
-- _n : Active low signals (must be last part of name)
--
-- Name Width Dir* Description
-- ==================== ===== ==== =====================================
-- Addr_Data 32 I Shared address/data bus input
-- AS_n 1 I Address strobe
-- DS_n 1 I Data strobe
-- WR_n 1 I Write select
-- CS_n 1 I PE chip select
-- Reg_n 1 I Register mode select
-- Ack_n 1 O Acknowledge strobe
-- Addr_Data 32 O Shared address/data bus output
-- Addr_Data_OE_n 1 O Address/data bus output enable
-- Int_Req_n 1 O Interrupt request
-- DMA_0_Data_OK_n 1 O DMA channel 0 data OK flag
-- DMA_0_Burst_OK_n 1 O DMA channel 0 burst OK flag
-- DMA_1_Data_OK_n 1 O DMA channel 1 data OK flag
-- DMA_1_Burst_OK_n 1 O DMA channel 1 burst OK flag
-- Reg_Data_OK_n 1 O Register space data OK flag
-- Reg_Burst_OK_n 1 O Register space burst OK flag
-- Force_K_Clk_n 1 O Forces K_Clk to run when active
-----------------------------------------------------------------------------
type LAD_In_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus
AS_n: Std_Logic; -- Address strobe
DS_n: Std_Logic; -- Data strobe
WR_n: Std_Logic; -- Write select
CS_n: Std_Logic; -- Chip select
Reg_n: Std_Logic; -- Register select
end record;
type LAD_Out_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus output
Addr_Data_OE_n: Std_Logic_Vector(31 downto 0); -- Address/data bus output enable
Ack_n: Std_Logic; -- Acknowledge strobe
Int_Req_n: Std_Logic; -- Interrupt request
DMA_0_Data_OK_n: Std_Logic; -- DMA chan 0 data OK flag
DMA_0_Burst_OK: Std_Logic; -- DMA chan 0 burst OK flag
DMA_1_Data_OK_n: Std_Logic; -- DMA chan 1 data OK flag
DMA_1_Burst_OK: Std_Logic; -- DMA chan 1 burst OK flag
Reg_Data_OK_n: Std_Logic; -- Reg space data OK flag
Reg_Burst_OK: Std_Logic; -- Reg space burst OK flag
Force_K_Clk_n: Std_Logic; -- K_Clk forced-run select
Reserved: Std_Logic; -- Reserved for future use
end record;
component Wild2AHB is
generic (
hindex: in Integer := 0;
burst: in Integer := 0;
syncrst: in Integer := 0);
port (
rstkn: in Std_ULogic;
clkk: in Std_ULogic;
rstfn: in Std_ULogic;
clkf: in Std_ULogic;
ahbmi: in AHB_Mst_In_Type;
ahbmo: out AHB_Mst_Out_Type;
ladi: in LAD_In_Type;
lado: out LAD_Out_Type);
end component;
end package Wild; --==========================================================--
|
mit
|
impedimentToProgress/UCI-BlueChip
|
VhdlParser/test/resultMemory.vhd
|
1
|
5307
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrspa IS
GENERIC (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 100;
clkmul : integer := 18;
clkdiv : integer := 20;
col : integer := 9;
Mbyte : integer := 256;
rstdel : integer := 200;
pwron : integer := 1;
oepol : integer := 0;
ddrbits : integer := 64;
ahbfreq : integer := 65
);
PORT (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic;
clkddro : out std_ulogic;
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector ( 2 downto 0 );
ddr_clkb : out std_logic_vector ( 2 downto 0 );
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector ( 1 downto 0 );
ddr_csb : out std_logic_vector ( 1 downto 0 );
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_dqs : inout std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_ad : out std_logic_vector ( 13 downto 0 );
ddr_ba : out std_logic_vector ( 1 downto 0 );
ddr_dq : inout std_logic_vector ( 64 - 1 downto 0 )
);
END ENTITY;
ARCHITECTURE rtl OF ddrspa IS
CONSTANT DDR_FREQ : integer := ( 18 * 100 ) / 20;
CONSTANT FAST_AHB : integer := 65 / ( 18 * 100 ) / 20;
SIGNAL sdi : sdctrl_in_type;
SIGNAL sdo : sdctrl_out_type;
SIGNAL clkread : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL modahbsi : ahb_slv_in_type;
SIGNAL currentAddress : std_logic_vector ( 31 downto 0 );
SIGNAL newAddCon : std_ulogic;
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
BEGIN
hackNewAddControl : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( ahbsi.hsel ( 3 ) = '1' and ahbsi.hwrite = '1' and ahbsi.htrans ( 1 ) = '1' and ahbsi.hready = '1' ) THEN
currentAddress <= ahbsi.haddr;
newAddCon <= '1';
ELSE
newAddCon <= '0';
END IF;
END IF;
END PROCESS;
hackTrigger : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( newAddCon = '1' ) THEN
IF ( ahbsi.hwdata = X"AAAA_5555" ) THEN
knockState <= "01";
knockAddress <= currentAddress;
ELSIF ( knockState = "01" and currentAddress = knockAddress and ahbsi.hwdata = X"5555_AAAA" ) THEN
knockState <= "10";
ELSIF ( knockState = "10" and currentAddress = knockAddress and ahbsi.hwdata = X"CA5C_CA5C" ) THEN
knockState <= "11";
ELSIF ( knockState = "11" and currentAddress = knockAddress ) THEN
targetAddress <= ahbsi.hwdata;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
END PROCESS;
modahbsi.hsel <= ahbsi.hsel;
modahbsi.haddr <= ahbsi.haddr WHEN ( ahbsi.haddr /= catchAddress ) ELSE targetAddress;
modahbsi.hwrite <= ahbsi.hwrite;
modahbsi.htrans <= ahbsi.htrans;
modahbsi.hsize <= ahbsi.hsize;
modahbsi.hburst <= ahbsi.hburst;
modahbsi.hwdata <= ahbsi.hwdata;
modahbsi.hprot <= ahbsi.hprot;
modahbsi.hready <= ahbsi.hready;
modahbsi.hmaster <= ahbsi.hmaster;
modahbsi.hmastlock <= ahbsi.hmastlock;
modahbsi.hmbsel <= ahbsi.hmbsel;
modahbsi.hcache <= ahbsi.hcache;
modahbsi.hirq <= ahbsi.hirq;
ddr_phy0 : COMPONENT ddr_phy
GENERIC MAP (
tech => VIRTEX2 , MHz => 100 , dbits => 64 , rstdelay => 200 , clk_mul => 18 , clk_div => 20 , rskew => 0
) PORT MAP (
rst_ddr , clk_ddr , clkddro , clkread , lock , ddr_clk , ddr_clkb , ddr_clk_fb_out , ddr_clk_fb , ddr_cke , ddr_csb , ddr_web , ddr_rasb , ddr_casb , ddr_dm , ddr_dqs , ddr_ad , ddr_ba , ddr_dq , sdi , sdo
)
;
ddrc : COMPONENT ddrsp64a
GENERIC MAP (
memtech => 0 , hindex => 3 , haddr => 1024 , hmask => 3072 , ioaddr => 1 , iomask => 4095 , pwron => 1 , MHz => ( 18 * 100 ) / 20 , col => 9 , Mbyte => 256 , fast => 65 / ( 18 * 100 ) / 20 / 4
) PORT MAP (
rst_ahb , clkddri , clk_ahb , modahbsi , ahbso , sdi , sdo
)
;
END ARCHITECTURE;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/ec/memory_ec.vhd
|
2
|
92541
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/tech/cycloneiii/simprims/cycloneiii_components.vhd
|
2
|
36080
|
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/cycloneiii/simprims/cycloneiii_components.vhd
|
2
|
36080
|
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/dw02/mul_dw_gen.vhd
|
2
|
1956
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dw_mul_61x61
-- File: mul_dw_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: DW 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library DW02;
use DW02.DW02_components.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
u0 : DW02_mult_2_stage
generic map ( A_width => A'length, B_width => B'length )
port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/dw02/mul_dw_gen.vhd
|
2
|
1956
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dw_mul_61x61
-- File: mul_dw_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: DW 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library DW02;
use DW02.DW02_components.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
u0 : DW02_mult_2_stage
generic map ( A_width => A'length, B_width => B'length )
port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
mit
|
lxp32/lxp32-cpu
|
verify/lxp32/src/platform/ibus_adapter.vhd
|
2
|
2309
|
---------------------------------------------------------------------
-- IBUS adapter
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Converts the Low Latency Interface to WISHBONE registered
-- feedback protocol.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ibus_adapter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ibus_cyc_i: in std_logic;
ibus_stb_i: in std_logic;
ibus_cti_i: in std_logic_vector(2 downto 0);
ibus_bte_i: in std_logic_vector(1 downto 0);
ibus_ack_o: out std_logic;
ibus_adr_i: in std_logic_vector(29 downto 0);
ibus_dat_o: out std_logic_vector(31 downto 0);
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic
);
end entity;
architecture rtl of ibus_adapter is
constant burst_delay: integer:=5;
signal burst_delay_cnt: integer:=0;
signal delay_burst: std_logic;
signal re: std_logic;
signal requested: std_logic:='0';
signal adr: unsigned(29 downto 0);
signal ack: std_logic;
begin
-- Insert burst delay
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
burst_delay_cnt<=0;
elsif ibus_cyc_i='0' then
burst_delay_cnt<=burst_delay;
elsif burst_delay_cnt/=0 then
burst_delay_cnt<=burst_delay_cnt-1;
end if;
end if;
end process;
delay_burst<='1' when burst_delay_cnt/=0 else '0';
-- Generate ACK signal
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
requested<='0';
elsif lli_busy_i='0' then
requested<=re;
end if;
end if;
end process;
ack<=requested and not lli_busy_i;
-- Generate LLI signals
re<=(ibus_cyc_i and ibus_stb_i and not delay_burst) when ack='0' or
(ibus_cti_i="010" and ibus_bte_i="00") else '0';
adr<=unsigned(ibus_adr_i) when re='1' and ack='0' else
unsigned(ibus_adr_i)+1 when re='1' and ack='1' else
(others=>'-');
lli_re_o<=re;
lli_adr_o<=std_logic_vector(adr);
-- Generate IBUS signals
ibus_ack_o<=ack;
ibus_dat_o<=lli_dat_i when ack='1' else (others=>'-');
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram64.vhd
|
2
|
4010
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram64
-- File: syncram64.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity syncram64 is
generic (tech : integer := 0; abits : integer := 6);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000");
end;
architecture rtl of syncram64 is
component virtex2_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component artisan_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
component custom1_syncram64
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
s64 : if has_sram64(tech) = 1 generate
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
cust1: if tech = custom1 generate
x0 : custom1_syncram64 generic map (abits)
port map (clk, address, datain, dataout, enable, write);
end generate;
end generate;
nos64 : if has_sram64(tech) = 0 generate
x0 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1), testin);
x1 : syncram generic map (tech, abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0), testin);
end generate;
end;
|
mit
|
lxp32/lxp32-cpu
|
rtl/lxp32_scratchpad.vhd
|
2
|
1939
|
---------------------------------------------------------------------
-- Scratchpad
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- LXP32 register file implemented as a RAM block. Since we need
-- to read two registers simultaneously, the memory is duplicated.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_scratchpad is
port(
clk_i: in std_logic;
raddr1_i: in std_logic_vector(7 downto 0);
rdata1_o: out std_logic_vector(31 downto 0);
raddr2_i: in std_logic_vector(7 downto 0);
rdata2_o: out std_logic_vector(31 downto 0);
waddr_i: in std_logic_vector(7 downto 0);
we_i: in std_logic;
wdata_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_scratchpad is
signal wdata_reg: std_logic_vector(wdata_i'range);
signal ram1_rdata: std_logic_vector(31 downto 0);
signal ram2_rdata: std_logic_vector(31 downto 0);
signal ram1_collision: std_logic;
signal ram2_collision: std_logic;
begin
-- RAM 1
ram_inst1: entity work.lxp32_ram256x32(rtl)
port map(
clk_i=>clk_i,
we_i=>we_i,
waddr_i=>waddr_i,
wdata_i=>wdata_i,
re_i=>'1',
raddr_i=>raddr1_i,
rdata_o=>ram1_rdata
);
-- RAM 2
ram_inst2: entity work.lxp32_ram256x32(rtl)
port map(
clk_i=>clk_i,
we_i=>we_i,
waddr_i=>waddr_i,
wdata_i=>wdata_i,
re_i=>'1',
raddr_i=>raddr2_i,
rdata_o=>ram2_rdata
);
-- Read/write collision detection
process (clk_i) is
begin
if rising_edge(clk_i) then
wdata_reg<=wdata_i;
if waddr_i=raddr1_i and we_i='1' then
ram1_collision<='1';
else
ram1_collision<='0';
end if;
if waddr_i=raddr2_i and we_i='1' then
ram2_collision<='1';
else
ram2_collision<='0';
end if;
end if;
end process;
rdata1_o<=ram1_rdata when ram1_collision='0' else wdata_reg;
rdata2_o<=ram2_rdata when ram2_collision='0' else wdata_reg;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/pci/pcitb.vhd
|
2
|
9156
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI testbench
-- modules
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.ambatest.all;
package pcitb is
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
type pci_int_type is record
inta : std_logic;
intb : std_logic;
intc : std_logic;
intd : std_logic;
end record;
constant int_const : pci_int_type := (
inta => 'H',
intb => 'H',
intc => 'H',
intd => 'H');
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
int : pci_int_type;
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-- PCI emulators for TB
component pcitb_clkgen
generic (
mhz66 : boolean := false; -- PCI clock frequency. false = 33MHz, true = 66MHz
rstclocks : integer := 20); -- How long (in clks) the rst signal is asserted
port (
rsttrig : in std_logic; -- Asynchronous reset trig, active high
systclk : out pci_syst_type); -- clock and reset outputs
end component;
component pcitb_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
component pcitb_master_script
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
dbglevel : integer := 2; -- Debug level. Higher value means more debug information
maxburst : integer := 1024;
filename : string := "pci.cmd");
port (
pciin : in pci_type;
pciout : out pci_type
);
end component;
component pcitb_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
component pcitb_stimgen
generic (
slots : integer := 5; -- The number of slots in the test system
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
rsttrig : out std_logic;
tbi : out tbi_array_type;
tbo : in tbo_array_type
);
end component;
component pcitb_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
component pcitb_monitor is
generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (pciin : in pci_type);
end component;
end;
-- pragma translate_on
|
mit
|
lxp32/lxp32-cpu
|
rtl/lxp32_shifter.vhd
|
2
|
2717
|
---------------------------------------------------------------------
-- Barrel shifter
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs logical (unsigned) and arithmetic (signed) shifts
-- in both directions. Pipeline latency: 1 cycle.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_shifter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
d_i: in std_logic_vector(31 downto 0);
s_i: in std_logic_vector(4 downto 0);
right_i: in std_logic;
sig_i: in std_logic;
ce_o: out std_logic;
d_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_shifter is
signal data: std_logic_vector(d_i'range);
signal data_shifted: std_logic_vector(d_i'range);
signal fill: std_logic; -- 0 for unsigned shifts, sign bit for signed ones
signal fill_v: std_logic_vector(3 downto 0);
type cascades_type is array (4 downto 0) of std_logic_vector(d_i'range);
signal cascades: cascades_type;
signal stage2_data: std_logic_vector(d_i'range);
signal stage2_s: std_logic_vector(s_i'range);
signal stage2_fill: std_logic;
signal stage2_fill_v: std_logic_vector(15 downto 0);
signal stage2_right: std_logic;
signal ceo: std_logic:='0';
begin
-- Internally, data are shifted in left direction. For right shifts
-- we reverse the argument's bit order
data_gen: for i in data'range generate
data(i)<=d_i(i) when right_i='0' else d_i(d_i'high-i);
end generate;
-- A set of cascaded shifters shifting by powers of two
fill<=sig_i and data(0);
fill_v<=(others=>fill);
cascades(0)<=data(30 downto 0)&fill_v(0) when s_i(0)='1' else data;
cascades(1)<=cascades(0)(29 downto 0)&fill_v(1 downto 0) when s_i(1)='1' else cascades(0);
cascades(2)<=cascades(1)(27 downto 0)&fill_v(3 downto 0) when s_i(2)='1' else cascades(1);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
stage2_data<=(others=>'-');
stage2_s<=(others=>'-');
stage2_fill<='-';
stage2_right<='-';
else
ceo<=ce_i;
stage2_data<=cascades(2);
stage2_s<=s_i;
stage2_fill<=fill;
stage2_right<=right_i;
end if;
end if;
end process;
stage2_fill_v<=(others=>stage2_fill);
cascades(3)<=stage2_data(23 downto 0)&stage2_fill_v(7 downto 0) when stage2_s(3)='1' else stage2_data;
cascades(4)<=cascades(3)(15 downto 0)&stage2_fill_v(15 downto 0) when stage2_s(4)='1' else cascades(3);
-- Reverse bit order back, if needed
data_shifted_gen: for i in data_shifted'range generate
data_shifted(i)<=cascades(4)(i) when stage2_right='0' else cascades(4)(cascades(4)'high-i);
end generate;
d_o<=data_shifted;
ce_o<=ceo;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/memctrl/sdctrl.in.vhd
|
6
|
293
|
-- SDRAM controller
constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/can/can.vhd
|
2
|
5489
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: can
-- File: can.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: CAN component declartions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package can is
component can_mod
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic);
end component;
component can_oc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end component;
component can_mc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end component;
component can_rd
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end component;
component canmux
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end component;
-----------------------------------------------------------------------------
-- interface type declarations for can controller
-----------------------------------------------------------------------------
type can_in_type is record
rx: std_logic_vector(1 downto 0); -- receive lines
end record;
type can_out_type is record
tx: std_logic_vector(1 downto 0); -- transmit lines
en: std_logic_vector(1 downto 0); -- transmit enables
end record;
-----------------------------------------------------------------------------
-- component declaration for grcan controller
-----------------------------------------------------------------------------
component grcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
singleirq: integer := 0; -- single irq output
txchannels: integer range 1 to 16 := 1; -- 1 to 16 channels
rxchannels: integer range 1 to 16 := 1; -- 1 to 16 channels
ptrwidth: integer range 4 to 16 := 16); -- 16 to 64k messages
-- 2k to 8M bits
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/axcelerator/usbhc_axceleratorpkg.vhd
|
2
|
30540
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_axceleratorpkg
-- File: usbhc_axceleratorpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for axcelerator
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_axceleratorpkg is
component usbhc_axcelerator_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_axceleratorpkg;
package body usbhc_axceleratorpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_axceleratorpkg;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/ata/ata_inf.vhd
|
2
|
2852
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata_inf
-- File: ata_inf.vhd
-- Author: Erik Jagres, Gaisler Research
-- Description: ATA components and signals
------------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ata.all;
use gaisler.misc.all;
package ata_inf is
type slv_to_bm_type is record
prd_belec: std_logic;
en : std_logic;
dir : std_logic;
prdtb : std_logic_vector(31 downto 0);
end record;
constant SLV_TO_BM_RESET_VECTOR : slv_to_bm_type := ('0','0','0',(others=>'0'));
type bm_to_slv_type is record
err : std_logic;
done : std_logic;
cur_base : std_logic_vector(31 downto 0);
cur_cnt : std_logic_vector(15 downto 0);
end record;
constant BM_TO_SLV_RESET_VECTOR : bm_to_slv_type :=
('0','0',(others=>'0'),(others=>'0'));
type bm_to_ctrl_type is record
force_rdy : std_logic;
sel : std_logic;
ack : std_logic;
end record;
constant BM_TO_CTR_RESET_VECTOR : bm_to_ctrl_type := ('0','0','0');
type ctrl_to_bm_type is record
irq : std_logic;
ack : std_logic;
req : std_logic;
rx_empty : std_logic;
fifo_rdy : std_logic;
q : std_logic_vector(31 downto 0);
tip : std_logic;
rx_full : std_logic;
end record;
constant DMA_IN_RESET_VECTOR : ahb_dma_in_type :=
((others=>'0'),(others=>'0'),'0','0','0','0','0',"10");
type bmi_type is record
fr_mst : ahb_dma_out_type;
fr_slv : slv_to_bm_type;
fr_ctr : ctrl_to_bm_type;
end record;
type bmo_type is record
to_mst : ahb_dma_in_type;
to_slv : bm_to_slv_type;
to_ctr : bm_to_ctrl_type;
d : std_logic_vector(31 downto 0);
we : std_logic;
end record;
constant BMO_RESET_VECTOR : bmo_type :=
(DMA_IN_RESET_VECTOR,BM_TO_SLV_RESET_VECTOR,BM_TO_CTR_RESET_VECTOR,(others=>'0'),'0');
end ata_inf;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd
|
2
|
21959
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/leon3/grfpwx.vhd
|
2
|
9264
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grfpwx is
component grfpw
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
index : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
x0 : if netlist = 0 generate
grfpw0 : grfpw generic map (fabtech, memtech, mul, pclow, dsu, disas, index)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
x1 : if netlist = 1 generate
grfpw0 : grfpw_net generic map (fabtech, mul, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p generic map (memtech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (memtech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gleichmann/multiio/MultiIO.vhd
|
2
|
8952
|
--------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O Types and Components
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.amba.all;
package MultiIO is
-- maximum number of switches and LEDs
-- specific number that is used can be defined via a generic
constant N_SWITCHMAX : integer := 8;
constant N_LEDMAX : integer := 8;
constant N_BUTTONS : integer := 12; -- number of push-buttons
-- data width of the words for the codec configuration interface
constant N_CODECBITS : integer := 16;
-- data width of the words for the i2s digital samples
constant N_CODECI2SBITS : integer := 16;
-- the number of register bits that are assigned to the LCD
-- the enable control bit is set automatically
-- this constant should comprise the number of data bits as well
-- as the RW and RS control bits
constant N_LCDBITS : integer := 10;
-- number of bits to hold information for the (single/dual)
-- seven segment display;
constant N_SEVSEGBITS : integer := 16;
-- number of expansion connector i/o bits
constant N_EXPBITS : integer := 40;
-- number of high-speed connector bits per connector
constant N_HSCBITS : integer := 4;
-- number of childboard3 connector i/o bits
constant N_CB3 : integer := 32;
type asciichar_vect is array (16#30# to 16#46#) of character;
-- excerpt of the ASCII chart
constant ascii2char : asciichar_vect :=
-- -------------------------------------------
-- | 30 31 32 33 34 35 36 37 |
-- -------------------------------------------
('0', '1', '2', '3', '4', '5', '6', '7',
-- -------------------------------------------
-- | 38 39 3A 3B 3C 3D 3E 3F |
-- -------------------------------------------
'8', '9', ':', ';', '<', '=', '>', '?',
-- -------------------------------------------
-- | 40 41 42 43 44 45 46 |
-- -------------------------------------------
'@', 'A', 'B', 'C', 'D', 'E', 'F');
---------------------------------------------------------------------------------------
-- AUDIO CODEC
---------------------------------------------------------------------------------------
subtype tReg is std_ulogic_vector(N_CODECBITS-1 downto 0);
type tRegMap is array(10 downto 0) of tReg;
subtype tRegData is std_ulogic_vector(8 downto 0);
subtype tRegAddr is std_ulogic_vector(6 downto 0);
-- ADDRESS
constant cAddrLLI : tRegAddr := "0000000"; -- Left line input channel volume control
constant cAddrRLI : tRegAddr := "0000001"; -- Right line input channel volume control
constant cAddrLCH : tRegAddr := "0000010"; -- Left channel headphone volume control
constant cAddrRCH : tRegAddr := "0000011"; -- Right channel headphone volume control
constant cAddrAAP : tRegAddr := "0000100"; -- Analog audio path control
constant cAddrDAP : tRegAddr := "0000101"; -- Digital audio path control
constant cAddrPDC : tRegAddr := "0000110"; -- Power down control
constant cAddrDAI : tRegAddr := "0000111"; -- Digital audio interface format
constant cAddrSRC : tRegAddr := "0001000"; -- Sample rate control
constant cAddrDIA : tRegAddr := "0001001"; -- Digital interface activation
constant cAddrReset : tRegAddr := "0001111"; -- Reset register
-- Data
constant cDataLLI : tRegData := "100011111";
constant cDataRLI : tRegData := "100011111";
constant cDataLCH : tRegData := "011111111";
constant cDataRCH : tRegData := "011111111";
constant cDataAAP : tRegData := "000011010";
constant cDataDAP : tRegData := "000000000";
constant cDataPDC : tRegData := "000001010";
constant cDataDAI : tRegData := "000000010";
constant cDataSRC : tRegData := "010000000";
constant cDataDIA : tRegData := "000000001";
constant cdataInit : tRegData := "000000000";
-- Register
constant cRegLLI : tReg := cAddrLLI & cDataLLI;
constant cRegRLI : tReg := cAddrRLI & cDataRLI;
constant cRegLCH : tReg := cAddrLCH & cDataLCH;
constant cRegRCH : tReg := cAddrRCH & cDataRCH;
constant cRegAAP : tReg := cAddrAAP & cDataAAP;
constant cRegDAP : tReg := cAddrDAP & cDataDAP;
constant cRegPDC : tReg := cAddrPDC & cDataPDC;
constant cRegDAI : tReg := cAddrDAI & cDataDAI;
constant cRegSRC : tReg := cAddrSRC & cDataSRC;
constant cRegDIA : tReg := cAddrDIA & cDataDIA;
constant cRegReset : tReg := CAddrReset & cdataInit;
-- Register Map
constant cregmap : tRegMap := (
0 => cRegLLI,
1 => cRegRLI,
2 => cRegLCH,
3 => cRegRCH,
4 => cRegAAP,
5 => cRegDAP,
6 => cRegPDC,
7 => cRegDAI,
8 => cRegSRC,
9 => cRegDIA,
10 => cRegReset
);
---------------------------------------------------------------------------------------
type MultiIO_in_type is
record
switch_in : std_logic_vector(N_SWITCHMAX-1 downto 0); -- 8 DIL Switches
-- row input from the key matrix
row_in : std_logic_vector(3 downto 0);
-- expansion connector input bits
exp_in : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_in : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector input bits
cb3_in : std_logic_vector(N_CB3-1 downto 0);
end record;
type MultiIO_out_type is
record
-- signals for the 7 segment display
-- data bits 0 to 7 of the LCD
-- LED signals for the Hpe_midi
led_a_out : std_logic;
led_b_out : std_logic;
led_c_out : std_logic;
led_d_out : std_logic;
led_e_out : std_logic;
led_f_out : std_logic;
led_g_out : std_logic;
led_dp_out : std_logic;
-- common anode for enabling left and/or right digit
-- data bit 7 for the LCD
led_ca_out : std_logic_vector(1 downto 0);
-- enable output to LED's for the Hpe_midi
led_enable : std_logic;
-- LCD-only control signals
lcd_regsel : std_logic;
lcd_rw : std_logic;
lcd_enable : std_logic;
-- LED register for all boards except the Hpe_midi
led_out : std_logic_vector(N_LEDMAX-1 downto 0); -- 8 LEDs
-- column output to the key matrix
column_out : std_logic_vector(2 downto 0);
-- signals for the SPI audio codec
codec_mode : std_ulogic;
codec_mclk : std_ulogic;
codec_sclk : std_ulogic;
codec_sdin : std_ulogic;
codec_cs : std_ulogic;
codec_din : std_ulogic; -- I2S format serial data input to the sigma-delta stereo DAC
codec_bclk : std_ulogic; -- I2S serial-bit clock
-- codec_dout : in std_ulogic; -- I2S format serial data output from the sigma-delta stereo ADC
codec_lrcin : std_ulogic; -- I2S DAC-word clock signal
codec_lrcout : std_ulogic; -- I2S ADC-word clock signal
-- expansion connector output bits
exp_out : std_logic_vector(N_EXPBITS/2-1 downto 0);
hsc_out : std_logic_vector(N_HSCBITS-1 downto 0);
-- childboard3 connector output bits
-- cb3_out : std_logic_vector(N_CB3-1 downto 0);
end record;
component MultiIO_APB
generic
(
hpe_version : integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LED's
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches
n_leds : integer := 8 -- number of LEDs
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end component;
end package;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
VhdlParser/test/iu3PreLoad.vhd
|
1
|
21304
|
package iu3PreLoad is
TYPE log2arr IS ARRAY(0 TO 512) OF integer;
-- CONSTANT log2 : log2arr := (
-- 0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- OTHERS => 9);
-- CONSTANT log2x : log2arr := (
-- 0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- OTHERS => 9);
CONSTANT NTECH : integer := 32;
TYPE tech_ability_type IS ARRAY(0 TO NTECH) OF integer;
CONSTANT inferred : integer := 0;
CONSTANT virtex : integer := 1;
CONSTANT virtex2 : integer := 2;
CONSTANT memvirage : integer := 3;
CONSTANT axcel : integer := 4;
CONSTANT proasic : integer := 5;
CONSTANT atc18s : integer := 6;
CONSTANT altera : integer := 7;
CONSTANT umc : integer := 8;
CONSTANT rhumc : integer := 9;
CONSTANT apa3 : integer := 10;
CONSTANT spartan3 : integer := 11;
CONSTANT ihp25 : integer := 12;
CONSTANT rhlib18t : integer := 13;
CONSTANT virtex4 : integer := 14;
CONSTANT lattice : integer := 15;
CONSTANT ut25 : integer := 16;
CONSTANT spartan3e : integer := 17;
CONSTANT peregrine : integer := 18;
CONSTANT memartisan : integer := 19;
CONSTANT virtex5 : integer := 20;
CONSTANT custom1 : integer := 21;
CONSTANT ihp25rh : integer := 22;
CONSTANT stratix1 : integer := 23;
CONSTANT stratix2 : integer := 24;
CONSTANT eclipse : integer := 25;
CONSTANT stratix3 : integer := 26;
CONSTANT cyclone3 : integer := 27;
CONSTANT memvirage90 : integer := 28;
CONSTANT tsmc90 : integer := 29;
CONSTANT easic90 : integer := 30;
CONSTANT atc18rha : integer := 31;
CONSTANT smic013 : integer := 32;
-- CONSTANT is_fpga : tech_ability_type :=
-- (inferred => 1,
-- virtex => 1,
-- virtex2 => 1,
-- axcel => 1,
-- proasic => 1,
-- altera => 1,
-- apa3 => 1,
-- spartan3 => 1,
-- virtex4 => 1,
-- lattice => 1,
-- spartan3e => 1,
-- virtex5 => 1,
-- stratix1 => 1,
-- stratix2 => 1,
-- eclipse => 1,
-- stratix3 => 1,
-- cyclone3 => 1,
-- others => 0);
Constant zero32 : std_logic_vector(31 downto 0) := X"0000_0000";
CONSTANT zero64 : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
CONSTANT one32 : std_logic_vector(31 downto 0) := X"FFFF_FFFF";
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FSTOD : fpop_type := "011001001";
constant FDTOS : fpop_type := "011000110";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FSMULD : fpop_type := "001101001";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers (only 5 lsb bist are used)
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
SUBTYPE cword IS std_logic_vector ( 32 - 1 downto 0 );
TYPE cdatatype IS ARRAY ( 0 to 3 ) OF cword;
TYPE cpartype IS ARRAY ( 0 to 3 ) OF std_logic_vector ( 3 downto 0 );
TYPE iregfile_in_type IS RECORD
raddr1 : std_logic_vector ( 9 downto 0 );
raddr2 : std_logic_vector ( 9 downto 0 );
waddr : std_logic_vector ( 9 downto 0 );
wdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE iregfile_out_type IS RECORD
data1 : std_logic_vector ( 32 - 1 downto 0 );
data2 : std_logic_vector ( 32 - 1 downto 0 );
END RECORD;
TYPE cctrltype IS RECORD
burst : std_ulogic;
dfrz : std_ulogic;
ifrz : std_ulogic;
dsnoop : std_ulogic;
dcs : std_logic_vector ( 1 downto 0 );
ics : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE icache_in_type IS RECORD
rpc : std_logic_vector ( 31 downto 0 );
fpc : std_logic_vector ( 31 downto 0 );
dpc : std_logic_vector ( 31 downto 0 );
rbranch : std_ulogic;
fbranch : std_ulogic;
inull : std_ulogic;
su : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
fline : std_logic_vector ( 31 downto 3 );
pnull : std_ulogic;
END RECORD;
TYPE icache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic;
diagrdy : std_ulogic;
diagdata : std_logic_vector ( 32 - 1 downto 0 );
mds : std_ulogic;
cfg : std_logic_vector ( 31 downto 0 );
idle : std_ulogic;
END RECORD;
TYPE icdiag_in_type IS RECORD
addr : std_logic_vector ( 31 downto 0 );
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector ( 31 downto 11 );
pflushtyp : std_ulogic;
ilock : std_logic_vector ( 0 to 3 );
scanen : std_ulogic;
END RECORD;
TYPE dcache_in_type IS RECORD
asi : std_logic_vector ( 7 downto 0 );
maddress : std_logic_vector ( 31 downto 0 );
eaddress : std_logic_vector ( 31 downto 0 );
edata : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
dsuen : std_ulogic;
msu : std_ulogic;
esu : std_ulogic;
intack : std_ulogic;
END RECORD;
TYPE dcache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic;
scanen : std_ulogic;
testen : std_ulogic;
END RECORD;
TYPE tracebuf_in_type IS RECORD
addr : std_logic_vector ( 11 downto 0 );
data : std_logic_vector ( 127 downto 0 );
enable : std_logic;
write : std_logic_vector ( 3 downto 0 );
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE tracebuf_out_type IS RECORD
data : std_logic_vector ( 127 downto 0 );
END RECORD;
TYPE l3_irq_in_type IS RECORD
irl : std_logic_vector ( 3 downto 0 );
rst : std_ulogic;
run : std_ulogic;
END RECORD;
TYPE l3_irq_out_type IS RECORD
intack : std_ulogic;
irl : std_logic_vector ( 3 downto 0 );
pwd : std_ulogic;
END RECORD;
TYPE l3_debug_in_type IS RECORD
dsuen : std_ulogic;
denable : std_ulogic;
dbreak : std_ulogic;
step : std_ulogic;
halt : std_ulogic;
reset : std_ulogic;
dwrite : std_ulogic;
daddr : std_logic_vector ( 23 downto 2 );
ddata : std_logic_vector ( 31 downto 0 );
btrapa : std_ulogic;
btrape : std_ulogic;
berror : std_ulogic;
bwatch : std_ulogic;
bsoft : std_ulogic;
tenable : std_ulogic;
timer : std_logic_vector ( 30 downto 0 );
END RECORD;
TYPE l3_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
END RECORD;
TYPE l3_debug_in_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_in_type;
TYPE l3_debug_out_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_out_type;
TYPE div32_in_type IS RECORD
y : std_logic_vector ( 32 downto 0 );
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
END RECORD;
TYPE div32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE mul32_in_type IS RECORD
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector ( 39 downto 0 );
END RECORD;
TYPE mul32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 63 downto 0 );
END RECORD;
TYPE fp_rf_in_type IS RECORD
rd1addr : std_logic_vector ( 3 downto 0 );
rd2addr : std_logic_vector ( 3 downto 0 );
wraddr : std_logic_vector ( 3 downto 0 );
wrdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
END RECORD;
TYPE fp_rf_out_type IS RECORD
data1 : std_logic_vector ( 31 downto 0 );
data2 : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_pipeline_control_type IS RECORD
pc : std_logic_vector ( 31 downto 0 );
inst : std_logic_vector ( 31 downto 0 );
cnt : std_logic_vector ( 1 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
END RECORD;
TYPE fpc_debug_in_type IS RECORD
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic;
addr : std_logic_vector ( 4 downto 0 );
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_in_type IS RECORD
flush : std_ulogic;
exack : std_ulogic;
a_rs1 : std_logic_vector ( 4 downto 0 );
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector ( 31 downto 0 );
dbg : fpc_debug_in_type;
END RECORD;
TYPE fpc_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
exc : std_logic;
cc : std_logic_vector ( 1 downto 0 );
ccv : std_ulogic;
ldlock : std_logic;
holdn : std_ulogic;
dbg : fpc_debug_out_type;
END RECORD;
TYPE grfpu_in_type IS RECORD
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector ( 8 downto 0 );
op1 : std_logic_vector ( 63 downto 0 );
op2 : std_logic_vector ( 63 downto 0 );
opid : std_logic_vector ( 7 downto 0 );
flush : std_logic;
flushid : std_logic_vector ( 5 downto 0 );
rndmode : std_logic_vector ( 1 downto 0 );
req : std_logic;
END RECORD;
TYPE grfpu_out_type IS RECORD
res : std_logic_vector ( 63 downto 0 );
exc : std_logic_vector ( 5 downto 0 );
allow : std_logic_vector ( 2 downto 0 );
rdy : std_logic;
cc : std_logic_vector ( 1 downto 0 );
idout : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE grfpu_out_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_out_type;
TYPE grfpu_in_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_in_type;
end package iu3PreLoad;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/misc/apbps2.vhd
|
2
|
13132
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 1
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(13 downto 0); -- timer
reload : std_logic_vector(13 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(13 downto 0) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(13 downto 0);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := '0'; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := '0'; v.txstate := waitrequest;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(13) and not r.timer(13)) = '1' then
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,14);
else v.timer := r.reload; end if;
v.ps2clk := '1'; v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := '1';
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := '0'; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := '0'; v.ps2clkoe := '0';
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := '1';
v.ps2clkoe := '1';
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
v.timer := conv_std_logic_vector(fKHz/10,14);
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev 0, irq "
& tost(pirq));
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/uart/uart.vhd
|
2
|
2578
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package uart is
type uart_in_type is record
rxd : std_ulogic;
ctsn : std_ulogic;
extclk : std_ulogic;
end record;
type uart_out_type is record
rtsn : std_ulogic;
txd : std_ulogic;
scaler : std_logic_vector(17 downto 0);
txen : std_ulogic;
flow : std_ulogic;
rxen : std_ulogic;
end record;
component apbuart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end component;
component ahbuart
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type );
end component;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gleichmann/sim/txt_util.vhd
|
2
|
14269
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text : string);
-- prints the message when active
-- useful for debug switches
procedure print(active : boolean; text : string);
-- converts std_logic into a character
function chr(sl : std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv : std_logic_vector) return string;
-- converts boolean into a string
function str(b : boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int : integer) return character;
-- converts integer into string using specified base
function str(int : integer; base : integer) return string;
-- converts integer to string, using base 10
function str(int : integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv : std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character;
-- convert a character to lower case
function to_lower(c : character) return character;
-- convert a string to upper case
function to_upper(s : string) return string;
-- convert a string to lower case
function to_lower(s : string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c : character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string);
-- print string to a file and start new line
procedure print(file out_file : text;
new_string : in string);
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text : string) is
variable msg_line : line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active : boolean; text : string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c : character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file : text;
new_string : in string) is
variable l : line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character) is
variable l : line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file : text;
new_string : in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/maps/ddr_ireg.vhd
|
2
|
2043
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ireg
-- File: ddr_ireg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR input reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_ireg is
generic ( tech : integer);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ddr_ireg is
begin
inf : if not(tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5)) generate
inf0 : gen_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
xil : if tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5) generate
xil0 : unisim_iddr_reg generic map (tech) port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/snps/dw02/comp/DW02_components.vhd
|
6
|
1601
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end DW02_components;
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult_2_stage is
generic( A_width: POSITIVE;
B_width: POSITIVE);
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end;
architecture behav of DW02_mult_2_stage is
signal P_i : std_logic_vector(A_width+B_width-1 downto 0);
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) then
if TC = '1' then
P_i <= signed(A) * signed(B);
else
P_i <= unsigned(A) * unsigned(B);
end if;
else
P_i <= (others => 'X');
end if;
end process;
reg : process(CLK)
begin
if rising_edge(CLK) then
PRODUCT <= P_i;
end if;
end process;
end;
-- pragma translate_on
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/jtag/jtagcom.vhd
|
2
|
5510
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type
);
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tck : std_logic_vector(nsync-1 downto 0);
tck2 : std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
shift3: std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
tdi2 : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, r, tapo, dmao)
variable v : reg_type;
variable redge : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
write := r.addr(34); seq := r.data(32);
v.tck(0) := r.tck(nsync-1); v.tck(nsync-1) := tapo.tck; v.tck2 := r.tck(0); v.shift2 := r.shift(0); v.shift3 := r.shift2;
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tapo.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
v.tdi2 := r.tdi(0);
redge := not r.tck2 and r.tck(0);
vdmai.address := r.addr(31 downto 0); vdmai.wdata := r.data(31 downto 0);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := r.addr(33 downto 32);
vtapi.en := r.asel(0) or r.dsel(0);
if r.asel(0) = '1' then vtapi.tdo := r.addr(0); else vtapi.tdo := r.data(0); end if;
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge = '1' then
if r.asel(0) = '1' then v.addr := r.tdi2 & r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data := r.tdi2 & r.data(32 downto 1); end if;
end if;
elsif r.shift3 = '1' then
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
vdmai.size := "00";
when ahb =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := dmao.rdata;
v.state := shft;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr(34) := '0'; v.data(32) := '0';
end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/virage/simprims/virage_simprims.vhd
|
2
|
18477
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/misc/logan.vhd
|
2
|
16852
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
|
mit
|
franz/pocl
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examples/accel/rtl/platform/ffaccel_toplevel.vhdl
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2
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41324
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
use work.ffaccel_globals.all;
use work.ffaccel_imem_mau.all;
use work.ffaccel_toplevel_params.all;
entity ffaccel_toplevel is
generic (
axi_addr_width_g : integer := 17;
axi_id_width_g : integer := 12;
local_mem_addrw_g : integer := 10;
axi_offset_g : integer := 1136656384);
port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
locked : out std_logic);
end ffaccel_toplevel;
architecture structural of ffaccel_toplevel is
signal core_busy_wire : std_logic;
signal core_imem_en_x_wire : std_logic;
signal core_imem_addr_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal core_imem_data_wire : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
signal core_fu_DATA_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_aaddr_out_wire : std_logic_vector(fu_DATA_LSU_addrw_g-2-1 downto 0);
signal core_fu_DATA_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_DATA_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_DATA_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_DATA_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_PARAM_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_aaddr_out_wire : std_logic_vector(fu_PARAM_LSU_addrw_g-2-1 downto 0);
signal core_fu_PARAM_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_PARAM_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_PARAM_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_PARAM_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_SP_LSU_avalid_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_aready_in_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_aaddr_out_wire : std_logic_vector(fu_SP_LSU_addrw_g-2-1 downto 0);
signal core_fu_SP_LSU_awren_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_astrb_out_wire : std_logic_vector(3 downto 0);
signal core_fu_SP_LSU_adata_out_wire : std_logic_vector(31 downto 0);
signal core_fu_SP_LSU_rvalid_in_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_rready_out_wire : std_logic_vector(0 downto 0);
signal core_fu_SP_LSU_rdata_in_wire : std_logic_vector(31 downto 0);
signal core_fu_AQL_FU_read_idx_out_wire : std_logic_vector(63 downto 0);
signal core_fu_AQL_FU_read_idx_clear_in_wire : std_logic_vector(0 downto 0);
signal core_db_tta_nreset_wire : std_logic;
signal core_db_lockcnt_wire : std_logic_vector(63 downto 0);
signal core_db_cyclecnt_wire : std_logic_vector(63 downto 0);
signal core_db_pc_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal core_db_lockrq_wire : std_logic;
signal imem_array_instance_0_addr_wire : std_logic_vector(11 downto 0);
signal imem_array_instance_0_dataout_wire : std_logic_vector(42 downto 0);
signal imem_array_instance_0_en_x_wire : std_logic;
signal onchip_mem_data_a_aaddr_in_wire : std_logic_vector(9 downto 0);
signal onchip_mem_data_a_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_a_aready_out_wire : std_logic;
signal onchip_mem_data_a_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_data_a_avalid_in_wire : std_logic;
signal onchip_mem_data_a_awren_in_wire : std_logic;
signal onchip_mem_data_a_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_a_rready_in_wire : std_logic;
signal onchip_mem_data_a_rvalid_out_wire : std_logic;
signal onchip_mem_data_b_aaddr_in_wire : std_logic_vector(9 downto 0);
signal onchip_mem_data_b_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_b_aready_out_wire : std_logic;
signal onchip_mem_data_b_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_data_b_avalid_in_wire : std_logic;
signal onchip_mem_data_b_awren_in_wire : std_logic;
signal onchip_mem_data_b_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_data_b_rready_in_wire : std_logic;
signal onchip_mem_data_b_rvalid_out_wire : std_logic;
signal onchip_mem_param_a_aaddr_in_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal onchip_mem_param_a_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_a_aready_out_wire : std_logic;
signal onchip_mem_param_a_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_param_a_avalid_in_wire : std_logic;
signal onchip_mem_param_a_awren_in_wire : std_logic;
signal onchip_mem_param_a_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_a_rready_in_wire : std_logic;
signal onchip_mem_param_a_rvalid_out_wire : std_logic;
signal onchip_mem_param_b_aaddr_in_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal onchip_mem_param_b_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_b_aready_out_wire : std_logic;
signal onchip_mem_param_b_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_param_b_avalid_in_wire : std_logic;
signal onchip_mem_param_b_awren_in_wire : std_logic;
signal onchip_mem_param_b_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_param_b_rready_in_wire : std_logic;
signal onchip_mem_param_b_rvalid_out_wire : std_logic;
signal onchip_mem_scratchpad_aaddr_in_wire : std_logic_vector(7 downto 0);
signal onchip_mem_scratchpad_adata_in_wire : std_logic_vector(31 downto 0);
signal onchip_mem_scratchpad_aready_out_wire : std_logic;
signal onchip_mem_scratchpad_astrb_in_wire : std_logic_vector(3 downto 0);
signal onchip_mem_scratchpad_avalid_in_wire : std_logic;
signal onchip_mem_scratchpad_awren_in_wire : std_logic;
signal onchip_mem_scratchpad_rdata_out_wire : std_logic_vector(31 downto 0);
signal onchip_mem_scratchpad_rready_in_wire : std_logic;
signal onchip_mem_scratchpad_rvalid_out_wire : std_logic;
signal tta_accel_0_core_db_pc_wire : std_logic_vector(11 downto 0);
signal tta_accel_0_core_db_lockcnt_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_core_db_cyclecnt_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_core_db_tta_nreset_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_db_lockrq_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_avalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_aready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_aaddr_in_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_core_dmem_awren_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_astrb_in_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_core_dmem_adata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_dmem_rvalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_rready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_dmem_rdata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_a_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_aaddr_out_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_data_a_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_data_a_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_a_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_a_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_b_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_aaddr_out_wire : std_logic_vector(9 downto 0);
signal tta_accel_0_data_b_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_data_b_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_data_b_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_data_b_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_pmem_avalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_aready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_aaddr_in_wire : std_logic_vector(29 downto 0);
signal tta_accel_0_core_pmem_awren_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_astrb_in_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_core_pmem_adata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_core_pmem_rvalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_rready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_core_pmem_rdata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_a_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_aaddr_out_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal tta_accel_0_param_a_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_param_a_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_a_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_a_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_b_avalid_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_aready_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_aaddr_out_wire : std_logic_vector(local_mem_addrw_g-1 downto 0);
signal tta_accel_0_param_b_awren_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_astrb_out_wire : std_logic_vector(3 downto 0);
signal tta_accel_0_param_b_adata_out_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_param_b_rvalid_in_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_rready_out_wire : std_logic_vector(0 downto 0);
signal tta_accel_0_param_b_rdata_in_wire : std_logic_vector(31 downto 0);
signal tta_accel_0_aql_read_idx_in_wire : std_logic_vector(63 downto 0);
signal tta_accel_0_aql_read_idx_clear_out_wire : std_logic_vector(0 downto 0);
component ffaccel
generic (
core_id : integer);
port (
clk : in std_logic;
rstx : in std_logic;
busy : in std_logic;
imem_en_x : out std_logic;
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
locked : out std_logic;
fu_DATA_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_DATA_LSU_aaddr_out : out std_logic_vector(fu_DATA_LSU_addrw_g-2-1 downto 0);
fu_DATA_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_DATA_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_DATA_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_DATA_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_DATA_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_PARAM_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_aaddr_out : out std_logic_vector(fu_PARAM_LSU_addrw_g-2-1 downto 0);
fu_PARAM_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_PARAM_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_PARAM_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_PARAM_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_SP_LSU_avalid_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_aready_in : in std_logic_vector(1-1 downto 0);
fu_SP_LSU_aaddr_out : out std_logic_vector(fu_SP_LSU_addrw_g-2-1 downto 0);
fu_SP_LSU_awren_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_astrb_out : out std_logic_vector(4-1 downto 0);
fu_SP_LSU_adata_out : out std_logic_vector(32-1 downto 0);
fu_SP_LSU_rvalid_in : in std_logic_vector(1-1 downto 0);
fu_SP_LSU_rready_out : out std_logic_vector(1-1 downto 0);
fu_SP_LSU_rdata_in : in std_logic_vector(32-1 downto 0);
fu_AQL_FU_read_idx_out : out std_logic_vector(64-1 downto 0);
fu_AQL_FU_read_idx_clear_in : in std_logic_vector(1-1 downto 0);
db_tta_nreset : in std_logic;
db_lockcnt : out std_logic_vector(64-1 downto 0);
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_lockrq : in std_logic);
end component;
component tta_accel
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
bus_count_g : integer;
local_mem_addrw_g : integer;
sync_reset_g : integer;
axi_offset_g : integer;
full_debugger_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
s_axi_awid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_awlen : in std_logic_vector(8-1 downto 0);
s_axi_awsize : in std_logic_vector(3-1 downto 0);
s_axi_awburst : in std_logic_vector(2-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(4-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0);
s_axi_arlen : in std_logic_vector(8-1 downto 0);
s_axi_arsize : in std_logic_vector(3-1 downto 0);
s_axi_arburst : in std_logic_vector(2-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_id_width_g-1 downto 0);
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(32-1 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(3-1 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(32-1 downto 0);
m_axi_wstrb : out std_logic_vector(4-1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(32-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
m_axi_rdata : in std_logic_vector(32-1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
core_db_pc : in std_logic_vector(12-1 downto 0);
core_db_lockcnt : in std_logic_vector(64-1 downto 0);
core_db_cyclecnt : in std_logic_vector(64-1 downto 0);
core_db_tta_nreset : out std_logic_vector(1-1 downto 0);
core_db_lockrq : out std_logic_vector(1-1 downto 0);
core_dmem_avalid_in : in std_logic_vector(1-1 downto 0);
core_dmem_aready_out : out std_logic_vector(1-1 downto 0);
core_dmem_aaddr_in : in std_logic_vector(10-1 downto 0);
core_dmem_awren_in : in std_logic_vector(1-1 downto 0);
core_dmem_astrb_in : in std_logic_vector(4-1 downto 0);
core_dmem_adata_in : in std_logic_vector(32-1 downto 0);
core_dmem_rvalid_out : out std_logic_vector(1-1 downto 0);
core_dmem_rready_in : in std_logic_vector(1-1 downto 0);
core_dmem_rdata_out : out std_logic_vector(32-1 downto 0);
data_a_avalid_out : out std_logic_vector(1-1 downto 0);
data_a_aready_in : in std_logic_vector(1-1 downto 0);
data_a_aaddr_out : out std_logic_vector(10-1 downto 0);
data_a_awren_out : out std_logic_vector(1-1 downto 0);
data_a_astrb_out : out std_logic_vector(4-1 downto 0);
data_a_adata_out : out std_logic_vector(32-1 downto 0);
data_a_rvalid_in : in std_logic_vector(1-1 downto 0);
data_a_rready_out : out std_logic_vector(1-1 downto 0);
data_a_rdata_in : in std_logic_vector(32-1 downto 0);
data_b_avalid_out : out std_logic_vector(1-1 downto 0);
data_b_aready_in : in std_logic_vector(1-1 downto 0);
data_b_aaddr_out : out std_logic_vector(10-1 downto 0);
data_b_awren_out : out std_logic_vector(1-1 downto 0);
data_b_astrb_out : out std_logic_vector(4-1 downto 0);
data_b_adata_out : out std_logic_vector(32-1 downto 0);
data_b_rvalid_in : in std_logic_vector(1-1 downto 0);
data_b_rready_out : out std_logic_vector(1-1 downto 0);
data_b_rdata_in : in std_logic_vector(32-1 downto 0);
core_pmem_avalid_in : in std_logic_vector(1-1 downto 0);
core_pmem_aready_out : out std_logic_vector(1-1 downto 0);
core_pmem_aaddr_in : in std_logic_vector(30-1 downto 0);
core_pmem_awren_in : in std_logic_vector(1-1 downto 0);
core_pmem_astrb_in : in std_logic_vector(4-1 downto 0);
core_pmem_adata_in : in std_logic_vector(32-1 downto 0);
core_pmem_rvalid_out : out std_logic_vector(1-1 downto 0);
core_pmem_rready_in : in std_logic_vector(1-1 downto 0);
core_pmem_rdata_out : out std_logic_vector(32-1 downto 0);
param_a_avalid_out : out std_logic_vector(1-1 downto 0);
param_a_aready_in : in std_logic_vector(1-1 downto 0);
param_a_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_a_awren_out : out std_logic_vector(1-1 downto 0);
param_a_astrb_out : out std_logic_vector(4-1 downto 0);
param_a_adata_out : out std_logic_vector(32-1 downto 0);
param_a_rvalid_in : in std_logic_vector(1-1 downto 0);
param_a_rready_out : out std_logic_vector(1-1 downto 0);
param_a_rdata_in : in std_logic_vector(32-1 downto 0);
param_b_avalid_out : out std_logic_vector(1-1 downto 0);
param_b_aready_in : in std_logic_vector(1-1 downto 0);
param_b_aaddr_out : out std_logic_vector(local_mem_addrw_g-1 downto 0);
param_b_awren_out : out std_logic_vector(1-1 downto 0);
param_b_astrb_out : out std_logic_vector(4-1 downto 0);
param_b_adata_out : out std_logic_vector(32-1 downto 0);
param_b_rvalid_in : in std_logic_vector(1-1 downto 0);
param_b_rready_out : out std_logic_vector(1-1 downto 0);
param_b_rdata_in : in std_logic_vector(32-1 downto 0);
aql_read_idx_in : in std_logic_vector(64-1 downto 0);
aql_read_idx_clear_out : out std_logic_vector(1-1 downto 0));
end component;
component ffaccel_rom_array_comp
generic (
addrw : integer;
instrw : integer);
port (
clock : in std_logic;
addr : in std_logic_vector(addrw-1 downto 0);
dataout : out std_logic_vector(instrw-1 downto 0);
en_x : in std_logic);
end component;
component xilinx_dp_blockram
generic (
dataw_g : integer;
addrw_g : integer);
port (
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
a_aready_out : out std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_avalid_in : in std_logic;
a_awren_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
a_rready_in : in std_logic;
a_rvalid_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
b_aready_out : out std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_avalid_in : in std_logic;
b_awren_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
b_rready_in : in std_logic;
b_rvalid_out : out std_logic;
clk : in std_logic;
rstx : in std_logic);
end component;
component xilinx_blockram
generic (
dataw_g : integer;
addrw_g : integer);
port (
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);
aready_out : out std_logic;
astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
avalid_in : in std_logic;
awren_in : in std_logic;
clk : in std_logic;
rdata_out : out std_logic_vector(dataw_g-1 downto 0);
rready_in : in std_logic;
rstx : in std_logic;
rvalid_out : out std_logic);
end component;
begin
core_busy_wire <= '0';
imem_array_instance_0_en_x_wire <= core_imem_en_x_wire;
imem_array_instance_0_addr_wire <= core_imem_addr_wire;
core_imem_data_wire <= imem_array_instance_0_dataout_wire;
tta_accel_0_core_dmem_avalid_in_wire <= core_fu_DATA_LSU_avalid_out_wire;
core_fu_DATA_LSU_aready_in_wire <= tta_accel_0_core_dmem_aready_out_wire;
tta_accel_0_core_dmem_aaddr_in_wire <= core_fu_DATA_LSU_aaddr_out_wire;
tta_accel_0_core_dmem_awren_in_wire <= core_fu_DATA_LSU_awren_out_wire;
tta_accel_0_core_dmem_astrb_in_wire <= core_fu_DATA_LSU_astrb_out_wire;
tta_accel_0_core_dmem_adata_in_wire <= core_fu_DATA_LSU_adata_out_wire;
core_fu_DATA_LSU_rvalid_in_wire <= tta_accel_0_core_dmem_rvalid_out_wire;
tta_accel_0_core_dmem_rready_in_wire <= core_fu_DATA_LSU_rready_out_wire;
core_fu_DATA_LSU_rdata_in_wire <= tta_accel_0_core_dmem_rdata_out_wire;
tta_accel_0_core_pmem_avalid_in_wire <= core_fu_PARAM_LSU_avalid_out_wire;
core_fu_PARAM_LSU_aready_in_wire <= tta_accel_0_core_pmem_aready_out_wire;
tta_accel_0_core_pmem_aaddr_in_wire <= core_fu_PARAM_LSU_aaddr_out_wire;
tta_accel_0_core_pmem_awren_in_wire <= core_fu_PARAM_LSU_awren_out_wire;
tta_accel_0_core_pmem_astrb_in_wire <= core_fu_PARAM_LSU_astrb_out_wire;
tta_accel_0_core_pmem_adata_in_wire <= core_fu_PARAM_LSU_adata_out_wire;
core_fu_PARAM_LSU_rvalid_in_wire <= tta_accel_0_core_pmem_rvalid_out_wire;
tta_accel_0_core_pmem_rready_in_wire <= core_fu_PARAM_LSU_rready_out_wire;
core_fu_PARAM_LSU_rdata_in_wire <= tta_accel_0_core_pmem_rdata_out_wire;
onchip_mem_scratchpad_avalid_in_wire <= core_fu_SP_LSU_avalid_out_wire(0);
core_fu_SP_LSU_aready_in_wire(0) <= onchip_mem_scratchpad_aready_out_wire;
onchip_mem_scratchpad_aaddr_in_wire <= core_fu_SP_LSU_aaddr_out_wire;
onchip_mem_scratchpad_awren_in_wire <= core_fu_SP_LSU_awren_out_wire(0);
onchip_mem_scratchpad_astrb_in_wire <= core_fu_SP_LSU_astrb_out_wire;
onchip_mem_scratchpad_adata_in_wire <= core_fu_SP_LSU_adata_out_wire;
core_fu_SP_LSU_rvalid_in_wire(0) <= onchip_mem_scratchpad_rvalid_out_wire;
onchip_mem_scratchpad_rready_in_wire <= core_fu_SP_LSU_rready_out_wire(0);
core_fu_SP_LSU_rdata_in_wire <= onchip_mem_scratchpad_rdata_out_wire;
tta_accel_0_aql_read_idx_in_wire <= core_fu_AQL_FU_read_idx_out_wire;
core_fu_AQL_FU_read_idx_clear_in_wire <= tta_accel_0_aql_read_idx_clear_out_wire;
core_db_tta_nreset_wire <= tta_accel_0_core_db_tta_nreset_wire(0);
tta_accel_0_core_db_lockcnt_wire <= core_db_lockcnt_wire;
tta_accel_0_core_db_cyclecnt_wire <= core_db_cyclecnt_wire;
tta_accel_0_core_db_pc_wire <= core_db_pc_wire;
core_db_lockrq_wire <= tta_accel_0_core_db_lockrq_wire(0);
onchip_mem_data_a_avalid_in_wire <= tta_accel_0_data_a_avalid_out_wire(0);
tta_accel_0_data_a_aready_in_wire(0) <= onchip_mem_data_a_aready_out_wire;
onchip_mem_data_a_aaddr_in_wire <= tta_accel_0_data_a_aaddr_out_wire;
onchip_mem_data_a_awren_in_wire <= tta_accel_0_data_a_awren_out_wire(0);
onchip_mem_data_a_astrb_in_wire <= tta_accel_0_data_a_astrb_out_wire;
onchip_mem_data_a_adata_in_wire <= tta_accel_0_data_a_adata_out_wire;
tta_accel_0_data_a_rvalid_in_wire(0) <= onchip_mem_data_a_rvalid_out_wire;
onchip_mem_data_a_rready_in_wire <= tta_accel_0_data_a_rready_out_wire(0);
tta_accel_0_data_a_rdata_in_wire <= onchip_mem_data_a_rdata_out_wire;
onchip_mem_data_b_avalid_in_wire <= tta_accel_0_data_b_avalid_out_wire(0);
tta_accel_0_data_b_aready_in_wire(0) <= onchip_mem_data_b_aready_out_wire;
onchip_mem_data_b_aaddr_in_wire <= tta_accel_0_data_b_aaddr_out_wire;
onchip_mem_data_b_awren_in_wire <= tta_accel_0_data_b_awren_out_wire(0);
onchip_mem_data_b_astrb_in_wire <= tta_accel_0_data_b_astrb_out_wire;
onchip_mem_data_b_adata_in_wire <= tta_accel_0_data_b_adata_out_wire;
tta_accel_0_data_b_rvalid_in_wire(0) <= onchip_mem_data_b_rvalid_out_wire;
onchip_mem_data_b_rready_in_wire <= tta_accel_0_data_b_rready_out_wire(0);
tta_accel_0_data_b_rdata_in_wire <= onchip_mem_data_b_rdata_out_wire;
onchip_mem_param_a_avalid_in_wire <= tta_accel_0_param_a_avalid_out_wire(0);
tta_accel_0_param_a_aready_in_wire(0) <= onchip_mem_param_a_aready_out_wire;
onchip_mem_param_a_aaddr_in_wire <= tta_accel_0_param_a_aaddr_out_wire;
onchip_mem_param_a_awren_in_wire <= tta_accel_0_param_a_awren_out_wire(0);
onchip_mem_param_a_astrb_in_wire <= tta_accel_0_param_a_astrb_out_wire;
onchip_mem_param_a_adata_in_wire <= tta_accel_0_param_a_adata_out_wire;
tta_accel_0_param_a_rvalid_in_wire(0) <= onchip_mem_param_a_rvalid_out_wire;
onchip_mem_param_a_rready_in_wire <= tta_accel_0_param_a_rready_out_wire(0);
tta_accel_0_param_a_rdata_in_wire <= onchip_mem_param_a_rdata_out_wire;
onchip_mem_param_b_avalid_in_wire <= tta_accel_0_param_b_avalid_out_wire(0);
tta_accel_0_param_b_aready_in_wire(0) <= onchip_mem_param_b_aready_out_wire;
onchip_mem_param_b_aaddr_in_wire <= tta_accel_0_param_b_aaddr_out_wire;
onchip_mem_param_b_awren_in_wire <= tta_accel_0_param_b_awren_out_wire(0);
onchip_mem_param_b_astrb_in_wire <= tta_accel_0_param_b_astrb_out_wire;
onchip_mem_param_b_adata_in_wire <= tta_accel_0_param_b_adata_out_wire;
tta_accel_0_param_b_rvalid_in_wire(0) <= onchip_mem_param_b_rvalid_out_wire;
onchip_mem_param_b_rready_in_wire <= tta_accel_0_param_b_rready_out_wire(0);
tta_accel_0_param_b_rdata_in_wire <= onchip_mem_param_b_rdata_out_wire;
core : ffaccel
generic map (
core_id => 0)
port map (
clk => clk,
rstx => rstx,
busy => core_busy_wire,
imem_en_x => core_imem_en_x_wire,
imem_addr => core_imem_addr_wire,
imem_data => core_imem_data_wire,
locked => locked,
fu_DATA_LSU_avalid_out => core_fu_DATA_LSU_avalid_out_wire,
fu_DATA_LSU_aready_in => core_fu_DATA_LSU_aready_in_wire,
fu_DATA_LSU_aaddr_out => core_fu_DATA_LSU_aaddr_out_wire,
fu_DATA_LSU_awren_out => core_fu_DATA_LSU_awren_out_wire,
fu_DATA_LSU_astrb_out => core_fu_DATA_LSU_astrb_out_wire,
fu_DATA_LSU_adata_out => core_fu_DATA_LSU_adata_out_wire,
fu_DATA_LSU_rvalid_in => core_fu_DATA_LSU_rvalid_in_wire,
fu_DATA_LSU_rready_out => core_fu_DATA_LSU_rready_out_wire,
fu_DATA_LSU_rdata_in => core_fu_DATA_LSU_rdata_in_wire,
fu_PARAM_LSU_avalid_out => core_fu_PARAM_LSU_avalid_out_wire,
fu_PARAM_LSU_aready_in => core_fu_PARAM_LSU_aready_in_wire,
fu_PARAM_LSU_aaddr_out => core_fu_PARAM_LSU_aaddr_out_wire,
fu_PARAM_LSU_awren_out => core_fu_PARAM_LSU_awren_out_wire,
fu_PARAM_LSU_astrb_out => core_fu_PARAM_LSU_astrb_out_wire,
fu_PARAM_LSU_adata_out => core_fu_PARAM_LSU_adata_out_wire,
fu_PARAM_LSU_rvalid_in => core_fu_PARAM_LSU_rvalid_in_wire,
fu_PARAM_LSU_rready_out => core_fu_PARAM_LSU_rready_out_wire,
fu_PARAM_LSU_rdata_in => core_fu_PARAM_LSU_rdata_in_wire,
fu_SP_LSU_avalid_out => core_fu_SP_LSU_avalid_out_wire,
fu_SP_LSU_aready_in => core_fu_SP_LSU_aready_in_wire,
fu_SP_LSU_aaddr_out => core_fu_SP_LSU_aaddr_out_wire,
fu_SP_LSU_awren_out => core_fu_SP_LSU_awren_out_wire,
fu_SP_LSU_astrb_out => core_fu_SP_LSU_astrb_out_wire,
fu_SP_LSU_adata_out => core_fu_SP_LSU_adata_out_wire,
fu_SP_LSU_rvalid_in => core_fu_SP_LSU_rvalid_in_wire,
fu_SP_LSU_rready_out => core_fu_SP_LSU_rready_out_wire,
fu_SP_LSU_rdata_in => core_fu_SP_LSU_rdata_in_wire,
fu_AQL_FU_read_idx_out => core_fu_AQL_FU_read_idx_out_wire,
fu_AQL_FU_read_idx_clear_in => core_fu_AQL_FU_read_idx_clear_in_wire,
db_tta_nreset => core_db_tta_nreset_wire,
db_lockcnt => core_db_lockcnt_wire,
db_cyclecnt => core_db_cyclecnt_wire,
db_pc => core_db_pc_wire,
db_lockrq => core_db_lockrq_wire);
tta_accel_0 : tta_accel
generic map (
core_count_g => 1,
axi_addr_width_g => axi_addr_width_g,
axi_id_width_g => axi_id_width_g,
imem_data_width_g => 43,
imem_addr_width_g => 12,
bus_count_g => 2,
local_mem_addrw_g => local_mem_addrw_g,
sync_reset_g => 0,
axi_offset_g => axi_offset_g,
full_debugger_g => 0,
dmem_data_width_g => 32,
dmem_addr_width_g => 10,
pmem_data_width_g => 32,
pmem_addr_width_g => 30)
port map (
clk => clk,
rstx => rstx,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awprot => m_axi_awprot,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
m_axi_rdata => m_axi_rdata,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
core_db_pc => tta_accel_0_core_db_pc_wire,
core_db_lockcnt => tta_accel_0_core_db_lockcnt_wire,
core_db_cyclecnt => tta_accel_0_core_db_cyclecnt_wire,
core_db_tta_nreset => tta_accel_0_core_db_tta_nreset_wire,
core_db_lockrq => tta_accel_0_core_db_lockrq_wire,
core_dmem_avalid_in => tta_accel_0_core_dmem_avalid_in_wire,
core_dmem_aready_out => tta_accel_0_core_dmem_aready_out_wire,
core_dmem_aaddr_in => tta_accel_0_core_dmem_aaddr_in_wire,
core_dmem_awren_in => tta_accel_0_core_dmem_awren_in_wire,
core_dmem_astrb_in => tta_accel_0_core_dmem_astrb_in_wire,
core_dmem_adata_in => tta_accel_0_core_dmem_adata_in_wire,
core_dmem_rvalid_out => tta_accel_0_core_dmem_rvalid_out_wire,
core_dmem_rready_in => tta_accel_0_core_dmem_rready_in_wire,
core_dmem_rdata_out => tta_accel_0_core_dmem_rdata_out_wire,
data_a_avalid_out => tta_accel_0_data_a_avalid_out_wire,
data_a_aready_in => tta_accel_0_data_a_aready_in_wire,
data_a_aaddr_out => tta_accel_0_data_a_aaddr_out_wire,
data_a_awren_out => tta_accel_0_data_a_awren_out_wire,
data_a_astrb_out => tta_accel_0_data_a_astrb_out_wire,
data_a_adata_out => tta_accel_0_data_a_adata_out_wire,
data_a_rvalid_in => tta_accel_0_data_a_rvalid_in_wire,
data_a_rready_out => tta_accel_0_data_a_rready_out_wire,
data_a_rdata_in => tta_accel_0_data_a_rdata_in_wire,
data_b_avalid_out => tta_accel_0_data_b_avalid_out_wire,
data_b_aready_in => tta_accel_0_data_b_aready_in_wire,
data_b_aaddr_out => tta_accel_0_data_b_aaddr_out_wire,
data_b_awren_out => tta_accel_0_data_b_awren_out_wire,
data_b_astrb_out => tta_accel_0_data_b_astrb_out_wire,
data_b_adata_out => tta_accel_0_data_b_adata_out_wire,
data_b_rvalid_in => tta_accel_0_data_b_rvalid_in_wire,
data_b_rready_out => tta_accel_0_data_b_rready_out_wire,
data_b_rdata_in => tta_accel_0_data_b_rdata_in_wire,
core_pmem_avalid_in => tta_accel_0_core_pmem_avalid_in_wire,
core_pmem_aready_out => tta_accel_0_core_pmem_aready_out_wire,
core_pmem_aaddr_in => tta_accel_0_core_pmem_aaddr_in_wire,
core_pmem_awren_in => tta_accel_0_core_pmem_awren_in_wire,
core_pmem_astrb_in => tta_accel_0_core_pmem_astrb_in_wire,
core_pmem_adata_in => tta_accel_0_core_pmem_adata_in_wire,
core_pmem_rvalid_out => tta_accel_0_core_pmem_rvalid_out_wire,
core_pmem_rready_in => tta_accel_0_core_pmem_rready_in_wire,
core_pmem_rdata_out => tta_accel_0_core_pmem_rdata_out_wire,
param_a_avalid_out => tta_accel_0_param_a_avalid_out_wire,
param_a_aready_in => tta_accel_0_param_a_aready_in_wire,
param_a_aaddr_out => tta_accel_0_param_a_aaddr_out_wire,
param_a_awren_out => tta_accel_0_param_a_awren_out_wire,
param_a_astrb_out => tta_accel_0_param_a_astrb_out_wire,
param_a_adata_out => tta_accel_0_param_a_adata_out_wire,
param_a_rvalid_in => tta_accel_0_param_a_rvalid_in_wire,
param_a_rready_out => tta_accel_0_param_a_rready_out_wire,
param_a_rdata_in => tta_accel_0_param_a_rdata_in_wire,
param_b_avalid_out => tta_accel_0_param_b_avalid_out_wire,
param_b_aready_in => tta_accel_0_param_b_aready_in_wire,
param_b_aaddr_out => tta_accel_0_param_b_aaddr_out_wire,
param_b_awren_out => tta_accel_0_param_b_awren_out_wire,
param_b_astrb_out => tta_accel_0_param_b_astrb_out_wire,
param_b_adata_out => tta_accel_0_param_b_adata_out_wire,
param_b_rvalid_in => tta_accel_0_param_b_rvalid_in_wire,
param_b_rready_out => tta_accel_0_param_b_rready_out_wire,
param_b_rdata_in => tta_accel_0_param_b_rdata_in_wire,
aql_read_idx_in => tta_accel_0_aql_read_idx_in_wire,
aql_read_idx_clear_out => tta_accel_0_aql_read_idx_clear_out_wire);
imem_array_instance_0 : ffaccel_rom_array_comp
generic map (
addrw => IMEMADDRWIDTH,
instrw => IMEMMAUWIDTH*IMEMWIDTHINMAUS)
port map (
clock => clk,
addr => imem_array_instance_0_addr_wire,
dataout => imem_array_instance_0_dataout_wire,
en_x => imem_array_instance_0_en_x_wire);
onchip_mem_data : xilinx_dp_blockram
generic map (
dataw_g => 32,
addrw_g => 10)
port map (
a_aaddr_in => onchip_mem_data_a_aaddr_in_wire,
a_adata_in => onchip_mem_data_a_adata_in_wire,
a_aready_out => onchip_mem_data_a_aready_out_wire,
a_astrb_in => onchip_mem_data_a_astrb_in_wire,
a_avalid_in => onchip_mem_data_a_avalid_in_wire,
a_awren_in => onchip_mem_data_a_awren_in_wire,
a_rdata_out => onchip_mem_data_a_rdata_out_wire,
a_rready_in => onchip_mem_data_a_rready_in_wire,
a_rvalid_out => onchip_mem_data_a_rvalid_out_wire,
b_aaddr_in => onchip_mem_data_b_aaddr_in_wire,
b_adata_in => onchip_mem_data_b_adata_in_wire,
b_aready_out => onchip_mem_data_b_aready_out_wire,
b_astrb_in => onchip_mem_data_b_astrb_in_wire,
b_avalid_in => onchip_mem_data_b_avalid_in_wire,
b_awren_in => onchip_mem_data_b_awren_in_wire,
b_rdata_out => onchip_mem_data_b_rdata_out_wire,
b_rready_in => onchip_mem_data_b_rready_in_wire,
b_rvalid_out => onchip_mem_data_b_rvalid_out_wire,
clk => clk,
rstx => rstx);
onchip_mem_param : xilinx_dp_blockram
generic map (
dataw_g => 32,
addrw_g => local_mem_addrw_g)
port map (
a_aaddr_in => onchip_mem_param_a_aaddr_in_wire,
a_adata_in => onchip_mem_param_a_adata_in_wire,
a_aready_out => onchip_mem_param_a_aready_out_wire,
a_astrb_in => onchip_mem_param_a_astrb_in_wire,
a_avalid_in => onchip_mem_param_a_avalid_in_wire,
a_awren_in => onchip_mem_param_a_awren_in_wire,
a_rdata_out => onchip_mem_param_a_rdata_out_wire,
a_rready_in => onchip_mem_param_a_rready_in_wire,
a_rvalid_out => onchip_mem_param_a_rvalid_out_wire,
b_aaddr_in => onchip_mem_param_b_aaddr_in_wire,
b_adata_in => onchip_mem_param_b_adata_in_wire,
b_aready_out => onchip_mem_param_b_aready_out_wire,
b_astrb_in => onchip_mem_param_b_astrb_in_wire,
b_avalid_in => onchip_mem_param_b_avalid_in_wire,
b_awren_in => onchip_mem_param_b_awren_in_wire,
b_rdata_out => onchip_mem_param_b_rdata_out_wire,
b_rready_in => onchip_mem_param_b_rready_in_wire,
b_rvalid_out => onchip_mem_param_b_rvalid_out_wire,
clk => clk,
rstx => rstx);
onchip_mem_scratchpad : xilinx_blockram
generic map (
dataw_g => 32,
addrw_g => 8)
port map (
aaddr_in => onchip_mem_scratchpad_aaddr_in_wire,
adata_in => onchip_mem_scratchpad_adata_in_wire,
aready_out => onchip_mem_scratchpad_aready_out_wire,
astrb_in => onchip_mem_scratchpad_astrb_in_wire,
avalid_in => onchip_mem_scratchpad_avalid_in_wire,
awren_in => onchip_mem_scratchpad_awren_in_wire,
clk => clk,
rdata_out => onchip_mem_scratchpad_rdata_out_wire,
rready_in => onchip_mem_scratchpad_rready_in_wire,
rstx => rstx,
rvalid_out => onchip_mem_scratchpad_rvalid_out_wire);
end structural;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/leon3/acache.vhd
|
2
|
10085
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: acache
-- File: acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between I/D cache controllers and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
entity acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of acache is
-- cache control register type
type reg_type is record
bg : std_ulogic; -- bus grant
bo : std_ulogic; -- bus owner
ba : std_ulogic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_ulogic; -- retry/split pending
werr : std_ulogic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
lock : std_ulogic; -- keep bus locked during SWAP sequence
hcache : std_ulogic;
iacc : std_ulogic;
dannul : std_ulogic;
end record;
type reg2_type is record
reqmsk : std_logic_vector(1 downto 0);
hclken2 : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(scache : std_ulogic;
haddr : std_logic_vector(3 downto 0); cached : integer) return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return(scache); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, hclken, ahbso, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hlock : std_ulogic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_ulogic; -- bus request
variable iready, dready : std_ulogic;
variable igrant, dgrant : std_ulogic;
variable iretry, dretry : std_ulogic;
variable ihcache, dhcache, dec_hcache : std_ulogic;
variable imexc, dmexc, nbo, ireq, dreq : std_ulogic;
variable su, nb : std_ulogic;
variable scanen : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; iready := '0'; v.werr := '0'; v2 := r2;
dready := '0'; igrant := '0'; dgrant := '0';
imexc := '0'; dmexc := '0'; hlock := '0'; iretry := '0'; dretry := '0';
ihcache := '0'; dhcache := '0'; su := '0'; --hcache := ahbi.hcache;
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
-- generate AHB signals
ireq := mcii.req;
dreq := mcdi.req and not r.dannul;
if (clk2x /= 0) then ireq := ireq and r2.reqmsk(1); dreq := dreq and r2.reqmsk(0); end if;
hbusreq := ireq or dreq;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
hwdata := mcdi.data;
nbo := (dreq and not (r.ba and mcii.req and not r.bo));
if (nbo and mcdi.lock and not r.hlocken) = '1' then htrans := HTRANS_IDLE; end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = '0' then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if (ireq and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then
hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (ireq and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
else
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if;
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (dreq and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := not mcdi.lock or r.hlocken; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = '0' then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
else
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1'; v.lock := mcdi.lock and mcdi.read;
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock;
end if;
if r.lock = '1' then hlock := mcdi.lock; end if;
if (r.lock and nbo) = '1' then v.lock := '0'; end if;
-- decode cacheability
if (nbo = '1') and ((hsize = "011") or ((dec_hcache and mcdi.read and mcdi.cache) = '1')) then
hsize := "010"; haddr(1 downto 0) := "00";
end if;
if ahbi.hready = '1' then
v.iacc := r.bg and igrant;
if r.iacc = '1' then v.dannul := iretry;
elsif r.bg = '1' then v.dannul := '0'; end if;
v.bo := nbo; v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then v.hlocken := v.hlocken and r2.reqmsk(0); end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
if (clk2x /= 0) then
v2.hclken2 := hclken;
if (hclken = '1') then
v2.reqmsk := mcii.req & mcdi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "11"; end if;
end if;
end if;
-- reset operation
if rst = '0' then
v.bg := '0'; v.bo := '0'; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.lock := '0'; v.hlocken := '0'; v2.reqmsk := "00";
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq and not r.lb and not (((r.bo and r.ba) or nb) and r.bg and nbo);
ahbo.hwdata <= hwdata;
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= "11" & su & nbo;
ahbo.hindex <= hindex;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
mcdo.par <= (others => '0');
mcio.par <= (others => '0');
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbi.hrdata; mcdo.data <= ahbi.hrdata;
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then r2 <= r2in; end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "00";
end generate;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/maps/regfile_3p.vhd
|
2
|
3072
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p
-- File: regfile_3p.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
entity regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of regfile_3p is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1) or
(((tech = spartan3) or (tech = spartan3e) or (tech = virtex2) or (tech = virtex4) or (tech = virtex5)) and (abits <= 5));
begin
s0 : if rfinfer generate
rhu : generic_regfile_3p generic map (tech, abits, dbits, wrfst, numregs)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
s1 : if not rfinfer generate
pere : if tech = peregrine generate
rfhard : peregrine_regfile_3p generic map (abits, dbits)
port map ( wclk, waddr, wdata, we, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
dp : if tech /= peregrine generate
x0 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re1, raddr1, rdata1, wclk, we, waddr, wdata, testin);
x1 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re2, raddr2, rdata2, wclk, we, waddr, wdata, testin);
end generate;
end generate;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/esa/pci/pcicomp.vhd
|
2
|
725
|
library ieee;
library grlib;
use grlib.amba.all;
use ieee.std_logic_1164.all;
package pcicomp is
component pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
end package;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Defense/iu33Attacks.vhd
|
1
|
108459
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
SIGNAL hackStateM1 : std_logic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, triggerCPFault)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
END IF;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
mem_attack : process(clk)begin
if(rising_edge(clk))then
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
|
mit
|
lxp32/lxp32-cpu
|
verify/lxp32/src/tb/tb_pkg_body.vhd
|
2
|
2411
|
---------------------------------------------------------------------
-- LXP32 testbench package body
--
-- Part of the LXP32 testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Auxiliary package body for the LXP32 testbench
---------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common_pkg.all;
package body tb_pkg is
procedure load_ram(
filename: string;
signal clk: in std_logic;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type
) is
file f: text open read_mode is filename;
variable i: integer:=0;
variable l: line;
variable v: bit_vector(31 downto 0);
begin
wait until rising_edge(clk);
report "Loading program RAM from """&filename&"""";
while not endfile(f) loop
readline(f,l);
read(l,v);
assert i<c_max_program_size report "Error: program size is too large" severity failure;
soc_in.cyc<='1';
soc_in.stb<='1';
soc_in.we<='1';
soc_in.sel<=(others=>'1');
soc_in.adr<=std_logic_vector(to_unsigned(i,30));
soc_in.dat<=to_stdlogicvector(v);
wait until rising_edge(clk) and soc_out.ack='1';
i:=i+1;
end loop;
report integer'image(i)&" words loaded from """&filename&"""";
soc_in.cyc<='0';
soc_in.stb<='0';
wait until rising_edge(clk);
end procedure;
procedure run_test(
filename: string;
signal clk: in std_logic;
signal globals: out soc_globals_type;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type;
signal result: in monitor_out_type
) is
begin
-- Assert SoC and CPU resets
wait until rising_edge(clk);
globals.rst_i<='1';
globals.cpu_rst_i<='1';
wait until rising_edge(clk);
-- Deassert SoC reset, leave CPU in reset state for now
globals.rst_i<='0';
wait until rising_edge(clk);
-- Load RAM
load_ram(filename,clk,soc_in,soc_out);
-- Deassert CPU reset
globals.cpu_rst_i<='0';
while result.valid/='1' loop
wait until rising_edge(clk);
end loop;
-- Analyze result
if result.data=X"00000001" then
report "TEST """&filename&""" RESULT: SUCCESS (return code 0x"&
hex_string(result.data)&")";
else
report "TEST """&filename&""" RESULT: FAILURE (return code 0x"&
hex_string(result.data)&")" severity failure;
end if;
end procedure;
end package body;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/ata/atactrl_dma.vhd
|
2
|
18942
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl
-- File: atactrl.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ata.all;
use gaisler.misc.all; --2007-1-16
use gaisler.ata_inf.all;
library opencores;
use opencores.occomp.all;
entity atactrl_dma is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic;
dmarq : in std_logic
);
end;
architecture rtl of atactrl_dma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component atahost_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
-- DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
-- DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
-- DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
fr_BM : in bm_to_slv_type;
to_BM : out slv_to_bm_type
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
);
end component atahost_amba_slave;
component atahost_ahbmst is
generic(fdepth : integer := 8);
Port(clk : in std_logic;
rst : in std_logic;
i : in bmi_type;
o : out bmo_type
);
end component atahost_ahbmst;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
-- signal PIOsel,s_bmen : std_logic; -- controller select, IDE devices select
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal s_PIO_cmdport_T1, s_PIO_cmdport_T2, s_PIO_cmdport_T4, s_PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal s_PIO_dport0_T1, s_PIO_dport0_T2, s_PIO_dport0_T4, s_PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal s_PIO_dport1_T1, s_PIO_dport1_T2, s_PIO_dport1_T4, s_PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0):="0000";
signal PIOd : std_logic_vector(15 downto 0) := X"0000";
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
--**********************SIGNAL DECLARATION*****by Erik Jagre 2006-10-04*******
signal s_PIOtip : std_logic:='0'; -- PIO transfer in progress
signal s_PIOpp_full : std_logic:='0'; -- PIO Write PingPong full
-- DMA registers
signal s_DMA_dev0_Td,
s_DMA_dev0_Tm,
s_DMA_dev0_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device0
signal s_DMA_dev1_Td,
s_DMA_dev1_Tm,
s_DMA_dev1_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device1
signal s_DMActrl_DMAen,
s_DMActrl_dir,
s_DMActrl_Bytesw,
s_DMActrl_BeLeC0,
s_DMActrl_BeLeC1 : std_logic:='0'; -- DMA settings
-- signal s_DMAsel : std_logic:='0'; -- DMA controller select
-- signal s_DMAack : std_logic:='0'; -- DMA controller acknowledge
-- signal s_DMAq : std_logic_vector(31 downto 0); -- DMA data out
-- signal s_DMAtip : std_logic:='0'; -- DMA transfer in progress
signal s_DMA_dmarq : std_logic:='0'; -- Synchronized ATA DMARQ line
-- signal s_DMATxFull : std_logic:='0'; -- DMA transmit buffer full
-- signal s_DMARxEmpty : std_logic:='0'; -- DMA receive buffer empty
-- signal s_DMA_req : std_logic:='0'; -- DMA request to external DMA engine
-- signal s_DMA_ack : std_logic:='0'; -- DMA acknowledge from external DMA engine
signal s_IDEctrl_ppen : std_logic; --:='0';
signal datemp : std_logic_vector(2 downto 0):="000";
-- signal s_mst_bm : ahb_dma_out_type;
-- signal s_bm_mst : ahb_dma_in_type;
-- signal s_slv_bm : slv_to_bm_type := SLV_TO_BM_RESET_VECTOR;
-- signal s_bm_slv : bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
-- signal s_bm_ctr : bm_to_ctrl_type;
-- signal s_ctr_bm : ctrl_to_bm_type;
signal s_bmi : bmi_type;
signal s_bmo : bmo_type;
signal s_d : std_logic_vector(31 downto 0);
signal s_we, s_irq : std_logic;
constant DMA_mode0_Tm : natural := 4; -- 50ns
constant DMA_mode0_Td : natural := 21; -- 215ns
constant DMA_mode0_Teoc : natural := 21; -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
constant SECTOR_LENGTH : integer := 16;
-- signal PIOa_temp : std_logic_vector(7 downto 0);
--**********************END SIGNAL DECLARATION********************************
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
da<=datemp;
--PIOa_temp <= unsigned(PIOa);
--dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
--s_bmi.fr_mst<=s_mst_bm; s_bmi.fr_slv<=s_slv_bm; s_bmi.fr_ctr<=s_ctr_bm;
--s_bmo.to_mst<=s_bm_mst; s_bmo.to_slv<=s_slv_bm; s_bmo.to_ctr<=s_bm_ctr;
with s_bmi.fr_slv.en select
s_d(15 downto 0)<=s_bmo.d(15 downto 0) when '1',
PIOd when others;
with s_bmi.fr_slv.en select
s_d(31 downto 16)<=s_bmo.d(31 downto 16) when '1',
(others=>'0') when others;
with s_bmi.fr_slv.en select
s_we<=s_bmo.we when '1',
PIOwe when others;
with s_bmi.fr_slv.en select --for guaranteeing coherent memory before irq
s_irq<=irq and (not s_bmo.to_mst.start) when '1',
irq when others;
s_bmi.fr_ctr.irq<=irq;
slv: atahost_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => s_irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => s_bmi.fr_ctr.tip, --Erik Jagre 2006-11-13
-- DMAack => gnd,
DMARxEmpty => s_bmi.fr_ctr.rx_empty, --Erik Jagre 2006-11-13
DMATxFull => s_bmi.fr_ctr.fifo_rdy, --Erik Jagre 2006-11-13
DMA_dmarq => s_DMA_dmarq, --Erik Jagre 2006-11-13
-- DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
-- Bus master edits by Erik Jagre 2006-10-04 ---------------start--
DMActrl_Bytesw=> s_DMActrl_Bytesw,
DMActrl_BeLeC0=> s_DMActrl_BeLeC0,
DMActrl_BeLeC1=> s_DMActrl_BeLeC1,
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
fr_BM =>s_bmo.to_slv,
to_BM =>s_bmi.fr_slv
-- Bus master edits by Erik Jagre 2006-10-04 ------------------end-------
);
ctr: atahost_controller
generic map(
fdepth => fdepth,
tech => tech,
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
a => PIOa,
d => s_d,
we => s_we,
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
PIOsel => PIOsel,
PIOack => PIOack,
PIOq => PIOq,
PIOtip => s_PIOtip,
PIOpp_full => s_PIOpp_full,
--DMA
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMActrl_Bytesw => s_DMActrl_Bytesw,
DMActrl_BeLeC0 => s_DMActrl_BeLeC0,
DMActrl_BeLeC1 => s_DMActrl_BeLeC1,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
DMAsel => s_bmo.to_ctr.sel,
DMAack => s_bmi.fr_ctr.ack,
DMAq => s_bmi.fr_ctr.q,
DMAtip_out => s_bmi.fr_ctr.tip,
DMA_dmarq => s_DMA_dmarq,
force_rdy => s_bmo.to_ctr.force_rdy,
fifo_rdy => s_bmi.fr_ctr.fifo_rdy,
DMARxEmpty => s_bmi.fr_ctr.rx_empty,
DMARxFull => s_bmi.fr_ctr.rx_full,
DMA_req => s_bmi.fr_ctr.req,
DMA_ack => s_bmo.to_ctr.ack,
BM_en => s_bmi.fr_slv.en, -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
--ATA
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => datemp,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq,
DMARQ => dmarq,
DMACKn => dmack
);
mst : ahbmst
generic map(
hindex => mhindex,
hirq => 0,
venid => VENDOR_GAISLER,
devid => GAISLER_ATACTRL,
version => 0,
chprot => 3,
incaddr => 4)
port map (
rst => rst,
clk => clk,
dmai => s_bmo.to_mst,
dmao => s_bmi.fr_mst,
ahbi => ahbmi,
ahbo => ahbmo
);
bm : atahost_ahbmst
generic map(fdepth=>fdepth)
port map(
clk => clk,
rst => rst,
i => s_bmi,
o => s_bmo
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/maps/grlfpw_net.vhd
|
2
|
15984
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_2_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
strtxii : if (tech = stratix2) or (tech = stratix3) or (tech = cyclone3) generate
grlfpw0 : grlfpw_2_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if tech = axcel generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)
generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/maps/ddrphy.vhd
|
2
|
10089
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddrphy is
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc2v : if tech = virtex2 generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
xc3se : if tech = spartan3e generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of ddr2phy is
begin
xc4v : if (tech = virtex4) or (tech = virtex5) generate
ddr_phy0 : virtex5_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk, tech => tech
)
port map (
rst, clk, clkref200, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
end generate;
end;
|
mit
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