repo_name
stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/ulpi_rx.vhd
|
1
|
8524
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_crc : in std_logic_vector(15 downto 0);
status : in std_logic_vector(7 downto 0);
usb_rx : out t_usb_rx );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token0, token1, token2, check_token, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(18 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_tvalid : std_logic;
signal crc_sync_i : std_logic;
signal rx_valid_d : std_logic;
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal valid_split : std_logic;
signal valid_handsh : std_logic;
signal valid_packet : std_logic;
signal data_valid : std_logic;
signal data_start : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal error : std_logic;
signal rx_data_d1 : std_logic_vector(7 downto 0);
signal rx_data_d2 : std_logic_vector(7 downto 0);
signal rx_valid_d1 : std_logic;
signal rx_valid_d2 : std_logic;
signal recv_d : std_logic_vector(1 to 3);
--signal ipd_counter : unsigned(tx_holdoff_delay'range) := (others => '0'); -- interpacket delay
begin
usb_rx.token <= vector_to_token(token_i(18 downto 8));
usb_rx.split_token <= vector_to_split_token(token_i(18 downto 0));
usb_rx.pid <= pid;
usb_rx.valid_token <= valid_token;
usb_rx.valid_split <= valid_split;
usb_rx.valid_handsh <= valid_handsh;
usb_rx.valid_packet <= valid_packet;
usb_rx.data_valid <= data_valid and rx_valid_d2;
usb_rx.data_start <= data_start;
usb_rx.data <= data_out;
usb_rx.error <= error;
usb_rx.receiving <= rx_store or recv_d(1) or recv_d(2) or recv_d(3) or status(4);
process(clock)
begin
if rising_edge(clock) then
error <= '0';
data_start <= '0';
valid_token <= '0';
valid_split <= '0';
valid_packet <= '0';
valid_handsh <= '0';
-- if rx_store = '1' then -- reset interpacket delay counter for transmit
-- tx_holdoff <= '1';
-- ipd_counter <= tx_holdoff_delay;
-- else
-- if ipd_counter = 0 then
-- tx_holdoff <= '0';
-- else
-- ipd_counter <= ipd_counter - 1;
-- end if;
-- end if;
recv_d <= rx_store & recv_d(1 to 2);
rx_data_d1 <= rx_data;
if data_valid='1' then
rx_data_d2 <= rx_data_d1;
data_out <= rx_data_d2;
rx_valid_d1 <= '1';
rx_valid_d2 <= rx_valid_d1;
end if;
data_valid <= '0';
rx_valid_d <= rx_valid;
case state is
when idle =>
rx_valid_d1 <= '0';
rx_valid_d2 <= '0';
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_support_token then
state <= token1;
else
error <= '1';
end if;
elsif is_split(rx_data(3 downto 0)) then
if g_support_split then
state <= token0;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token0 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token1;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= resync;
end if;
when token1 =>
if rx_store='1' then
token_i(15 downto 8) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= resync;
end if;
when token2 =>
if rx_store='1' then
token_i(18 downto 16) <= rx_data(2 downto 0);
state <= check_token;
end if;
when data =>
data_valid <= rx_store;
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
if token_crc = "11001" then
if is_split(pid) then
valid_split <= '1';
else
valid_token <= '1';
end if;
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
-- tx_holdoff <= '0';
end if;
end if;
end process;
r_token: if g_support_token or g_support_split generate
i_token_crc: entity work.token_crc_check
port map (
clock => clock,
sync => crc_sync_i,
valid => crc_tvalid,
data_in => rx_data,
crc => token_crc );
end generate;
crc_sync_i <= (rx_valid and rx_store) when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
crc_tvalid <= rx_store when (state = token0) or (state = token1) or (state = token2) else '0';
crc_sync <= crc_sync_i;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_bfm/io_bus_bfm_pkg.vhd
|
4
|
3912
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.io_bus_pkg.all;
package io_bus_bfm_pkg is
type t_io_bus_bfm_object;
type p_io_bus_bfm_object is access t_io_bus_bfm_object;
type t_io_bfm_command is ( e_io_none, e_io_read, e_io_write );
type t_io_bus_bfm_object is record
next_bfm : p_io_bus_bfm_object;
name : string(1 to 256);
command : t_io_bfm_command;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable io_bus_bfms : p_io_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
------------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
end io_bus_bfm_pkg;
package body io_bus_bfm_pkg is
procedure register_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_io_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if io_bus_bfms = null then -- first entry
io_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := io_bus_bfms;
io_bus_bfms := pntr;
end if;
end register_io_bus_bfm;
procedure bind_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
variable p : p_io_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := io_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_io_bus_bfm;
------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_read;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
data := io.data;
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_write;
io.data := data;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/sampler/vhdl_source/sampler.vhd
|
4
|
9000
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : out std_logic;
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler is
signal voice_state : t_voice_state_array(0 to g_num_voices-1) := (others => c_voice_state_init);
signal voice_sample_reg_h : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_sample_reg_l : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_i : integer range 0 to g_num_voices-1;
signal fetch_en : std_logic;
signal fetch_addr : unsigned(25 downto 0);
signal fetch_tag : std_logic_vector(7 downto 0);
signal interrupt : std_logic_vector(g_num_voices-1 downto 0);
signal interrupt_clr : std_logic_vector(g_num_voices-1 downto 0);
signal current_control : t_voice_control;
signal first_chan : std_logic;
signal cur_sam : signed(15 downto 0);
signal cur_vol : unsigned(5 downto 0);
signal cur_pan : unsigned(3 downto 0);
begin
i_regs: entity work.sampler_regs
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
rd_addr => voice_i,
control => current_control,
irq_status => interrupt,
irq_clear => interrupt_clr );
irq <= '1' when unsigned(interrupt) /= 0 else '0';
process(clock)
variable current_state : t_voice_state;
variable next_state : t_voice_state;
variable sample_reg : signed(15 downto 0);
variable v : integer range 0 to 15;
begin
if rising_edge(clock) then
if voice_i = g_num_voices-1 then
voice_i <= 0;
else
voice_i <= voice_i + 1;
end if;
for i in interrupt'range loop
if interrupt_clr(i)='1' then
interrupt(i) <= '0';
end if;
end loop;
fetch_en <= '0';
current_state := voice_state(0);
sample_reg := voice_sample_reg_h(voice_i) & voice_sample_reg_l(voice_i);
next_state := current_state;
case current_state.state is
when idle =>
if current_control.enable then
next_state.state := fetch1;
next_state.position := (others => '0');
next_state.divider := current_control.rate;
next_state.sample_out := (others => '0');
end if;
when playing =>
if current_state.divider = 0 then
next_state.divider := current_control.rate;
next_state.sample_out := sample_reg;
next_state.state := fetch1;
if (current_state.position = current_control.repeat_b) then
if current_control.enable and current_control.repeat then
next_state.position := current_control.repeat_a;
end if;
elsif current_state.position = current_control.length then
next_state.state := finished;
if current_control.interrupt then
interrupt(voice_i) <= '1';
end if;
end if;
else
next_state.divider := current_state.divider - 1;
end if;
if not current_control.enable and not current_control.repeat then
next_state.state := idle;
end if;
when finished =>
if not current_control.enable then
next_state.state := idle;
end if;
when fetch1 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
if current_control.mode = mono8 then
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 2; -- this and the next byte
else
next_state.position := current_state.position + 1; -- this byte only
end if;
else
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '0'; -- low
next_state.position := current_state.position + 1; -- go to the next byte
next_state.state := fetch2;
end if;
when fetch2 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 3; -- this and the two next bytes
else
next_state.position := current_state.position + 1; -- this byte only
end if;
when others =>
null;
end case;
cur_sam <= current_state.sample_out;
cur_vol <= current_control.volume;
cur_pan <= current_control.pan;
if voice_i=0 then
first_chan <= '1';
else
first_chan <= '0';
end if;
-- write port - state --
voice_state <= voice_state(1 to g_num_voices-1) & next_state;
-- write port - sample data --
if mem_resp.dack_tag(7 downto 5) = "110" then
v := to_integer(unsigned(mem_resp.dack_tag(4 downto 1)));
if mem_resp.dack_tag(0)='1' then
voice_sample_reg_h(v) <= signed(mem_resp.data);
else
voice_sample_reg_l(v) <= signed(mem_resp.data);
end if;
end if;
if reset='1' then
voice_i <= 0;
next_state.state := idle; -- shifted into the voice state vector automatically.
interrupt <= (others => '0');
end if;
end if;
end process;
b_mem_fifo: block
signal rack : std_logic;
signal fifo_din : std_logic_vector(33 downto 0);
signal fifo_dout : std_logic_vector(33 downto 0);
begin
fifo_din <= fetch_tag & std_logic_vector(fetch_addr);
i_fifo: entity work.srl_fifo
generic map (
Width => 34,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => fetch_en,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
DataInFifo => mem_req.request );
mem_req.read_writen <= '1';
mem_req.address <= unsigned(fifo_dout(25 downto 0));
mem_req.tag <= fifo_dout(33 downto 26);
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time (can be optimized!)
rack <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(7 downto 5)="110") else '0';
end block;
i_accu: entity work.sampler_accu
port map (
clock => clock,
reset => reset,
first_chan => first_chan,
sample_in => cur_sam,
volume_in => cur_vol,
pan_in => cur_pan,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
end gideon;
|
gpl-3.0
|
multiple1902/xjtu_comp-org-lab
|
modules/memory/memory.vhdl
|
1
|
1620
|
-- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity memory is
port (
cs : in std_logic; -- Chip select
re, we : in std_logic; -- Read / Write Enable
clk : in std_logic;
addr_h, addr_l
: in std_logic_vector(4 downto 0);
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end memory;
architecture behv of memory is
type core_type is array(1023 downto 0) of std_logic_vector(15 downto 0);
signal core: core_type;
signal addr: std_logic_vector(9 downto 0);
begin
process(clk,cs,re,we,addr_h,addr_l)
begin
if clk='1' and cs='1' and re='1' then
addr(9 downto 5)<= addr_h(4 downto 0);
addr(4 downto 0)<= addr_l(4 downto 0);
data_out <= core(conv_integer(std_logic_vector(addr)));
elsif clk='1' and cs='1' and we='1' then
addr(9 downto 5)<= addr_h(4 downto 0);
addr(4 downto 0)<= addr_l(4 downto 0);
-- core(to_integer(unsigned(addr)))<= data_in;
-- core(to_integer(unsigned(addr)))<= data_in;
core(conv_integer(std_logic_vector(addr)))<= data_in;
data_out <= core(to_integer(unsigned(addr)));
assert false report "hello" severity note;
-- data_out <= "ZZZZZZZZZZZZZZZZ";
--else
-- data_out <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
end behv;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/c2n_playback/vhdl_source/c2n_playback.vhd
|
5
|
4623
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/zpu/vhdl_source/zpu_8bit_ok.vhd
|
5
|
28212
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_i : in unsigned(c_opcode_width-1 downto 0);
c_valid_i : in std_logic;
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_o : out unsigned(c_opcode_width-1 downto 0);
c_en_o : out std_logic;
c_we_o : out std_logic );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
-- constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal dec_valid : std_logic;
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= '1';
b_en_o <= '1';
c_en_o <= '1' when state = st_fetch else c_en_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
byte_cnt_d <= byte_cnt;
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
dec_valid <= not c_mux_d and c_valid_i;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
if dec_valid = '1' then
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_en_r <= '1';
-- c_mux_r <= '1';
-- byte_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
end if; -- decode valid
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
if c_valid_i = '1' then
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
end if;
if byte_cnt = "00" then
c_mux_r <= '0';
c_en_r <= '0';
end if;
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_en_r <= '0';
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
first <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: zpu_8bit
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/cpu_unit/mblite/hw/std/sram_4en.vhd
|
2
|
2971
|
----------------------------------------------------------------------------------------------
--
-- Input file : sram_4en.vhd
-- Design name : sram_4en
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory with 4 write enable
-- ports.
-- Architecture 'arch' : Default implementation
-- Architecture 'arch2' : Alternative implementation
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
entity sram_4en is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end sram_4en;
-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
-- supported by many devices (although it comes straight from the library. Many devices give
-- cryptic synthesization errors on this implementation, so it is not the default.
architecture arch2 of sram_4en is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
type sel_type is array(WIDTH/8 - 1 downto 0) of std_logic_vector(7 downto 0);
signal ram: ram_type;
signal di: sel_type;
begin
process(wre_i, dat_i, adr_i)
begin
for i in 0 to WIDTH/8 - 1 loop
if wre_i(i) = '1' then
di(i) <= dat_i((i+1)*8 - 1 downto i*8);
else
di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 downto i*8);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
dat_o <= di(3) & di(2) & di(1) & di(0);
end if;
end if;
end process;
end arch2;
-- Less convenient but very general memory block with four separate write
-- enable signals. (4x8 bit)
architecture arch of sram_4en is
begin
mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/ip/busses/vhdl_bfm/mem_bus_master_bfm_pkg.vhd
|
5
|
4335
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.mem_bus_pkg.all;
package mem_bus_master_bfm_pkg is
type t_mem_bus_master_bfm_object;
type p_mem_bus_master_bfm_object is access t_mem_bus_master_bfm_object;
type t_mem_bus_bfm_command is ( e_mem_none, e_mem_read, e_mem_write );
type t_mem_bus_master_bfm_object is record
next_bfm : p_mem_bus_master_bfm_object;
name : string(1 to 256);
command : t_mem_bus_bfm_command;
poll_time : time;
tag : std_logic_vector(7 downto 0);
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable mem_bus_master_bfms : p_mem_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_mem_bus_master_bfm(named : string; variable pntr: inout p_mem_bus_master_bfm_object);
procedure bind_mem_bus_master_bfm(named : string; variable pntr: inout p_mem_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure mem_read(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure mem_write(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
end mem_bus_master_bfm_pkg;
package body mem_bus_master_bfm_pkg is
procedure register_mem_bus_master_bfm(named : string;
variable pntr : inout p_mem_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_mem_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if mem_bus_master_bfms = null then -- first entry
mem_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := mem_bus_master_bfms;
mem_bus_master_bfms := pntr;
end if;
pntr.tag := X"01";
pntr.poll_time := 2 ns;
end register_mem_bus_master_bfm;
procedure bind_mem_bus_master_bfm(named : string;
variable pntr : inout p_mem_bus_master_bfm_object) is
variable p : p_mem_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := mem_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_mem_bus_master_bfm;
------------------------------------------------------------------------------
procedure mem_read(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(25 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_mem_read;
while m.command /= e_mem_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure mem_write(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(25 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_mem_write;
m.data := data;
while m.command /= e_mem_none loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/hf_noise.vhd
|
2
|
3289
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hf_noise is
generic (
g_hp_filter : boolean := true );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
q : out signed(15 downto 0) );
end entity;
architecture structural of hf_noise is
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
constant c_type : string := "Fibonacci";
constant c_polynom : std_logic_vector := X"E10000";
constant c_seed : std_logic_vector := X"000001";
signal raw_lfsr : std_logic_vector(c_polynom'length-1 downto 0);
signal noyse : signed(15 downto 0);
signal hp : signed(15 downto 0);
begin
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_seed => c_seed )
port map (
clock => clock,
enable => enable,
reset => reset,
q => raw_lfsr );
-- Reordering the bits somehow randomly,
-- gives a better spectral distribution
-- in case of Galois (flat!)! In face of Fibonacci,
-- this reordering gives ~20dB dips at odd
-- locations, depending on the reorder choice.
noyse(15) <= raw_lfsr(1);
noyse(14) <= raw_lfsr(4);
noyse(13) <= raw_lfsr(7);
noyse(12) <= raw_lfsr(10);
noyse(11) <= raw_lfsr(13);
noyse(10) <= raw_lfsr(16);
noyse(09) <= raw_lfsr(19);
noyse(08) <= raw_lfsr(22);
noyse(07) <= raw_lfsr(20);
noyse(06) <= raw_lfsr(17);
noyse(05) <= raw_lfsr(14);
noyse(04) <= raw_lfsr(11);
noyse(03) <= raw_lfsr(8);
noyse(02) <= raw_lfsr(5);
noyse(01) <= raw_lfsr(2);
noyse(00) <= raw_lfsr(18);
-- taking an up-range or down range gives a reasonably
-- flat frequency response, but lacks low frequencies (~20 dB)
-- In case of our high-freq noise that we need, this is not
-- a bad thing, as our filter doesn't need to be so sharp.
-- Fibonacci gives less low frequency noise than Galois!
-- differences seen with 1st order filter below were 5-10dB in
-- our band of interest.
-- noise <= signed(raw_lfsr(20 downto 5));
r_hp: if g_hp_filter generate
signal hp_a : signed(15 downto 0);
begin
i_hp: entity work.high_pass
generic map (
g_width => 15 )
port map (
clock => clock,
enable => enable,
reset => reset,
x => noyse(14 downto 0),
-- q => hp_a );
-- i_hp_b: entity work.high_pass
-- generic map (
-- g_width => 16 )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- x => hp_a,
q => hp );
end generate;
q <= hp(15 downto 0) when g_hp_filter else noyse;
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_source/io_to_dma_bridge.vhd
|
4
|
1937
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end entity;
architecture rtl of io_to_dma_bridge is
signal dma_rwn_i : std_logic;
begin
dma_req.address <= io_req.address(15 downto 0);
dma_req.read_writen <= dma_rwn_i;
dma_req.data <= io_req.data;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if dma_resp.rack='1' then
dma_req.request <= '0';
if dma_rwn_i='0' then -- was write
io_resp.ack <= '1';
end if;
end if;
if dma_resp.dack='1' then
io_resp.data <= dma_resp.data;
io_resp.ack <= '1';
end if;
if io_req.write='1' then
if c64_stopped='1' then
dma_req.request <= '1';
dma_rwn_i <= '0';
else
io_resp.ack <= '1';
end if;
elsif io_req.read='1' then
if c64_stopped='1' then
dma_req.request <= '1';
dma_rwn_i <= '1';
else
io_resp.ack <= '1';
end if;
end if;
if reset='1' then
dma_req.request <= '0';
dma_rwn_i <= '1';
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/ip/synchroniser/vhdl_source/input_synchronizer.vhd
|
5
|
3069
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/command_interface/vhdl_source/command_protocol.vhd
|
1
|
13404
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
io_irq : out std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal irq_mask : std_logic_vector(2 downto 0);
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_cif_io_irq_mask =>
irq_mask <= io_req.data(2 downto 0);
when c_cif_io_irq_mask_set =>
irq_mask <= irq_mask or io_req.data(2 downto 0);
when c_cif_io_irq_mask_clear =>
irq_mask <= irq_mask and not io_req.data(2 downto 0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when c_cif_io_irq_mask =>
io_resp.data(2 downto 0) <= irq_mask;
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
irq_mask <= "111";
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
io_irq <= '1' when (handshake_in and not irq_mask) /= "000" else '0';
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/cpu_unit/vhdl_source/mblite_sdram.vhd
|
2
|
7172
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
entity mblite_sdram is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
BUTTON : in std_logic_vector(0 to 2);
MOTOR_LEDn : out std_logic;
DISK_ACTn : out std_logic );
end entity;
architecture arch of mblite_sdram is
constant c_tag_i : std_logic_vector(7 downto 0) := X"10";
constant c_tag_d : std_logic_vector(7 downto 0) := X"11";
constant c_tag_test : std_logic_vector(7 downto 0) := X"91";
signal reset_in : std_logic;
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal irq : std_logic;
signal mem_req_32_cpu : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_cpu : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_test : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_test : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal txd, rxd : std_logic := '1';
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := (others => '0');
begin
reset_in <= not BUTTON(1);
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
soft_reset => reset_in,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_proc: entity work.mblite_wrapper
generic map (
g_tag_i => c_tag_i,
g_tag_d => c_tag_d )
port map(
clock => clock,
reset => reset,
irq_i => irq,
irq_o => open,
invalidate => invalidate,
inv_addr => inv_addr,
io_req => io_req,
io_resp => io_resp,
mem_req => mem_req_32_cpu,
mem_resp => mem_resp_32_cpu );
invalidate <= '1' when (mem_resp_32_test.rack_tag = c_tag_test) and (mem_req_32_test.read_writen = '0') else '0';
inv_addr(31 downto 26) <= (others => '0');
inv_addr(25 downto 0) <= std_logic_vector(mem_req_32_test.address);
i_mem_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_ports => 2,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_32_test,
reqs(1) => mem_req_32_cpu,
resps(0) => mem_resp_32_test,
resps(1) => mem_resp_32_cpu,
req => mem_req,
resp => mem_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= '1';
DISK_ACTn <= '0';
i_itu: entity work.itu
generic map (
g_version => X"00",
g_uart => true,
g_baudrate => 5_000_000,
g_capabilities => X"80000000"
)
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
irq_timer_tick => '0',
irq_in => "000000",
irq_out => irq,
uart_txd => txd,
uart_rxd => rxd );
-- IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if io_req.write = '1' then -- write
case io_req.address is
when X"00010" => -- UART_DATA
byte := io_req.data;
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
process
--constant c_test : std_logic_vector(1 to 10) := "1111111110";
begin
mem_req_32_test.address <= to_unsigned(16#40000#, mem_req_32_test.address'length);
mem_req_32_test.tag <= c_tag_test;
wait;
wait for 600 us;
for i in 1 to 10000 loop
wait until clock = '1';
mem_req_32_test.byte_en <= "1111";
mem_req_32_test.data <= X"12345678";
mem_req_32_test.read_writen <= '0'; --c_test(i);
mem_req_32_test.request <= '1';
L1: while true loop
wait until clock = '1';
if mem_resp_32_test.rack_tag = c_tag_test then
exit L1;
end if;
end loop;
mem_req_32_test.request <= '0';
mem_req_32_test.address <= mem_req_32_test.address + 0;
wait until clock = '1';
wait until clock = '1';
end loop;
wait;
end process;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/itu/vhdl_source/itu_pkg.vhd
|
1
|
1529
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package itu_pkg is
constant c_itu_irq_global : unsigned(3 downto 0) := X"0";
constant c_itu_irq_enable : unsigned(3 downto 0) := X"1";
constant c_itu_irq_disable : unsigned(3 downto 0) := X"2";
constant c_itu_irq_edge : unsigned(3 downto 0) := X"3";
constant c_itu_irq_clear : unsigned(3 downto 0) := X"4";
constant c_itu_irq_active : unsigned(3 downto 0) := X"5";
constant c_itu_timer : unsigned(3 downto 0) := X"6";
constant c_itu_irq_timer_en : unsigned(3 downto 0) := X"7";
constant c_itu_irq_timer_hi : unsigned(3 downto 0) := X"8"; -- big endian word
constant c_itu_irq_timer_lo : unsigned(3 downto 0) := X"9";
constant c_itu_hw_flags : unsigned(3 downto 0) := X"A";
constant c_itu_fpga_version : unsigned(3 downto 0) := X"B";
constant c_itu_capabilities0 : unsigned(3 downto 0) := X"C";
constant c_itu_capabilities1 : unsigned(3 downto 0) := X"D";
constant c_itu_capabilities2 : unsigned(3 downto 0) := X"E";
constant c_itu_capabilities3 : unsigned(3 downto 0) := X"F";
-- second block
constant c_itu_ms_timer_hi : unsigned(3 downto 0) := X"2";
constant c_itu_ms_timer_lo : unsigned(3 downto 0) := X"3";
constant c_itu_usb_busy : unsigned(3 downto 0) := X"4";
constant c_itu_sd_busy : unsigned(3 downto 0) := X"5";
constant c_itu_misc_io : unsigned(3 downto 0) := X"6";
end package;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/copper/vhdl_source/copper_pkg.vhd
|
5
|
3337
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package copper_pkg is
constant c_copper_command : unsigned(3 downto 0) := X"0";
constant c_copper_status : unsigned(3 downto 0) := X"1";
constant c_copper_measure_l : unsigned(3 downto 0) := X"2";
constant c_copper_measure_h : unsigned(3 downto 0) := X"3";
constant c_copper_framelen_l : unsigned(3 downto 0) := X"4";
constant c_copper_framelen_h : unsigned(3 downto 0) := X"5";
constant c_copper_break : unsigned(3 downto 0) := X"6";
constant c_copper_cmd_play : std_logic_vector(3 downto 0) := X"1"; -- starts program in ram
constant c_copper_cmd_record : std_logic_vector(3 downto 0) := X"2"; -- waits for sync, records all writes until next sync.
constant c_copcode_write_reg : std_logic_vector(7 downto 0) := X"00"; -- starting from 00-2F or so.. takes 1 argument
constant c_copcode_read_reg : std_logic_vector(7 downto 0) := X"40"; -- starting from 40-6F or so.. no arguments
constant c_copcode_wait_irq : std_logic_vector(7 downto 0) := X"81"; -- waits until falling edge of IRQn
constant c_copcode_wait_sync : std_logic_vector(7 downto 0) := X"82"; -- waits until sync pulse from timer
constant c_copcode_timer_clr : std_logic_vector(7 downto 0) := X"83"; -- clears timer
constant c_copcode_capture : std_logic_vector(7 downto 0) := X"84"; -- copies timer to measure register
constant c_copcode_wait_for : std_logic_vector(7 downto 0) := X"85"; -- takes a 1 byte argument
constant c_copcode_wait_until: std_logic_vector(7 downto 0) := X"86"; -- takes 2 bytes argument (wait until timer match)
constant c_copcode_repeat : std_logic_vector(7 downto 0) := X"87"; -- restart at program address 0.
constant c_copcode_end : std_logic_vector(7 downto 0) := X"88"; -- ends operation and return to idle
constant c_copcode_trigger_1 : std_logic_vector(7 downto 0) := X"89"; -- pulses on trigger_1 output
constant c_copcode_trigger_2 : std_logic_vector(7 downto 0) := X"8A"; -- pulses on trigger_1 output
type t_copper_control is record
command : std_logic_vector(3 downto 0);
frame_length : unsigned(15 downto 0);
stop : std_logic;
end record;
constant c_copper_control_init : t_copper_control := (
command => X"0",
frame_length => X"4D07", -- 313 lines of 63.. (is incorrect, is one line too long, but to init is fine!)
stop => '0' );
type t_copper_status is record
running : std_logic;
measured_time : unsigned(15 downto 0);
end record;
constant c_copper_status_init : t_copper_status := (
running => '0',
measured_time => X"FFFF" );
end package;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_sim/usb_controller_tb.vhd
|
5
|
3711
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
signal clock_50 : std_logic := '0';
signal clock_60 : std_logic := '0';
signal clock_50_shifted : std_logic := '1';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- ULPI Interface
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
-- LED interface
signal usb_busy : std_logic;
-- Memory interface
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp := c_mem_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
begin
clock_50 <= not clock_50 after 10 ns;
clock_60 <= not clock_60 after 8.3 ns;
reset <= '1', '0' after 100 ns;
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock_50,
req => io_req,
resp => io_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", iom);
io_write(iom, X"1000", X"01"); -- enable core
wait;
end process;
i_phy: entity work.ulpi_phy_bfm
port map (
clock => clock_60,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_mut: entity work.usb_controller
port map (
ulpi_clock => clock_60,
ulpi_reset => reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- LED interface
usb_busy => usb_busy,
-- register interface bus
sys_clock => clock_50,
sys_reset => reset,
sys_mem_req => mem_req,
sys_mem_resp=> mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp );
clock_50_shifted <= transport clock_50 after 15 ns; -- 270 deg
i_mc: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => true )
port map (
clock => clock_50,
clk_shifted => clock_50_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
MEM_A => SDRAM_A,
MEM_D => SDRAM_D );
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/usb2/vhdl_sim/usb_controller_tb.vhd
|
5
|
3711
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
signal clock_50 : std_logic := '0';
signal clock_60 : std_logic := '0';
signal clock_50_shifted : std_logic := '1';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- ULPI Interface
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
-- LED interface
signal usb_busy : std_logic;
-- Memory interface
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp := c_mem_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
begin
clock_50 <= not clock_50 after 10 ns;
clock_60 <= not clock_60 after 8.3 ns;
reset <= '1', '0' after 100 ns;
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock_50,
req => io_req,
resp => io_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", iom);
io_write(iom, X"1000", X"01"); -- enable core
wait;
end process;
i_phy: entity work.ulpi_phy_bfm
port map (
clock => clock_60,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_mut: entity work.usb_controller
port map (
ulpi_clock => clock_60,
ulpi_reset => reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- LED interface
usb_busy => usb_busy,
-- register interface bus
sys_clock => clock_50,
sys_reset => reset,
sys_mem_req => mem_req,
sys_mem_resp=> mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp );
clock_50_shifted <= transport clock_50 after 15 ns; -- 270 deg
i_mc: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => true )
port map (
clock => clock_50,
clk_shifted => clock_50_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
MEM_A => SDRAM_A,
MEM_D => SDRAM_D );
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_bfm/mem_bus_slave_bfm.vhd
|
5
|
1640
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_sim/usb_harness.vhd
|
2
|
2204
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-01-27
-- Author: Gideon
-- Description: Harness for USB Host Controller
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity usb_harness is
port (
clocks_stopped : in boolean := false );
end entity;
architecture arch of usb_harness is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal clock : std_logic := '0';
signal reset : std_logic;
signal sys_io_req : t_io_req;
signal sys_io_resp : t_io_resp;
signal ulpi_nxt : std_logic;
signal ulpi_stp : std_logic;
signal ulpi_dir : std_logic;
signal ulpi_data : std_logic_vector(7 downto 0);
begin
sys_clock <= not sys_clock after 10 ns when not clocks_stopped;
sys_reset <= '1', '0' after 50 ns;
clock <= not clock after 8 ns when not clocks_stopped;
reset <= '1', '0' after 250 ns;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io" )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp );
i_host: entity work.usb_host_controller
generic map (
g_simulation => true )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_ulpi_phy: entity work.ulpi_master_bfm
generic map (
g_given_name => "device" )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_device: entity work.usb_device_model;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_peripheral.vhd
|
4
|
5893
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/usb/vhdl_source/data_crc.vhd
|
5
|
1812
|
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity data_crc is
port (
clock : in std_logic;
sync : in std_logic;
valid : in std_logic;
data_in : in std_logic_vector(7 downto 0);
crc : out std_logic_vector(15 downto 0) );
end data_crc;
architecture Gideon of data_crc is
constant polynom : std_logic_vector(15 downto 0) := X"8004";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
if sync = '1' then
tmp := (others => '1');
end if;
if valid = '1' then
for i in data_in'reverse_range loop -- LSB first!
d := data_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
end if;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/delta_sigma_2to5.vhd
|
5
|
2460
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/1541/vhdl_bfm/iec_bus_bfm.vhd
|
4
|
17537
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
package iec_bus_bfm_pkg is
type t_iec_bus_bfm_object;
type p_iec_bus_bfm_object is access t_iec_bus_bfm_object;
type t_iec_status is (ok, no_devices, no_response, timeout, no_eoi_ack);
type t_iec_state is (idle, talker, listener);
type t_iec_command is (none, send_atn, send_msg, atn_to_listen);
type t_iec_data is array(natural range <>) of std_logic_vector(7 downto 0);
type t_iec_message is record
data : t_iec_data(0 to 256);
len : integer;
end record;
type t_iec_to_bfm is
record
command : t_iec_command;
end record;
type t_iec_from_bfm is
record
busy : boolean;
end record;
constant c_iec_to_bfm_init : t_iec_to_bfm := (
command => none );
constant c_iec_from_bfm_init : t_iec_from_bfm := (
busy => false );
type t_iec_bus_bfm_object is record
next_bfm : p_iec_bus_bfm_object;
name : string(1 to 256);
-- interface to the user
status : t_iec_status;
state : t_iec_state;
stopped : boolean;
sample_time : time;
-- buffer
msg_buf : t_iec_message;
-- internal to bfm
to_bfm : t_iec_to_bfm;
-- internal from bfm
from_bfm : t_iec_from_bfm;
end record;
constant c_atn_to_ckl : time := 5 us;
constant c_atn_resp_max : time := 1000 us;
constant c_non_eoi : time := 40 us;
constant c_clk_low : time := 50 us;
constant c_clk_high : time := 50 us;
constant c_frame_hs_max : time := 1000 us;
constant c_frame_release : time := 20 us;
constant c_byte_to_byte : time := 100 us;
constant c_eoi_min : time := 200 us;
constant c_eoi : time := 500 us; -- was 250
constant c_eoi_hold : time := 60 us;
constant c_tlkr_resp_dly : time := 60 us; -- max
constant c_talk_atn_rel : time := 30 us;
constant c_talk_atn_ack : time := 250 us; -- ?
------------------------------------------------------------------------------------
shared variable iec_bus_bfms : p_iec_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
procedure bind_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
------------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0));
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string);
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message);
procedure iec_print_message(variable msg : inout t_iec_message);
end iec_bus_bfm_pkg;
package body iec_bus_bfm_pkg is
procedure register_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_iec_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
pntr.status := ok;
pntr.state := idle;
pntr.stopped := false; -- active;
pntr.sample_time := 1 us;
pntr.to_bfm := c_iec_to_bfm_init;
pntr.from_bfm := c_iec_from_bfm_init;
-- add this pointer to the head of the linked list
if iec_bus_bfms = null then -- first entry
iec_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := iec_bus_bfms;
iec_bus_bfms := pntr;
end if;
end register_iec_bus_bfm;
procedure bind_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
variable p : p_iec_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := iec_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_iec_bus_bfm;
------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.stopped := true;
end procedure;
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := talker;
end procedure;
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := listener;
end procedure;
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0)) is
begin
bfm.msg_buf.data(0) := byte;
bfm.msg_buf.len := 1;
bfm.to_bfm.command := send_atn;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := atn_to_listen;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message) is
begin
bfm.msg_buf := msg;
bfm.to_bfm.command := send_msg;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string) is
variable leng : integer;
begin
leng := msg'length;
for i in 1 to leng loop
bfm.msg_buf.data(i-1) := conv_std_logic_vector(character'pos(msg(i)), 8);
end loop;
bfm.msg_buf.len := leng;
iec_send_message(bfm, bfm.msg_buf);
end procedure;
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message) is
begin
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.state = listener loop
wait for bfm.sample_time;
end loop;
msg := bfm.msg_buf;
end procedure;
procedure iec_print_message(variable msg : inout t_iec_message) is
variable L : line;
variable c : character;
begin
for i in 0 to msg.len-1 loop
c := character'val(conv_integer(msg.data(i)));
write(L, c);
end loop;
writeline(output, L);
end procedure;
end;
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
library work;
use work.iec_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity iec_bus_bfm is
port (
iec_clock : inout std_logic;
iec_data : inout std_logic;
iec_atn : inout std_logic );
end iec_bus_bfm;
architecture bfm of iec_bus_bfm is
shared variable this : p_iec_bus_bfm_object := null;
signal bound : boolean := false;
signal clk_i : std_logic;
signal clk_o : std_logic;
signal data_i : std_logic;
signal data_o : std_logic;
signal atn_i : std_logic;
signal atn_o : std_logic;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_iec_bus_bfm(iec_bus_bfm'path_name, this);
bound <= true;
wait;
end process;
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
-- |<--------- Byte sent under attention (to devices) ------------>|
--
-- ___ ____ _____ _____
-- ATN |________________________________________________________|
-- : :
-- ___ ______ ________ ___ ___ ___ ___ ___ ___ ___ ___ :
-- CLK : |_____| |_| |_| |_| |_| |_| |_| |_| |_| |______________ _____
-- : : : : :
-- : Tat : :Th: Tne : : Tf : Tr :
-- ____ ________ : : :___________________________________:____:
-- DATA ___|\\\\\__:__| |__||__||__||__||__||__||__||__| |_________ _____
-- : 0 1 2 3 4 5 6 7 :
-- : LSB MSB :
-- : : :
-- : : Data Valid Listener: Data Accepted
-- : Listener READY-FOR-DATA
protocol: process
procedure do_send_atn is
begin
atn_o <= '0';
wait for c_atn_to_ckl;
clk_o <= '0';
if data_i='1' then
wait until data_i='0' for c_atn_resp_max;
end if;
if data_i='1' then
this.status := no_devices;
return;
end if;
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= this.msg_buf.data(0)(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_frame_release;
atn_o <= '1';
end procedure;
procedure send_byte(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
end procedure;
procedure end_handshake(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
-- wait for c_eoi;
-- data_o <= '0';
-- wait for c_eoi_hold;
-- data_o <= '1';
wait until data_i='0' for c_eoi; -- wait for 250 µs to see that listener has acked eoi
if data_i='1' then
this.status := no_eoi_ack;
return;
end if;
wait until data_i='1'; -- wait for listener to be ready again
wait for c_tlkr_resp_dly;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
end procedure;
procedure talk_atn_turnaround is
begin
wait for c_talk_atn_rel;
clk_o <= '1';
data_o <= '0';
wait for c_talk_atn_rel;
wait until clk_i = '0';
this.state := listener;
this.msg_buf.len := 0; -- clear buffer for incoming data
end procedure;
procedure receive_byte is
variable b : std_logic_vector(7 downto 0);
variable eoi : boolean;
variable c : character;
variable L : LINE;
begin
eoi := false;
if clk_i='0' then
wait until clk_i='1';
end if;
wait for c_clk_low; -- dummy
data_o <= '1';
-- check for end of message handshake (data pulses low after >200 µs for >60 µs)
wait until clk_i = '0' for c_eoi_min;
if clk_i='1' then -- eoi timeout
eoi := true;
-- ack eoi
data_o <= '0';
wait for c_eoi_hold;
data_o <= '1';
end if;
for i in 0 to 7 loop
wait until clk_i='1';
b(i) := data_i;
end loop;
-- c := character'val(conv_integer(b));
-- write(L, c);
-- writeline(output, L);
--
this.msg_buf.data(this.msg_buf.len) := b;
this.msg_buf.len := this.msg_buf.len + 1;
wait until clk_i='0';
if eoi then
this.state := idle;
data_o <= '1';
else
data_o <= '0';
end if;
end procedure;
begin
atn_o <= '1';
data_o <= '1';
clk_o <= '1';
wait until bound;
while not this.stopped loop
wait for this.sample_time;
case this.to_bfm.command is
when none =>
null;
when send_atn =>
this.from_bfm.busy := true;
do_send_atn;
this.from_bfm.busy := false;
when send_msg =>
this.from_bfm.busy := true;
if this.msg_buf.len > 1 then
L1: for i in 0 to this.msg_buf.len-2 loop
send_byte(this.msg_buf.data(i));
if this.status /= ok then
exit L1;
end if;
end loop;
end if;
assert this.status = ok
report "Sending data message failed."
severity error;
end_handshake(this.msg_buf.data(this.msg_buf.len-1));
assert this.status = ok
report "Sending data message failed (Last Byte)."
severity error;
this.from_bfm.busy := false;
when atn_to_listen =>
this.from_bfm.busy := true;
talk_atn_turnaround;
this.from_bfm.busy := false;
end case;
this.to_bfm.command := none;
if this.state = listener then
receive_byte;
end if;
end loop;
wait;
end process;
-- if in idle state, and atn_i becomes '0', then become device and listen
-- but that is only needed for devices... (not for the controller)
-- if listener (means that I am addressed), listen to all bytes
-- if end of message is detected, switch back to idle state.
end bfm;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/iec_interface/vhdl_source/s3_iec.vhd
|
5
|
6091
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd
|
4
|
1974
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_write : std_logic;
io_address : unsigned(15 downto 0); -- for late reads/writes
io_read : std_logic;
io_read_early : std_logic;
io_write : std_logic;
late_write : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_slot_resp is record
data : std_logic_vector(7 downto 0);
reg_output : std_logic;
irq : std_logic;
end record;
constant c_slot_req_init : t_slot_req := (
bus_address => X"0000",
bus_write => '0',
io_read_early => '0',
io_address => X"0000",
io_read => '0',
io_write => '0',
late_write => '0',
data => X"00" );
constant c_slot_resp_init : t_slot_resp := (
data => X"00",
reg_output => '0',
irq => '0' );
type t_slot_req_array is array(natural range <>) of t_slot_req;
type t_slot_resp_array is array(natural range <>) of t_slot_resp;
function or_reduce(ar: t_slot_resp_array) return t_slot_resp;
end package;
package body slot_bus_pkg is
function or_reduce(ar: t_slot_resp_array) return t_slot_resp is
variable ret : t_slot_resp;
begin
ret := c_slot_resp_init;
for i in ar'range loop
ret.reg_output := ret.reg_output or ar(i).reg_output;
if ar(i).reg_output='1' then
ret.data := ret.data or ar(i).data;
end if;
ret.irq := ret.irq or ar(i).irq;
end loop;
return ret;
end function or_reduce;
end package body;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/cpu_unit/mblite/hw/core/decode.vhd
|
1
|
19605
|
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_SUPPORT_SPR: boolean := true;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
block_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_o.int_ack <= r.int_ack;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.inst_valid,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
v.int_ack := '0';
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if decode_i.inst_valid = '0' then
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
-- not a hazard, just a nop
elsif (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if decode_i.interrupt_enable = '1' and decode_i.interrupt = '1' and reg.block_interrupt = '0' then
v_reg.interrupt := '1';
end if;
if decode_i.interrupt_enable = '0' then
v_reg.block_interrupt := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := "00";
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_ex.msr_op := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.interrupt := '0';
v_reg.block_interrupt := '1'; -- because interrupt enable is cleared in exec, we block here any new interrupts until MSR_I bit is cleared.
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.int_ack := '1';
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110"; -- link register is r14
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.msr_op := MSR_CLR_I;
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA; -- will read 0 because reg_a = 0
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Pass modifier for CMP and CMPU
if (compare(opcode, "000101") = '1') then
v.ctrl_ex.operation := instruction(1 downto 0);
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
elsif opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.delay := instruction(20);
-- Link: WRITE THE CURRENT PC TO REGISTER D. In the MEM stage, a multiplexer decides that PC is being written in case of a branch.
if instruction(18) = '1' then
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
end if;
if instruction(19) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.reg_a := (others => '0'); -- select register 0 to emulate 0.
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v.ctrl_ex.msr_op := MSR_SET_I;
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := '1';
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_SUPPORT_SPR and opcode = "100101" then
if instruction(15 downto 14) = "11" then -- MTS, SPR[Sd] := Ra
v.ctrl_ex.msr_op := LOAD_MSR; -- Ra will be written to the status bits
elsif instruction(15 downto 14) = "10" then -- MFS, Rd := SPR[Sd]
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
else -- 00 (MSRSET/MSRCLR) and 01 -> illegal
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
v.ctrl_wrb.reg_write := '1';
if instruction(16)='0' then -- SET
v.ctrl_ex.msr_op := MSR_SET;
else -- CLR
v.ctrl_ex.msr_op := MSR_CLR;
end if;
end if;
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= "00";
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
reg.block_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/fpga_top/ultimate_fpga/vhdl_source/boot_700a.vhd
|
5
|
9109
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_700a.vhd
|
3
|
9853
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_700a is
generic (
g_version : unsigned(7 downto 0) := X"F8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_700a;
architecture structural of ultimate_1541_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_analyzer => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_sim/mash_tb.vhd
|
5
|
4130
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mash_tb is
end mash_tb;
architecture tb of mash_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal dac_in : signed(11 downto 0);
signal dac_in_u : unsigned(11 downto 0);
signal dac_out : integer;
signal vc : real := 0.0;
signal min_out : integer := 10000;
signal max_out : integer := -10000;
constant R : real := 2200.0;
constant C : real := 0.00000001;
begin
clock <= not clock after 10 ns; -- 50 MHz
reset <= '1', '0' after 100 ns;
dac_in_u(dac_in_u'high) <= not dac_in(dac_in'high);
dac_in_u(dac_in_u'high-1 downto 0) <= unsigned(dac_in(dac_in'high-1 downto 0));
dac: entity work.mash
generic map (4, 12)
port map (
clock => clock,
reset => reset,
dac_in => dac_in_u,
dac_out => dac_out );
test:process
begin
dac_in <= X"000";
wait for 100 us;
for i in 0 to 9 loop
wait until clock='1';
dac_in <= X"7FF";
wait until clock='1';
dac_in <= X"800";
end loop;
dac_in <= X"001";
wait for 100 us;
dac_in <= X"002";
wait for 100 us;
dac_in <= X"003";
wait for 100 us;
dac_in <= X"011";
wait for 100 us;
dac_in <= X"022";
wait for 100 us;
dac_in <= X"033";
wait for 100 us;
dac_in <= X"100";
wait for 100 us;
dac_in <= X"200";
wait for 100 us;
dac_in <= X"400";
wait for 100 us;
dac_in <= X"7FF";
wait for 100 us;
dac_in <= X"800";
wait for 100 us;
dac_in <= X"C00";
wait for 100 us;
dac_in <= X"E00";
wait for 100 us;
dac_in <= X"F00";
wait for 100 us;
dac_in <= X"F80";
wait for 100 us;
dac_in <= X"FC0";
wait for 100 us;
dac_in <= X"FE0";
wait for 100 us;
dac_in <= X"FF0";
wait for 100 us;
dac_in <= X"FF8";
wait for 100 us;
dac_in <= X"FFC";
wait for 100 us;
dac_in <= X"FFE";
wait for 100 us;
dac_in <= X"FFF";
wait for 100 us;
-- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave)
for i in 0 to 400 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 5 us;
end loop;
-- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave)
for i in 0 to 1000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 2 us;
end loop;
-- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave)
for i in 0 to 2000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 1 us;
end loop;
dac_in <= X"000";
wait;
end process;
filter: process(clock)
variable v_dac : real;
variable i_r : real;
variable q_c : real;
begin
if rising_edge(clock) then
if dac_out > max_out then
max_out <= dac_out;
end if;
if dac_out < min_out then
min_out <= dac_out;
end if;
-- if dac_out='0' then
-- v_dac := 0.0;
-- else
-- v_dac := 3.3;
-- end if;
v_dac := real(dac_out);
i_r := (v_dac - vc) / R;
q_c := i_r * 20.0e-9; -- 20 ns;
vc <= vc + (q_c / C);
end if;
end process;
end tb;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/uart_lite/vhdl_source/uart_peripheral_io.vhd
|
1
|
5172
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_io is
generic (
g_tx_fifo : boolean := true;
g_divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq : out std_logic;
txd : out std_logic;
rxd : in std_logic := '1';
rts : out std_logic;
cts : in std_logic := '1' );
end uart_peripheral_io;
architecture gideon of uart_peripheral_io is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
constant c_uart_data : unsigned(1 downto 0) := "00";
constant c_uart_get : unsigned(1 downto 0) := "01";
constant c_uart_flags : unsigned(1 downto 0) := "10";
constant c_uart_imask : unsigned(1 downto 0) := "11";
begin
my_tx: entity work.tx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
cts => cts,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if g_tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => io_req.data,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
io_resp <= c_io_resp_init;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
txfifo_put <= '0';
if g_tx_fifo then
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
else
dotx <= '0'; -- default, overridden with write
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when c_uart_data => -- dout
if not g_tx_fifo then
txchar <= io_req.data;
dotx <= '1';
else -- there is a fifo
txfifo_put <= '1';
end if;
when c_uart_get => -- din
rxfifo_get <= '1';
when c_uart_flags => -- clear flags
overflow <= overflow and not io_req.data(0);
when c_uart_imask => -- interrupt control
imask <= io_req.data(7 downto 6);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
io_resp.data <= rdata_mux;
end if;
if (flags(7 downto 6) and imask) /= "00" then
irq <= '1';
else
irq <= '0';
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
rts <= not rxfifo_full;
with io_req.address(1 downto 0) select rdata_mux <=
rxfifo_dout when c_uart_data,
flags when c_uart_flags,
imask & "000000" when c_uart_imask,
X"00" when others;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/uart_lite/vhdl_sim/tb_rx.vhd
|
5
|
2848
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Testbench for Serial receiver: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.conversion_pkg.all;
entity tb_rx is
end tb_rx;
architecture tb of tb_rx is
component tx is
generic (clks_per_bit : integer := 434);
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
txd : out std_logic;
done : out std_logic );
end component;
component rx is
generic (clks_per_bit : integer := 434);
port (
clk : in std_logic;
reset : in std_logic;
rxd : in std_logic;
rxchar : out std_logic_vector(7 downto 0);
rx_ack : out std_logic );
end component;
signal clk : std_logic;
signal reset : std_logic;
signal dotx : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal txd : std_logic;
signal done : std_logic;
constant teststring : string := "Gideon is gek";
begin
ck: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
test: process
begin
reset <= '1';
dotx <= '0';
txchar <= (others => '0');
wait for 80 ns;
reset <= '0';
wait until clk='1';
for i in teststring'range loop
txchar <= CharToStd(teststring(i));
dotx <= '1';
wait until clk='1';
dotx <= '0';
wait until clk='1';
while done='0' loop
wait until clk='1';
end loop;
end loop;
wait;
end process;
my_tx: tx
generic map (20)
port map (
clk => clk,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: rx
generic map (20)
port map (
clk => clk,
reset => reset,
rxd => txd,
rxchar => rxchar,
rx_ack => rx_ack );
end tb;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/sid6581/vhdl_source/sid_debug_pkg.vhd
|
6
|
1235
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_debug_pkg is
type t_voice_debug is record
state : unsigned(1 downto 0);
enveloppe : unsigned(7 downto 0);
pre15 : unsigned(14 downto 0);
pre5 : unsigned(4 downto 0);
presc : unsigned(14 downto 0);
gate : std_logic;
attack : std_logic_vector(3 downto 0);
decay : std_logic_vector(3 downto 0);
sustain : std_logic_vector(3 downto 0);
release : std_logic_vector(3 downto 0);
end record;
type t_voice_debug_array is array(natural range <>) of t_voice_debug;
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/cart_slot/vhdl_source/slot_timing.vhd
|
4
|
5720
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 63 := 0;
signal phase_l : integer range 0 to 63 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
constant c_sample : integer := 6;
constant c_probe_end : integer := 11;
constant c_sample_vic : integer := 10;
constant c_io : integer := 19;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- if (phi2_rec_i='0' and allow_tick_h) or
-- (phi2_rec_i='1' and allow_tick_l) then
-- phi2_rec_i <= PHI2;
-- end if;
-- related to rising edge
-- if then -- rising edge
if ((edge_recover = '1') and (phase_l = 24)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 63 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 46 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 63 then
phase_l <= phase_l + 1;
end if;
if phase_l = 46 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
if phase_h = 0 then
inhibit <= serve_en_i;
elsif phase_h = c_sample then
inhibit <= '0';
end if;
do_sample_addr <= '0';
if phase_h = timing_addr then
do_sample_addr <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
if serve_vic='1' then
if phase_l = (c_sample_vic - c_memdelay) then
inhibit <= serve_en_i;
elsif phase_l = (c_sample_vic - 1) then
do_sample_addr <= '1';
end if;
end if;
if phase_l = c_sample_vic then
inhibit <= '0';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 63;
phase_l <= 63;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_source/io_bus_arbiter_pri.vhd
|
4
|
2183
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity io_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_io_req_array(0 to g_ports-1);
resps : out t_io_resp_array(0 to g_ports-1);
req : out t_io_req;
resp : in t_io_resp );
end entity;
architecture rtl of io_bus_arbiter_pri is
signal req_i : t_io_req;
signal select_i : integer range 0 to g_ports-1;
signal select_c : integer range 0 to g_ports-1;
type t_state is (idle, busy);
signal state : t_state;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_io_req_init;
select_i <= 0;
for i in reqs'range loop
if reqs(i).read='1' or reqs(i).write='1' then
req_i <= reqs(i);
select_i <= i;
exit;
end if;
end loop;
end process;
p_access: process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
req <= req_i;
if req_i.read='1' then
select_c <= select_i;
state <= busy;
elsif req_i.write='1' then
select_c <= select_i;
state <= busy;
end if;
when busy =>
req <= reqs(select_c);
if resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
-- send the reply to everyone, but mask the acks to non-active clients
process(resp, select_c)
begin
for i in resps'range loop
resps(i) <= resp;
if i /= select_c then
resps(i).ack <= '0';
end if;
end loop;
end process;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/ip/nano_cpu/vhdl_source/nano.vhd
|
1
|
8347
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity nano is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic;
-- system interface (to write code into the nano)
sys_clock : in std_logic := '0';
sys_reset : in std_logic := '0';
sys_io_req : in t_io_req := c_io_req_init;
sys_io_resp : out t_io_resp );
end entity;
architecture structural of nano is
signal sys_enable : std_logic;
signal sys_bram_addr : std_logic_vector(10 downto 0);
-- instruction/data ram
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal sys_io_req_bram : t_io_req;
signal sys_io_resp_bram : t_io_resp;
signal sys_io_req_regs : t_io_req;
signal sys_io_resp_regs : t_io_resp;
signal sys_core_reset : std_logic;
signal usb_reset_tig : std_logic;
signal usb_core_reset : std_logic;
signal bram_reset : std_logic;
signal bram_data : std_logic_vector(7 downto 0);
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 11,
g_ports => 2 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => sys_io_req_bram,
reqs(1) => sys_io_req_regs,
resps(0) => sys_io_resp_bram,
resps(1) => sys_io_resp_regs );
i_core: entity work.nano_cpu
port map (
clock => clock,
reset => usb_core_reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
stall => stall );
i_buf_ram: RAMB16_S9_S18
generic map (
INIT_00 => X"A028A02783E60AA7E8C1A0CA0AC3C0180BFFA03783E60AA4A0C40AB9A0CA0AB2",
INIT_01 => X"E84D0AB0C0262AB27893E026A0CA0AAEE00B83E683FD0AA4C0100BFDE9EAE8F7",
INIT_02 => X"0AA4C8352AA7783FE84D08F5A0C40AC1A0CA0AC3E028A0CA0AB2C0262AA67893",
INIT_03 => X"C03CE854C8420BFDA02883E60AA5A03EA0263AA55AA5E028C0312AA7783F83E6",
INIT_04 => X"08ECE8E780ECE05AA03EE84D0AA6A02783E60AA7E8AA83E683FD0AA4E028A028",
INIT_05 => X"C8630BFCC8420BFDC840E854B800A03783E6A03ED859783EB800C84E80EC5AA5",
INIT_06 => X"C87E52A60BFEA0C488CA80CA4AC92AA70BFEA03783E61AA80BE6E05AE9EAE8F7",
INIT_07 => X"C828E854A03EE074E8E7C87D2AA7783F80CA5AA5C07D08CA80CA0AB0A0260AA5",
INIT_08 => X"E099C87E52A52AA7783FE8E7C87E52A52AA7783FC8900BFEC09A0BFCC8420BFD",
INIT_09 => X"E8C1A030E84D0AB8A020A031A025C87E52A62AA7783FE8E7C87E52A62AA7783F",
INIT_0A => X"E0B283FE0AA4C0B02AA6783FE05A83E62ACB0BE6E8E7E8E7A027D8A15AA50ABB",
INIT_0B => X"80EC5AA508ECE8E7D0CB7839C0E10BFEA039A02980EC0ACAA0C40ABC83FE0AA5",
INIT_0C => X"08F6A020A03183FE0AA60000B800A03EA0C488CA80CA4AC62AA7A0260BFEC8BA",
INIT_0D => X"0AA7A030E0D1C8DB5AA50AC7A021C0DE80EC5AA508ECC8D35AA50AC7A03180EC",
INIT_0E => X"00400045004600000000B800D8E85AA50ABDE0C1C8E180EC5AA508ECE8E780EC",
INIT_0F => X"81E10BF281E00BF181DF0BF0B800C8FA0BF0004B15E000500055005500560050",
INIT_10 => X"B80083F00AA483F209E183F709E6E91081E50BF681E40BF581E30BF481E20BF3",
INIT_11 => X"A06309E5A06109DEA07009E4A07109E3D18B09DF81DC0AA481DB0AA7A06209E0",
INIT_12 => X"C96F52B6C13B52B5C14252B4C14852A42AAA81E6D9247864C93509E5A06009DF",
INIT_13 => X"09DFA0631AAD09E5E8E7C93052B12AAA81E6D9357864E11C81DB5AA5C16F09DB",
INIT_14 => X"2ABA39E609DF81DB0AA781DD2ACD09E6E16FC91C2AB309DFC91C09DCE124A060",
INIT_15 => X"49DD09DCA0724AA7C16109DDA07409DED956783DC1612AB609DF81DD0AA4C153",
INIT_16 => X"783DD91C51E209DDD16FC16F81E159DD09E181DE4AB609DE81DF3ABA09DF81DC",
INIT_17 => X"4AA781DD09E2D17E51E209E1A07409DE81E72AA7A07009E4A07109E3B800D96F",
INIT_18 => X"19DE1AB4C98F09DDE972B80081E36AA409E381E449DD09E4A0734AA749E72ACC",
INIT_19 => X"09E5E972C19F81E159DD09E181DE4AB609DEA06009DFD993783DA06309E5A061",
INIT_1A => X"81E6D9AD7864E1CA52B6C1D252B4C1D852B5C1C052B12AAA81E6D9A17864C9AD",
INIT_1B => X"E1D581DB5AA5C1CA09DBE1A1A0602AB709DFE8E7A0631AAD09E5C9CA52B12AAA",
INIT_1C => X"18EB2AAB09E680EB2ABA09DFC98C09E181DC49DD09DC81DB0AA781DF3ABA09DF",
INIT_1D => X"00000000000000000000E1B6C1C009E5E1A1A06009DFC1CA2AB309DFB80081E6",
INIT_1E => X"80EB89E881E90AA481E80AC00000000000000000000000000000000000000000",
INIT_1F => X"00000000B800C9EE52BF81E84AAC09E881E94AA509E9CA012ABEC9EE50EB89E8",
INIT_20 => X"DA1F51FE59FF783B81FF88EB80EB4AA909E881FE88EB80EB4AA809E881DF0000",
INIT_21 => X"783BB80090EB09FE80EB4AA409E881FEB80090EB09FE80EB4AA909E881FEE1F5",
INIT_22 => X"81E36AA409E381E449E40A00E1F5CA4B2AB189E8CA312AB409DFC1F5EA92EA11",
INIT_23 => X"09DFE910EA70EA2AEA2AEA2A81E36AA40BE481E44BE58200EA88C1F5EA85B800",
INIT_24 => X"6AA40BE081E44BE30BE1E1F5EA8DA028EA9709DCEA9719E90A00C26509DCEA18",
INIT_25 => X"83E34AAF0BE3A028EA9709DCEA9719E90BE3C26509DCEA1809DFE910EA7081E3",
INIT_26 => X"E1F5A028EA9709E6EA9719E90AC8C1F552B42AAA09E6E1F583E30AA4C9F553E2",
INIT_27 => X"09E881E288EB80EB4AA709E881E188EB80EB4AA609E881E088EB80EB4AA509E8",
INIT_28 => X"2AC44AA50BFAB8008AA382A34AC20BFAB8003BFA0BFBB80081E588EB80EB4AB2",
INIT_29 => X"2AC54AA50BF992A30AA282A34ABF0BF982A2B8003BF82AC54AA50BF9B80083FA",
INIT_2A => X"0010000E00800008F7FF700000050004000300020001000000000000B80083F9",
INIT_2B => X"0320FDFF0751005000200800004500A0FFBF4000300020000400000610000FA0",
INIT_2C => X"0000000003FFFFFCFFFB007800F1FFF002EE00ED007F003F006603A0006102E0",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKB => clock,
SSRB => reset,
ENB => ram_en,
WEB => ram_we,
ADDRB => ram_addr,
DIB => ram_wdata,
DIPB => "00",
DOB => ram_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_enable,
WEA => sys_io_req_bram.write,
ADDRA => sys_bram_addr,
DIA => sys_io_req_bram.data,
DIPA => "0",
DOA => bram_data );
sys_bram_addr(10 downto 1) <= std_logic_vector(sys_io_req_bram.address(10 downto 1));
sys_bram_addr(0) <= not sys_io_req_bram.address(0);
sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read;
bram_reset <= not sys_enable;
sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00";
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp_bram.ack <= sys_enable;
sys_io_resp_regs <= c_io_resp_init;
sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read;
if sys_io_req_regs.write = '1' then -- any address
sys_core_reset <= not sys_io_req_regs.data(0);
end if;
if sys_reset = '1' then
sys_core_reset <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
usb_reset_tig <= sys_core_reset;
usb_core_reset <= usb_reset_tig;
end if;
end process;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/host_sequencer.vhd
|
1
|
16329
|
-------------------------------------------------------------------------------
-- Title : host_sequencer
-- Author : Gideon Zweijtzer
-------------------------------------------------------------------------------
-- Description: This block generates the traffic on the downstream USB port.
-- This block has knowledge about the speeds, the USB frames,
-- and generates traffic within the right time within the frame.
-- The data interface of this block is a BRAM interface. This
-- block implements the three-time retry as well.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
entity host_sequencer is
generic (
g_buffer_depth_bits : natural := 11 ); -- 2K
port (
clock : in std_logic;
reset : in std_logic;
-- Access to buffer memory
buf_address : out unsigned(g_buffer_depth_bits-1 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
-- mode selection
sof_enable : in std_logic;
sof_tick : out std_logic;
speed : in std_logic_vector(1 downto 0);
frame_count : out unsigned(15 downto 0);
-- low level command interface
usb_cmd_req : in t_usb_cmd_req;
usb_cmd_resp : out t_usb_cmd_resp;
-- I/O to interface block
usb_rx : in t_usb_rx;
usb_tx_req : out t_usb_tx_req;
usb_tx_resp : in t_usb_tx_resp );
end entity;
architecture rtl of host_sequencer is
-- length identifiers to ram address counters
signal tx_length : unsigned(9 downto 0);
signal tx_no_data : std_logic;
signal receive_en : std_logic := '0';
signal rx_length : unsigned(9 downto 0);
signal rx_no_data : std_logic;
signal send_packet_cmd : std_logic;
signal usb_tx_req_i : t_usb_tx_req;
signal valid_packet_received : std_logic;
signal data_toggle_received : std_logic := '0';
signal data_transmission_done : std_logic := '0';
begin
b_bram_control: block
signal buffer_addr_i : unsigned(9 downto 0) := (others => '1'); -- was undefined
type t_state is (idle, prefetch, transmit_msg, wait_tx_done);
signal state : t_state;
signal transmit_en : std_logic := '0';
signal tx_last_i : std_logic;
signal tx_data_valid : std_logic;
signal tx_send_packet : std_logic;
signal buffer_index : unsigned(1 downto 0);
begin
buffer_index <= usb_cmd_req.buffer_index;
buf_address <= buffer_index & buffer_addr_i(8 downto 0);
buf_we <= usb_rx.data_valid and receive_en;
buf_wdata <= usb_rx.data;
buf_en <= receive_en or transmit_en;
transmit_en <= '1' when (state = prefetch) or
((state = transmit_msg) and (usb_tx_resp.data_wait='0'))
else '0';
tx_data_valid <= '1' when (state = transmit_msg) and (usb_tx_resp.data_wait='0')
else '0';
tx_last_i <= '1' when (buffer_addr_i = tx_length) else '0';
process(clock)
begin
if rising_edge(clock) then
if usb_rx.data_start = '1' or send_packet_cmd = '1' then
buffer_addr_i <= (others => '0');
rx_no_data <= '1';
elsif (receive_en = '1' and usb_rx.data_valid = '1') or
((transmit_en = '1') and not (tx_last_i='1' and tx_data_valid='1')) then
buffer_addr_i <= buffer_addr_i + 1;
rx_no_data <= '0';
end if;
valid_packet_received <= '0';
data_transmission_done <= '0';
if usb_rx.valid_packet = '1' and receive_en='1' then
rx_length <= buffer_addr_i;
valid_packet_received <= '1';
data_toggle_received <= get_togglebit(usb_rx.pid);
end if;
case state is
when idle =>
if send_packet_cmd = '1' then
state <= prefetch;
end if;
when prefetch =>
tx_send_packet <= '1';
state <= transmit_msg;
when transmit_msg =>
if tx_send_packet = '0' and tx_no_data = '1' then
state <= wait_tx_done;
elsif tx_last_i = '1' and tx_data_valid = '1' then
state <= wait_tx_done;
end if;
when wait_tx_done =>
if usb_tx_resp.busy = '0' then
data_transmission_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if usb_tx_resp.request_ack = '1' then
tx_send_packet <= '0';
end if;
if reset='1' then
state <= idle;
buffer_addr_i <= (others => '0');
tx_send_packet <= '0';
end if;
end if;
end process;
usb_tx_req_i.data <= buf_rdata;
usb_tx_req_i.data_valid <= tx_data_valid;
usb_tx_req_i.data_last <= tx_last_i when transmit_en='1' else '0';
usb_tx_req_i.send_packet <= tx_send_packet;
usb_tx_req_i.no_data <= tx_no_data;
end block;
usb_tx_req <= usb_tx_req_i;
b_replay: block
type t_state is (idle, wait_sof, wait_split_done, do_token, wait_token_done, do_data, wait_tx_done, wait_device_response, wait_handshake_done );
signal state : t_state;
signal timeout : std_logic;
signal start_timer : std_logic;
signal cmd_done : std_logic;
signal frame_div : integer range 0 to 8191;
signal frame_cnt : unsigned(15 downto 0) := (others => '0');
signal do_sof : std_logic;
signal sof_guard : std_logic := '0';
signal start_split_active : boolean;
signal complete_split_active : boolean;
begin
start_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '0') and (speed = "10");
complete_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '1') and (speed = "10");
process(clock)
begin
if rising_edge(clock) then
send_packet_cmd <= '0';
if frame_div = 800 then -- the last ~10% is unused for new transactions (test)
sof_guard <= '1';
end if;
if frame_div = 0 then
frame_div <= 7499; -- microframes
do_sof <= sof_enable;
sof_guard <= '0';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
cmd_done <= '0';
sof_tick <= '0';
case state is
when idle =>
receive_en <= '0';
if do_sof='1' then
sof_tick <= '1';
do_sof <= '0';
usb_tx_req_i.pid <= c_pid_sof;
usb_tx_req_i.token.device_addr <= std_logic_vector(frame_cnt(9 downto 3));
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(frame_cnt(13 downto 10));
case speed is
when "00" => -- low speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_handsh <= '1';
state <= wait_sof;
end if;
when "01" => -- full speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
end if;
when "10" => -- high speed
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
when others =>
null;
end case;
elsif sof_guard = '0' and usb_cmd_req.request = '1' and cmd_done = '0' then
-- default response
usb_cmd_resp.no_data <= '1';
usb_cmd_resp.data_length <= (others => '0');
usb_tx_req_i.split_token.e <= '0';
usb_tx_req_i.split_token.et <= usb_cmd_req.split_et;
usb_tx_req_i.split_token.sc <= usb_cmd_req.split_sc;
usb_tx_req_i.split_token.s <= usb_cmd_req.split_sp;
usb_tx_req_i.split_token.hub_address <= std_logic_vector(usb_cmd_req.split_hub_addr);
usb_tx_req_i.split_token.port_address <= "000" & std_logic_vector(usb_cmd_req.split_port_addr);
usb_tx_req_i.token.device_addr <= std_logic_vector(usb_cmd_req.device_addr);
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(usb_cmd_req.endp_addr);
if usb_cmd_req.do_split = '1' then
usb_tx_req_i.pid <= c_pid_split;
usb_tx_req_i.send_split <= '1';
state <= wait_split_done;
else
state <= do_token;
end if;
end if;
when wait_sof =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= idle;
end if;
when wait_split_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_token;
end if;
when do_token =>
usb_tx_req_i.send_token <= '1';
state <= wait_token_done;
case usb_cmd_req.command is
when setup =>
usb_tx_req_i.pid <= c_pid_setup;
when in_request =>
usb_tx_req_i.pid <= c_pid_in;
when out_data =>
usb_tx_req_i.pid <= c_pid_out;
when others =>
usb_tx_req_i.pid <= c_pid_ping;
end case;
when wait_token_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_data;
end if;
when do_data =>
case usb_cmd_req.command is
when setup | out_data =>
if usb_cmd_req.do_data = '1' then
send_packet_cmd <= '1';
tx_no_data <= usb_cmd_req.no_data;
tx_length <= usb_cmd_req.data_length;
if usb_cmd_req.togglebit='0' then
usb_tx_req_i.pid <= c_pid_data0;
else
usb_tx_req_i.pid <= c_pid_data1;
end if;
state <= wait_tx_done;
else
state <= wait_device_response;
end if;
when in_request =>
receive_en <= usb_cmd_req.do_data;
state <= wait_device_response;
when others =>
state <= wait_device_response;
end case;
when wait_tx_done =>
if data_transmission_done = '1' then
state <= wait_device_response;
end if;
when wait_device_response =>
usb_tx_req_i.pid <= c_pid_ack;
if usb_rx.valid_handsh = '1' then
usb_cmd_resp.result <= encode_result(usb_rx.pid);
cmd_done <= '1';
state <= idle;
elsif usb_rx.error='1' or timeout='1' then
usb_cmd_resp.result <= res_error;
cmd_done <= '1';
state <= idle;
elsif valid_packet_received = '1' then -- woohoo!
usb_cmd_resp.result <= res_data;
usb_cmd_resp.no_data <= rx_no_data;
usb_cmd_resp.data_length <= rx_length;
usb_cmd_resp.togglebit <= data_toggle_received;
-- we send an ack to the device. Thank you!
if complete_split_active and usb_cmd_req.split_et(0)='1' then
cmd_done <= '1';
state <= idle;
else
usb_tx_req_i.send_handsh <= '1';
state <= wait_handshake_done;
end if;
end if;
when wait_handshake_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
cmd_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
usb_tx_req_i.pid <= X"0";
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_split <= '0';
usb_tx_req_i.send_handsh <= '0';
do_sof <= '0';
end if;
end if;
end process;
usb_cmd_resp.done <= cmd_done;
frame_count <= frame_cnt;
start_timer <= usb_tx_resp.busy or usb_rx.receiving;
i_timer: entity work.timer
generic map (
g_width => 10 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => to_unsigned(767, 10),
timeout => timeout );
end block;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/sid6581/vhdl_source/sid_mixer.vhd
|
6
|
3710
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sid_mixer is
port (
clock : in std_logic;
reset : in std_logic;
valid_in : in std_logic := '0';
direct_out : in signed(17 downto 0);
high_pass : in signed(17 downto 0);
band_pass : in signed(17 downto 0);
low_pass : in signed(17 downto 0);
filter_hp : in std_logic;
filter_bp : in std_logic;
filter_lp : in std_logic;
volume : in unsigned(3 downto 0);
mixed_out : out signed(17 downto 0);
valid_out : out std_logic );
end sid_mixer;
architecture arith of sid_mixer is
signal mix_i : signed(17 downto 0);
signal mix_uns : unsigned(16 downto 0);
signal vol_uns : unsigned(16 downto 0);
signal vol_s : signed(16 downto 0);
signal state : integer range 0 to 7;
signal p_mul : unsigned(33 downto 0);
signal p_mul_s : signed(34 downto 0);
type t_volume_lut is array(natural range <>) of unsigned(15 downto 0);
constant c_volume_lut : t_volume_lut(0 to 15) := (
X"0000", X"0EEF", X"1DDE", X"2CCD", X"3BBC", X"4AAA", X"5999", X"6888",
X"7777", X"8666", X"9555", X"A444", X"B333", X"C221", X"D110", X"DFFF" );
begin
process(clock)
variable mix_total : signed(17 downto 0);
begin
if rising_edge(clock) then
valid_out <= '0';
state <= state + 1;
case state is
when 0 =>
if valid_in = '1' then
mix_i <= sum_limit(direct_out, to_signed(16384, 18));
else
state <= 0;
end if;
when 1 =>
if filter_hp='1' then
mix_i <= sum_limit(mix_i, high_pass);
end if;
when 2 =>
if filter_bp='1' then
mix_i <= sum_limit(mix_i, band_pass);
end if;
when 3 =>
if filter_lp='1' then
mix_i <= sum_limit(mix_i, low_pass);
end if;
when 4 =>
-- p_mul <= mix_uns * vol_uns;
p_mul_s <= mix_i * vol_s;
valid_out <= '1';
state <= 0;
when others =>
state <= 0;
end case;
-- mix_total := not(p_mul(32)) & signed(p_mul(31 downto 15));
-- mixed_out <= mix_total; -- + to_signed(16384, 18);
mixed_out <= p_mul_s(33 downto 16);
if reset='1' then
mix_i <= (others => '0');
state <= 0;
end if;
end if;
end process;
-- vol_uns <= "0" & volume & volume & volume & volume;
-- vol_uns <= '0' & c_volume_lut(to_integer(volume));
-- mix_uns <= not mix_i(17) & unsigned(mix_i(16 downto 1));
vol_s <= '0' & signed(c_volume_lut(to_integer(volume)));
end arith;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/ip/memory/vhdl_source/dpram_rdw.vhd
|
5
|
4658
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/AP9_cpu_b.vhd
|
2
|
16087
|
--SETCARRY NEEDS TO BE FIXED!!!
---------------------------------------------------
--APx-ARCH AP9 Micro-processor---------------------
--16-bits width bus--------------------------------
--External clock-----------------------------------
--Builded by MicroENIX, copyright (r) 2011---------
--For detailed description about this--------------
--architechture, please refer to the AP9 reference--
--manual.------------------------------------------
---------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AP9_cpu IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MEM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_WDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RW : OUT STD_LOGIC;
VGA_DRAW : OUT STD_LOGIC;
VGA_POS : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
VGA_CC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
PC_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
HALT_ACK : OUT STD_LOGIC
);
END AP9_cpu;
ARCHITECTURE main OF AP9_cpu IS
TYPE STATES IS (fetch, decode, exec, halted);
TYPE REGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE LOADREGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC;
CONSTANT LOAD : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110000";
CONSTANT STORE : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110001";
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111000";
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111100";
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111101";
CONSTANT MOV : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110011";
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110010";
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110101";
CONSTANT ARITH : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT SUB : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT DIV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT INC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LMOD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT CMP : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110";
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT LAND : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT LOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT LXOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LNOT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT JMP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000010";
CONSTANT CALL : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000011";
CONSTANT RTS : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000100";
CONSTANT PUSH : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000101";
CONSTANT POP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000110";
CONSTANT NOP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
CONSTANT SETC : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001000";
CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111";
CONSTANT sULA : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT sMEM : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT sM4 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT sKEY : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT FRGREATER : INTEGER := 0;
CONSTANT FRLESSER : INTEGER := 1;
CONSTANT FREQUAL : INTEGER := 2;
CONSTANT FRZERO : INTEGER := 3;
CONSTANT FRCARRY : INTEGER := 4;
CONSTANT FRARITHOF : INTEGER := 5;
CONSTANT FRDIVZERO : INTEGER := 6;
CONSTANT FRSTACKOF : INTEGER := 7;
CONSTANT FRSTACKUF : INTEGER := 8;
CONSTANT IF1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT IFE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT IFNE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT IFZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT IFNZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT IFC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT IFNC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT IFGR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT IFLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT IFEG : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
CONSTANT IFEL : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
CONSTANT IFOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
CONSTANT IFNOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
SIGNAL OP : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL X, Y, RESULT: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL FR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL auxFR : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE STATE : STATES;
VARIABLE PC : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE SP : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE MAR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RX : INTEGER;
VARIABLE RY : INTEGER;
VARIABLE RZ : INTEGER;
VARIABLE selM2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE selM6 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE IncPC : STD_LOGIC;
VARIABLE IncSP : STD_LOGIC;
VARIABLE DecSP : STD_LOGIC;
VARIABLE LoadPC : STD_LOGIC;
VARIABLE LoadMAR : STD_LOGIC;
VARIABLE LoadIR : STD_LOGIC;
VARIABLE LoadREG : LOADREGISTERS;
VARIABLE COND : STD_LOGIC;
VARIABLE REG : REGISTERS;
BEGIN
IF(RST = '1') THEN
STATE := fetch;
PC := x"0000";
SP := x"3FFC";
IR := x"0000";
MAR := x"0000";
selM2 := sMEM;
selM6 := sULA;
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadPC := '0';
LoadMAR := '0';
LoadIR := '0';
LoadREG := x"00";
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
HALT_ACK <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(HALT_REQ = '1') THEN
STATE := halted;
END IF;
IF(LoadPC = '1') THEN
PC := MEM_DATA;
LoadPC := '0';
END IF;
CASE selM2 IS
WHEN sMEM =>
M2 := MEM_DATA;
WHEN sM4 =>
M2 := M4;
WHEN sKEY =>
M2(15 DOWNTO 8) := x"00";
M2(7 DOWNTO 0) := KEY;
WHEN sULA =>
M2 := RESULT;
WHEN OTHERS =>
END CASE;
IF(LoadMAR = '1') THEN
MAR := MEM_DATA;
LoadMAR := '0';
END IF;
IF(IncSP = '1') THEN
SP := SP + x"1";
IncSP := '0';
END IF;
IF(DecSP = '1') THEN
SP := SP - x"1";
DecSP := '0';
END IF;
IF(LoadIR = '1') THEN
IR := MEM_DATA;
LoadIR := '0';
END IF;
IF(LoadREG(RX) = '1') THEN
REG(RX) := M2;
LoadREG(RX) := '0';
END IF;
IF(IncPC = '1') THEN
PC := PC + x"1";
IncPC := '0';
END IF;
CASE selM6 IS
WHEN sULA =>
FR <= auxFR;
WHEN sMEM =>
FR <= MEM_DATA;
WHEN OTHERS =>
END CASE;
selM6 := sULA;
PC_DATA <= PC;
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
RX := conv_integer(IR(9 DOWNTO 7));
RY := conv_integer(IR(6 DOWNTO 4));
RZ := conv_integer(IR(3 DOWNTO 1));
CASE STATE IS
WHEN fetch =>
MEM_ADDR <= PC;
LoadIR := '1';
IncPC := '1';
STATE := decode;
WHEN decode =>
IF(IR(15 DOWNTO 14) = ARITH) THEN
CASE IR(13 DOWNTO 10) IS
WHEN INC =>
X <= REG(RX);
M4 := x"0001";
Y <= M4;
IF(IR(6) = '0') THEN
OP <= '0' & ARITH & ADD;
ELSE
OP <= '0' & ARITH & SUB;
END IF;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= IR(0) & ARITH & IR(13 DOWNTO 10);
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSIF(IR(15 DOWNTO 14) = LOGIC) THEN
CASE IR(13 DOWNTO 10) IS
WHEN LNOT =>
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & LNOT;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN CMP =>
X <= REG(RX);
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & CMP;
STATE := fetch;
WHEN SHIFT =>
CASE IR(6 DOWNTO 4) IS
WHEN "000" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "001" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "010" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "011" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "100" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROL conv_integer(IR(3 DOWNTO 0)));
WHEN "110" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROR conv_integer(IR(3 DOWNTO 0)));
WHEN OTHERS =>
END CASE;
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= '0' & LOGIC & IR(13 DOWNTO 10);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSE
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN STORE =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN LOADIMED =>
MEM_ADDR <= PC;
selM2 := sMEM;
LoadREG(RX) := '1';
IncPC := '1';
STATE := fetch;
WHEN LOADINDEX =>
M4 := REG(RY);
MEM_ADDR <= M4;
selM2 := sMEM;
LoadREG(RX) := '1';
STATE := fetch;
WHEN STOREINDEX =>
MEM_ADDR <= REG(RX);
M4 := REG(RY);
MEM_WDATA <= M4;
MEM_RW <= '1';
STATE := fetch;
WHEN MOV =>
M4 := REG(RY);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OUTCHAR =>
VGA_CC <= REG(RX);
M4 := REG(RY);
VGA_POS <= M4;
VGA_DRAW <= '1';
STATE := fetch;
WHEN INCHAR =>
selM2 := sKEY;
LoadReg(RX) := '1';
STATE := fetch;
WHEN JMP =>
MEM_ADDR <= PC;
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
LoadPC := '1';
ELSE
IncPC := '1';
END IF;
STATE := fetch;
WHEN CALL =>
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
MEM_WDATA <= PC;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := exec;
ELSE
IncPC := '1';
STATE := fetch;
END IF;
WHEN RTS =>
IncSP := '1';
STATE := exec;
WHEN PUSH =>
IF(IR(6) = '0') THEN
MEM_WDATA <= REG(RX);
ELSE
MEM_WDATA <= FR;
END IF;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := fetch;
WHEN POP =>
IncSP := '1';
STATE := exec;
WHEN NOP =>
STATE := fetch;
WHEN SETC =>
selM6 := sULA;
FR(FRCARRY) <= IR(9);
STATE := fetch;
WHEN HALT =>
STATE := halted;
WHEN OTHERS =>
STATE := fetch;
END CASE;
END IF;
WHEN exec =>
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= MAR;
selM2 := sMEM;
LoadReg(RX) := '1';
STATE := fetch;
WHEN STORE =>
MEM_ADDR <= MAR;
MEM_WDATA <= REG(RX);
MEM_RW <= '1';
STATE := fetch;
WHEN CALL =>
MEM_ADDR <= PC;
LoadPC := '1';
STATE := fetch;
WHEN RTS =>
MEM_ADDR <= SP;
LoadPC := '1';
IncPC := '1';
STATE := fetch;
WHEN POP =>
MEM_ADDR <= SP;
selM2 := sMEM;
IF(IR(6) = '0') THEN
LoadREG(RX) := '1';
ELSE
selM6 := sMEM;
END IF;
STATE := fetch;
WHEN OTHERS =>
STATE := fetch;
END CASE;
WHEN halted =>
HALT_ACK <= '1';
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(OP, X, Y, RST)
VARIABLE AUX : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
ELSE
auxFR <= FR;
IF(OP(5 DOWNTO 4) = ARITH) THEN
CASE OP(3 DOWNTO 0) IS
WHEN ADD =>
IF(OP(6) = '1') THEN
AUX := X + Y + FR(FRCARRY);
RESULT32 := (x"00000000" + X + Y + FR(FRCARRY));
ELSE
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
END IF;
IF(RESULT32 > "01111111111111111") THEN
auxFR(FRCARRY) <= '1';
ELSE
auxFR(FRCARRY) <= '0';
END IF;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 DOWNTO 0);
IF(RESULT32 > x"0000FFFF") THEN
auxFR(FRARITHOF) <= '1';
ELSE
auxFR(FRARITHOF) <= '0';
END IF;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(FRDIVZERO) <= '1';
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(FRDIVZERO) <= '0';
END IF;
WHEN LMOD =>
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) MOD CONV_INTEGER(Y), 16);
WHEN OTHERS =>
AUX := X;
END CASE;
IF(AUX = x"0000") THEN
auxFR(3) <= '1';
ELSE
auxFR(3) <= '0';
END IF;
RESULT <= AUX;
ELSIF(OP (5 DOWNTO 4) = LOGIC) THEN
IF(OP (3 DOWNTO 0) = CMP) THEN
result <= x;
IF(X > Y) THEN
auxFR(2 DOWNTO 0) <= "001";
ELSIF (X < Y) THEN
auxFR(2 DOWNTO 0) <= "010";
ELSIF (X = Y) THEN
auxFR(2 DOWNTO 0) <= "100";
END IF;
ELSE
CASE OP (3 DOWNTO 0) IS
WHEN LAND =>
RESULT <= X AND Y;
WHEN LXOR =>
RESULT <= X XOR Y;
WHEN LOR =>
RESULT <= X OR Y;
WHEN LNOT =>
RESULT <= NOT Y;
WHEN OTHERS =>
RESULT <= X;
END CASE;
IF(RESULT = x"0000") THEN
auxFR(FRZERO) <= '1';
ELSE
auxFR(FRZERO) <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END main;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/videolatch.vhd
|
1
|
1180
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY videolatch IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
iDRAW : IN STD_LOGIC;
iLPOS : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
iCHAR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
oDRAW : out STD_LOGIC;
oLPOS : out STD_LOGIC_VECTOR(15 DOWNTO 0);
oCHAR : out STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END videolatch;
ARCHITECTURE behavioral OF videolatch IS
SIGNAL DRAW : STD_LOGIC := '0';
SIGNAL LPOS : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHAR : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
process(clk)
begin
if(rising_edge(clk)) then
oDRAW <= DRAW;
oLPOS <= LPOS;
oCHAR <= CHAR;
end if;
end process;
process(iDRAW)
begin
if(rising_edge(iDRAW)) then
DRAW <= iDRAW;
LPOS <= iLPOS;
CHAR <= iCHAR;
-- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco !
if( iCHAR(11 downto 8) = "0000" ) then
CHAR(11 downto 8) <= "1111";
elsif( iCHAR(11 downto 8) = "1111" ) then
CHAR(11 downto 8) <= "0000";
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/KB_TRANSCEIVER.vhd
|
4
|
3439
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/REG2.vhd
|
1
|
736
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY REG2 IS
PORT(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
LID : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
I : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END REG2;
ARCHITECTURE main OF REG2 IS
BEGIN
PROCESS(CLK, CLR)
VARIABLE DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IF(CLR = '1') THEN
DATA := x"0000";
O <= x"0000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(LID(0) = '1') THEN
DATA := I;
ELSIF(LID(1) = '1') THEN
DATA := DATA + x"1";
ELSIF(LID(2) = '1') THEN
DATA := DATA - x"1";
END IF;
END IF;
O <= DATA;
END PROCESS;
END main;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/dec_keyboard.vhd
|
1
|
5918
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY dec_keyboard IS
PORT( hex_bus : IN STD_LOGIC_VECTOR(7 downto 0);
scan_rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
bin_digit : OUT STD_LOGIC_VECTOR(7 downto 0);
int : out std_LOGIC;
rst : in std_LOGIC
);
END dec_keyboard;
-------------------------- -- ------------------------------------
ARCHITECTURE a OF dec_keyboard IS
type states is (idle, press, pressed, released);
signal state : states;
signal code : std_logic_vector(7 downto 0) := x"00";
signal buffero : std_logic_vector(7 downto 0) := x"00";
signal f : std_logic;
signal f2 : std_logic;
signal f3 : std_logic;
signal s : std_logic;
BEGIN
------------------------ -- ----------------------------------------
PROCESS (clk, rst)
variable saida : STD_LOGIC_VECTOR (7 downto 0) := x"00";
BEGIN
if(rst = '1') then
state <= idle;
int <= '0';
elsif(rising_edge(clk)) then
case hex_bus is --bloco das teclas normais (n�o e' case sensitive)
when x"1c" => saida := x"41"; --A
when x"32" => saida := x"42"; --B
when x"21" => saida := x"43"; --C
when x"23" => saida := x"44"; --D
when x"24" => saida := x"45"; --E
when x"2b" => saida := x"46"; --F
when x"34" => saida := x"47"; --G
when x"33" => saida := x"48"; --H
when x"43" => saida := x"49"; --I
when x"3b" => saida := x"4a"; --J
when x"42" => saida := x"4b"; --K
when x"4b" => saida := x"4c"; --L
when x"3a" => saida := x"4d"; --M
when x"31" => saida := x"4e"; --N
when x"44" => saida := x"4f"; --O
when x"4d" => saida := x"50"; --P
when x"15" => saida := x"51"; --Q
when x"2d" => saida := x"52"; --R
when x"1b" => saida := x"53"; --S
when x"2c" => saida := x"54"; --T
when x"3c" => saida := x"55"; --U
when x"2a" => saida := x"56"; --V
when x"1d" => saida := x"57"; --W
when x"22" => saida := x"58"; --X
when x"35" => saida := x"59"; --Y
when x"1a" => saida := x"5a"; --Z
when x"29" => saida := x"20"; --space
when x"66" => saida := x"08"; --backspace
when x"5a" => saida := x"0d"; --enter
when x"12" => saida := x"0e"; --shift esquerdo
when x"59" => saida := x"0f"; --shift direito
when x"14" => saida := x"fd"; --ctrl Codigo Inventado
when x"11" => saida := x"fe"; --alt Codigo Inventado
when x"0d" => saida := x"09"; --tab
when x"76" => saida := x"1b"; --ESC
when x"41" => saida := x"3c"; -- <
when x"49" => saida := x"3e"; -- >
when x"61" => saida := x"5c"; -- \
when x"4a" => saida := x"3f"; -- ?
when x"51" => saida := x"2f"; -- /
when x"4c" => saida := x"3b"; -- ;
when x"52" => saida := x"7e"; -- ~
when x"5d" => saida := x"5d"; -- ]
when x"54" => saida := x"60"; -- `
when x"5b" => saida := x"5b"; -- [
when x"69" => saida := x"e1"; --num1 Codigo Inventado
when x"72" => saida := x"e2"; --num2 Codigo Inventado
when x"7a" => saida := x"e3"; --num3 Codigo Inventado
when x"6b" => saida := x"e4"; --num4 Codigo Inventado
when x"73" => saida := x"e5"; --num5 Codigo Inventado
when x"74" => saida := x"e6"; --num6 Codigo Inventado
when x"6c" => saida := x"e7"; --num7 Codigo Inventado
when x"75" => saida := x"e8"; --num8 Codigo Inventado
when x"7d" => saida := x"e9"; --num9 Codigo Inventado
when x"16" => saida := x"31"; --1
when x"1e" => saida := x"32"; --2
when x"26" => saida := x"33"; --3
when x"25" => saida := x"34"; --4
when x"2e" => saida := x"35"; --5
when x"36" => saida := x"36"; --6
when x"3d" => saida := x"37"; --7
when x"3e" => saida := x"38"; --8
when x"46" => saida := x"39"; --9
when x"45" => saida := x"30"; --0
when x"05" => saida := x"f1"; --F1 Codigo Inventado
when x"06" => saida := x"f2"; --F2 Codigo Inventado
when x"04" => saida := x"f3"; --F3 Codigo Inventado
when x"0C" => saida := x"f4"; --F4 Codigo Inventado
when x"03" => saida := x"f5"; --F5 Codigo Inventado
when x"0B" => saida := x"f6"; --F6 Codigo Inventado
when x"83" => saida := x"f7"; --F7 Codigo Inventado
when x"0A" => saida := x"f8"; --F8 Codigo Inventado
when x"01" => saida := x"f9"; --F9 Codigo Inventado
when x"09" => saida := x"fa"; --F10 Codigo Inventado
when x"78" => saida := x"fb"; --F11 Codigo Inventado
when x"07" => saida := x"fc"; --F12 Codigo Inventado
when others => saida := x"ff"; -- Se nao for nenhum desses, responde FF
end case;
case state is
when idle =>
int <= '0';
if(saida /= x"ff") then --pressiona
state <= press;
end if;
buffero <= saida;
when press =>
int <= '1';
state <= pressed;
when pressed =>
if(saida = x"ff") then --pressiona
state <= released;
end if;
int <= '0';
when released =>
buffero <= x"80" or buffero;
int <= '1';
saida := x"ff";
state <= idle;
when others =>
state <= idle;
end case;
bin_digit <= buffero;
end if;
END PROCESS;
PROCESS (f2, scan_rd)
BEGIN
if(f2='0') then
if(scan_rd'EVENT AND scan_rd='1') then
f<='1';
end if;
else
f<='0';
end if;
END PROCESS;
----------------- -- -------------------------------
PROCESS(clk)
BEGIN
if(rising_edge(clk))then
if(f='1') then
case s is
when '0' =>
f3 <= '1';
s <= '1';
when '1' =>
f3 <= '0';
f2 <= '1';
s <= '0';
end case;
else
f2 <='0';
end if;
end if;
END PROCESS;
--------------- -- ----------------------------------
END a;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/lpm_dff2.vhd
|
3
|
3921
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/pit.vhdl
|
1
|
4427
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PIT IS
PORT(
clk : in std_logic;
rst : in std_logic;
bus_dq : inout std_logic_vector(15 downto 0);
bus_rw : in std_logic;
bus_req : in std_logic;
bus_addr : in std_logic_vector(15 downto 0);
int : out std_logic_vector(2 downto 0);
bus_ack : out std_logic_vector(2 downto 0)
);
END PIT;
ARCHITECTURE behavioral OF PIT IS
-- Internal Registers
signal div1 : unsigned(15 downto 0) := x"ffff";
signal div1c : unsigned(15 downto 0):= x"0000";
signal f1 : std_logic :='0';
signal div2 : unsigned(15 downto 0):= x"ffff";
signal div2c : unsigned(15 downto 0):= x"0000";
signal f2 : std_logic:='0';
signal div3 : unsigned(15 downto 0):= x"ffff";
signal div3c : unsigned(15 downto 0):= x"0000";
signal f3 : std_logic:='0';
signal controller : std_logic_vector(15 downto 0) := x"0000";
signal counter1 : unsigned(15 downto 0):= x"000A";
signal counter2 : unsigned(15 downto 0):= x"0064";
signal counter3 : unsigned(15 downto 0):= x"03E8";
signal inta : std_logic_vector(2 downto 0);
BEGIN
process(clk, rst)
begin
if(rst='1') then
controller <= (others => '0');
div1 <= (others => '1');
div2 <= (others => '1');
div3 <= (others => '1');
elsif(rising_edge(clk)) then
bus_ack <= "000";
if(bus_req = '1') then
case bus_addr is
when x"0990" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div1 <= unsigned(bus_dq);
else
bus_dq <= std_logic_vector(counter1);
bus_ack <= "001";
end if;
when x"0991" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div2 <= unsigned(bus_dq);
else
bus_dq <=std_logic_vector(counter2);
bus_ack <= "010";
end if;
when x"0992" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div3 <= unsigned(bus_dq);
else
bus_dq <=std_logic_vector(counter3);
bus_ack <= "100";
end if;
when x"0993" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
controller <= bus_dq;
else
bus_dq <= (others => '0');
end if;
when others =>
end case;
end if;
end if;
end process;
--geradore de clock
process(clk, rst)
begin
if(rst = '1') then
div1c <= x"0000";
elsif(rising_edge(clk)) then
IF div1c < div1 THEN
div1c <= div1c + '1';
ELSE
div1c <= x"0000";
f1 <= not f1;
END IF;
IF div2c < div2 THEN
div2c <= div2c + '1';
ELSE
div2c <= x"0000";
f2 <= not f2;
END IF;
IF div3c < div3 THEN
div3c <= div3c + '1';
ELSE
div3c <= x"0000";
f3 <= not f3;
END IF;
end if;
end process;
process(f1, div1, rst)
begin
if(rst='1') then
counter1 <= x"000A";
elsif(rising_edge(f1)) then
counter1 <= counter1 - 1;
if(std_logic_vector(counter1) = x"0000") then
counter1 <= x"000A";
end if;
end if;
end process;
process(f2, div2, rst)
begin
if(rst = '1') then
counter2<= x"0064";
elsif(rising_edge(f2)) then
counter2 <= counter2 - 1;
if(std_logic_vector(counter2) = x"0000") then
counter2 <= x"0064";
end if;
end if;
end process;
process(f3, div3, rst)
begin
if(rst = '1') then
counter3 <= x"03E8";
elsif(rising_edge(f3)) then
counter3 <= counter3 - 1;
if(std_logic_vector(counter3) = x"0000") then
counter3 <= x"03E8";
end if;
end if;
end process;
process(rst, clk)
begin
if(rst = '1') then
int <= "000";
elsif(rising_edge(clk))then
int <= "000";
if(std_logic_vector(counter1) = x"0000") then
if(controller(0) = '1' and inta(0) = '0') then
int(0) <= '1';
inta(0) <= '1';
end if;
else
inta(0) <= '0';
end if;
if(std_logic_vector(counter2) = x"0000") then
if(controller(1) = '1' and inta(1) = '0') then
int(1) <= '1';
inta(1) <= '1';
end if;
else
inta(1) <= '0';
end if;
if(std_logic_vector(counter3) = x"0000") then
if(controller(2) = '1' and inta(2) = '0') then
int(2) <= '1';
inta(2) <= '1';
end if;
else
inta(2) <= '0';
end if;
end if;
end process;
END behavioral;
|
gpl-3.0
|
quicky2000/top_chenillard
|
testbench/tb_chenillard.vhd
|
1
|
2820
|
--
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_chenillard IS
END tb_chenillard;
ARCHITECTURE behavior OF tb_chenillard IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT chenillard
PORT(
clk : IN std_logic;
reset : IN std_logic;
button : IN std_logic;
led1 : OUT std_logic;
led2 : OUT std_logic;
led3 : OUT std_logic;
led4 : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal button : std_logic := '0';
--Outputs
signal led1 : std_logic;
signal led2 : std_logic;
signal led3 : std_logic;
signal led4 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: chenillard PORT MAP (
clk => clk,
reset => reset,
button => button,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/alias4.vhd
|
5
|
412
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
asicguy/crash
|
fpga/src/common/synchronizer.vhd
|
2
|
3005
|
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers. If
-- the signal is a strobe, the edge can be specified.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end entity;
architecture RTL of synchronizer is
component edge_detect
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic;
reset : in std_logic;
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
signal async_meta1 : std_logic;
signal async_meta2 : std_logic;
begin
proc_synchronize : process(clk,reset)
begin
if (reset = '1') then
async_meta1 <= RESET_OUTPUT;
async_meta2 <= RESET_OUTPUT;
else
if rising_edge(clk) then
async_meta1 <= async;
async_meta2 <= async_meta1;
end if;
end if;
end process;
gen_if_use_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) /= 'N') generate
inst_edge_detect : edge_detect
generic map (
EDGE => STROBE_EDGE)
port map (
clk => clk,
reset => reset,
input_detect => async_meta2,
edge_detect_stb => sync);
end generate;
gen_if_no_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) = 'N') generate
sync <= async_meta2;
end generate;
end RTL;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/proc1.vhd
|
5
|
380
|
entity proc1 is
end entity;
architecture test of proc1 is
procedure add1(x : in integer; y : out integer) is
begin
y := x + 1;
end procedure;
begin
process is
variable a, b : integer;
begin
a := 2;
add1(a, b);
assert b = 3;
add1(5, b);
assert b = 6;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/issue221.vhd
|
5
|
723
|
package fred4 is
type fred4_t is protected
impure function is_empty return boolean;
impure function hi_there return string;
end protected fred4_t;
end package fred4;
package body fred4 is
type fred4_t is protected body
----------------------------------------
impure function is_empty return boolean is
begin
return TRUE;
end function is_empty;
----------------------------------------
impure function hi_there return string is
begin
if is_empty then
return "perfect";
else
return "we have a problem";
end if;
end function hi_there;
----------------------------------------
end protected body fred4_t;
end package body fred4;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/elab19.vhd
|
5
|
916
|
entity sub2 is
port (
x : in bit;
y : out bit );
end entity;
architecture test of sub2 is
begin
y <= x after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture test of sub1 is
begin
sub_g: for i in x'range generate
sub2_i: entity work.sub2
port map ( x(i), y(i) );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab19 is
end entity;
architecture test of elab19 is
signal o : bit_vector(7 downto 0);
begin
sub1_i: entity work.sub1
port map ( X"ab", o );
process is
begin
wait for 2 ns;
assert o = X"ab";
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/bounds/issue200.vhd
|
5
|
255
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/gcr_encoder.vhd
|
5
|
1636
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/usb2/vhdl_source/ulpi_tx.vhd
|
1
|
11383
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_tx is
generic (
g_simulation : boolean := false;
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
-- Bus Interface
tx_start : out std_logic;
tx_last : out std_logic;
tx_valid : out std_logic;
tx_next : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
rx_busy : in std_logic;
-- CRC calculator
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_to_crc : out std_logic_vector(7 downto 0);
data_crc : in std_logic_vector(15 downto 0);
-- Status
status : in std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp );
end ulpi_tx;
architecture gideon of ulpi_tx is
type t_state is (idle, crc_1, crc_2, token0, token1, token2, token3,
transmit, wait4next, write_end, handshake, gap, gap2);
signal state : t_state;
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_last_i : std_logic;
signal token_crc : std_logic_vector(4 downto 0) := "00000";
signal split_crc : std_logic_vector(4 downto 0) := "00000";
signal no_data_d : std_logic;
signal gap_count : integer range 0 to 2047;
signal rd_data : std_logic_vector(7 downto 0);
signal rd_last : std_logic;
signal rd_next : std_logic;
signal token_vector : std_logic_vector(18 downto 0);
signal long : boolean;
signal fifo_flush : std_logic;
signal busy : std_logic;
signal sending_sof : boolean;
signal tx_allowed : std_logic;
signal start_value : unsigned(10 downto 0);
signal start_timer : std_logic;
signal tx_put : std_logic;
signal almost_full : std_logic;
-- internal fifo is 3 bytes as it seems. 3 bytes is at max 40 bits incl. 1.5 SE0 EOP. at Full speed this is 40*5 = 200 clocks
-- at low speed this is 40*40 clocks = 1600
type t_int_array is array (natural range <>) of integer;
constant c_gap_values : t_int_array(0 to 3) := ( 1599, 199, 13, 13 );
-- XILINX USB STICK:
-- On high speed, gap values 0x05 - 0x25 WORK.. (bigger than 0x25 doesn't, smaller than 0x05 doesn't..)
-- TRUST USB 2.0 Hub:
-- On high speed, gap values 0x07 - 0x1D WORK.. with the exception of 0x09.
-- Samsung DVD-Burner:
-- On high speed, gap values 0x00 - 0x23 WORK.. with the exception of 0x04.
-- Western Digital external HD:
-- On high speed, gap values 0x05 - 0x21 WORK.. with the exception of 0x06 and 0x09.
--
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
begin
usb_tx_resp.request_ack <= (usb_tx_req.send_token or usb_tx_req.send_handsh or usb_tx_req.send_packet or usb_tx_req.send_split)
when (state = idle) and (tx_allowed = '1') else '0';
usb_tx_resp.busy <= busy;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
fifo_flush <= '0';
tx_data_i <= X"00";
no_data_d <= usb_tx_req.no_data;
long <= false;
sending_sof <= usb_tx_req.pid = c_pid_sof;
if tx_allowed = '1' then
if usb_tx_req.send_token='1' and g_support_token then
token_vector <= token_to_vector(usb_tx_req.token) & X"00";
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= token1;
elsif usb_tx_req.send_split='1' and g_support_split then
token_vector <= split_token_to_vector(usb_tx_req.split_token);
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
long <= true;
state <= token0;
elsif usb_tx_req.send_handsh='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
tx_last_i <= '1';
state <= handshake;
elsif usb_tx_req.send_packet='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= wait4next;
end if;
end if;
when wait4next =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '1';
if no_data_d='1' then
state <= crc_1;
else
state <= transmit;
end if;
end if;
when handshake =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= gap;
end if;
when write_end =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
when crc_1 =>
if tx_next = '1' then
tx_last_i <= '1';
fifo_flush <= '1';
state <= crc_2;
end if;
when crc_2 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when token0 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(7 downto 0);
state <= token1;
end if;
when token1 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(15 downto 8);
state <= token2;
end if;
when token2 =>
if tx_next = '1' then
if long then
tx_data_i <= split_crc & token_vector(18 downto 16);
else
tx_data_i <= token_crc & token_vector(18 downto 16);
end if;
tx_last_i <= '1';
state <= token3;
end if;
when token3 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when gap => -- pulse timer
state <= gap2;
when gap2 =>
if tx_allowed = '1' then
state <= idle;
end if;
when transmit =>
if tx_next='1' and rd_last='1' then
state <= crc_1;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
fifo_flush <= '0';
end if;
end if;
end process;
crc_dvalid <= '1' when (state = transmit) and tx_next='1' else '0';
--crc_sync <= '1' when (state = idle) else '0';
crc_sync <= usb_tx_req.send_packet;
busy <= '0' when (state = idle) else '1'; -- or (state = gap) else '1';
g_token: if g_support_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
token_in => token_vector(18 downto 8),
crc => token_crc );
end generate;
g_split: if g_support_split generate
i_split_crc: entity work.token_crc_19
port map (
clock => clock,
token_in => token_vector(18 downto 0),
crc => split_crc );
end generate;
with state select tx_data <=
rd_data when transmit,
data_crc(7 downto 0) when crc_1,
data_crc(15 downto 8) when crc_2,
tx_data_i when others;
tx_last <= tx_last_i;
rd_next <= '1' when (tx_next = '1') and (state = transmit) else '0';
tx_put <= usb_tx_req.data_valid and not almost_full;
usb_tx_resp.data_wait <= almost_full;
i_tx_fifo: entity work.srl_fifo
generic map (
Width => 9,
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => rd_next,
PutElement => tx_put,
FlushFifo => fifo_flush,
DataIn(8) => usb_tx_req.data_last,
DataIn(7 downto 0) => usb_tx_req.data,
DataOut(8) => rd_last,
DataOut(7 downto 0) => rd_data,
SpaceInFifo => open,
AlmostFull => almost_full,
DataInFifo => open );
data_to_crc <= rd_data;
start_timer <= '1' when state = gap else rx_busy; -- we start the tx_backoff timer when we are receiving, or when we finished transmitting
process(sending_sof, speed, status)
begin
if g_simulation then
start_value <= to_unsigned(15, start_value'length);
elsif rx_busy = '1' then
start_value <= to_unsigned(12, start_value'length);
elsif sending_sof and speed(1)='1' then
start_value <= to_unsigned(22, start_value'length);
else
case speed is
when "00" => start_value <= to_unsigned(c_gap_values(0), start_value'length);
when "01" => start_value <= to_unsigned(c_gap_values(1), start_value'length);
when others => start_value <= to_unsigned(c_gap_values(2), start_value'length);
end case;
end if;
end process;
i_timer: entity work.timer
generic map (
g_reset => '1',
g_width => 11 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => start_value,
timeout => tx_allowed );
end gideon;
|
gpl-3.0
|
luigicalligaris/cms-phase2upgrade-tt-firmware
|
firmware/post_am_htrz/htrz_components/hdl/htrz_top.vhd
|
1
|
27284
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--
--
-- htrz_constants.vhd
--
--
package htrz_constants is
constant width_phi : natural := 18;
constant width_rS : natural := 18;
constant base_rS : real := 7.62939453125e-5;
constant width_zS : natural := 18;
constant base_zS : real := 7.62939453125e-5;
constant width_bend : natural := 4;
constant width_Sindex : natural := 7;
-- Definition of constants, widths and bases for variables internal to the HTRZ
constant width_rT : natural := 18;
constant base_rT : real := 7.62939453125e-5;
constant width_zC : natural := 18;
constant base_zC : real := 7.62939453125e-5;
constant width_zG : natural := 18;
constant base_zG : real := 7.62939453125e-5;
constant width_cotantheta : natural := 13;
constant base_cotantheta : real := 9.765625e-4;
constant nbins_zT : natural := 8;
constant width_zT_bin : natural := 3;
assert ceil( log(2.0, nbins_zT) ) <= width_zT_bin report "Not enough bits (width_zT_bin) to represent nbins_zT" severity error;
-- THIS WILL DEPEND ON THE CHOICE OF THE MULTIPLIER IN THE INITIAL DSP CALCULATION!!!!!!!
-- IT IS CRITICALLY IMPORTANT TO CHOOSE IT PROPERLY OR YOU WILL BE PICKING UP EITHER
-- SCRAMBLED NUMBERS OR ALL '1' OR '0'
constant bitposition_msb_zT_bin_in_zT : natural := 15;
constant bitposition_lsb_overflow_guard_in_zT : natural := 15;
constant bitposition_msb_overflow_guard_in_zT : natural := 18;
constant nbins_cotantheta : natural := 8;
constant nboundaries_cotantheta : natural := nbins_cotantheta + 1;
constant n_stubs_per_roadlayer : natural := 4;
constant n_layers : natural := 6;
end;
--
--
-- htrz_data_types.vhd
--
--
package htrz_data_types is
type t_stub is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub : t_stub := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_stub_no_z is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_no_z : t_stub_no_z := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_roadlayer is array (n_stubs_per_roadlayer - 1 downto 0) of t_stub;
constant null_roadlayer : t_roadlayer := (others => null_stub)
type t_road is array (n_layers - 1 downto 0) of t_roadlayer;
constant null_road : t_road := (others => null_roadlayer)
type t_valid_column is std_logic_vector(nbins_zT - 1 downto 0);
constant null_valid_column : t_valid_column := (others => '0');
type t_valid_cell_matrix is array (nbins_cotantheta - 1 downto 0) of t_valid_column;
constant null_valid_cell_matrix := ( others => null_valid_column );
type t_valid_cell_matrixarray is array (natural range<>) of t_valid_cell_matrix;
-- constant null_valid_cell_matrixarray := ( others => null_valid_cell_matrix );
type t_valid_border_matrix is array (nboundaries_cotantheta - 1 downto 0) of t_valid_column;
constant null_stubvalid_bordermatrix := ( others => null_valid_column );
end;
--
--
-- htrz_stub_validity_borders2cells.vhd
--
--
entity htrz_stub_validity_borders2cells is
port (
clk : in std_logic;
valid_stub_in : in std_logic;
valid_borders_in : in t_valid_border_matrix;
valid_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_borders2cells is
signal local1_valid_stub : std_logic;
signal local1_valid_borders : t_valid_border_matrix := null_stubvalid_bordermatrix;
signal local2_valid_cell_matrix : t_valid_cell_matrix := null_valid_cell_matrix;
begin
valid_cells_out <= local2_valid_cell_matrix;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_valid_stub <= valid_stub_in;
local1_valid_borders <= valid_borders_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- LOOSE ACCEPTANCE POLICY (recommended)
-- B C B
-- --------
-- 0| 0 |0
-- 1| 1 |0
-- 1| 1 |1
-- 0| 1 |1
-- 0| 0 |0
local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] or local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- TIGHT ACCEPTANCE POLICY
-- B C B
-- --------
-- 0| 0 |0
-- 1| 0 |0
-- 1| 1 |1
-- 0| 0 |1
-- 0| 0 |0
-- local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] and local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- NOTE: In case the stub line gradients are above 1, i.e. the jump can be larger than one cell up/down, you will have also to manage the case
-- highlighted by the ? below. For this reason, gradients equal or below 1 make the firmware simpler.
--
-- B C B
-- --------
-- 1| 0 |0
-- 1| ? |0
-- 0| ? |0
-- 0| ? |1
-- 0| 0 |1
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_layer_validity_stubs2layer.vhd
--
--
entity htrz_layer_validity_stubs2layer is
port (
clk : in std_logic;
stubs_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
layer_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_layer_validity_stubs2layer is
signal local1_stubs_cellmatrices : t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_layer_cells : t_valid_cell_matrix := null_valid_cell_matrix;
begin
layer_cells_out <= local2_layer_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_stubs_cellmatrices <= stubs_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_stubs_validity : std_logic_vector(n_stubs_per_roadlayer - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells into the vector...
-- /| /| /| /| /|
-- / | / | / | / | / |
-- / | / | / | / | / |
-- /00 | / | / | / | ---> thiscell_stubs_validity(0,1,2,3) for cell [4,4] /## |
-- / 0| / | / | / X | / #|
-- / | / | / | / | --vec OR reduction--> / |
-- | / | / | 2 / | X / | # /
-- | / | / | 2 / | / ---> thiscell_stubs_validity(0,1,2,3) for cell [2,2] | # /
-- | / | / |2 / | / |# /
-- | / | / | / | / | /
-- |/ |/ |/ |/ |/
-- e.g. INVALID (therefore, ignored)
-- Stub0 Stub1 Stub2 Stub3 Layer valid cells
--
gen_layers : for iStub in 0 to n_stubs_per_roadlayer generate
thiscell_stubs_validity[iStub] <= local1_stubs_cellmatrices[iStub][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = or thiscell_stubs_validity;
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_road_validity_layermajority.vhd
--
--
entity htrz_road_validity_layermajority is
generic(
layercount_threshold : natural := 5
);
port (
clk : in std_logic;
layer_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
road_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_validity_layermajority is
signal local1_layer_cellmatrices : t_valid_cell_matrixarray(n_layers - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
function majority( hitpattern: std_logic_vector( n_layers - 1 downto 0 ); threshold: integer ) return std_logic is
variable counter: integer := 0;
begin
for k in n_layers - 1 downto 0 loop
if hitpattern( k ) = '1' then
counter := counter + 1;
end if;
end loop;
if counter > threshold - 1 then
return '1';
end if;
return '0';
end function;
begin
road_cells_out <= local2_road_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_layer_cellmatrices <= layer_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_layer_validity : std_logic_vector(n_layers - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells to the vector...
-- /| /| /| /| /| /| /|
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | / |
-- / 0 | / 1 | / 2 | / 3 | / | / 5 | ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [4,4] / # |
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | --majority--> / |
-- | / | / | / | / | / | / | /
-- | 0 / | 1 / | / | 3 / | 4 / | 5 / ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [2,2] | # /
-- | / | / | / | / | / | / | /
-- | / | / | / | / | / | / | /
-- |/ |/ |/ |/ |/ |/ |/
--
-- Layer0 Layer1 Layer2 Layer3 Layer4 Layer5 Road valid cells
--
gen_layers : for iLayer in 0 to n_layers generate
thiscell_layer_validity[iLayer] <= local1_layer_cellmatrices[iLayer][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = majority(thiscell_layer_validity, layercount_threshold);
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_stub_validity_stub_vs_road.vhd
--
--
entity htrz_stub_validity_stub_vs_road is
port (
clk : in std_logic;
road_cells_in : in t_valid_cell_matrix;
stub_cells_in : in t_valid_cell_matrix;
stub_valid_cells_out : out t_valid_cell_matrix;
stub_valid_out : out std_logic
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_stub_vs_road is
signal local1_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local1_stub_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells_asvec : std_logic_vector(nbins_cotantheta * nbins_zT - 1 downto 0) := ( others => '0');
signal local3_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local3_stub_valid : std_logic := '0';
begin
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_road_cells <= road_cells_in;
local1_stub_cells <= stub_cells_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
begin
-- /| /| /|
-- / | / | / |
-- / | / | / |
-- / S | / R | ---> (S and R) for cell [4,4] / # |
-- / | / | / |
-- / | / | / | --> CAST TO std_logic_vector (X*Y bit) --> OR reduce --> stub validity (1 bit)
-- | / | / | /
-- | S / | / ---> (S and R) for cell [2,2] | /
-- | / | / | /
-- | / | / | /
-- |/ |/ |/
--
-- Stub Road Stub AND Road
local2_stub_valid_cells_asvec[iCotanColumn * nbins_zT + iZtRow] <= local2_stub_valid_cells[iCotanColumn][iZtRow];
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_stub_valid_cells[iCotanColumn][iZtRow] = local1_road_cells[iCotanColumn][iZtRow] and local1_stub_cells[iCotanColumn][iZtRow];
end if;
end process;
end generate;
end generate;
stub_valid_cells_out <= local3_stub_valid_cells;
stub_valid_out <= local3_stub_valid;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 3
local3_stub_valid_cells <= local2_stub_valid_cells;
-- OR reduction
local3_stub_valid <= or local2_stub_valid_cells_asvec;
end if;
end process;
end;
--
--
-- htrz_stub_column.vhd
--
--
entity htrz_stub_column is
generic(
ibin_cotantheta : natural
);
port (
clk : in std_logic;
zT_lo_in : in std_logic_vector(zT_width - 1 downto 0);
zT_hi_in : in std_logic_vector(zT_width - 1 downto 0);
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
zG_in : in std_logic_vector(zG_width - 1 downto 0);
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_column is
-- LOCALCLK 1
signal local1_zT_lo_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zT_hi_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
signal local2_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
-- LOCALCLK 2
signal local2_zT_lo_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_hi_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_bin_lo_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal local2_zT_bin_hi_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal stubvalid_column : t_valid_column => null_valid_column;
constant delay_stubvalid_column : natural := ( (nbins_cotantheta - 1) - ibin_cotantheta ) * 2;
type t_shiftreg_stubvalid_column is array ( natural range<> ) of t_valid_column;
signal shiftreg_stubvalid_column : t_shiftreg_stubvalid_column (delay_stubvalid_column downto 0) := (others => null_valid_column);
begin
-- Outputs are asynchronously bound to output registers
zT_lo_out <= local2_zT_lo_right;
zT_hi_out <= local2_zT_hi_right;
zG_out <= local2_zG;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
-- Input registers
local1_zT_lo_left <= zT_lo_in;
local1_zT_hi_left <= zT_hi_in;
local1_zG <= zG_in;
-- LOCALCLK 2
-- Calc and write into output registers (see async copy to outputs above)
local2_zT_lo_right <= std_logic_vector( resize( signed(local1_zT_lo_left) + signed(local1_zG), zT_width - 1 ) );
local2_zT_hi_right <= std_logic_vector( resize( signed(local1_zT_hi_left) + signed(local1_zG), zT_width - 1 ) );
local2_zG <= local1_zG;
-- LOCALCLK 3
local2_zT_bin_lo_right <= local2_zT_lo_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
local2_zT_bin_hi_right <= local2_zT_hi_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
for iZT in nbins_zT - 1 downto 0 loop
-- Depending on the width of zT, an addidional guard against over/under-flows may be needed
shiftreg_stubvalid_column[delay_stubvalid_column][iZT] <= (local2_zT_bin_lo_right <= iZT) and (local2_zT_bin_hi_right >= iZT)
end loop;
-- Shift register to delay the results
shiftreg_stubvalid_column[delay_stubvalid_column] <= stubvalid_column;
if delay_stubvalid_column > 0 then
for i_shift in delay_stubvalid_column downto 1 loop
shiftreg_stubvalid_column[i_shift - 1] <= shiftreg_stubvalid_column[i_shift];
end loop;
end if;
delayed_stubvalid_column_out <= shiftreg_stubvalid_column[0];
end if;
end process;
end;
--
--
-- htrz_gradient_unit.vhd
--
--
entity htrz_gradient_unit is
port (
clk : in std_logic;
stub_in : in t_stub;
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
-- zT_lo_underflow_out : out std_logic;
-- zT_lo_overflow_out : out std_logic;
-- zT_hi_underflow_out : out std_logic;
-- zT_hi_overflow_out : out std_logic;
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_gradient_unit is
attribute ram_style of stubIDRam: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
end if;
end process;
end;
end;
--
--
-- htrz_stub_ring_delay.vhd
--
--
entity htrz_stub_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_ring_delay is
-- These numbers are FPGA-specific, consult the FPGA memory user guide to find out the RAM depth
constant min_delay : natural := 1 + 1 + 0 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
constant max_delay : natural := 1 + 1 + 511 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
assert delay < min_delay report "Delay is too small for this component" severity error;
assert delay > max_delay report "Delay is too long for this component to use on-chip BRAMS" severity error;
constant ring_delay : natural := delay - 4;
constant ram_pointer_width : natural := 9;
-- Total 36 bits
type t_stub_ram0 is
record
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
end record;
constant null_stub_ram0 : t_stub_ram0 := ( Ri => (others => '0'), z => (others => '0') );
-- Total 30 bits
type t_stub_ram1 is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex : std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_ram1 : t_stub_ram1 := ( valid => '0', phi => (others => '0'), Bend => (others => '0'), Sindex => (others => '0'), );
signal stub_writereg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_writereg_ram1 : t_stub_ram1 := null_stub_ram1;
signal stub_readreg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_readreg_ram1 : t_stub_ram1 := null_stub_ram1;
signal write_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( ring_delay ) );
signal read_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( 0 ) );
type t_ringbuffer_ram0 is array ( natural range <> ) of t_stub_ram0;
type t_ringbuffer_ram1 is array ( natural range <> ) of t_stub_ram1;
signal ringbuffer_ram0: t_bufferRam_ram0( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram0 );
signal ringbuffer_ram1: t_bufferRam_ram1( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram1 );
attribute ram_style of ringbuffer_ram0: signal is "block";
attribute ram_style of ringbuffer_ram1: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
-- Repack input into write register
stub_writereg_ram0.Ri <= road_in.Ri ;
stub_writereg_ram0.z <= road_in.z ;
stub_writereg_ram1.valid <= road_in.valid ;
stub_writereg_ram1.phi <= road_in.phi ;
stub_writereg_ram1.Bend <= road_in.Bend ;
stub_writereg_ram1.Sindex <= road_in.Sindex;
-- Read from write register and write into BRAM
ringbuffer_ram0[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram0;
ringbuffer_ram1[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram1;
-- Read from BRAM into read register
stub_readreg_ram0 <= ringbuffer_ram0[ to_integer( unsigned( read_pointer ) ) ];
stub_readreg_ram1 <= ringbuffer_ram1[ to_integer( unsigned( read_pointer ) ) ];
-- Repack from read register into output
road_out.Ri <= stub_writereg_ram0.Ri ;
road_out.z <= stub_writereg_ram0.z ;
road_out.valid <= stub_writereg_ram1.valid ;
road_out.phi <= stub_writereg_ram1.phi ;
road_out.Bend <= stub_writereg_ram1.Bend ;
road_out.Sindex <= stub_writereg_ram1.Sindex;
-- Move one step further
write_pointer <= std_logic_vector( unsigned( write_pointer ) + 1 ) when unsigned( write_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
read_pointer <= std_logic_vector( unsigned( read_pointer ) + 1 ) when unsigned( read_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
end if;
end process;
end;
--
--
-- htrz_road_ring_delay.vhd
--
--
entity htrz_road_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
road_in : in t_road;
road_out : out t_road
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_ring_delay is
component htrz_stub_ring_delay
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
begin
gen_layers_in_road: for iLayer in 0 to n_layers - 1 generate
signal stubs_in_this_layer_in : t_roadlayer := null_roadlayer;
signal stubs_in_this_layer_out : t_roadlayer := null_roadlayer;
begin
stubs_in_this_layer_in <= road_in [iLayer];
road_out[iLayer] <= stubs_in_this_layer_out;
gen_stubs_in_layer: for iStub in 0 to n_stubs_per_roadlayer - 1 generate
signal this_stub_in : t_stub := null_stub;
signal this_stub_out : t_stub := null_stub;
begin
this_stub_in <= stubs_in_this_layer_in[iStub];
stubs_in_this_layer_out[iStub] <= this_stub_out;
instance_stubdelay: htrz_stub_ring_delay generic map ( delay ) port map (clk, this_stub_in, this_stub_out);
end generate;
end generate;
end;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/sid6581/vhdl_source/sid_top.vhd
|
1
|
11900
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity sid_top is
generic (
g_8voices : boolean := false;
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
comb_wave_l : in std_logic := '0';
comb_wave_r : in std_logic := '0';
io_req_filt0 : in t_io_req := c_io_req_init;
io_resp_filt0 : out t_io_resp;
io_req_filt1 : in t_io_req := c_io_req_init;
io_resp_filt1 : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_top;
architecture structural of sid_top is
-- Voice index in pipe
signal voice_osc : unsigned(3 downto 0);
signal voice_wave : unsigned(3 downto 0);
signal voice_mul : unsigned(3 downto 0);
signal enable_osc : std_logic;
signal enable_wave : std_logic;
signal enable_mul : std_logic;
-- Oscillator parameters
signal freq : unsigned(15 downto 0);
signal test : std_logic;
signal sync : std_logic;
-- Wave map parameters
signal msb_other : std_logic;
signal comb_mode : std_logic;
signal ring_mod : std_logic;
signal wave_sel : std_logic_vector(3 downto 0);
signal sq_width : unsigned(11 downto 0);
-- ADSR parameters
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
-- Filter enable
signal filter_en : std_logic;
-- globals
signal volume_l : unsigned(3 downto 0);
signal filter_co_l : unsigned(10 downto 0);
signal filter_res_l : unsigned(3 downto 0);
signal filter_ex_l : std_logic;
signal filter_hp_l : std_logic;
signal filter_bp_l : std_logic;
signal filter_lp_l : std_logic;
signal voice3_off_l : std_logic;
signal volume_r : unsigned(3 downto 0);
signal filter_co_r : unsigned(10 downto 0);
signal filter_res_r : unsigned(3 downto 0);
signal filter_ex_r : std_logic;
signal filter_hp_r : std_logic;
signal filter_bp_r : std_logic;
signal filter_lp_r : std_logic;
signal voice3_off_r : std_logic;
-- readback
signal osc3 : std_logic_vector(7 downto 0);
signal env3 : std_logic_vector(7 downto 0);
-- intermediate flags and signals
signal test_wave : std_logic;
signal osc_val : unsigned(23 downto 0);
signal carry_20 : std_logic;
signal enveloppe : unsigned(7 downto 0);
signal waveform : unsigned(11 downto 0);
signal valid_sum : std_logic;
signal valid_filt : std_logic;
signal valid_mix : std_logic;
signal filter_out_l: signed(17 downto 0) := (others => '0');
signal direct_out_l: signed(17 downto 0) := (others => '0');
signal high_pass_l : signed(17 downto 0) := (others => '0');
signal band_pass_l : signed(17 downto 0) := (others => '0');
signal low_pass_l : signed(17 downto 0) := (others => '0');
signal mixed_out_l : signed(17 downto 0) := (others => '0');
signal filter_out_r: signed(17 downto 0) := (others => '0');
signal direct_out_r: signed(17 downto 0) := (others => '0');
signal high_pass_r : signed(17 downto 0) := (others => '0');
signal band_pass_r : signed(17 downto 0) := (others => '0');
signal low_pass_r : signed(17 downto 0) := (others => '0');
signal mixed_out_r : signed(17 downto 0) := (others => '0');
begin
i_regs: entity work.sid_regs
generic map (
g_8voices => g_8voices )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
comb_wave_l => comb_wave_l,
comb_wave_r => comb_wave_r,
---
voice_osc => voice_osc,
voice_wave => voice_wave,
voice_adsr => voice_wave,
voice_mul => voice_mul,
-- Oscillator parameters
freq => freq,
test => test,
sync => sync,
-- Wave map parameters
comb_mode => comb_mode,
ring_mod => ring_mod,
wave_sel => wave_sel,
sq_width => sq_width,
-- ADSR parameters
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
-- mixer parameters
filter_en => filter_en,
-- globals
volume_l => volume_l,
filter_co_l => filter_co_l,
filter_res_l=> filter_res_l,
filter_ex_l => filter_ex_l,
filter_hp_l => filter_hp_l,
filter_bp_l => filter_bp_l,
filter_lp_l => filter_lp_l,
voice3_off_l=> voice3_off_l,
volume_r => volume_r,
filter_co_r => filter_co_r,
filter_res_r=> filter_res_r,
filter_ex_r => filter_ex_r,
filter_hp_r => filter_hp_r,
filter_bp_r => filter_bp_r,
filter_lp_r => filter_lp_r,
voice3_off_r=> voice3_off_r,
-- readback
osc3 => osc3,
env3 => env3 );
i_ctrl: entity work.sid_ctrl
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
start_iter => start_iter,
voice_osc => voice_osc,
enable_osc => enable_osc );
osc: entity work.oscillator
generic map (g_num_voices)
port map (
clock => clock,
reset => reset,
voice_i => voice_osc,
voice_o => voice_wave,
enable_i => enable_osc,
enable_o => enable_wave,
freq => freq,
test => test,
sync => sync,
osc_val => osc_val,
test_o => test_wave,
carry_20 => carry_20,
msb_other => msb_other );
wmap: entity work.wave_map
generic map (
g_num_voices => g_num_voices,
g_sample_bits => 12 )
port map (
clock => clock,
reset => reset,
test => test_wave,
osc_val => osc_val,
carry_20 => carry_20,
msb_other => msb_other,
voice_i => voice_wave,
enable_i => enable_wave,
comb_mode => comb_mode,
wave_sel => wave_sel,
ring_mod => ring_mod,
sq_width => sq_width,
voice_o => voice_mul,
enable_o => enable_mul,
wave_out => waveform );
adsr: entity work.adsr_multi
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
voice_i => voice_wave,
enable_i => enable_wave,
voice_o => open,
enable_o => open,
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
env_state=> open, -- for testing only
env_out => enveloppe );
sum: entity work.mult_acc(signed_wave)
port map (
clock => clock,
reset => reset,
voice_i => voice_mul,
enable_i => enable_mul,
voice3_off_l=> voice3_off_l,
voice3_off_r=> voice3_off_r,
enveloppe => enveloppe,
waveform => waveform,
filter_en => filter_en,
--
osc3 => osc3,
env3 => env3,
--
valid_out => valid_sum,
filter_out_L => filter_out_L,
filter_out_R => filter_out_R,
direct_out_L => direct_out_L,
direct_out_R => direct_out_R );
i_filt_left: entity work.sid_filter
port map (
clock => clock,
reset => reset,
io_req => io_req_filt0,
io_resp => io_resp_filt0,
filt_co => filter_co_l,
filt_res => filter_res_l,
valid_in => valid_sum,
input => filter_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
error_out => open,
valid_out => valid_filt );
-- Now we have to add the following signals together:
-- direct_out
-- high_pass (when filter_hp='1')
-- band_pass (when filter_bp='1')
-- low_pass (when filter_lp='1')
--
-- .. and apply the final volume control
mix: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
filter_hp => filter_hp_l,
filter_bp => filter_bp_l,
filter_lp => filter_lp_l,
volume => volume_l,
mixed_out => mixed_out_L,
valid_out => valid_mix );
r_right_filter: if g_num_voices > 8 generate
i_filt: entity work.sid_filter
port map (
clock => clock,
reset => reset,
io_req => io_req_filt1,
io_resp => io_resp_filt1,
filt_co => filter_co_r,
filt_res => filter_res_r,
valid_in => valid_sum,
input => filter_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
error_out => open,
valid_out => open );
mix_right: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
filter_hp => filter_hp_r,
filter_bp => filter_bp_r,
filter_lp => filter_lp_r,
volume => volume_r,
mixed_out => mixed_out_R,
valid_out => open );
end generate;
sample_left <= mixed_out_L;
sample_right <= mixed_out_R when g_num_voices > 8 else mixed_out_L;
end structural;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/memory/vhdl_source/dpram_sc.vhd
|
2
|
3164
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram_sc is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_global_init : std_logic_vector := X"0000";
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_sc : entity is "yes";
end entity;
architecture xilinx of dpram_sc is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => g_global_init);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
p_port_b: process(clock)
begin
if rising_edge(clock) then
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/driver5.vhd
|
5
|
513
|
entity driver5 is
end entity;
architecture test of driver5 is
type int_vec is array (integer range <>) of integer;
function resolved(x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal s : rint;
begin
s <= 5;
process is
begin
assert s = 2;
wait for 0 ns;
assert s = 2;
s <= 4;
wait for 1 ns;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/group/issue95.vhd
|
5
|
289
|
entity issue95 is
end entity;
architecture behav of issue95 is
type point is record
x : integer;
z : boolean;
end record point;
type point_array is array(0 to 2) of point;
signal points : point_array := (others => (x => 1, z => true));
begin
end behav;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/nios_dut/nios_dut/synthesis/submodules/virtual_jtag.vhd
|
2
|
4026
|
-- virtual_jtag.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity virtual_jtag is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; -- .tdo
ir_in : out std_logic_vector(3 downto 0); -- .ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => '0'); -- .ir_out
virtual_state_cdr : out std_logic; -- .virtual_state_cdr
virtual_state_sdr : out std_logic; -- .virtual_state_sdr
virtual_state_e1dr : out std_logic; -- .virtual_state_e1dr
virtual_state_pdr : out std_logic; -- .virtual_state_pdr
virtual_state_e2dr : out std_logic; -- .virtual_state_e2dr
virtual_state_udr : out std_logic; -- .virtual_state_udr
virtual_state_cir : out std_logic; -- .virtual_state_cir
virtual_state_uir : out std_logic; -- .virtual_state_uir
tck : out std_logic -- tck.clk
);
end entity virtual_jtag;
architecture rtl of virtual_jtag is
component sld_virtual_jtag is
generic (
sld_auto_instance_index : string := "YES";
sld_instance_index : integer := 0;
sld_ir_width : integer := 1
);
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(3 downto 0); -- ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component sld_virtual_jtag;
begin
virtual_jtag_0 : component sld_virtual_jtag
generic map (
sld_auto_instance_index => "YES",
sld_instance_index => 0,
sld_ir_width => 4
)
port map (
tdi => tdi, -- jtag.tdi
tdo => tdo, -- .tdo
ir_in => ir_in, -- .ir_in
ir_out => ir_out, -- .ir_out
virtual_state_cdr => virtual_state_cdr, -- .virtual_state_cdr
virtual_state_sdr => virtual_state_sdr, -- .virtual_state_sdr
virtual_state_e1dr => virtual_state_e1dr, -- .virtual_state_e1dr
virtual_state_pdr => virtual_state_pdr, -- .virtual_state_pdr
virtual_state_e2dr => virtual_state_e2dr, -- .virtual_state_e2dr
virtual_state_udr => virtual_state_udr, -- .virtual_state_udr
virtual_state_cir => virtual_state_cir, -- .virtual_state_cir
virtual_state_uir => virtual_state_uir, -- .virtual_state_uir
tck => tck -- tck.clk
);
end architecture rtl; -- of virtual_jtag
|
gpl-3.0
|
chiggs/nvc
|
test/regress/block1.vhd
|
5
|
591
|
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/lower/assign2.vhd
|
4
|
470
|
entity assign2 is
end entity;
architecture test of assign2 is
begin
process is
variable x : bit_vector(7 downto 0) := (1 => '1', others => '0');
subtype myint is integer range 1 to 10;
type myint_array is array (integer range <>) of myint;
variable y : myint_array(1 to 3);
begin
assert x(0) = '0';
assert x(4) = x(7);
x(2) := '1';
y(1) := y(3);
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/lower/assign1.vhd
|
4
|
455
|
entity assign1 is
end entity;
architecture test of assign1 is
begin
process is
variable x : integer := 64;
variable y : integer := -4;
begin
wait for 4 ns;
assert x = 64;
assert y = -4;
x := y * 2;
assert x = -8;
x := 5;
y := 7;
assert x = 5;
assert y = 7;
wait for 1 ns;
assert x + y = 12;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/usb/vhdl_sim/token_crc_tb.vhd
|
2
|
1527
|
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
|
gpl-3.0
|
chiggs/nvc
|
test/parse/process.vhd
|
2
|
334
|
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/elab2.vhd
|
5
|
764
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v5.vhd
|
1
|
16254
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
entity harness_v5 is
end harness_v5;
architecture tb of harness_v5 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal LB_ADDR : std_logic_vector(14 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal logic_SDRAM_CSn : std_logic;
signal logic_SDRAM_RASn : std_logic;
signal logic_SDRAM_CASn : std_logic;
signal logic_SDRAM_WEn : std_logic;
signal logic_SDRAM_CKE : std_logic;
signal logic_SDRAM_CLK : std_logic;
signal logic_SDRAM_DQM : std_logic;
signal logic_LB_ADDR : std_logic_vector(14 downto 0);
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal sys_shifted : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
-- shared variable rom : h_mem_object;
-- shared variable bram : h_mem_object;
-- memory controller interconnect
signal memctrl_inhibit : std_logic := '0';
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- cache monitoring
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
mut: entity work.ultimate_logic
generic map (
g_simulation => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => true,
g_ram_expansion => true,
g_extended_reu => true,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- io bus for simulation
sim_io_req => io_req,
sim_io_resp => io_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_CLOCK => ULPI_CLOCK,
ULPI_RESET => ULPI_RESET,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Buttons
BUTTON => BUTTON );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => '0', --memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => logic_SDRAM_CSn,
SDRAM_RASn => logic_SDRAM_RASn,
SDRAM_CASn => logic_SDRAM_CASn,
SDRAM_WEn => logic_SDRAM_WEn,
SDRAM_CKE => logic_SDRAM_CKE,
SDRAM_CLK => logic_SDRAM_CLK,
MEM_A => logic_LB_ADDR,
MEM_D => LB_DATA );
-- clock to out.. for data it is inside of the memory controller, because it's bidirectional
SDRAM_CSn <= transport logic_SDRAM_CSn after 4.9 ns;
SDRAM_RASn <= transport logic_SDRAM_RASn after 4.9 ns;
SDRAM_CASn <= transport logic_SDRAM_CASn after 4.9 ns;
SDRAM_WEn <= transport logic_SDRAM_WEn after 4.9 ns;
SDRAM_CKE <= transport logic_SDRAM_CKE after 4.9 ns;
SDRAM_CLK <= transport logic_SDRAM_CLK after 4.9 ns;
LB_ADDR <= transport logic_LB_ADDR after 4.9 ns;
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
sys_shifted <= transport sys_clock after 15 ns; -- 270 degrees
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_ulpi_phy: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 100000 )
port map (
clock => ULPI_CLOCK,
reset => ULPI_RESET,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
-- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome
-- process. It would work with a good model of the serial spi flash, but since it is not included in the public
-- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram:
load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"D400";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
-- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
-- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
-- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
-- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
-- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
-- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
-- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
-- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
-- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
-- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
-- constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
-- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
-- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/attr11.vhd
|
5
|
383
|
entity attr11 is
end entity;
architecture test of attr11 is
begin
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0';
assert i'a = "101";
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/elab16.vhd
|
5
|
1143
|
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
x : out int8 );
end entity;
architecture test of sub is
begin
xg: for i in int8'range generate
x(i) <= val + i;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab16 is
end entity;
use work.elab16_pack.all;
architecture test of elab16 is
signal xs : int8_vector(0 to 7);
begin
sub_g: for i in 0 to 7 generate
sub_i: entity work.sub
generic map (
val => i * 8 )
port map (
x => xs(i) );
end generate;
process is
begin
wait for 1 ns;
for i in 0 to 7 loop
for j in 0 to 7 loop
assert xs(i)(j) = (i * 8) + j;
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/func1.vhd
|
5
|
355
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
assert r = 3 report integer'image(r);
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
target/simulation/vhdl_bfm/sram_model_8.vhd
|
5
|
2119
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/issue115.vhd
|
5
|
552
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/altera/u2p_cia_io.vhd
|
1
|
6320
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.io_bus_pkg.all;
entity u2p_cia_io is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
addr : out std_logic_vector(3 downto 0);
cs_n : out std_logic;
cs2 : out std_logic;
reset_n : out std_logic;
rw_n : out std_logic;
phi2 : out std_logic;
irq_n : in std_logic;
rising : out std_logic;
falling : out std_logic;
db_from_my_cia : in std_logic_vector(7 downto 0);
pb_from_my_cia : in std_logic_vector(7 downto 0);
hs_from_my_cia : in std_logic_vector(4 downto 0);
irq_from_my_cia : in std_logic;
db_to_cia : out std_logic_vector(7 downto 0);
db_from_cia : in std_logic_vector(7 downto 0);
db_drive : out std_logic;
pa_to_cia : out std_logic_vector(7 downto 0);
pa_from_cia : in std_logic_vector(7 downto 0);
pa_drive : out std_logic_vector(7 downto 0);
pb_to_cia : out std_logic_vector(7 downto 0);
pb_from_cia : in std_logic_vector(7 downto 0);
pb_drive : out std_logic_vector(7 downto 0);
hs_to_cia : out std_logic_vector(4 downto 0);
hs_from_cia : in std_logic_vector(4 downto 0);
hs_drive : out std_logic_vector(4 downto 0) );
end entity;
architecture rtl of u2p_cia_io is
signal reg_addr : std_logic_vector(3 downto 0);
signal reg_cs_n : std_logic;
signal reg_cs2 : std_logic;
signal reg_reset_n : std_logic;
signal reg_rw_n : std_logic;
signal reg_phi2 : std_logic;
signal reg_hs_to_cia : std_logic_vector(4 downto 0);
begin
process(clock, reset)
variable local : unsigned(3 downto 0);
begin
if reset = '1' then -- switched to asynchronous reset
reg_addr <= X"0";
reg_cs_n <= '1';
reg_cs2 <= '0';
reg_reset_n <= '1';
reg_rw_n <= '1';
reg_phi2 <= '0';
db_to_cia <= (others => '0');
pa_to_cia <= (others => '0');
pa_drive <= (others => '0');
pb_to_cia <= (others => '0');
pb_drive <= (others => '0');
reg_hs_to_cia <= (others => '0');
hs_drive <= (others => '0');
elsif rising_edge(clock) then
local := io_req.address(3 downto 0);
io_resp <= c_io_resp_init;
if io_req.read = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
io_resp.data(3 downto 0) <= reg_addr;
when X"1" =>
io_resp.data <= db_from_cia;
when X"2" | X"3" =>
io_resp.data(0) <= reg_cs_n;
io_resp.data(1) <= reg_cs2;
io_resp.data(2) <= reg_reset_n;
io_resp.data(3) <= reg_rw_n;
io_resp.data(4) <= reg_phi2;
when X"4" | X"5" =>
io_resp.data <= pa_from_cia;
when X"6" | X"7" =>
io_resp.data <= pb_from_cia;
when X"8" | X"9" =>
io_resp.data(4 downto 0) <= hs_from_cia;
io_resp.data(5) <= irq_n;
when X"B" =>
io_resp.data <= db_from_my_cia;
when X"C" =>
io_resp.data <= pb_from_my_cia;
when X"D" =>
io_resp.data(4 downto 0) <= hs_from_my_cia;
io_resp.data(5) <= not irq_from_my_cia;
when others =>
null;
end case;
end if;
rising <= '0';
falling <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
reg_addr <= io_req.data(3 downto 0);
when X"1" =>
db_to_cia <= io_req.data;
when X"2" =>
reg_cs_n <= reg_cs_n or io_req.data(0);
reg_cs2 <= reg_cs2 or io_req.data(1);
reg_reset_n <= reg_reset_n or io_req.data(2);
reg_rw_n <= reg_rw_n or io_req.data(3);
reg_phi2 <= reg_phi2 or io_req.data(4);
rising <= not reg_phi2 and io_req.data(4); -- pulse if it was zero.
when X"3" =>
reg_cs_n <= reg_cs_n and not io_req.data(0);
reg_cs2 <= reg_cs2 and not io_req.data(1);
reg_reset_n <= reg_reset_n and not io_req.data(2);
reg_rw_n <= reg_rw_n and not io_req.data(3);
reg_phi2 <= reg_phi2 and not io_req.data(4);
falling <= reg_phi2 and io_req.data(4); -- pulse if it was one.
when X"4" =>
pa_to_cia <= io_req.data;
when X"5" =>
pa_drive <= io_req.data;
when X"6" =>
pb_to_cia <= io_req.data;
when X"7" =>
pb_drive <= io_req.data;
when X"8" =>
reg_hs_to_cia <= reg_hs_to_cia or io_req.data(4 downto 0);
when X"9" =>
reg_hs_to_cia <= reg_hs_to_cia and not io_req.data(4 downto 0);
when X"A" =>
hs_drive <= io_req.data(4 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
addr <= reg_addr;
cs_n <= reg_cs_n;
cs2 <= reg_cs2;
reset_n <= reg_reset_n;
rw_n <= reg_rw_n;
phi2 <= reg_phi2;
hs_to_cia <= reg_hs_to_cia;
db_drive <= '1' when reg_rw_n = '0' and reg_cs_n = '0' and reg_cs2 = '1' else '0';
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/for2.vhd
|
5
|
372
|
entity for2 is
end entity;
architecture test of for2 is
type myint is range -1 to 4;
type myenum is (A, B, C, D);
begin
process is
begin
for x in myint loop
report myint'image(x);
end loop;
for y in myenum loop
report myenum'image(y);
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/access1.vhd
|
5
|
1592
|
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := new list;
n.link := l;
n.value := v;
l := n;
end procedure;
procedure list_print(variable l : in list_ptr) is
begin
if l /= null then
report integer'image(l.all.value);
list_print(l.all.link);
end if;
end procedure;
procedure list_free(l : inout list_ptr) is
variable tmp : list_ptr;
begin
while l /= null loop
tmp := l.all.link;
deallocate(l);
l := tmp;
end loop;
end procedure;
signal p1_done : boolean := false;
type str_ptr is access string;
begin
p1: process is
variable p, q : int_ptr;
begin
assert p = null;
p := new integer;
p.all := 5;
assert p.all = 5;
q := p;
assert q.all = 5;
q.all := 6;
assert p.all = 6;
deallocate(p);
assert p = null;
p1_done <= true;
wait;
end process;
p2: process is
variable l, p : list_ptr;
begin
wait until p1_done;
for i in 1 to 10 loop
list_add(l, i);
end loop;
list_print(l);
list_free(l);
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/floppy_mem.vhd
|
5
|
3736
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy
-------------------------------------------------------------------------------
-- File : floppy_mem.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the interface to the buffer, for the
-- floppy model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_mem is
generic (
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
drv_wdata : in std_logic_vector(7 downto 0);
drv_rdata : out std_logic_vector(7 downto 0);
do_read : in std_logic;
do_write : in std_logic;
do_advance : in std_logic;
track_start : in std_logic_vector(25 downto 0);
max_offset : in std_logic_vector(13 downto 0);
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy_mem;
architecture gideon of floppy_mem is
type t_state is (idle, reading, writing);
signal state : t_state;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable offset_count : unsigned(13 downto 0);
procedure advance is
begin
if offset_count >= unsigned(max_offset) then
offset_count := (others => '0');
else
offset_count := offset_count + 1;
end if;
end procedure;
begin
if rising_edge(clock) then
case state is
when idle =>
if do_read='1' then
advance;
state <= reading;
mem_req.read_writen <= '1';
mem_req.request <= '1';
elsif do_write='1' then
advance;
state <= writing;
mem_req.read_writen <= '0';
mem_req.request <= '1';
elsif do_advance='1' then
advance;
end if;
mem_req.data <= drv_wdata;
mem_req.address <= unsigned(track_start) + offset_count;
when reading =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when writing =>
if mem_rack='1' then
mem_req.request <= '0';
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
offset_count := (others => '0');
state <= idle;
mem_req <= c_mem_req_init;
mem_req.tag <= g_tag;
drv_rdata <= X"FF";
end if;
end if;
end process;
end gideon;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/usb2/vhdl_source/token_crc.vhd
|
2
|
1838
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc is
port (
clock : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc;
architecture Gideon of token_crc is
-- CRC-5 = x5 + x2 + 1
constant polynom : std_logic_vector(4 downto 0) := "00101";
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := tmp(tmp'high) xor token_in(i); -- loop xor
tmp := tmp(tmp'high-1 downto 0) & '0'; -- cyclic shift
if d = '1' then -- if highest bit was '1' then apply polynom
tmp := tmp xor polynom;
end if;
tmp(0) := d;
end loop;
for i in tmp'range loop -- reverse
crc(crc'high-i) <= not tmp(i);
end loop;
end if;
end process;
end Gideon;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/drive_registers.vhd
|
1
|
7128
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_clock_freq : natural := 50_000_000;
g_multi_mode : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
disk_change_n : out std_logic;
force_ready : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 1);
stop_on_freeze : out std_logic;
drive_type : out natural range 0 to 2;
do_snd_insert : out std_logic;
do_snd_remove : out std_logic;
track : in unsigned(6 downto 0);
side : in std_logic := '0';
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 1);
signal inserted_i : std_logic;
signal disk_change_i : std_logic;
signal force_ready_i : std_logic;
signal stop_when_frozen : std_logic;
signal drive_type_i : std_logic_vector(1 downto 0);
signal write_delay : unsigned(10 downto 0); -- max 2047 = 2 sec
signal write_busy : std_logic;
signal manual_write : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
manual_write <= '0';
do_snd_insert <= '0';
do_snd_remove <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data(7 downto 1);
when c_drvreg_man_write =>
manual_write <= '1';
when c_drvreg_diskchng =>
disk_change_i <= io_req.data(0);
force_ready_i <= io_req.data(1);
when c_drvreg_drivetype =>
if g_multi_mode then
drive_type_i <= io_req.data(1 downto 0);
end if;
when c_drvreg_sound =>
do_snd_insert <= io_req.data(0);
do_snd_remove <= io_req.data(1);
when others =>
null;
end case;
end if; -- write
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i & '0';
when c_drvreg_diskchng =>
io_resp.data(0) <= disk_change_i;
io_resp.data(1) <= force_ready_i;
when c_drvreg_drivetype =>
if g_multi_mode then
io_resp.data(1 downto 0) <= drive_type_i;
end if;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= std_logic_vector(track(6 downto 0));
when c_drvreg_side =>
io_resp.data(0) <= side;
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
io_resp.data(2) <= write_busy;
when others =>
null;
end case;
end if; -- read
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
disk_change_i <= '0';
use_c64_reset_i <= '1';
stop_when_frozen <= '1';
force_ready_i <= '0';
drive_type_i <= "00";
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if drv_reset_i = '1' then
write_busy <= '0';
write_delay <= (others => '0');
elsif (mode = '0' and motor_on = '1') or manual_write = '1' then
write_busy <= '1';
write_delay <= (others => '1');
elsif write_delay = 0 then
write_busy <= '0';
elsif tick_1kHz = '1' then
write_delay <= write_delay - 1;
end if;
end if;
end process;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
disk_change_n <= not disk_change_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
force_ready <= force_ready_i;
drive_type <= to_integer(unsigned(drive_type_i));
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/elab/issue184.vhd
|
5
|
345
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd
|
1
|
2502
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_rwn : std_logic; -- for async reads and writes
bus_write : std_logic; -- Qualified write condition after setup
io_address : unsigned(15 downto 0); -- for late reads/writes
io_read : std_logic;
io_read_early : std_logic;
io_write : std_logic;
late_write : std_logic;
data : std_logic_vector(7 downto 0);
rom_access : std_logic; -- synchronized version of ROML and ROMH combined
sample_io : std_logic; -- timing signal, pulses when IO lines and address should be stable
end record;
type t_slot_resp is record
data : std_logic_vector(7 downto 0);
reg_output : std_logic;
irq : std_logic;
nmi : std_logic;
end record;
constant c_slot_req_init : t_slot_req := (
bus_address => X"0000",
bus_rwn => '1',
bus_write => '0',
io_read_early => '0',
io_address => X"0000",
io_read => '0',
io_write => '0',
late_write => '0',
rom_access => '0',
sample_io => '0',
data => X"00" );
constant c_slot_resp_init : t_slot_resp := (
data => X"00",
reg_output => '0',
irq => '0',
nmi => '0' );
type t_slot_req_array is array(natural range <>) of t_slot_req;
type t_slot_resp_array is array(natural range <>) of t_slot_resp;
function or_reduce(ar: t_slot_resp_array) return t_slot_resp;
end package;
package body slot_bus_pkg is
function or_reduce(ar: t_slot_resp_array) return t_slot_resp is
variable ret : t_slot_resp;
begin
ret := c_slot_resp_init;
for i in ar'range loop
ret.reg_output := ret.reg_output or ar(i).reg_output;
if ar(i).reg_output='1' then
ret.data := ret.data or ar(i).data;
end if;
ret.irq := ret.irq or ar(i).irq;
ret.nmi := ret.nmi or ar(i).nmi;
end loop;
return ret;
end function or_reduce;
end package body;
|
gpl-3.0
|
chiggs/nvc
|
test/parse/seq.vhd
|
4
|
2984
|
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when foo = 5;
end process;
-- Signal assignment to aggregate
process is
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case f is
when 1 =>
for i in x'range loop
end loop;
end case;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/ambiguous.vhd
|
4
|
4603
|
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
gpl-3.0
|
chiggs/nvc
|
test/regress/const1.vhd
|
5
|
474
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/usb2/vhdl_sim/usb_test_nano2.vhd
|
1
|
6245
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 2 for USB host
-- This testcase initializes a repeated IN transfer in Circular Mem Buffer mode
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano2 is
generic (
g_report_file_name : string := "work/usb_test_nano2.rpt"
);
end entity;
architecture arch of usb_test_nano2 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
interrupt => interrupt,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable res : std_logic_vector(7 downto 0);
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
variable data : std_logic_vector(15 downto 0);
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1';
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- L1: while true loop
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- if (attr_fifo_head /= attr_fifo_tail) then
-- exit L1;
-- end if;
-- end loop;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
sctb_trace("Fifo read: " & hstr(data));
result := data;
end procedure;
procedure check_result(expected : std_logic_vector(7 downto 0); exp_result : std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
variable byte : std_logic_vector(7 downto 0);
begin
io_read_word(Command_Length, data);
sctb_trace("Command length: " & hstr(data));
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
sctb_check(data, exp_result, "Unexpected response");
byte := read_memory_8(mem, X"00550000");
sctb_check(byte, expected, "Erroneous byte");
write_memory_8(mem, X"00550000", X"00");
end procedure;
-- procedure wait_command_done is
-- begin
-- L1: while true loop
-- io_read(io => io, addr => Command, data => res);
-- if res(1) = '1' then -- check if paused bit has been set
-- exit L1;
-- end if;
-- end loop;
-- end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path::path", g_report_file_name);
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
io_write_word(Command_DevEP, X"0007"); -- EP7: NAK NAK DATA0 NAK NAK DATA1 NAK STALL
io_write_word(Command_MemHi, X"0055");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Interval, X"0002"); -- every other microframe
io_write_word(Command_Length, X"0010");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"44", X"8001");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5842"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"6B", X"8801");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"00", X"C400");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
--restart; mem load -infile nano_code.hex -format hex /usb_test_nano2/i_harness/i_host/i_nano/i_buf_ram/mem; run 2000 us
|
gpl-3.0
|
chiggs/nvc
|
test/regress/issue152.vhd
|
5
|
883
|
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
begin
sum := 0;
for i in vec.all'range loop
sum := sum + vec.all(i);
end loop;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue152 is
end entity;
use work.pkg.all;
architecture test of issue152 is
begin
process is
variable sum : integer;
variable vec : integer_vector_ptr;
begin
vec := new integer_vector'(1, 2, 3, 4, 5);
get(vec, sum);
assert sum = 15;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/video/vhdl_source/char_generator_peripheral.vhd
|
1
|
6519
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
data_enable : in std_logic := '1';
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_regs_p : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_regs_p : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_bridge: entity work.io_bus_bridge2
generic map (
g_addr_width => 20
)
port map(
clock_a => clock,
reset_a => reset,
req_a => io_req_regs,
resp_a => io_resp_regs,
clock_b => pix_clock,
reset_b => pix_reset,
req_b => io_req_regs_p,
resp_b => io_resp_regs_p );
i_regs: entity work.char_generator_regs
port map (
clock => pix_clock,
reset => pix_reset,
io_req => io_req_regs_p,
io_resp => io_resp_regs_p,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
data_enable => data_enable,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
|
gpl-3.0
|
chiggs/nvc
|
test/lower/issue135.vhd
|
5
|
489
|
entity issue135 is
end entity;
architecture test of issue135 is
function bad_performance (
constant a : string;
constant b : natural := 0;
constant c : character := ',';
constant d : time := 0 ns;
constant e : string := "i" )
return string is
begin
return (natural'image(b) &
time'image(d) & -- Uncomment this line to increase runtime further
c &
e &
c );
end function;
begin
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/const3.vhd
|
5
|
311
|
entity const3 is
end entity;
architecture test of const3 is
type bit_str_map is array (bit) of string(1 to 4);
constant const : bit_str_map := ( "zero", "one " );
begin
process is
begin
report const('0');
report const('1');
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
target/simulation/vhdl_bfm/mb_model.vhd
|
2
|
32264
|
-------------------------------------------------------------------------------
-- Title : mb_model
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Instruction level model of the microblaze
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model is
generic (
g_io_mask : unsigned(31 downto 0) := X"FC000000" );
port (
clock : in std_logic;
reset : in std_logic;
io_addr : out unsigned(31 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_byte_en : out std_logic_vector(3 downto 0);
io_wdata : out std_logic_vector(31 downto 0);
io_rdata : in std_logic_vector(31 downto 0);
io_ack : in std_logic );
end entity;
architecture bfm of mb_model is
type t_word_array is array(natural range <>) of std_logic_vector(31 downto 0);
type t_signed_array is array(natural range <>) of signed(31 downto 0);
constant c_memory_size_bytes : natural := 20; -- 1 MB
constant c_memory_size_words : natural := c_memory_size_bytes - 2;
shared variable reg : t_signed_array(0 to 31) := (others => (others => '0'));
shared variable imem : t_word_array(0 to 2**c_memory_size_words -1);
alias dmem : t_word_array(0 to 2**c_memory_size_words -1) is imem;
signal pc_reg : unsigned(31 downto 0);
signal C_flag : std_logic;
signal I_flag : std_logic;
signal B_flag : std_logic;
signal D_flag : std_logic;
constant p : string := "PC: ";
constant i : string := ", Inst: ";
constant c : string := ", ";
constant ras : string := ", Ra=";
constant rbs : string := ", Rb=";
constant rds : string := ", Rd=";
impure function get_msr(len : natural) return std_logic_vector is
variable msr : std_logic_vector(31 downto 0);
begin
msr := (31 => C_flag,
3 => B_flag,
2 => C_flag,
1 => I_flag,
others => '0' );
return msr(len-1 downto 0);
end function;
function to_std(b : boolean) return std_logic is
begin
if b then return '1'; end if;
return '0';
end function;
begin
process
variable new_pc : unsigned(31 downto 0);
variable do_delay : std_logic := '0';
variable imm : signed(31 downto 0);
variable imm_lock : std_logic := '0';
variable ra : integer range 0 to 31;
variable rb : integer range 0 to 31;
variable rd : integer range 0 to 31;
procedure dbPrint(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); str : string) is
variable s : line;
begin
write(s, p);
write(s, hstr(pc));
write(s, i);
write(s, hstr(inst));
write(s, ras);
write(s, hstr(unsigned(reg(ra))));
write(s, rbs);
write(s, hstr(unsigned(reg(rb))));
write(s, rds);
write(s, hstr(unsigned(reg(rd))));
write(s, c);
write(s, str);
-- writeline(output, s);
end procedure;
procedure set_msr(a : std_logic_vector(13 downto 0)) is
begin
B_flag <= a(3);
C_flag <= a(2);
I_flag <= a(1);
end procedure;
procedure perform_add(a, b : signed(31 downto 0); carry : std_logic; upd_c : boolean) is
variable t33: signed(32 downto 0);
begin
if carry = '1' then
t33 := ('0' & a) + ('0' & b) + 1;
else
t33 := ('0' & a) + ('0' & b);
end if;
reg(rd) := t33(31 downto 0);
if upd_c then
C_flag <= t33(32);
end if;
end procedure;
procedure illegal(pc : unsigned) is
begin
report "Illegal instruction @ " & hstr(pc)
severity error;
end procedure;
procedure unimplemented(msg : string) is
begin
report msg;
end procedure;
procedure do_branch(pc : unsigned(31 downto 0); offset : signed(31 downto 0); delay, absolute, link : std_logic; chk : integer) is
variable take : boolean;
begin
case chk is
when 0 => take := (reg(ra) = 0);
when 1 => take := (reg(ra) /= 0);
when 2 => take := (reg(ra) < 0);
when 3 => take := (reg(ra) <= 0);
when 4 => take := (reg(ra) > 0);
when 5 => take := (reg(ra) >= 0);
when others => take := true;
end case;
if link='1' then
reg(rd) := signed(pc);
end if;
if take then
if absolute='1' then
new_pc := unsigned(offset);
else
new_pc := unsigned(signed(pc) + offset);
end if;
end if; -- else: default: new_pc := pc + 4;
if take then
do_delay := delay;
end if;
end procedure;
function is_io(addr : unsigned(31 downto 0)) return boolean is
begin
return (addr and g_io_mask) /= 0;
end function;
procedure load_byte(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(7 downto 0) := loaded(31 downto 24);
when "01" => data(7 downto 0) := loaded(23 downto 16);
when "10" => data(7 downto 0) := loaded(15 downto 8);
when "11" => data(7 downto 0) := loaded(7 downto 0);
when others => data := (others => 'X');
end case;
end procedure;
procedure load_half(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '0');
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => null;
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(15 downto 0) := loaded(31 downto 16);
when "10" => data(15 downto 0) := loaded(15 downto 0);
when others => report "Unalligned halfword read" severity error;
end case;
end procedure;
procedure load_word(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '1');
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := loaded;
assert addr(1 downto 0) = "00"
report "Unalligned dword read" severity error;
end procedure;
procedure store_byte(addr : unsigned(31 downto 0); data : std_logic_vector(7 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data & data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 24) := data;
when "01" => loaded(23 downto 16) := data;
when "10" => loaded(15 downto 8) := data;
when "11" => loaded(7 downto 0) := data;
when others => null;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
end procedure;
procedure store_half(addr : unsigned(31 downto 0); data : std_logic_vector(15 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 16) := data;
when "10" => loaded(15 downto 0) := data;
when others => report "Unalligned halfword write" severity error;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
assert addr(0) = '0'
report "Unalligned halfword write" severity error;
end procedure;
procedure store_word(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0)) is
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data;
io_byte_en <= "1111";
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := data;
end if;
assert addr(1 downto 0) = "00"
report "Unalligned dword write" severity error;
end procedure;
procedure check_zero(a : std_logic_vector) is
begin
assert unsigned(a) = 0
report "Modifier bits not zero.. Illegal instruction?"
severity warning;
end procedure;
procedure dbPrint3(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", R" & str(rb));
end procedure;
procedure dbPrint2(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra));
end procedure;
procedure dbPrint2i(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", 0x" & hstr(unsigned(imm)));
end procedure;
procedure dbPrintBr(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); delay, absolute, link, immediate : std_logic; chk : integer) is
variable base : string(1 to 6) := " ";
variable n : integer := 4;
begin
case chk is
when 0 => base(1 to 3) := "BEQ";
when 1 => base(1 to 3) := "BNE";
when 2 => base(1 to 3) := "BLT";
when 3 => base(1 to 3) := "BLE";
when 4 => base(1 to 3) := "BGT";
when 5 => base(1 to 3) := "BGE";
when others => base(1 to 2) := "BR"; n := 3;
end case;
if absolute='1' then base(n) := 'A'; n := n + 1; end if;
if link='1' then base(n) := 'L'; n := n + 1; end if;
if immediate='1' then base(n) := 'I'; n := n + 1; end if;
if delay='1' then base(n) := 'D'; n := n + 1; end if;
if link='1' then
dbPrint(pc, inst, base & " R" & str(rd) & " => " & hstr(new_pc));
elsif chk = 15 then
dbPrint(pc, inst, base & " => " & hstr(new_pc));
else
dbPrint(pc, inst, base & " R" & str(ra) & " => " & hstr(new_pc));
end if;
end procedure;
procedure execute_instruction(pc : unsigned(31 downto 0)) is
variable inst : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable temp : std_logic;
begin
inst := imem(to_integer(pc(c_memory_size_bytes-1 downto 2)));
rd := to_integer(unsigned(inst(25 downto 21)));
ra := to_integer(unsigned(inst(20 downto 16)));
rb := to_integer(unsigned(inst(15 downto 11)));
reg(0) := (others => '0');
imm(15 downto 0) := signed(inst(15 downto 0));
if imm_lock='0' then
imm(31 downto 16) := (others => inst(15)); -- sign extend
end if;
imm_lock := '0';
io_write <= '0';
io_read <= '0';
io_addr <= (others => '0');
io_byte_en <= (others => '0');
new_pc := pc + 4;
case inst(31 downto 26) is
when "000000" => -- ADD Rd,Ra,Rb
dbPrint3(pc, inst, "ADD ");
perform_add(reg(ra), reg(rb), '0', true);
check_zero(inst(10 downto 0));
when "000001" => -- RSUB Rd,Ra,Rb
dbPrint3(pc, inst, "RSUB ");
perform_add(not reg(ra), reg(rb), '1', true);
check_zero(inst(10 downto 0));
when "000010" => -- ADDC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDC ");
perform_add(reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000011" => -- RSUBC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBC ");
perform_add(not reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000100" => -- ADDK Rd,Ra,Rb
dbPrint3(pc, inst, "ADDK ");
perform_add(reg(ra), reg(rb), '0', false);
check_zero(inst(10 downto 0));
when "000101" => -- RSUBK Rd,Ra,Rb / CMP Rd,Ra,Rb / CMPU Rd,Ra,Rb
if inst(1 downto 0) = "01" then -- CMP
dbPrint3(pc, inst, "CMP ");
temp := not to_std(signed(reg(rb)) >= signed(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
elsif inst(1 downto 0) = "11" then -- CMPU
dbPrint3(pc, inst, "CMPU ");
temp := not to_std(unsigned(reg(rb)) >= unsigned(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
else
dbPrint3(pc, inst, "RSUBK ");
perform_add(not reg(ra), reg(rb), '1', false);
end if;
check_zero(inst(10 downto 2));
when "000110" => -- ADDKC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDKC ");
perform_add(reg(ra), reg(rb), C_flag, false);
check_zero(inst(10 downto 0));
when "000111" => -- RSUBKC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBKC ");
perform_add(not reg(ra), reg(rb), C_flag, false);
when "001000" => -- ADDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDI ");
perform_add(reg(ra), imm, '0', true);
when "001001" => -- RSUBI Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBI ");
perform_add(not reg(ra), imm, '1', true);
when "001010" => -- ADDIC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIC ");
perform_add(reg(ra), imm, C_flag, true);
when "001011" => -- RSUBIC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIC ");
perform_add(not reg(ra), imm, C_flag, true);
when "001100" => -- ADDIK Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIK ");
perform_add(reg(ra), imm, '0', false);
when "001101" => -- RSUBIK Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIK ");
perform_add(not reg(ra), imm, '1', false);
when "001110" => -- ADDIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIKC ");
perform_add(reg(ra), imm, C_flag, false);
when "001111" => -- RSUBIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIKC ");
perform_add(not reg(ra), imm, C_flag, false);
when "010000" => -- MUL/MULH/MULHSU/MULHU Rd,Ra,Rb
unimplemented("MUL/MULH/MULHSU/MULHU Rd,Ra,Rb");
when "010001" => -- BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)
unimplemented("BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)");
when "010010" => -- IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb
unimplemented("IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb");
when "010011" => --
illegal(pc);
when "010100" => --
illegal(pc);
when "010101" => --
illegal(pc);
when "010110" => --
illegal(pc);
when "010111" => --
illegal(pc);
when "011000" => -- MULI Rd,Ra,Imm
unimplemented("MULI Rd,Ra,Imm");
when "011001" => -- BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm
unimplemented("BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm");
when "011010" => --
illegal(pc);
when "011011" => --
illegal(pc);
when "011100" => --
illegal(pc);
when "011101" => --
illegal(pc);
when "011110" => --
illegal(pc);
when "011111" => --
illegal(pc);
when "100000" => -- OR Rd,Ra,Rb / PCMPBF Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPBF Rd,Ra,Rb");
else
dbPrint3(pc, inst, "OR ");
reg(rd) := reg(ra) or reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100001" => -- AND Rd,Ra,Rb
dbPrint3(pc, inst, "AND ");
reg(rd) := reg(ra) and reg(rb);
check_zero(inst(10 downto 0));
when "100010" => -- XOR Rd,Ra,Rb / PCMPEQ Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPEQ Rd,Ra,Rb");
else
dbPrint3(pc, inst, "XOR ");
reg(rd) := reg(ra) xor reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100011" => -- ANDN Rd,Ra,Rb/ PCMPNE Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPNE Rd,Ra,Rb");
else
dbPrint3(pc, inst, "ANDN ");
reg(rd) := reg(ra) and not reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100100" => -- SRA Rd,Ra / SRC Rd,Ra / SRL Rd,Ra/ SEXT8 Rd,Ra / SEXT16 Rd,Ra
case inst(15 downto 0) is
when X"0001" => -- SRA
dbPrint2(pc, inst, "SRA ");
C_flag <= reg(ra)(0);
reg(rd) := reg(ra)(31) & reg(ra)(31 downto 1);
when X"0021" => -- SRC
dbPrint2(pc, inst, "SRC ");
C_flag <= reg(ra)(0);
reg(rd) := C_flag & reg(ra)(31 downto 1);
when X"0041" => -- SRL
dbPrint2(pc, inst, "SRL ");
C_flag <= reg(ra)(0);
reg(rd) := '0' & reg(ra)(31 downto 1);
when X"0060" => -- SEXT8
dbPrint2(pc, inst, "SEXT8 ");
reg(rd)(31 downto 8) := (others => reg(ra)(7));
reg(rd)(7 downto 0) := reg(ra)(7 downto 0);
when X"0061" => -- SEXT16
dbPrint2(pc, inst, "SEXT16 ");
reg(rd)(31 downto 16) := (others => reg(ra)(15));
reg(rd)(15 downto 0) := reg(ra)(15 downto 0);
when others =>
illegal(pc);
end case;
when "100101" => -- MTS Sd,Ra / MFS Rd,Sa / MSRCLR Rd,Imm / MSRSET Rd,Imm
case inst(15 downto 14) is
when "00" => -- SET/CLR
reg(rd) := get_msr(32);
if inst(16)='0' then -- set
dbPrint(pc, inst, "MSRSET R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) or inst(13 downto 0));
else -- clear
dbPrint(pc, inst, "MSRCLR R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) and not inst(13 downto 0));
end if;
when "10" => -- MFS (read)
dbPrint(pc, inst, "MFS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"4000" =>
reg(rd) := signed(pc);
when X"4001" =>
reg(rd) := signed(get_msr(32));
when others =>
unimplemented("MFS register type " & hstr(inst(13 downto 0)));
end case;
check_zero(inst(20 downto 16));
when "11" => -- MTS (write)
dbPrint(pc, inst, "MTS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"C001" =>
set_msr(std_logic_vector(reg(ra)(13 downto 0)));
when others =>
unimplemented("MTS register type " & hstr(inst(13 downto 0)));
end case;
when others =>
illegal(pc);
end case;
when "100110" => -- BR(A)(L)(D) (Rb,)Rb / BRK Rd,Rb
do_branch(pc => pc, offset => reg(rb), delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '0', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
check_zero(inst(10 downto 0));
when "100111" => -- Bxx Ra,Rb (Rd = type of branch)
do_branch(pc => pc, offset => reg(rb), delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '0', chk => to_integer(unsigned(inst(23 downto 21))));
check_zero(inst(10 downto 0));
when "101000" => -- ORI Rd,Ra,Imm
dbPrint2i(pc, inst, "ORI ");
reg(rd) := reg(ra) or imm;
when "101001" => -- ANDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDI ");
reg(rd) := reg(ra) and imm;
when "101010" => -- XORI Rd,Ra,Imm
dbPrint2i(pc, inst, "XORI ");
reg(rd) := reg(ra) xor imm;
when "101011" => -- ANDNI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDNI ");
reg(rd) := reg(ra) and not imm;
when "101100" => -- IMM Imm
dbPrint(pc, inst, "IMM " & hstr(inst(15 downto 0)));
imm(31 downto 16) := signed(inst(15 downto 0));
imm_lock := '1';
check_zero(inst(25 downto 16));
when "101101" => -- RTSD Ra,Imm / RTID Ra,Imm / RTBD Ra,Imm / RTED Ra,Imm
case inst(25 downto 21) is
when "10000" =>
dbPrint(pc, inst, "RTSD R" & str(ra) & ", " & str(to_integer(imm)));
null;
when "10001" =>
dbPrint(pc, inst, "RTID R" & str(ra) & ", " & str(to_integer(imm)));
I_flag <= '1';
when "10010" =>
dbPrint(pc, inst, "RTBD R" & str(ra) & ", " & str(to_integer(imm)));
B_flag <= '0';
when "10100" =>
unimplemented("Return from exception RTED");
when others =>
illegal(pc);
end case;
new_pc := unsigned(reg(ra) + imm);
do_delay := '1';
when "101110" => -- BR(A)(L)I(D) Imm Ra / BRKI Rd,Imm
do_branch(pc => pc, offset => imm, delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '1', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
when "101111" => -- BxxI Ra,Imm (Rd = type of branch)
do_branch(pc => pc, offset => imm, delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '1', chk => to_integer(unsigned(inst(23 downto 21))));
when "110000" => -- LBU Rd,Ra,Rb
dbPrint3(pc, inst, "LBU ");
load_byte(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110001" => -- LHU Rd,Ra,Rb
dbPrint3(pc, inst, "LHU ");
load_half(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110010" => -- LW Rd,Ra,Rb
dbPrint3(pc, inst, "LW ");
load_word(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110011" => --
illegal(pc);
when "110100" => -- SB Rd,Ra,Rb
dbPrint3(pc, inst, "SB ");
store_byte(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(7 downto 0)));
check_zero(inst(10 downto 0));
when "110101" => -- SH Rd,Ra,Rb
dbPrint3(pc, inst, "SH ");
store_half(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(15 downto 0)));
check_zero(inst(10 downto 0));
when "110110" => -- SW Rd,Ra,Rb
dbPrint3(pc, inst, "SW ");
store_word(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)));
check_zero(inst(10 downto 0));
when "110111" => --
illegal(pc);
when "111000" => -- LBUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LBUI ");
load_byte(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111001" => -- LHUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LHUI ");
load_half(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111010" => -- LWI Rd,Ra,Imm
dbPrint2i(pc, inst, "LWI ");
load_word(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111011" => --
illegal(pc);
when "111100" => -- SBI Rd,Ra,Imm
dbPrint2i(pc, inst, "SBI ");
store_byte(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(7 downto 0)));
when "111101" => -- SHI Rd,Ra,Imm
dbPrint2i(pc, inst, "SHI ");
store_half(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(15 downto 0)));
when "111110" => -- SWI Rd,Ra,Imm
dbPrint2i(pc, inst, "SW ");
store_word(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)));
when "111111" => --
illegal(pc);
when others =>
illegal(pc);
end case;
end procedure execute_instruction;
variable old_pc : unsigned(31 downto 0);
begin
if reset='1' then
pc_reg <= (others => '0');
io_addr <= (others => '0');
io_wdata <= (others => '0');
io_read <= '0';
io_write <= '0';
else
D_flag <= '0';
execute_instruction(pc_reg);
old_pc := pc_reg;
pc_reg <= new_pc;
if do_delay='1' then
wait until clock='1';
D_flag <= '1';
do_delay := '0';
execute_instruction(old_pc + 4); -- old PC + 4
end if;
end if;
wait until clock='1';
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/supersede.vhd
|
4
|
361
|
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest(fum)
port map (
a => a,
b => b
);
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/bounds9.vhd
|
5
|
365
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/attr.vhd
|
3
|
4179
|
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
signal i : int_vec(1 to 3);
attribute foo of i : signal is 6; -- OK
begin
process is
variable v : integer;
begin
v := x'foo; -- OK
report y'bar; -- OK
end process;
process is
begin
report z'foo; -- Error
end process;
process is
variable v : int_vec_ptr;
begin
assert v'length = 5;
assert v.all'length = 62;
end process;
process is
begin
report e'path_name; -- OK
report e'instance_name; -- OK
report a1'path_name; -- OK
report a1'instance_name; -- OK
end process;
process is
begin
assert i'event; -- OK
assert i(1)'event; -- OK
assert i(x)'event; -- OK
assert i'foo = 1; -- OK
assert i(1)'foo = 2; -- Error
end process;
end architecture;
architecture a2 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of z : signal is string'("boo"); -- Error
attribute bar of x : signal is 73; -- Error
attribute foo of q : signal is 71; -- Error
attribute foo of yah : label is 12; -- Ignored
begin
end architecture;
architecture a3 of e is
type int10_vec is array (integer range 1 to 10) of integer;
begin
process is
variable x : integer;
begin
assert int10_vec'low = 1; -- OK
assert int10_vec'high = 10; -- OK
assert int10_vec'left = 1; -- OK
assert int10_vec'right = 10; -- OK
assert int10_vec'low(1) = 1; -- OK
assert int10_vec'left(x) = 2; -- Error
end process;
end architecture;
package p is
function func(x : in integer) return integer;
end package;
package body p is
function func(x : in integer) return integer is
begin
report func'instance_name;
return x + 1;
end function;
end package body;
entity issue39 is
generic (
g : bit := '0'
);
begin
assert (g = '0' or g = '1')
report issue39'instance_name & "oops!"
severity failure;
end entity issue39;
architecture a4 of e is
begin
process is
begin
assert integer'image(0)(0) = '0'; -- OK
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0'; -- OK
assert i'b(1) = 1; -- Error
end process;
process is
variable i : integer;
attribute a : boolean;
attribute a of i : signal is true; -- Error
begin
end process;
process is
variable x : integer;
begin
assert x'last_event = 0 ns; -- Error
end process;
process is
type bv_ptr is access bit_vector;
variable a : bv_ptr;
type r is record
x : integer;
end record;
variable b : r;
begin
a(a'range) := "110101"; -- OK
a(bit_vector'range) := "110101"; -- Error
a(b'range) := "101010"; -- Error
a(e'range) := "110101"; -- Error
end process;
process is
function func(x : integer) return bit_vector;
variable a : bit_vector(1 to 10);
begin
a(func(4)'range) := (others => '1'); -- OK
end process;
process is
type bvptr is access bit_vector;
variable b : bvptr;
begin
for i in b.all'range loop -- OK
end loop;
for i in b'range loop -- OK
end loop;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/issue103.vhd
|
5
|
535
|
use std.textio.all;
entity issue103 is
end entity;
architecture test of issue103 is
procedure puts(TAG:inout LINE; MSG:in STRING) is
variable text_line : LINE;
begin
write(text_line, TAG(TAG'range), RIGHT, 10);
write(text_line, string'(" "));
write(text_line, MSG);
writeline(OUTPUT, text_line);
end procedure;
begin
main: process
variable tag : line;
begin
write(tag , string'(">>"));
puts(tag, "test");
wait;
end process;
end test;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/audio/lp_filter.vhd
|
1
|
6015
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity lp_filter is
generic (
g_divider : natural := 221 );
port (
clock : in std_logic;
reset : in std_logic;
signal_in : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
error_out : out std_logic;
valid_out : out std_logic );
end entity;
architecture dsvf of lp_filter is
signal filter_q : signed(signal_in'range);
signal filter_f : signed(signal_in'range);
signal input_sc : signed(signal_in'range);
signal xa : signed(signal_in'range);
signal xb : signed(signal_in'range);
signal sum_b : signed(signal_in'range);
signal sub_a : signed(signal_in'range);
signal sub_b : signed(signal_in'range);
signal x_reg : signed(signal_in'range) := (others => '0');
signal bp_reg : signed(signal_in'range);
signal hp_reg : signed(signal_in'range);
signal lp_reg : signed(signal_in'range);
signal temp_reg : signed(signal_in'range);
signal error : std_logic := '0';
signal divider : integer range 0 to g_divider-1;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
begin
-- -- Derive the actual 'f' and 'q' parameters
-- i_q_table: entity work.Q_table
-- port map (
-- Q_reg => X"6",
-- filter_q => filter_q ); -- 2.16 format
filter_q <= to_signed(65536, filter_q'length); -- 92682
filter_f <= to_signed(16384, filter_f'length);
input_sc <= signal_in; -- shift_right(signal_in, 1);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg when xb_select='0' else hp_reg;
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(17 downto 0);
variable sub_result : signed(17 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 16);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
temp_reg <= sum_result;
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
divider <= 0;
elsif divider = g_divider-1 then
divider <= 0;
else
divider <= divider + 1;
if divider < c_program'length then
instruction <= c_program(divider);
end if;
end if;
if divider = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg;
band_pass <= bp_reg;
low_pass <= lp_reg;
error_out <= error;
end dsvf;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/stepper.vhd
|
1
|
2734
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stepper is
port (
clock : in std_logic;
reset : in std_logic;
-- timing
tick_1KHz : in std_logic;
-- track interface from wd177x
goto_track : in unsigned(6 downto 0);
cur_track : in unsigned(6 downto 0);
step_time : in unsigned(4 downto 0);
enable : in std_logic := '1';
busy : out std_logic;
do_track_in : out std_logic; -- for stand alone mode (pure 1581)
do_track_out : out std_logic;
-- Index pulse
motor_en : in std_logic;
index_out : out std_logic;
-- emulated output as if stepping comes from VIA
step : out std_logic_vector(1 downto 0) );
end entity;
architecture behavioral of stepper is
constant c_max_track : natural := 83;
signal track : unsigned(1 downto 0);
signal timer : unsigned(4 downto 0);
signal index_cnt : unsigned(7 downto 0) := X"00";
begin
process(clock)
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
if timer /= 0 and tick_1KHz = '1' then
timer <= timer - 1;
end if;
if enable = '0' then -- follow passively when disabled (i.e. when in 1541 mode)
track <= unsigned(cur_track(1 downto 0));
elsif timer = 0 then
if (cur_track < goto_track) and (cur_track /= c_max_track) then
do_track_in <= '1';
track <= track + 1;
timer <= step_time;
elsif cur_track > goto_track then
do_track_out <= '1';
track <= track - 1;
timer <= step_time;
end if;
end if;
if reset = '1' then
track <= "00";
timer <= to_unsigned(1, 5);
end if;
end if;
end process;
step <= std_logic_vector(track);
busy <= enable when (cur_track /= goto_track) else '0';
process(clock)
begin
if rising_edge(clock) then
if tick_1kHz = '1' and motor_en = '1' then
if index_cnt = 0 then
index_out <= '1';
index_cnt <= X"C7";
else
index_out <= '0';
index_cnt <= index_cnt - 1;
end if;
end if;
if reset = '1' then
index_cnt <= X"C7";
index_out <= '0';
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/cpu_unit/vhdl_sim/mblite_simu_wrapped.vhd
|
1
|
9132
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_wrapped is
end entity;
architecture test of mblite_simu_wrapped is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mb_reset : std_logic := '1';
signal mem_req : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_busy : std_logic;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal irqs : std_logic_vector(7 downto 0) := X"00";
signal plaag_interrupt : std_logic := '0';
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 4194303) := (1024 => X"00000000", others => X"F0000000"); -- 16MB
signal last_char : std_logic_vector(7 downto 0);
constant g_latency : natural := 1;
signal pipe : t_mem_req_32_array(0 to g_latency-1) := (others => c_mem_req_32_init);
signal isr, yield, leave1, leave2 : std_logic := '0';
signal task : std_logic_vector(7 downto 0) := X"FF";
signal curTCB, save, restore, critical : std_logic_vector(31 downto 0) := (others => 'X');
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
mb_reset <= '1', '0' after 2 us;
--plaag_interrupt <= transport '0', '1' after 25 ms, '0' after 30 ms;
i_core: entity work.mblite_wrapper
generic map (
g_icache => false,
g_dcache => false,
g_tag_i => X"0A",
g_tag_d => X"0B"
)
port map (
clock => clock,
reset => reset,
irq_i => irq_i,
irq_o => irq_o,
mb_reset => mb_reset,
disable_i => '0',
disable_d => '0',
invalidate => invalidate,
inv_addr => inv_addr,
io_req => io_req,
io_resp => io_resp,
io_busy => io_busy,
mem_req => mem_req,
mem_resp => mem_resp
);
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
variable irqdiv : natural := 50000;
variable irqdiv2 : natural := 60000;
variable not_ready : natural := 3;
begin
if rising_edge(clock) then
if irqdiv = 0 then
irqs(0) <= '1';
irqdiv := 400000;
else
irqdiv := irqdiv - 1;
end if;
-- if irqdiv2 = 0 then
-- irqs(2) <= '1';
-- irqdiv2 := 97127;
-- else
-- irqdiv2 := irqdiv2 - 1;
-- end if;
io_resp <= c_io_resp_init;
leave1 <= '0';
leave2 <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case io_req.address is
when X"00028" => -- enter IRQ
isr <= '1';
when X"00029" => -- enter yield
yield <= '1';
when X"0002A" => -- leave
isr <= '0';
yield <= '0';
if io_req.data(1) = '1' then
leave1 <= '1'; -- with IRQ ON
else
leave2 <= '1'; -- with IRQ OFF
end if;
when X"00000" => -- interrupt
null;
when X"60304" => -- profiler
null;
when X"60305" => -- profiler
task <= io_req.data;
null;
when X"00004" => -- interupt ack
irqs <= irqs and not io_req.data;
when X"00010" => -- UART_DATA
not_ready := 500;
byte := io_req.data;
char := character'val(to_integer(unsigned(byte)));
last_char <= byte;
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
null;
-- report "I/O write to " & hstr(io_req.address) & " dropped";
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case io_req.address is
when X"00005" => -- IRQ Flags
io_resp.data <= irqs;
when X"0000C" => -- Capabilities 11D447B9
io_resp.data <= X"11";
when X"0000D" => -- Capabilities 11D447B9
io_resp.data <= X"D4";
when X"0000E" => -- Capabilities 11D447B9
io_resp.data <= X"47";
when X"0000F" => -- Capabilities 11D447B9
io_resp.data <= X"99";
when X"00012" => -- UART_FLAGS
if not_ready > 0 then
io_resp.data <= X"50";
not_ready := not_ready - 1;
else
io_resp.data <= X"40";
end if;
when X"2000A" => -- 1541_A memmap
io_resp.data <= X"3F";
when X"2000B" => -- 1541_A audiomap
io_resp.data <= X"3E";
when others =>
-- report "I/O read to " & hstr(io_req.address) & " dropped";
io_resp.data <= X"00";
end case;
end if;
irqs(7) <= plaag_interrupt;
if reset = '1' then
irqs <= X"00";
end if;
end if;
end process;
-- memory
process(clock)
variable addr : natural;
begin
if rising_edge(clock) then
mem_resp <= c_mem_resp_32_init;
pipe(g_latency-1) <= c_mem_req_32_init;
if mem_req.request = '1' and mem_resp.rack = '0' then
mem_resp.rack <= '1';
mem_resp.rack_tag <= mem_req.tag;
pipe(g_latency-1) <= mem_req;
assert mem_req.address(1 downto 0) = "00" report "Lower address bits are non-zero!" severity warning;
if mem_req.read_writen = '0' then
case to_integer(mem_req.address) is
when 16|20 =>
report "Write to illegal address!"
severity warning;
-- when 16#16d20# =>
-- report "Debug: Writing Current TCB to " & hstr(mem_req.data);
-- curTCB <= mem_req.data;
---- when 16#16954# =>
---- critical <= mem_req.data;
-- when 16#FFC# =>
-- report "Debug: Save context, TCB = " & hstr(mem_req.data);
-- save <= mem_req.data;
-- when 16#FF8# =>
-- report "Debug: Restore context, TCB = " & hstr(mem_req.data);
-- restore <= mem_req.data;
when others =>
end case;
end if;
end if;
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
mem_resp.dack_tag <= (others => '0');
mem_resp.data <= (others => '0');
if pipe(0).request='1' then
addr := to_integer(pipe(0).address(21 downto 2));
if pipe(0).read_writen='1' then
mem_resp.dack_tag <= pipe(0).tag;
mem_resp.data <= memory(addr);
else
for i in 0 to 3 loop
if pipe(0).byte_en(i)='1' then
memory(addr)(i*8+7 downto i*8) := pipe(0).data(i*8+7 downto i*8);
end if;
end loop;
end if;
end if;
end if;
end process;
irq_i <= '1' when irqs /= X"00" else '0';
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/copper/vhdl_source/copper_pkg.vhd
|
5
|
3337
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package copper_pkg is
constant c_copper_command : unsigned(3 downto 0) := X"0";
constant c_copper_status : unsigned(3 downto 0) := X"1";
constant c_copper_measure_l : unsigned(3 downto 0) := X"2";
constant c_copper_measure_h : unsigned(3 downto 0) := X"3";
constant c_copper_framelen_l : unsigned(3 downto 0) := X"4";
constant c_copper_framelen_h : unsigned(3 downto 0) := X"5";
constant c_copper_break : unsigned(3 downto 0) := X"6";
constant c_copper_cmd_play : std_logic_vector(3 downto 0) := X"1"; -- starts program in ram
constant c_copper_cmd_record : std_logic_vector(3 downto 0) := X"2"; -- waits for sync, records all writes until next sync.
constant c_copcode_write_reg : std_logic_vector(7 downto 0) := X"00"; -- starting from 00-2F or so.. takes 1 argument
constant c_copcode_read_reg : std_logic_vector(7 downto 0) := X"40"; -- starting from 40-6F or so.. no arguments
constant c_copcode_wait_irq : std_logic_vector(7 downto 0) := X"81"; -- waits until falling edge of IRQn
constant c_copcode_wait_sync : std_logic_vector(7 downto 0) := X"82"; -- waits until sync pulse from timer
constant c_copcode_timer_clr : std_logic_vector(7 downto 0) := X"83"; -- clears timer
constant c_copcode_capture : std_logic_vector(7 downto 0) := X"84"; -- copies timer to measure register
constant c_copcode_wait_for : std_logic_vector(7 downto 0) := X"85"; -- takes a 1 byte argument
constant c_copcode_wait_until: std_logic_vector(7 downto 0) := X"86"; -- takes 2 bytes argument (wait until timer match)
constant c_copcode_repeat : std_logic_vector(7 downto 0) := X"87"; -- restart at program address 0.
constant c_copcode_end : std_logic_vector(7 downto 0) := X"88"; -- ends operation and return to idle
constant c_copcode_trigger_1 : std_logic_vector(7 downto 0) := X"89"; -- pulses on trigger_1 output
constant c_copcode_trigger_2 : std_logic_vector(7 downto 0) := X"8A"; -- pulses on trigger_1 output
type t_copper_control is record
command : std_logic_vector(3 downto 0);
frame_length : unsigned(15 downto 0);
stop : std_logic;
end record;
constant c_copper_control_init : t_copper_control := (
command => X"0",
frame_length => X"4D07", -- 313 lines of 63.. (is incorrect, is one line too long, but to init is fine!)
stop => '0' );
type t_copper_status is record
running : std_logic;
measured_time : unsigned(15 downto 0);
end record;
constant c_copper_status_init : t_copper_status := (
running => '0',
measured_time => X"FFFF" );
end package;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/busses/vhdl_source/avalon_to_io_bridge.vhd
|
6
|
2741
|
-------------------------------------------------------------------------------
-- Title : avalon_to_io_bridge
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module bridges the avalon bus to I/O
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_to_io_bridge is
port (
clock : in std_logic;
reset : in std_logic;
-- 8 bits Avalon bus interface
avs_read : in std_logic;
avs_write : in std_logic;
avs_address : in std_logic_vector(19 downto 0);
avs_writedata : in std_logic_vector(7 downto 0);
avs_ready : out std_logic;
avs_readdata : out std_logic_vector(7 downto 0);
avs_readdatavalid : out std_logic;
avs_irq : out std_logic;
io_read : out std_logic;
io_write : out std_logic;
io_address : out std_logic_vector(19 downto 0);
io_wdata : out std_logic_vector(7 downto 0);
io_rdata : in std_logic_vector(7 downto 0);
io_ack : in std_logic;
io_irq : in std_logic );
end entity;
architecture rtl of avalon_to_io_bridge is
type t_state is (idle, read_pending, write_pending);
signal state : t_state;
begin
avs_irq <= io_irq;
avs_ready <= '1' when (state = idle) else '0';
avs_readdatavalid <= '1' when (state = read_pending) and (io_ack = '1') else '0';
avs_readdata <= io_rdata;
process(clock)
begin
if rising_edge(clock) then
io_read <= '0';
io_write <= '0';
case state is
when idle =>
io_wdata <= avs_writedata;
io_address <= avs_address;
if avs_read='1' then
io_read <= '1';
state <= read_pending;
elsif avs_write='1' then
io_write <= '1';
state <= write_pending;
end if;
when read_pending =>
if io_ack = '1' then
state <= idle;
end if;
when write_pending =>
if io_ack = '1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/usb2/vhdl_sim/usb_controller_tb.vhd
|
5
|
3711
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
signal clock_50 : std_logic := '0';
signal clock_60 : std_logic := '0';
signal clock_50_shifted : std_logic := '1';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- ULPI Interface
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
-- LED interface
signal usb_busy : std_logic;
-- Memory interface
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp := c_mem_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
begin
clock_50 <= not clock_50 after 10 ns;
clock_60 <= not clock_60 after 8.3 ns;
reset <= '1', '0' after 100 ns;
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock_50,
req => io_req,
resp => io_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", iom);
io_write(iom, X"1000", X"01"); -- enable core
wait;
end process;
i_phy: entity work.ulpi_phy_bfm
port map (
clock => clock_60,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_mut: entity work.usb_controller
port map (
ulpi_clock => clock_60,
ulpi_reset => reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- LED interface
usb_busy => usb_busy,
-- register interface bus
sys_clock => clock_50,
sys_reset => reset,
sys_mem_req => mem_req,
sys_mem_resp=> mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp );
clock_50_shifted <= transport clock_50 after 15 ns; -- 270 deg
i_mc: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => true )
port map (
clock => clock_50,
clk_shifted => clock_50_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
MEM_A => SDRAM_A,
MEM_D => SDRAM_D );
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/simp/cfold.vhd
|
3
|
2672
|
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
|
gpl-3.0
|
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