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luebbers/reconos
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demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_fifo_pkg.vhd
|
1
|
14650
|
-------------------------------------------------------------------------------
--
-- Module : BRAM_fifo_pkg.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Package of Block SelectRAM FIFO components
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package BRAM_fifo_pkg is
component BRAM_fifo
generic (
BRAM_MACRO_NUM: integer := 1;
WR_DWIDTH: integer := 32;
RD_DWIDTH: integer := 32;
RD_REM_WIDTH: integer:=2;
WR_REM_WIDTH: integer:=2;
USE_LENGTH: boolean := false;
glbtm: time:=2 ns
);
port (
-- Reset
fifo_gsr_in: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- signals tranceiving from User Application using standardized
-- specification for FifO interface
read_data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
read_rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
read_sof_out_n: out std_logic;
read_eof_out_n: out std_logic;
read_enable_in: in std_logic;
-- signals trasceiving from Aurora
write_data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
write_rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
write_sof_in_n: in std_logic;
write_eof_in_n: in std_logic;
write_enable_in: in std_logic;
-- FifO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
full_out: out std_logic;
empty_out: out std_logic;
data_valid_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_rdy_out: out std_logic;
len_err_out: out std_logic);
end component;
component BRAM_macro is
generic (
BRAM_MACRO_NUM : integer := 1; --Number of BRAM Blocks.
--Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
RD_PAD_WIDTH : integer := 1;
RD_ADDR_FULL_WIDTH: integer := 10;
RD_ADDR_WIDTH : integer := 9;
ADDR_MINOR_WIDTH: integer := 1;
WR_PAD_WIDTH : integer := 1;
WR_ADDR_FULL_WIDTH: integer := 10;
WR_ADDR_WIDTH : integer := 9;
glbtm : time := 1 ns );
port (
-- Reset
fifo_gsr: in std_logic;
-- clocks
wr_clk: in std_logic;
rd_clk: in std_logic;
rd_allow: in std_logic;
rd_allow_minor: in std_logic;
rd_addr_full: in std_logic_vector(RD_PAD_WIDTH+RD_ADDR_FULL_WIDTH-1 downto 0);
rd_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
rd_addr: in std_logic_vector(RD_PAD_WIDTH + RD_ADDR_WIDTH -1 downto 0);
rd_data: out std_logic_vector(RD_DWIDTH -1 downto 0);
rd_rem: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
rd_sof_n: out std_logic;
rd_eof_n: out std_logic;
wr_allow: in std_logic;
wr_allow_minor: in std_logic;
wr_addr: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
wr_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
wr_addr_full: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_FULL_WIDTH-1 downto 0);
wr_data: in std_logic_vector(WR_DWIDTH-1 downto 0);
wr_rem: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
wr_sof_n: in std_logic;
wr_eof_n: in std_logic
);
end component;
component BRAM_S8_S72
port (ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S18_S72
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S36_S72
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S72_S72
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S8_S144
port (ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S16_S144
port (ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S36_S144
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S72_S144
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S144_S144
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (127 downto 0);
DIPA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (127 downto 0);
DOPA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
end BRAM_fifo_pkg;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
8
|
142019
|
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`protect end_protected
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.2/ml605/ml605_light/pcores/dcr_v29_v9_00_a/hdl/vhdl/or_muxcy.vhd
|
7
|
10361
|
-------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
|
gpl-3.0
|
luebbers/reconos
|
core/pcores/xps_osif_v2_01_a/hdl/vhdl/mem_plb46.vhd
|
1
|
31388
|
--!
--! \file mem_plb46.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
entity mem_plb46 is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
--C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13 -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to 11); -- number of bytes to transfer (0..4096)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusReset : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 11);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
-- LocalLink Interface
Bus2IP_MstRd_d : in std_logic_vector(0 to C_PLB_DWIDTH-1);
Bus2IP_MstRd_rem : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_MstRd_sof_n : in std_logic;
Bus2IP_MstRd_eof_n : in std_logic;
Bus2IP_MstRd_src_rdy_n : in std_logic;
Bus2IP_MstRd_src_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : out std_logic;
IP2Bus_MstRd_dst_dsc_n : out std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_PLB_DWIDTH-1);
IP2Bus_MstWr_rem : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstWr_sof_n : out std_logic;
IP2Bus_MstWr_eof_n : out std_logic;
IP2Bus_MstWr_src_rdy_n : out std_logic;
IP2Bus_MstWr_src_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : in std_logic;
Bus2IP_MstWr_dst_dsc_n : in std_logic
);
end entity mem_plb46;
architecture arch of mem_plb46 is
constant BYTES_PER_BEAT : integer := C_PLB_DWIDTH/8;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_PLB_DWIDTH/8-1);
signal mst_cmd_sm_xfer_type : std_logic;
signal mst_cmd_sm_xfer_length : std_logic_vector(0 to 11);
signal mst_cmd_sm_start_rd_llink : std_logic;
signal mst_cmd_sm_start_wr_llink : std_logic;
-- signals for master model read locallink interface state machine
type RD_LLINK_SM_TYPE is (LLRD_IDLE, LLRD_GO);
signal mst_llrd_sm_state : RD_LLINK_SM_TYPE;
signal mst_llrd_sm_dst_rdy : std_logic;
-- signals for master model write locallink interface state machine
type WR_LLINK_SM_TYPE is (LLWR_IDLE, LLWR_SNGL_INIT, LLWR_SNGL, LLWR_BRST_INIT, LLWR_BRST, LLWR_BRST_LAST_BEAT);
signal mst_llwr_sm_state : WR_LLINK_SM_TYPE;
signal mst_llwr_sm_src_rdy : std_logic;
signal mst_llwr_sm_sof : std_logic;
signal mst_llwr_sm_eof : std_logic;
signal mst_llwr_byte_cnt : integer;
signal bram_offset : integer;
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
signal mst_fifo_valid_read_xfer_d1 : std_logic;
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_ip2bus_be : std_logic_vector(0 to 7); -- FIXME: Hardcoded for 64 bit master
signal mst_go : std_logic;
signal xfer_cross_wrd_bndry : std_logic;
signal rolled_MstRd_d : std_logic_vector(0 to C_PLB_DWIDTH-1);
signal rolled_mst_ip2bus_be : std_logic_vector(0 to 7);
signal be_offset : integer range 0 to 7;
signal prefetch_data : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal burstData_current : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal prefetch_first : std_logic;
signal save_first : std_logic;
begin
-- get byte enable offset from target address
be_offset <= TO_INTEGER(ieee.numeric_std.unsigned(i_targetAddr(C_AWIDTH-3 to C_AWIDTH-1)));
mst_reg : process(Bus2IP_Clk, Bus2IP_Reset)
constant BE_32 : std_logic_vector := X"F0";
begin
if Bus2IP_Reset = '1' then
mst_xfer_length <= (others => '0');
mst_cntl_rd_req <= '0';
mst_cntl_wr_req <= '0';
mst_ip2bus_addr <= (others => '0');
mst_ip2bus_be <= (others => '0');
mst_cntl_burst <= '0';
xfer_cross_wrd_bndry <= '0';
mst_go <= '0';
elsif rising_edge(Bus2IP_Clk) then
if (i_burstRdReq = '1' or i_burstWrReq = '1') then -- if incoming burst request
mst_xfer_length <= i_burstLen(3 to 11) & "000"; -- burst length in bytes
mst_cntl_rd_req <= i_burstRdReq; -- read request
mst_cntl_wr_req <= i_burstWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '1'; -- burst
xfer_cross_wrd_bndry <= '0'; -- bursts can't cross word boundary
mst_ip2bus_be <= X"00"; -- bursts do not look at BE
mst_go <= '1';
elsif (i_singleRdReq = '1' or i_singleWrReq = '1') then
mst_cntl_rd_req <= i_singleRdReq; -- read request
mst_cntl_wr_req <= i_singleWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '0'; -- no burst
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) srl be_offset); -- calc byte enables from address
if be_offset > 4 then
-- 32 Bit transfer across 64 Bit boundary, we need to split this
xfer_cross_wrd_bndry <= '1';
end if;
mst_go <= '1';
elsif mst_cmd_sm_set_done = '1' and xfer_cross_wrd_bndry = '1' then -- if last transfer was a single word that crossed a 64bit boundary
xfer_cross_wrd_bndry <= '0'; -- repeat transfer with remaining data
mst_ip2bus_addr <= i_targetAddr + 8-be_offset; -- new target address
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) sll 8-be_offset); -- remaining byte enables
mst_go <= '1';
elsif mst_cmd_sm_clr_go = '1' then
mst_go <= '0';
end if;
end if;
end process;
-- command_decoder protocol to mst_* protocol conversion assignments
mst_cntl_bus_lock <= '0'; -- never lock the bus
-- user logic master command interface assignments
IP2Bus_MstRdReq <= mst_cmd_sm_rd_req;
IP2Bus_MstWrReq <= mst_cmd_sm_wr_req;
IP2Bus_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_MstBE <= mst_cmd_sm_ip2bus_be;
IP2Bus_MstBurst <= mst_cmd_sm_xfer_type;
IP2Bus_MstNum <= mst_cmd_sm_xfer_length;
IP2Bus_MstBusLock <= mst_cmd_sm_bus_lock;
IP2Bus_MstBusReset <= mst_cmd_sm_reset;
-- handshake output signals
o_busy <= mst_cmd_sm_busy or mst_go or i_singleRdReq or i_singleWrReq or i_burstRdReq or i_burstWrReq or mst_cmd_sm_set_done;
o_rdDone <= mst_cmd_sm_set_done and mst_cntl_rd_req and not xfer_cross_wrd_bndry;
o_wrDone <= mst_cmd_sm_set_done and mst_cntl_wr_req and not xfer_cross_wrd_bndry;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
-- state transition
case mst_cmd_sm_state is
-- waiting for transfer
when CMD_IDLE =>
if (mst_go = '1') then -- new transfer initiated?
mst_cmd_sm_state <= CMD_RUN; -- go to RUN state
mst_cmd_sm_clr_go <= '1'; -- clear go register (REMOVEME)
if (mst_cntl_rd_req = '1') then -- read request?
mst_cmd_sm_start_rd_llink <= '1'; -- start ll read
elsif (mst_cntl_wr_req = '1') then -- write request?
mst_cmd_sm_start_wr_llink <= '1'; -- start ll write
end if;
else
mst_cmd_sm_state <= CMD_IDLE; -- otherwise, stay here and do nothing
mst_cmd_sm_busy <= '0';
end if;
-- transfer initiated
when CMD_RUN =>
if (Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0') then -- command acknowledged and not completed?
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- go to WAIT_FOR_DATA state
elsif (Bus2IP_Mst_Cmplt = '1') then -- command completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
if (Bus2IP_Mst_Cmd_Timeout = '1') then -- was it a timeout?
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1'; -- set error and timeout flags
mst_cmd_sm_set_timeout <= '1';
elsif (Bus2IP_Mst_Error = '1') then -- was it an error
-- PLB data transfer error
mst_cmd_sm_set_error <= '1'; -- set only the error flag
end if;
else
mst_cmd_sm_state <= CMD_RUN; -- if it wasn't acknowledged or completed yet (i.e. new request)
mst_cmd_sm_rd_req <= mst_cntl_rd_req; -- set read and write request flags
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr; -- set target address
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be; -- set byte enables
mst_cmd_sm_xfer_type <= mst_cntl_burst; -- set transfer type
mst_cmd_sm_xfer_length <= mst_xfer_length; -- set transfer length (in bytes?)
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock; -- set bus lock (always 0?)
end if; -- and stay in RUN state (i.e. wait for acceptance/abort)
-- transfer request accepted, transfer in progress
when CMD_WAIT_FOR_DATA =>
if (Bus2IP_Mst_Cmplt = '1') then -- transfer completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
else -- otherwise
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- stay here
end if;
-- transfer completed or aborted
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE; -- go to IDLE state
mst_cmd_sm_set_done <= '1'; -- signal that we're done
mst_cmd_sm_busy <= '0'; -- and not busy
-- default catchall
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
----------------------------------------------------
-- LOCAL LINK INTERFACE
----------------------------------------------------
-- user logic master read locallink interface assignments
IP2Bus_MstRd_dst_rdy_n <= not(mst_llrd_sm_dst_rdy);
IP2Bus_MstRd_dst_dsc_n <= '1'; -- do not throttle data
-- implement a simple state machine to enable the
-- read locallink interface to transfer data
LLINK_RD_SM_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
else
-- default condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
-- state transition
case mst_llrd_sm_state is
when LLRD_IDLE =>
if (mst_cmd_sm_start_rd_llink = '1') then -- if we got start signal from master FSM
mst_llrd_sm_state <= LLRD_GO; -- go to GO state
else
mst_llrd_sm_state <= LLRD_IDLE; -- otherwise stay here and keep waiting
end if;
when LLRD_GO =>
-- done, end of packet
if (mst_llrd_sm_dst_rdy = '1' and -- if we are ready to receive
Bus2IP_MstRd_src_rdy_n = '0' and -- the sender is ready to send
Bus2IP_MstRd_eof_n = '0') then -- and the sender is done sending
mst_llrd_sm_state <= LLRD_IDLE; -- we're done
-- not done yet, continue receiving data
else -- otherwise
mst_llrd_sm_state <= LLRD_GO; -- stay in this state
mst_llrd_sm_dst_rdy <= '1'; -- and be ready to receive
end if;
-- default catchall
when others =>
mst_llrd_sm_state <= LLRD_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_RD_SM_PROCESS;
-- user logic master write locallink interface assignments
IP2Bus_MstWr_src_rdy_n <= not(mst_llwr_sm_src_rdy);
IP2Bus_MstWr_src_dsc_n <= '1'; -- do not throttle data
IP2Bus_MstWr_rem <= (others => '0'); -- no remainder mask
IP2Bus_MstWr_sof_n <= not(mst_llwr_sm_sof);
IP2Bus_MstWr_eof_n <= not(mst_llwr_sm_eof);
-- implement a simple state machine to enable the
-- write locallink interface to transfer data
LLINK_WR_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
else
-- default condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
-- state transition
case mst_llwr_sm_state is
-- wait for start of transfer
when LLWR_IDLE =>
if (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '0') then -- single write request?
mst_llwr_sm_state <= LLWR_SNGL_INIT;
elsif (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '1') then -- burst write request?
mst_llwr_sm_state <= LLWR_BRST_INIT;
else
mst_llwr_sm_state <= LLWR_IDLE;
end if;
-- init single transfer
when LLWR_SNGL_INIT =>
mst_llwr_sm_state <= LLWR_SNGL;
mst_llwr_sm_src_rdy <= '1'; -- ready to send
mst_llwr_sm_sof <= '1'; -- signal single transfer by asserting both SOF and EOF
mst_llwr_sm_eof <= '1';
-- do single transfer
when LLWR_SNGL =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and Bus2IP_MstWr_dst_rdy_n = '0') then -- if discontinue from target
mst_llwr_sm_state <= LLWR_IDLE; -- reset back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_eof <= '0';
-- single data beat transfer complete
elsif (mst_fifo_valid_read_xfer = '1') then -- if local memory read has been completed
mst_llwr_sm_state <= LLWR_IDLE; -- go back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_SNGL; -- otherwise keep trying to transfer single word
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- init burst transfer
when LLWR_BRST_INIT =>
mst_llwr_sm_state <= LLWR_BRST;
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_byte_cnt <= CONV_INTEGER(mst_xfer_length);
-- do burst transfer
when LLWR_BRST =>
if (mst_fifo_valid_read_xfer = '1') then -- if a word has been transferred (i.e. we are actively writing)
mst_llwr_sm_sof <= '0'; -- deassert SOF signal
else
mst_llwr_sm_sof <= mst_llwr_sm_sof;
end if;
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '1'; -- and properly terminate transfer
mst_llwr_sm_eof <= '1';
-- last data beat write
elsif (mst_fifo_valid_read_xfer = '1' and -- if this was the second to last beat to transfer
(mst_llwr_byte_cnt-BYTES_PER_BEAT) <= BYTES_PER_BEAT) then
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- go to LAST_BEAT state
mst_llwr_sm_src_rdy <= '1'; -- and signal termination of transfer
mst_llwr_sm_eof <= '1';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST; -- otherwise keep writing data
mst_llwr_sm_src_rdy <= '1';
-- decrement write transfer counter if it's a valid write
if (mst_fifo_valid_read_xfer = '1') then
mst_llwr_byte_cnt <= mst_llwr_byte_cnt - BYTES_PER_BEAT;
else
mst_llwr_byte_cnt <= mst_llwr_byte_cnt;
end if;
end if;
-- do last beat of write burst
when LLWR_BRST_LAST_BEAT =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0'; -- and mark ourselves as not ready (?)
-- last data beat done
elsif (mst_fifo_valid_read_xfer = '1') then -- if this transfer was successful
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- otherwise keep trying to send
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- default catchall
when others =>
mst_llwr_sm_state <= LLWR_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_WR_SM_PROC;
-- determine whether a data beat was successfully written
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n) and mst_llrd_sm_dst_rdy;
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n) and mst_llwr_sm_src_rdy;
-- connect burst ram
o_burstAddr <= i_localAddr(C_AWIDTH-C_BURST_AWIDTH to C_AWIDTH-1) + bram_offset;
o_burstData <= Bus2IP_MstRd_d;
o_burstWE <= mst_cntl_rd_req and mst_cntl_burst and mst_fifo_valid_write_xfer;
o_burstBE <= (others => '1');
-- delay read enable for edge detection and prefetch
mst_fifo_valid_read_xfer_d1 <= mst_fifo_valid_read_xfer when rising_edge(clk) else mst_fifo_valid_read_xfer_d1;
-- prefetch data from burst ram for contiguous writes
prefetch : process(clk, reset)
begin
if reset = '1' then
prefetch_data <= (others => '0');
elsif rising_edge(clk) then
if mst_fifo_valid_read_xfer_d1 = '1' or save_first = '1' then
prefetch_data <= i_burstData;
end if;
end if;
end process;
-- on the first beat of a back-to-back transfer, use the prefetched data, otherwise use the RAM output
burstData_current <= prefetch_data when mst_fifo_valid_read_xfer_d1 = '0' and mst_fifo_valid_read_xfer = '1' else i_burstData;
-- generate address signals for burst ram
burst_addr : process(clk, reset)
begin
if reset = '1' then
bram_offset <= 0;
save_first <= '0';
prefetch_first <= '0';
elsif rising_edge(clk) then
save_first <= '0';
if i_burstRdReq = '1' then -- new burst request
bram_offset <= 0;
elsif i_burstWrReq = '1' then -- new burst request
bram_offset <= 0;
prefetch_first <= '1';
elsif prefetch_first = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
prefetch_first <= '0';
save_first <= '1';
elsif mst_fifo_valid_write_xfer = '1' or mst_fifo_valid_read_xfer = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
end if;
end if;
end process;
-- multiplex burst ram and single data register to bus (possibly shifted)
IP2Bus_MstWr_d <= burstData_current when mst_cntl_burst = '1' else
std_logic_vector(ieee.numeric_std.unsigned(i_singleData & X"00000000") ror be_offset*8);
-- implement single data register
rolled_MstRd_d <= std_logic_vector(ieee.numeric_std.unsigned(Bus2IP_MstRd_d) rol be_offset*8);
rolled_mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(mst_ip2bus_be) rol be_offset);
single_reg : process(Bus2IP_Clk, Bus2IP_Reset, mst_ip2bus_be)
variable bit_enable : std_logic_vector(0 to C_DWIDTH-1);
variable assembled_data : std_logic_vector(0 to C_DWIDTH-1);
begin
for i in 0 to 3 loop
bit_enable(i*8 to i*8+7) := (others => rolled_mst_ip2bus_be(i));
end loop;
if Bus2IP_Reset = '1' then
assembled_data := (others => '0');
elsif rising_edge(Bus2IP_Clk) then
if (mst_cntl_rd_req = '1' and mst_cntl_burst = '0' and mst_fifo_valid_write_xfer = '1') then
assembled_data := (assembled_data and (not bit_enable)) or (rolled_MstRd_d(0 to C_DWIDTH-1) and bit_enable);
end if;
end if;
o_singleData <= assembled_data;
end process;
end arch;
|
gpl-3.0
|
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/my_core_wrapper.vhd
|
1
|
8558
|
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library osif_tb_v1_00_c;
use osif_tb_v1_00_c.All;
entity my_core_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to 7);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component osif_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_PLB_NUM_MASTERS : integer;
C_PLB_MID_WIDTH : integer;
C_FAMILY : string
);
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_MErr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to (C_PLB_AWIDTH-1));
PLB_BE : in std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_PLB_MID_WIDTH-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to (1));
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to (C_PLB_AWIDTH-1));
M_BE : out std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to (1));
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : osif_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_PLB_NUM_MASTERS => 2,
C_PLB_MID_WIDTH => 1,
C_FAMILY => "virtex2p"
)
port map (
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Dispatcher_uCode_0_0/synth/OpenSSD2_Dispatcher_uCode_0_0.vhd
|
4
|
14096
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY OpenSSD2_Dispatcher_uCode_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END OpenSSD2_Dispatcher_uCode_0_0;
ARCHITECTURE OpenSSD2_Dispatcher_uCode_0_0_arch OF OpenSSD2_Dispatcher_uCode_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_Dispatcher_uCode_0_0_arch : ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_Dispatcher_uCode_0_0_arch: ARCHITECTURE IS "OpenSSD2_Dispatcher_uCode_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=OpenSSD2_Dispatcher_uCode_0_0.mif,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.700549 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "OpenSSD2_Dispatcher_uCode_0_0.mif",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.700549 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END OpenSSD2_Dispatcher_uCode_0_0_arch;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_pipeliner.vhd
|
1
|
5772
|
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_mst_pipeliner
-- Architectures: lipif_mst_pipeliner_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 25.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_pipeliner is
generic (
C_NUM_WIDTH : integer := 5
);
port(
clk : in std_logic;
reset : in std_logic;
xfer_num_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
xfer_adv_i : in std_logic;
xfer_nxt_i : in std_logic;
xfer_req_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rdy_o : out std_logic;
prim_valid_o : out std_logic;
prim_last_o : out std_logic;
prim_ack_o : out std_logic;
prim_nburst_o : out std_logic;
pipe_nburst_o : out std_logic
);
end lipif_mst_pipeliner;
architecture lipif_mst_pipeliner_rtl of lipif_mst_pipeliner is
signal num_prim : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_prim_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_sec : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_sec_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal num_tri : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal xfer_last : std_logic;
signal xfer_last_n : std_logic;
signal xfer_comp : std_logic;
signal valid_prim : std_logic;
signal valid_sec : std_logic;
signal valid_tri : std_logic;
signal ack_prim : std_logic;
signal ack_sec : std_logic;
begin
-- Connect ports to internal signals
xfer_rdy_o <= not valid_tri;
xfer_comp <= xfer_nxt_i;
prim_valid_o <= valid_prim;
prim_last_o <= xfer_last;
prim_ack_o <= ack_prim;
-- Next xfer last state calculated from next value of primary burst counter
xfer_last_n <= '1' when (num_prim_n(C_NUM_WIDTH-1 downto 1)=0) else '0';
-- Pipelined next burst signal should only be asserted if a transfer is actually pipelined
-- Don't need to check for a new transfer being pipelined this cycle: it can't have been
-- acknowledged yet!
pipe_nburst_o <= '0' when (num_sec_n(C_NUM_WIDTH-1 downto 1)=0) else valid_sec;
prim_nburst_o <= not xfer_last_n;
-- Generate next counts for primary and secondary stages
process(xfer_comp, valid_prim, valid_sec, valid_tri, xfer_adv_i, xfer_num_i, num_prim, num_sec, num_tri) begin
-- Primary Stage
if(xfer_comp='1' or valid_prim='0') then
if(valid_sec='0') then
num_prim_n <= xfer_num_i;
else
num_prim_n <= num_sec;
end if;
elsif(xfer_adv_i='1') then
-- NOTE: This is synthesized into both a subtractor and down-counter.
-- May save a few slices if the down-counter is removed.
num_prim_n <= num_prim - 1;
else
num_prim_n <= num_prim;
end if;
-- Secondary Stage
if(xfer_comp='1' or valid_sec='0') then
if(valid_tri='0') then
num_sec_n <= xfer_num_i;
else
num_sec_n <= num_tri;
end if;
else
num_sec_n <= num_sec;
end if;
end process;
-- Latch next counter values for all three stages
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
num_prim <= (others=>'0');
num_sec <= (others=>'0');
num_tri <= (others=>'0');
else
-- Primary and secondary stages have next value calculated externally
num_prim <= num_prim_n;
num_sec <= num_sec_n;
-- Trinary Stage
if(xfer_comp='1' or valid_tri='0') then
num_tri <= xfer_num_i;
end if;
-- Last indicator can also be latched
xfer_last <= xfer_last_n;
end if;
end if;
end process;
-- Generate ack state signals for first two pipeline stages
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
ack_prim <= '0';
ack_sec <= '0';
else
-- Primary Stage
if(xfer_comp='1' or ack_prim='0') then
ack_prim <= ack_sec or xfer_ack_i;
end if;
-- Secondary Stage
if(xfer_comp='1' or ack_sec='0') then
ack_sec <= xfer_ack_i and ack_prim and (not xfer_comp or ack_sec);
end if;
end if;
end if;
end process;
-- Generate valid signals for each pipeline stage
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
valid_prim <= '0';
valid_sec <= '0';
valid_tri <= '0';
else
-- Primary Stage
if(xfer_comp='1' or valid_prim='0') then
valid_prim <= valid_sec or xfer_req_i;
end if;
-- Secondary Stage
if(xfer_comp='1' or valid_sec='0') then
valid_sec <= valid_tri or (xfer_req_i and valid_prim and (valid_sec or not xfer_comp));
end if;
-- Trinary Stage
if(xfer_comp='1' or valid_tri='0') then
valid_tri <= xfer_req_i and valid_sec and not xfer_comp;
end if;
end if;
end if;
end process;
end lipif_mst_pipeliner_rtl;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBDCFIFO36x16DR/sim/DPBDCFIFO36x16DR.vhd
|
4
|
33448
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBDCFIFO36x16DR IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END DPBDCFIFO36x16DR;
ARCHITECTURE DPBDCFIFO36x16DR_arch OF DPBDCFIFO36x16DR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 36,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 36,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 3,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBDCFIFO36x16DR_arch;
|
gpl-3.0
|
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@a@l@u_@controller/_primary.vhd
|
2
|
228
|
library verilog;
use verilog.vl_types.all;
entity ALU_Controller is
port(
ALU_op : in vl_logic_vector(3 downto 0);
ALU_ctr : out vl_logic_vector(2 downto 0)
);
end ALU_Controller;
|
gpl-3.0
|
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/fifo_utils.vhd
|
1
|
44568
|
-------------------------------------------------------------------------------
--
-- Module : fifo_utils.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Utility package created for LocalLink FIFO Design
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package fifo_u is
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- data type conversion functions
function to_character (bv : bit_vector(3 downto 0)) return character;
function conv_ascii_logic_vector(nib:std_logic_vector(3 downto 0))
return std_logic_vector;
function to_string (bv : bit_vector) return string;
function to_string (b : bit) return string;
function conv_std_logic_vector (ch : character) return std_logic_vector;
function to_std_logic_vector (b : bit_vector) return std_logic_vector;
function to_std_logic (b : bit) return std_logic;
function boolean_to_std_logic (b : boolean) return std_logic;
function to_bit_vector (a : std_logic_vector) return bit_vector;
function slv2int (S: std_logic_vector) return integer;
function bitv2int (S: bit_vector) return integer;
function int2bv (int_value, width : integer) return bit_vector;
function revByteOrder( arg : std_logic_vector) return std_logic_vector;
-- arithmetic
function log2 (i: natural) return natural;
function POWER2 (p: integer) return integer;
function SQUARE2 (p: integer) return integer;
function maxNat (arg1, arg2 : natural) return natural;
function allZeroes (inp : std_logic_vector) return boolean;
function allOnes (inp : std_logic_vector) return boolean;
function bin_to_gray ( a : std_logic_vector) return std_logic_vector;
function gray_to_bin ( a : std_logic_vector) return std_logic_vector;
function bit_duplicate (b : std_logic; size : natural) return std_logic_vector;
-- FIFO related functions
function GET_ADDR_WIDTH (dw : integer) return integer;
function GET_ADDR_MAJOR_WIDTH (a ,b : integer) return integer;
function GET_ADDR_MINOR_WIDTH (a ,b : integer) return integer;
function GET_WIDTH (i, a, b, m, RorW : integer) return integer;
function GET_MAX_WIDTH(a, b: integer) return integer;
function GET_CTRL_WIDTH(ra,wa,rb,wb:integer) return integer;
function GET_HIGH_VALUE(ra,wa: integer) return integer;
function GET_ADDR_FULL_B(ra, wa, RorW: integer) return integer;
function GET_ADDR_MAJOR_WIDTH(ra, wa, RorW: integer) return integer;
function GET_REM_WIDTH(a: integer) return integer;
function GET_PAR_WIDTH(a: integer) return integer;
function GET_EOF_REM_WIDTH(ra, wa: integer) return integer;
function GET_RATIO(ra, wa, par: integer) return integer;
function GET_WR_SOF_EOF_WIDTH(ra, wa : integer) return integer;
function GET_RD_SOF_EOF_WIDTH(ra, wa : integer) return integer;
function GET_WR_CTRL_REM_WIDTH(ra, wa : integer) return integer;
function GET_RD_CTRL_REM_WIDTH(ra, wa : integer) return integer;
function GET_C_WR_ADDR_WIDTH(ra, wa, mem_num: integer) return integer;
function GET_C_RD_ADDR_WIDTH(ra, wa, mem_num: integer) return integer;
function GET_C_RD_TEMP_WIDTH(ra, wa: integer) return integer;
function GET_C_WR_TEMP_WIDTH(ra, wa: integer) return integer;
function GET_WR_PAD_WIDTH(rd, wd, c_wa, waf, wa: integer) return integer;
function GET_RD_PAD_WIDTH(da, db: integer) return integer;
function GET_NUM_DIV(ra, wa : integer) return integer;
function GET_WR_EN_FACTOR(NUM_DIV, MEM_NUM: integer) return integer;
function GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH : integer) return integer;
function GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH : integer) return integer;
end fifo_u;
package body fifo_u is
-------------------------------------------------------------------------------
-- data type conversion functions
-------------------------------------------------------------------------------
-- duplicate the bit value to specific width, e.g. '1' -> "1111"
function bit_duplicate (b : std_logic; size : natural)
return std_logic_vector is
variable o : std_logic_vector(size -1 downto 0);
begin
for i in size -1 downto 0 loop
o(i) := b;
end loop;
return o;
end function;
-- convert a character to a nibble wide std_logic_vector
function conv_std_logic_vector (ch : character) return std_logic_vector is
begin
case ch is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' => return "1010";
when 'b' => return "1011";
when 'c' => return "1100";
when 'd' => return "1101";
when 'e' => return "1110";
when 'f' => return "1111";
when others => assert false report "unrecognised character"
severity failure;
end case;
return "0000";
end conv_std_logic_vector;
-- convert bit to std_logic
function to_std_logic (b : bit) return std_logic is
begin
case b is
when '0' => return '0';
when '1' => return '1';
when others => assert false report "unrecognised bit value"
severity failure;
end case;
return '0';
end to_std_logic;
-- convert boolean to std_logic
function boolean_to_std_logic (b : boolean) return std_logic is
begin
case b is
when FALSE => return '0';
when TRUE => return '1';
when others => return '0';
end case;
return '0';
end boolean_to_std_logic;
-- Convert 4-bit vector to a character
function to_character (bv : bit_vector(3 downto 0)) return character is
begin -- to_character
case bv is
when b"0000" => return '0';
when b"0001" => return '1';
when b"0010" => return '2';
when b"0011" => return '3';
when b"0100" => return '4';
when b"0101" => return '5';
when b"0110" => return '6';
when b"0111" => return '7';
when b"1000" => return '8';
when b"1001" => return '9';
when b"1010" => return 'a';
when b"1011" => return 'b';
when b"1100" => return 'c';
when b"1101" => return 'd';
when b"1110" => return 'e';
when b"1111" => return 'f';
end case;
end to_character;
function conv_ascii_logic_vector (nib : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nib is
when "0000" => return "00110000";
when "0001" => return "00110001";
when "0010" => return "00110010";
when "0011" => return "00110011";
when "0100" => return "00110100";
when "0101" => return "00110101";
when "0110" => return "00110110";
when "0111" => return "00110111";
when "1000" => return "00111000";
when "1001" => return "00111001";
when "1010" => return "01000001";
when "1011" => return "01000010";
when "1100" => return "01000011";
when "1101" => return "01000100";
when "1110" => return "01000101";
when "1111" => return "01000110";
when others => return "00100000";
end case;
return "00100000";
end conv_ascii_logic_vector;
-- Convert n-bits vector to n/4-character string
function to_string (bv : bit_vector) return string is
constant strlen : integer := bv'length / 4;
variable str : string(1 to strlen);
begin -- to_string
for i in 0 to strlen - 1 loop
str(strlen-i) := to_character(bv((i * 4) + 3 downto (i * 4)));
end loop; -- i
return str;
end to_string;
-- Convert 1-bit to 1-character string
function to_string (b : bit) return string is
begin
case b is
when '0' => return "0";
when '1' => return "1";
when others => assert false report "unrecognised bit value"
severity failure;
end case;
return "0";
end to_string;
-- Convert std_logic_vector to bit_vector
function to_bit_vector (a : std_logic_vector) return bit_vector is
variable b : bit_vector(a'length -1 downto 0);
begin
for i in 0 to a'length - 1 loop
b(i) := to_bit (a(i));
end loop;
return b;
end to_bit_vector;
-- Convert bit_vector to std_logic_vector
function to_std_logic_vector (b : bit_vector) return std_logic_vector is
variable a : std_logic_vector(b'length -1 downto 0);
begin
for i in 0 to b'length - 1 loop
a(i) := to_std_logic (b(i));
end loop;
return a;
end to_std_logic_vector;
-- std_logic_vector to integer
function slv2int (S: std_logic_vector) return integer is
variable S_i: std_logic_vector(S'Length-1 downto 0) := S;
variable N : integer := 0;
begin
for i in S_i'Right to S_i'Left loop
if (S_i(i)) = '1' then
N := N + (2**i);
elsif (S_i(i)) = 'X' then
N := 0;
end if;
end loop;
return N;
end;
-- bit_vector to integer
function bitv2int (S: bit_vector) return integer is
variable S_i: bit_vector(S'Length-1 downto 0) := S;
variable N : integer := 0;
begin
for i in S_i'Right to S_i'Left loop
if (S_i(i)) = '1' then
N := N + (2**i);
end if;
end loop;
return N;
end;
function int2bv (int_value, width : integer) return bit_vector is
variable result : bit_vector(width-1 downto 0) := (others => '0');
begin
for i in 0 to width-1 loop
if ( ((int_value/(2**i)) mod 2) = 1) then
result(i) := '1';
end if;
end loop;
return result;
end int2bv;
function revByteOrder( arg : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(arg'high downto 0); -- length is numNibs
variable numbytes : integer;
begin
numbytes := arg'length/8;
lp0: for i in 0 to numbytes -1 loop
tmp( (8*(numbytes-i)-1) downto 8*(numbytes-i-1) ) := arg( (8*i+7) downto 8*i);
end loop lp0;
return tmp ;
end revbyteOrder;
-------------------------------------------------------------------------------
-- arithmetic
-------------------------------------------------------------------------------
function allZeroes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '1' then
t := false;
end if;
end loop;
return t;
end allZeroes;
function allOnes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '0' then
t := false;
end if;
end loop;
return t;
end allOnes;
-- returns the maximum of two naturals
function maxNat (arg1, arg2 : natural)
return natural is
begin -- maxNat
if arg1 >= arg2 then
return arg1;
else
return arg2;
end if;
end maxNat;
-- a function to calculate log2(i)
function log2 (i: natural) return natural is
variable answer : natural ;
begin
for n in 1 to 32 loop -- works for upto 32 bits
if (2**(n-1) < i) and (2**n >= i) then
return (n);
end if;
end loop;
return (1);
end log2;
-- a function to caculate 2 ** p
function POWER2 ( p: in integer) return integer is
variable answer : integer ;
begin
answer := 2**p;
return answer;
end function POWER2;
-- a function to caculate square2(p)
function SQUARE2 ( p: in integer) return integer is
variable answer : integer ;
begin
case p is
when 1 => answer := 0;
when 2 => answer := 1;
when 4 => answer := 2;
when 8 => answer := 3;
when 16 => answer := 4;
when 32 => answer := 5;
when 64 => answer := 6;
when 128 => answer := 7;
when 256 => answer := 8;
when 512 => answer := 9;
when 1024 => answer := 10;
when others => assert false report "overflow or input exceeds acceptable range." severity failure;
end case;
return answer;
end function SQUARE2;
-- convert binary code to gray code
function bin_to_gray ( a : std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(a'range);
begin
b(b'high) := a(a'high);
for i in b'high -1 downto 0 loop
b(i) := a(i+1) XOR a(i);
end loop;
return b;
end function;
-- conver gray code to binary code
function gray_to_bin ( a : std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(a'range);
begin
for i in a'range loop
if i = a'left then
b(i) := a(i);
else
b(i) := a(i) xor b(i+1);
end if;
end loop;
return b;
end function;
-- generate the address width according to the data width, for FIFO
function GET_ADDR_WIDTH (dw : in integer) return integer is
variable aw : integer;
begin
case dw is
when 1 => aw := 14;
when 2 => aw := 13;
when 4 => aw := 12;
when 8 => aw := 11;
when 16=> aw := 10;
when 32=> aw := 9;
when 64=> aw := 9;
when 128=> aw := 9;
when others => assert false report "input is not acceptable." severity failure;
end case;
return aw;
end function GET_ADDR_WIDTH;
-- generate the major address width, for FIFO
function GET_ADDR_MAJOR_WIDTH (a , b: in integer) return integer is
variable result : integer;
begin
if a < b then -- A's data width is shorter than B's data width
-- Then A's addr width is longer than B's addr width
-- The Major & Minor Addrs are positive. The major addr is equal to
-- B's address width
result := GET_ADDR_WIDTH(b);
else -- otherwise, No minor addr exsits
result := GET_ADDR_WIDTH(a);
end if;
return result;
end function GET_ADDR_MAJOR_WIDTH;
-- generate the minor address width, for BRAM_FIFO
function GET_ADDR_MINOR_WIDTH (a , b : in integer) return integer is
variable result : integer;
begin
if a < b then -- A's data width is shorter than B's data width
-- Then A's addr width is longer than B's addr width
-- The Major & Minor Addrs are positive. The minor addr is equal to
-- the differential value between A & B's address width
if b > 32 then
if b = 64 then
result := GET_ADDR_WIDTH(a)+1 - GET_ADDR_WIDTH(b);
elsif b = 128 then
if a = 64 then
result := GET_ADDR_WIDTH(a)+1 - GET_ADDR_WIDTH(b);
else
result := GET_ADDR_WIDTH(a)+2 - GET_ADDR_WIDTH(b);
end if;
end if;
else
result := GET_ADDR_WIDTH(a) - GET_ADDR_WIDTH(b);
end if;
elsif a > b then -- otherwise, invert the result
-- It may be zero which means no minor address exsits.
if a > 32 then
if a = 64 then
result := GET_ADDR_WIDTH(b)+1 - GET_ADDR_WIDTH(a);
elsif a = 128 then
if b = 64 then
result := GET_ADDR_WIDTH(b)+1 - GET_ADDR_WIDTH(a);
else
result := GET_ADDR_WIDTH(b)+2 - GET_ADDR_WIDTH(a);
end if;
end if;
else
result := GET_ADDR_WIDTH(b) - GET_ADDR_WIDTH(a);
end if;
else
result := 1;
end if;
return result;
end function GET_ADDR_MINOR_WIDTH;
function GET_WIDTH (i, a, b, m, RorW : in integer) return integer is
-- m: 1 get major address width; 2 get minor address width
-- RorW: 0 : Rd 1: Wr
-- a: Rd data width ; b: Wr data width
variable result : integer;
begin
if a < b then
if m = 1 then
result := i;
elsif m = 2 then
if RorW = 0 then
result := SQUARE2(b) - SQUARE2(a);
else
result := 1;
end if;
end if;
else -- Rd > Wr
if m = 1 then
result := i;
elsif m = 2 then
if RorW = 0 then --
result := 1;
else
result := SQUARE2(a) - SQUARE2(b);
end if;
end if;
end if;
if result = 0 then
result := result + 1;
return result;
else
return result;
end if;
end function GET_WIDTH;
function GET_MAX_WIDTH(a, b: in integer) return integer is
variable result: integer;
begin
if a < b then
result := b;
else
result := a;
end if;
return result;
end function GET_MAX_WIDTH;
function GET_CTRL_WIDTH(ra,wa,rb,wb: integer) return integer is
variable result: integer;
begin
if rb < wb then
result := wa + 2;
else
result := ra + 2;
end if;
return result;
end function GET_CTRL_WIDTH;
function GET_HIGH_VALUE(ra,wa: integer) return integer is
variable result: integer;
begin
if (wa > ra) then
result := wa - ra;
else
result := 1;
end if;
return result;
end function GET_HIGH_VALUE;
function GET_ADDR_FULL_B(ra, wa, RorW: integer) return integer is
variable result : integer;
begin
if (ra > wa) then
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
elsif RorW = 1 then
if ra > 36 then
if ra = 64 then
result := GET_ADDR_WIDTH(wa)+1;
elsif ra = 128 then
if wa = 64 then
result := GET_ADDR_WIDTH(wa) + 1;
else
result := GET_ADDR_WIDTH(wa) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(wa);
end if;
end if;
else
if RorW = 0 then
if wa > 36 then
if wa = 64 then
result := GET_ADDR_WIDTH(ra)+1;
elsif wa = 128 then
if ra = 64 then
result := GET_ADDR_WIDTH(ra) + 1;
else
result := GET_ADDR_WIDTH(ra) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(ra);
end if;
elsif RorW = 1 then
result := GET_ADDR_WIDTH(wa);
end if;
end if;
return result;
end function GET_ADDR_FULL_B;
function GET_ADDR_MAJOR_WIDTH(ra, wa, RorW: integer) return integer is
variable result : integer;
begin
if ra > wa then
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
elsif RorW = 1 then
if ra > 36 then
if ra = 64 then
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 1;
elsif ra = 128 then
if wa = 64 then
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 1;
else
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa);
end if;
end if;
elsif ra < wa then
if RorW = 0 then
if wa > 36 then
if wa = 64 then
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+1;
elsif wa = 128 then
if ra = 64 then
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+1;
else
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+2;
end if;
end if;
else
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa);
end if;
elsif RorW = 1 then
result := GET_ADDR_WIDTH(wa);
end if;
else
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
else
result := GET_ADDR_WIDTH(wa);
end if;
end if;
return result;
end function GET_ADDR_MAJOR_WIDTH;
function GET_REM_WIDTH(a: integer) return integer is
variable result : integer;
begin
if a = 0 then
result := 1;
else
result := a;
end if;
return result;
end function GET_REM_WIDTH;
function GET_PAR_WIDTH(a: integer) return integer is
variable result : integer;
begin
case a is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 16;
when others => NULL;
end case;
return result;
end function GET_PAR_WIDTH;
function GET_EOF_REM_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if ra > wa then
result := ra;
else
result := wa;
end if;
return result;
end function GET_EOF_REM_WIDTH;
function GET_RATIO(ra, wa, par: integer) return integer is
variable result : integer;
begin
result := (par * ra) / wa;
return result;
end function GET_RATIO;
function GET_WR_SOF_EOF_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 4;
when 32 => result := 4;
when 64 => result := 4;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 8;
when 32 => result := 8;
when 64 => result := 8;
when 128 => result := 8;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 32;
when 16 => result := 32;
when 32 => result := 8;
when 64 => result := 16;
when 128 => result := 16;
when others => NULL;
end case;
end if;
return result;
end function GET_WR_SOF_EOF_WIDTH;
function GET_RD_SOF_EOF_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 8;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 16;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 16;
when others => NULL;
end case;
end if;
return result;
end function GET_RD_SOF_EOF_WIDTH;
function GET_WR_CTRL_REM_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 1;
when 64 => result := 3;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 2;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 4;
when 32 => result := 4;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 16;
when 16 => result := 8;
when 32 => result := 16;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_WR_CTRL_REM_WIDTH;
function GET_RD_CTRL_REM_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 3;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 16;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 1;
when 32 => result := 4;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 16;
when 16 => result := 1;
when 32 => result := 4;
when 64 => result := 3;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_RD_CTRL_REM_WIDTH;
function GET_C_WR_ADDR_WIDTH(ra, wa, mem_num: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 =>
if mem_num < 8 then
result := 13;
elsif mem_num = 8 then
result := 14;
elsif mem_num = 16 then
result := 15;
else
result := 16;
end if;
when 16 => result := 13;
when 32 => result := 13;
when 64 =>
if mem_num <= 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 12;
when 16 => result := 14;
when 32 => result := 13;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 13;
when 16 => result := 13;
when 32 => result := 12;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 13;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 =>
if mem_num <= 2 then
result := 10;
elsif mem_num = 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 16 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 32 => result := 12;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 10;
when 16 => result := 8;
when 32 => result := 11;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_C_WR_ADDR_WIDTH;
function GET_C_RD_ADDR_WIDTH(ra, wa, mem_num: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 =>
if mem_num < 8 then
result := 13;
elsif mem_num = 8 then
result := 14;
elsif mem_num = 16 then
result := 15;
else
result := 16;
end if;
when 16 => result := 13;
when 32 => result := 13;
when 64 =>
if mem_num <= 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 13;
when 16 => result := 14;
when 32 => result := 13;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 13;
when 16 => result := 14;
when 32 => result := 12;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 13;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 =>
if mem_num <= 2 then
result := 13;
elsif mem_num = 4 then
result := 14;
elsif mem_num = 8 then
result := 15;
elsif mem_num = 16 then
result := 16;
else
result := 17;
end if;
when 16 =>
if mem_num <= 8 then
result := 14;
else
result := 15;
end if;
when 32 => result := 12;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 13;
when 16 => result := 8;
when 32 => result := 13;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_C_RD_ADDR_WIDTH;
function GET_C_RD_TEMP_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 16 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 8;
when 32 => result := 8;
when others => result := 8;
end case;
elsif wa = 64 then
case ra is
when 16 => result := 8;
when 8 => result := 8;
when 128 => result := 16;
when others => result := 8;
end case;
elsif wa = 128 then
case ra is
when 16 => result := 4;
when 64 => result := 8;
when others => result := 8;
end case;
else
result := 8;
end if;
return result;
end function GET_C_RD_TEMP_WIDTH;
function GET_C_WR_TEMP_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 16 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 8;
when 32 => result := 8;
when others => result := 8;
end case;
elsif wa = 64 then
case ra is
when 16 => result := 8;
when 8 => result := 8;
when others => result := 8;
end case;
elsif wa = 128 then
case ra is
when 16 => result := 32;
when 64 => result := 16;
when others => result := 8;
end case;
else
result := 8;
end if;
return result;
end function GET_C_WR_TEMP_WIDTH;
function GET_WR_PAD_WIDTH(rd, wd, c_wa, waf, wa: integer) return integer is
variable result: integer;
begin
if rd> wd then
if c_wa - wa >= 0 then
result := c_wa - wa;
else
result := 0;
end if;
else
if c_wa - waf >= 0 then
result := c_wa - waf;
else
result := 0;
end if;
end if;
return result;
end function GET_WR_PAD_WIDTH;
function GET_RD_PAD_WIDTH(da, db: integer) return integer is
variable result : integer;
begin
if da-db >= 0 then
result := da - db;
else
result := 0;
end if;
return result;
end function GET_RD_PAD_WIDTH;
function GET_NUM_DIV(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 16 => result := 8;
when 64 => result := 2;
when others => result := 1;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when others => result := 1;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 4;
when others => result := 1;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 2;
when others => result := 1;
end case;
else
result := 1;
end if;
return result;
end function GET_NUM_DIV;
function GET_WR_EN_FACTOR(NUM_DIV, MEM_NUM: integer) return integer is
variable result : integer;
begin
if MEM_NUM < NUM_DIV then
result :=1;
else
result := MEM_NUM/NUM_DIV;
end if;
return result;
end function GET_WR_EN_FACTOR;
function GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH : integer) return integer is
variable result : integer;
begin
if RD_DWIDTH > WR_DWIDTH then
result := RD_DWIDTH / WR_DWIDTH;
else
result := 1;
end if;
return result;
end function GET_RDDWdivWRDW;
function GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH : integer) return integer is
variable result : integer;
begin
if WR_DWIDTH > RD_DWIDTH then
result := WR_DWIDTH / RD_DWIDTH;
else
result := 1;
end if;
return result;
end function GET_WRDW_div_RDDW;
end fifo_u;
|
gpl-3.0
|
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@ex@number/_primary.vhd
|
1
|
386
|
library verilog;
use verilog.vl_types.all;
entity ExNumber is
port(
IR : in vl_logic_vector(15 downto 0);
Ex_top : in vl_logic;
ALU_SrcB : in vl_logic_vector(2 downto 0);
Rt_out : in vl_logic_vector(31 downto 0);
B_in : out vl_logic_vector(31 downto 0)
);
end ExNumber;
|
gpl-3.0
|
luebbers/reconos
|
tests/simulation/plb/mutex/test_mutex.vhd
|
1
|
3092
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mutex is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mutex;
architecture Behavioral of test_mutex is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
type t_state is (STATE_INIT, STATE_HALLO, STATE_LOCK, STATE_READ, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
out_value <= in_value + 1;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
if done then
state <= STATE_HALLO;
end if;
when STATE_HALLO =>
reconos_write(done, o_osif, i_osif, X"10000002", X"AFFEDEAD");
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, in_value);
if done then
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, out_value);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/vector_heater_a_v1_00_a/hdl/vhdl/vector_heater_a.vhd
|
1
|
21648
|
------------------------------------------------------------------------------
-- vector_heater_a.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: vector_heater_a.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Feb 28 11:50:03 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library vector_heater_a_v1_00_a;
use vector_heater_a_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity vector_heater_a is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity vector_heater_a;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of vector_heater_a is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity vector_heater_a_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
gpl-3.0
|
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/ADXL362Ctrl.vhd
|
1
|
44750
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 16:48:39 02/20/2014
-- Design Name:
-- Module Name: ADXL362Ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the controller for the Nexys4 onboard ADXL362 Accelerometer device.
-- The module uses the SPI Interface component to communicate with the ADXL362.
-- At initialization time, the module resets the ADXL362, then configures its internal registers.
-- After configuring its internal registers, the acceleration will be read on the three axes followed
-- by the temperature data: A set of 8 data bytes are read: XDATA_L, XDATA_H, YDATA_L, YDATA_H, ZDATA_L,
-- ZDATA_H, TEMP_L and TEMP_H, see the ADXL362 datasheet for details.
-- Reading is done continuously and an average is made from a number of reads. The number of reads
-- for which average is made should be a power of two and is determined by the NUM_READS_AVG parameter,
-- by default 16. The UPDATE_FREQUENCY_HZ parameter sets a counter to a period of 1/UPDATE_FREQUENCY_HZ.
-- The state machine will wait for this period of time before starting a number of NUM_READS_AVG times
-- data read procedure.
-- Before reading a set of data, the state machine reads and checks the status register to see when
-- new data is available at the ADXL362. Therefore the real sample time depends on the ADXL362 sample
-- frequency, set in the Filter Control Register, address 0x2C, in this project set by default to 200Hz.
--
-- The module consists of three state machines, named by the signals holding the states:
-- - SPI Send/Receive Control State Machine: StC_Spi_SendRec. This state machine creates a handshake transaction
-- with the SPI Interface component, using the Start and Done signals to:
-- - Send the number of bytes specified by the Cnt_Bytes_Sent counter (3 when configuring an ADXL362 internal
-- register, 2 when sending a Read Command). The bytes to be sent through the SPI interface are taken from the
-- command register, Cmd_Reg.
-- - Receive the number of bytes specified by the Cnt_Bytes_Rec counter (8 when reading acceleration and
-- temperature data, 1 when reading the status register), when reading is required (SPI_RnW = 1).
-- The acceleration and temperature data is stored in the data register, Data_Reg
--
-- - SPI Transaction State machine, StC_Spi_Trans. This state machine controls the previously described SPI
-- Send/Receive Control State Machine, using handshake with the the StartSpiSendRec (write) and SPI_SendRec_Done (read)
-- signals:
-- - Prepares and loads the command register, Cmd_Reg with the appropiate command string (configure a specific
-- register, read data or read status)
-- - Loads Cnt_Bytes_Sent and Cnt_Bytes_Rec with the number of bytes to be sent and/or received
-- - Activates StartSpiSendRec to start the SPI Send/Receive Control State Machine and wait for its answer
-- by reading the SPI_SendRec_Done signal
--
-- Note that between each SPI transaction (Register write or Register read) the SS signal has to be deactivated
-- for at least 10nS before a new command is issued
--
-- - ADXL 362 Control State Machine, StC_Adxl_Ctrl. This state machine controls the previously described SPI
-- Transaction State machine, also by using handshake with the StartSpiTr (write) and SPI_Trans_Done (read) signals:
-- 1. First, Cmd_Reg will be loaded with the reset command from the Cmd_Reg_Data ROM and the state machine starts
-- the SPI Transaction State Machine to send the reset command to the ADXL362 accelerometer
-- 2. The state machine waits for a period of time and then sends the remaining configuration register data from
-- Cmd_Reg_Data to the ADXL362 accelerometer
-- 3. After configuring ADXL362, the state machine waits for a period of time equal to 1/UPDATE_FREQUENCY_HZ
-- before starts reading
-- 4. After the period of time elapsed the state machine reads the status register and, when there is new data available, reads the
-- reads the X, Y and Z acceleration data, followed by temperature data.
-- A number of reads equal to NUM_READS_AVG is performed, i.e. Step 4 is repeated NUM_READS_AVG times.
-- 5. The data read is averaged in the ACCEL_X_SUM, ACCEL_Y_SUM, ACCEL_Z_SUM and ACCEL_TMP_SUM registers. The
-- NUM_READS_AVG is power of 2 in order to make averaging easier by removing the least significant bits. After
-- a number of reads equal to NUM_READS_AVG is done, the state machine updates the output data, ACCEL_X, ACCEL_Y,
-- ACCEL_Z and ACCEL_TMP, stored in 12-bit two's complement format and signals to the output by activating for one
-- clock period the Data_Ready signal.
-- After that the state machine proceeds to Step 3, in an infinite loop. The state machine restarts from Step 1 only
-- when the FPGA is reconfigured or the Reset signal is activated.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
use IEEE.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADXL362Ctrl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 1000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data signals
ACCEL_X : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_TMP : out STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : out STD_LOGIC;
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end ADXL362Ctrl;
architecture Behavioral of ADXL362Ctrl is
-- SPI Interface component declaration
component SPI_If is
generic
(
SYSCLK_FREQUENCY_HZ : integer:= 100000000;
SCLK_FREQUENCY_HZ : integer:= 1000000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0); -- Data to be transmitted
Dout : out STD_LOGIC_VECTOR (7 downto 0); -- Data received;
Start : in STD_LOGIC; -- used to start the transmission
Done : out STD_LOGIC; -- Signaling that transmission ended
HOLD_SS : in STD_LOGIC; -- Signal that forces SS low in the case of multiple byte
-- transmit/receive mode
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end component;
--**************************************
-- Constant Definitions
--**************************************
-- To create the update frequency counter
constant UPDATE_DIV_RATE : integer := (SYSCLK_FREQUENCY_HZ / UPDATE_FREQUENCY_HZ);
constant SYS_CLK_PERIOD_PS : integer := ((1000000000 / SYSCLK_FREQUENCY_HZ) * 1000);
--ADXL 362 Read and Write Command
constant READ_CMD : STD_LOGIC_VECTOR (7 downto 0) := X"0B";
constant WRITE_CMD : STD_LOGIC_VECTOR (7 downto 0) := X"0A";
-- Data read will be always performed starting from Address X"0E",
-- representing XACC_H. A total number of 8 bytes will be read.
constant READ_STARTING_ADDR : STD_LOGIC_VECTOR (7 downto 0):= X"0E";
-- Status Register Read will be used to check when new data is available (Bit 0 is 1)
constant STATUS_REG_ADDR : STD_LOGIC_VECTOR (7 downto 0):= X"0B";
-- Number of bytes to write when configuring registers
constant NUMBYTES_CMD_CONFIG_REG : integer := 3;
-- Number of bytes to write when reading registers
constant NUMBYTES_CMD_READ : integer := 2;
-- Number of bytes to read when reading data from ADXL362
constant NUMBYTES_READ_DATA : integer := 8;
-- Number of bytes to read when reading status register from ADXL362
constant NUMBYTES_READ_STATUS : integer := 1;
-- number of command vectors to send, one command vector
-- represents ADXL362 register address followed by command byte,
-- i.e. one command vector will mean two bytes
constant NUM_COMMAND_VEC : integer := 4;
-- Number of reads to be performed for which average is calculated, default is 16
constant NUM_READS : natural := NUM_READS_AVG;
-- Number of extra bits when creating the average of the reads
constant NUM_READS_BITS : natural := natural(ceil(log(real(NUM_READS), 2.0)));
-- after each SPI transaction, SS needs to be inactive for at least 10ns before a new command is issued
constant SS_INACTIVE_PERIOD_NS : integer := 10000;
constant SS_INACTIVE_CLOCKS : integer := (SS_INACTIVE_PERIOD_NS/(SYS_CLK_PERIOD_PS/1000));
-- To specify encoding of the state machines
attribute FSM_ENCODING : string;
--SPI Interface Control Signals
signal Start : STD_LOGIC; -- Signal controlling the SPI interface, controlled by the SPI Send/Receive State Machine
signal Done : STD_LOGIC; -- Signaling that transmission ended, coming from the SPI interface
signal HOLD_SS : STD_LOGIC; -- Signal that forces SS low in the case of multiple byte
-- transmit/receive mode, controlled by the SPI Transaction State Machine
-- Create the initialization vector, i.e.
-- the register data to be written to initialize ADXL362
type rom_type is array (0 to ((2* NUM_COMMAND_VEC)-1)) of STD_LOGIC_VECTOR (7 downto 0);
constant Cmd_Reg_Data : rom_type := ( X"1F", X"52", -- Soft Reset Register Address and Reset Command
X"1F", X"00", -- Soft Reset Register Address, clear Command
X"2D", X"02", -- Power Control Register, Enable Measure Command
X"2C", X"14" -- Filter Control Register, 2g range, 1/4 Bandwidth, 200HZ Output Data Rate
);
--address the reg_data ROM
signal Cmd_Reg_Data_Addr: integer range 0 to (NUM_COMMAND_VEC - 1) := 0;
-- Enable Incrementing Cmd_Reg_Data_Addr, controlled by the ADXL Control State machine
signal EN_Advance_Cmd_Reg_Addr: STD_LOGIC := '0';
-- will enable incrementing by 2 Cmd_Reg_Data_Addr
signal Advance_Cmd_Reg_Addr: STD_LOGIC := '0';
-- signal that shows that all of the addresses were read
signal Cmd_Reg_Addr_Done : STD_LOGIC := '0';
-- SPI Transfer Send Data signals. Writing Commands will be always a 3-byte transfer,
-- therefore commands will be temporarry stored in a 3X8 shift register.
type command_reg_type is array (0 to 2) of STD_LOGIC_VECTOR (7 downto 0);
signal Cmd_Reg: command_reg_type := (X"00", X"00", WRITE_CMD);
-- command_reg control signals
signal Load_Cmd_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Transaction State Machine,
-- the command register is load with the appropiate command
signal Shift_Cmd_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Send/Receive State Machine,
-- advance to the next command when a byte was sent
-- to count the bytes to be sent
-- Cnt_Bytes_Sent will decrement at the same time when
-- cmd_reg is shifted, therefore its control signal is the same as
-- for Cmd_Reg: EN_Shift_Cmd_Reg
signal Cnt_Bytes_Sent : integer range 0 to 3 :=0;
-- Load Cnt_Bytes_Sent with the number of bytes to be sent
-- according to the command to be sent
signal Load_Cnt_Bytes_Sent : STD_LOGIC := '0'; -- controlled by the SPI Transaction State Machine
signal Reset_Cnt_Bytes : STD_LOGIC := '0'; -- Controlled by the Main State Machine
-- will reset both the sent and received byte counter
-- SPI Transfer Receive Data signals. Reading data will be a 8-byte transfer:
-- XACC_H, XACC_L, YACC_H, YACC_L, ZACC_H, ZACC_L, TEMP_H, TEMP_L
-- therefore an 8X8 shift register is created.
type data_reg_type is array (0 to (NUMBYTES_READ_DATA - 1)) of STD_LOGIC_VECTOR (7 downto 0);
signal Data_Reg: data_reg_type := (others => X"00");
-- data_reg control signals:
signal EN_Shift_Data_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Send/Receive State Machine
-- Shift when a new byte was received
-- Data Reg will be shifted when a new byte comes, i.e. Shift_Data_Reg <= EN_Shift_Data_Reg AND Done;
signal Shift_Data_Reg : STD_LOGIC := '0';
-- to count the bytes to be received
-- Cnt_Bytes_Rec will decrement at the same time when Data_Reg is shifted,
-- therefore its control signal is the same as for Data_Reg: Shift_Data_Reg
signal Cnt_Bytes_Rec : integer range 0 to NUMBYTES_READ_DATA - 1 := 0;
-- Load Cnt_Bytes_Rec with the number of bytes to be received, controlled by the SPI Transaction State Machine
signal Load_Cnt_Bytes_Rec : STD_LOGIC := '0';
-- SPI Data to Send and Data Received registers
-- Data to send register will be loaded together with shifting
-- a new byte in Cmd_Reg, i.e. its control signal is Shift_Cmd_Reg
-- Data Received Register will be read when shifting Data_Reg
signal D_Send : STD_LOGIC_VECTOR (7 downto 0) := X"00";
signal D_Rec : STD_LOGIC_VECTOR (7 downto 0) := X"00";
-- SPI Send/Receive State Machine internal condition signals
signal StartSpiSendRec : STD_LOGIC := '0'; -- Start SPI transfer, controlled by the SPI Transaction State Machine
signal SPI_RnW : STD_LOGIC := '0'; -- Write 3 bytes or write 2 bytes followed by read 1 byte or 8 bytes
signal SPI_WR_Done : STD_LOGIC := '0'; -- Active when the write transfer is done, i.e. 2 or 3 bytes were written
signal SPI_RD_Done : STD_LOGIC := '0'; -- Active when the read transfer is done, i.e. 8 bytes were read
-- SPI Send/Receive State Machine status signals, used by the SPI Transaction State Machine
signal SPI_SendRec_Done : STD_LOGIC := '0';
-- Define Control Signals, Status signals and States for the SPI Send/Receive State Machine
-- From MSB: 6:Shift_Cmd_Reg, 5:EN_Shift_Data_Reg, 4:SPI_SendRec_Done, 3:Start, 2:STC(2), 1:STC(1), 0:STC(0)
-- bit 6543210
constant stSpiSendRecIdle : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; -- Idle state, wait for StartSpiSendRec
constant stSpiPrepareCmd : STD_LOGIC_VECTOR (6 downto 0) := "1000001"; -- Load D_Send with the next byte and shift the command register
constant stSpiSendStartW : STD_LOGIC_VECTOR (6 downto 0) := "0001011"; -- Send the Start command to the SPI interface
constant stSpiWaitOnDoneW : STD_LOGIC_VECTOR (6 downto 0) := "0000111"; -- Wait until Done comes
constant stSpiSendStartR : STD_LOGIC_VECTOR (6 downto 0) := "0001110"; -- Send Start command again to the SPI interface if read was requested
constant stSpiWaitOnDoneR : STD_LOGIC_VECTOR (6 downto 0) := "0100100"; -- Wait until Done comes
constant stSpiSendRecDone : STD_LOGIC_VECTOR (6 downto 0) := "0010101"; -- Done state, return to Idle
--State Machine Signal Definitions
signal StC_Spi_SendRec, StN_Spi_SendRec : STD_LOGIC_VECTOR (6 downto 0) := stSpiSendRecIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Spi_SendRec: signal is "USER";
-- Self-blocking counter for SS_INACTIVE_CLOCKS periods while SS is inactive
signal Cnt_SS_Inactive : integer range 0 to (SS_INACTIVE_CLOCKS -1) := 0;
-- controlled by the SPI Transaction State Machine
signal Reset_Cnt_SS_Inactive : STD_LOGIC := '0';
-- Signaling that SS_INACTIVE_PERIOD passed
signal Cnt_SS_Inactive_done : STD_LOGIC := '0';
-- Signaling that SPI Transaction is done
signal SPI_Trans_Done : STD_LOGIC := '0';
-- SPI Transaction State Machine internal Condition Signals, controlled
-- by the ADXL 362 Control State Machine
signal StartSpiTr : STD_LOGIC := '0'; -- Start SPI transaction
-- Define Control Signals, Status signals and States for the SPI Transaction State Machine
-- From MSB: 9:Load_Cmd_Reg, 8:Load_Cnt_Bytes_Sent, 7:Load_Cnt_Bytes_Rec, 6:StartSpiSendRec,
-- 5:HOLD_SS, 4:Reset_Cnt_SS_Inactive, 3:SPI_Trans_Done, 2:STC(2), 1:STC(1), 0:STC(0)
-- bit 9876543210
constant stSpiTransIdle : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; -- Idle state, wait for StartSpiTr
constant stSpiPrepAndSendCmd : STD_LOGIC_VECTOR (9 downto 0) := "1111100001"; -- Load Cmd_Reg with the command string and activate StartSpiSendRec
constant stSpiWaitonDoneSR : STD_LOGIC_VECTOR (9 downto 0) := "0000110011"; -- Wait until SPI_SendRec_Done becomes active
constant stSpiWaitForSsInact : STD_LOGIC_VECTOR (9 downto 0) := "0000000010"; -- Wait for SS_INACTIVE_PERIOD
constant stSpiTransDone : STD_LOGIC_VECTOR (9 downto 0) := "0000001110"; -- Done state, return to Idle
--State Machine Signal Definitions
signal StC_Spi_Trans, StN_Spi_Trans : STD_LOGIC_VECTOR (9 downto 0) := stSpiTransIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Spi_Trans: signal is "USER";
-- Data from the ADXL 362 will be sampled at a period defined by UPDATE_DIV_RATE
-- Divider used to generate the Sample_Rate_Tick, used also for timing
signal Sample_Rate_Div : integer range 0 to (UPDATE_DIV_RATE - 1) := 0;
signal Reset_Sample_Rate_Div : STD_LOGIC := '0';
signal Sample_Rate_Tick : STD_LOGIC := '0';
-- A number of 16 reads will be performed from the ADXL 362,
-- and their average will be sent as data
signal Cnt_Num_Reads : integer range 0 to (NUM_READS - 1) := 0;
signal CE_Cnt_Num_Reads : STD_LOGIC := '0'; -- enable counting, controlled by the ADXL 362 Control State Machine
signal Reset_Cnt_Num_Reads : STD_LOGIC := '0';
--Signaling that a number of 16 reads were done
signal Cnt_Num_Reads_Done : STD_LOGIC := '0';
-- Summing of incoming data will be stored in these signals
-- These will be used as accumulators, on two's complement
signal ACCEL_X_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_Y_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_Z_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_TMP_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
-- Enables Summing the incomming data
signal Enable_Sum : STD_LOGIC := '0';
-- Pipe Data_Ready to have stable data at the output when activates
signal Data_Ready_1 : STD_LOGIC := '0';
-- ADXL 362 Control State Machine - The Main State Machine Internal Condition Signal
signal Adxl_Data_Ready : STD_LOGIC := '0'; -- showing that data is ready, read from the ADXL 362 Status Register
signal Adxl_Conf_Err : STD_LOGIC := '0'; -- showing that a configuration error ocurred, read from the ADXL 362 Status Register
-- Define Control Signals, Status signals and States for the ADXL 362 Control State Machine
-- From MSB: 11:Reset_Cnt_Bytes, 10:EN_Advance_Cmd_Reg_Addr, 9:StartSpiTr, 8:Reset_Cnt_Num_Reads,
-- 7:CE_Cnt_Num_Reads, 6:Reset_Sample_Rate_Div, 5:Enable_Sum, 4:Data_Ready_1, 3:STC(3), 2:STC(2), 1:STC(1), 0:STC(0)
-- 11
-- bit 109876543210
constant stAdxlCtrlIdle : STD_LOGIC_VECTOR (11 downto 0) := "100100000000"; -- Idle state, wait for 10 clock periods before start
constant stAdxlSendResetCmd : STD_LOGIC_VECTOR (11 downto 0) := "011001000001"; -- Send the Reset Command for ADXL
constant stAdxlWaitResetDone : STD_LOGIC_VECTOR (11 downto 0) := "010000000011"; -- Wait for some time until ADXL initializes.
-- The sample rate divider is used for timing
constant stAdxlConf_Remaining : STD_LOGIC_VECTOR (11 downto 0) := "011001000010"; -- Clear the Reset Register,
-- then configure the remaining registers
constant stAdxlWaitSampleRateTick : STD_LOGIC_VECTOR (11 downto 0) := "000100000110"; -- wait until the sample time passes
constant stAdxlRead_Status : STD_LOGIC_VECTOR (11 downto 0) := "011001000111"; -- Read the status register from ADXL 362
constant stAdxlRead_Data : STD_LOGIC_VECTOR (11 downto 0) := "011000000101"; -- Read the data from ADXL 362
constant stAdxlFormatandSum : STD_LOGIC_VECTOR (11 downto 0) := "000010101101"; -- Store and sum the received data
-- If 16 reads were done, go to the Done state
constant stAdxlRead_Done : STD_LOGIC_VECTOR (11 downto 0) := "000001011111"; -- Done state, return to stAdxlWaitSampleRateTick
--State Machine Signal Definitions
signal StC_Adxl_Ctrl, StN_Adxl_Ctrl : STD_LOGIC_VECTOR (11 downto 0) := stAdxlCtrlIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Adxl_Ctrl: signal is "USER";
begin
--Instantiate the SPI interface first
SPI_Interface: SPI_If
generic map
(
SYSCLK_FREQUENCY_HZ => SYSCLK_FREQUENCY_HZ,
SCLK_FREQUENCY_HZ => SCLK_FREQUENCY_HZ
)
port map
(
SYSCLK => SYSCLK,
RESET => RESET,
Din => D_Send,
Dout => D_Rec,
Start => Start,
Done => Done,
HOLD_SS => HOLD_SS,
--SPI Interface Signals
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
SS => SS
);
-- Assign the control and status signals of the SPI Send/Receive State Machine
Shift_Cmd_Reg <= StC_Spi_SendRec(6); -- Shift Cmd_Reg when New data is loading into D_Send
EN_Shift_Data_Reg <= StC_Spi_SendRec(5); -- Enable shifting the data register from D_Rec, shifting is performed when a new byte comes, i.e Done becomes active
SPI_SendRec_Done <= StC_Spi_SendRec(4); -- Transfer of the number of bytes is done
Start <= StC_Spi_SendRec(3); -- Send the Start command to the SPI interface
--in the stSpiSendStartW (writing) or stSpiSendStartR (Reading) states
-- Load D_Send with the new data to be transmitted
Load_D_Send: process (SYSCLK, RESET, Cmd_Reg, Shift_Cmd_Reg)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
D_Send <= X"00";
elsif Shift_Cmd_Reg = '1' then
D_Send <= Cmd_Reg (2);
end if;
end if;
end process Load_D_Send;
-- Assign the control and status signals of the SPI Transaction State Machine
Load_Cmd_Reg <= StC_Spi_Trans(9); -- Load the Command Register when preparing the command to be sent to ADXL
Load_Cnt_Bytes_Sent <= StC_Spi_Trans(8); -- Also load the counter of bytes to be sent
Load_Cnt_Bytes_Rec <= StC_Spi_Trans(7); -- And, in the case of reception, the counter of bytes to be received
StartSpiSendRec <= StC_Spi_Trans(6); -- Also send the start command to the SPI Send/Receive State Machine
-- Note that the signals above are active at the same time, i.e identical. They will be optimized by the synthesizer
HOLD_SS <= StC_Spi_Trans(5); -- Each SPI send/receive will be multiple byte transfer, so activate HOLD_SS
Reset_Cnt_SS_Inactive <= StC_Spi_Trans(4); -- Keep the Cnt_SS_Inactive counter reset, until the transfer is done
-- in the next state the state machine will raise SS for a period of SS_INACTIVE_PERIOD_NS
SPI_Trans_Done <= StC_Spi_Trans(3); -- Signals that the SPI transfer is done
-- Assign the control and status signals of the ADXL 362 Control State Machine
Reset_Cnt_Bytes <= StC_Adxl_Ctrl(11); -- Reset the counters for bytes to send and receive. These counters are reset
-- at initializing, then reloaded at each new transaction
EN_Advance_Cmd_Reg_Addr <= StC_Adxl_Ctrl(10); -- Advance the address of the command vectors, to load a new command
StartSpiTr <= StC_Adxl_Ctrl(9); -- Send the Start command to the SPI Transaction State Machine
Reset_Cnt_Num_Reads <= StC_Adxl_Ctrl(8); -- Reset the counter, once at initialization time, then before starting data read,
-- i.e in the stAdxlRead_Status state
CE_Cnt_Num_Reads <= StC_Adxl_Ctrl(7); -- Increment Cnt_Num_Reads after a new set of data come i.e. in the stAdxlFormatandSum state
Reset_Sample_Rate_Div <= StC_Adxl_Ctrl(6); -- Reset the Sample_Rate_Div counter before entering in the sample period wait state
-- i.e. in the stAdxlConf_Remaining and the stAdxlRead_Done
Enable_Sum <= StC_Adxl_Ctrl(5); -- After new data set come, enable summing
Data_Ready_1 <= StC_Adxl_Ctrl(4); -- To signal external components that new data set is available, coming from 16 reads
-- Load and shift Cmd_Reg according to the active commands
Load_Shift_Cmd_Reg: process (SYSCLK, Cmd_Reg, Cmd_Reg_Data_Addr, StC_Adxl_Ctrl, Load_Cmd_Reg, Shift_Cmd_Reg)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Load_Cmd_Reg = '1' then -- Load with data
if (StC_Adxl_Ctrl = stAdxlSendResetCmd)
or (StC_Adxl_Ctrl = stAdxlConf_Remaining) then -- In this case load with command vectors
Cmd_Reg(2) <= WRITE_CMD;
Cmd_Reg(1) <= Cmd_Reg_Data (2 * Cmd_Reg_Data_Addr);
Cmd_Reg(0) <= Cmd_Reg_Data ((2 * Cmd_Reg_Data_Addr) + 1);
elsif (StC_Adxl_Ctrl = stAdxlRead_Status) then
Cmd_Reg(2) <= READ_CMD;
Cmd_Reg(1) <= STATUS_REG_ADDR;
Cmd_Reg(0) <= X"00";
elsif (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In this case load with command vectors
Cmd_Reg(2) <= READ_CMD;
Cmd_Reg(1) <= READ_STARTING_ADDR;
Cmd_Reg(0) <= X"00";
end if;
elsif Shift_Cmd_Reg = '1' then -- shift to load D_send with the new command byte
Cmd_Reg(2) <= Cmd_Reg(1);
Cmd_Reg(1) <= Cmd_Reg(0);
Cmd_Reg(0) <= X"00";
end if;
end if;
end process Load_Shift_Cmd_Reg;
-- Create the address counter for the Cmd_Reg_Data command vectors
-- Increment by two the Cmd_Reg_Data_Addr after a SPI Register Write transaction is done
Advance_Cmd_Reg_Addr <= EN_Advance_Cmd_Reg_Addr AND SPI_Trans_Done;
Count_Addr: process (SYSCLK, RESET, Cmd_Reg_Data_Addr, StC_Adxl_Ctrl, Advance_Cmd_Reg_Addr)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' or StC_Adxl_Ctrl = stAdxlCtrlIdle then
Cmd_Reg_Data_Addr <= 0;
elsif Advance_Cmd_Reg_Addr = '1' then
if Cmd_Reg_Data_Addr = (NUM_COMMAND_VEC - 1) then -- Avoid to address Cmd_Reg_Data out of range
Cmd_Reg_Data_Addr <= 0;
else
Cmd_Reg_Data_Addr <= Cmd_Reg_Data_Addr + 1;
end if;
end if;
end if;
end process Count_Addr;
-- Signal when all of the addresses were read
Cmd_Reg_Addr_Done <= '1' when Cmd_Reg_Data_Addr = (NUM_COMMAND_VEC - 1) else '0';
-- Shift Data_Reg when a new byte comes
Shift_Data_Reg <= EN_Shift_Data_Reg AND Done;
-- Read incoming data
Read_Data: process (SYSCLK, Shift_Data_Reg, D_Rec, Data_Reg) -- When reading the status register, one byte is read, therefore
variable i: integer range 0 to 6 := 0; -- the status register data will be on Data_Reg(0)
begin -- When reading incoming data, exactly 8 reads are performed,
if SYSCLK'EVENT AND SYSCLK = '1' then -- therefore no initialization is required for Data_Reg
if Shift_Data_Reg = '1' then
for i in 0 to 6 loop
Data_Reg(i+1) <= Data_Reg(i);
end loop;
Data_Reg(0) <= D_Rec;
end if;
end if;
end process Read_Data;
-- Count the bytes to be send and to be received
Count_Bytes_Send: process (SYSCLK, Reset_Cnt_Bytes, Load_Cnt_Bytes_Sent, Shift_Cmd_Reg, Cnt_Bytes_Sent)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Bytes = '1' then
Cnt_Bytes_Sent <= 0;
elsif Load_Cnt_Bytes_Sent = '1' then
if (StC_Adxl_Ctrl = stAdxlSendResetCmd)
or (StC_Adxl_Ctrl = stAdxlConf_Remaining) then -- In this case send 3 command bytes
-- Decrementing and shifting Cmd_Reg will be done BEFORE sending data
-- through the serial interface, therefore load NUMBYTES_CMD_CONFIG_REG or NUMBYTES_CMD_READ.
-- The condition to end SPI send operation is Cnt_Bytes_Sent = 0 AND Done = '1'
Cnt_Bytes_Sent <= NUMBYTES_CMD_CONFIG_REG;
elsif (StC_Adxl_Ctrl = stAdxlRead_Status)
or (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In the case of read command, send 2 command bytes
Cnt_Bytes_Sent <= NUMBYTES_CMD_READ;
else
Cnt_Bytes_Sent <= 0;
end if;
elsif Shift_Cmd_Reg = '1' then -- When shifting Cmd_Reg, decrement the counter
if Cnt_Bytes_Sent = 0 then
Cnt_Bytes_Sent <= 0; -- Stay at 0, reload at the next SPI transaction
else
Cnt_Bytes_Sent <= Cnt_Bytes_Sent - 1;
end if;
end if;
end if;
end process Count_Bytes_Send;
Count_Bytes_Rec: process (SYSCLK, Reset_Cnt_Bytes, Load_Cnt_Bytes_Rec, Shift_Data_Reg, Cnt_Bytes_Rec)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Bytes = '1' then
Cnt_Bytes_Rec <= 0;
elsif Load_Cnt_Bytes_Rec = '1' then
if (StC_Adxl_Ctrl = stAdxlRead_Status) then -- In this case we have to read 1 byte
-- Decrementing and shifting Data_Reg will be done AFTER sending data
-- through the serial interface, therefore load NUMBYTES_READ_STATUS - 1 or NUMBYTES_READ_DATA - 1.
-- The condition to end SPI receive operation is Cnt_Bytes_Rec = 0 AND Done = '1'
Cnt_Bytes_Rec <= NUMBYTES_READ_STATUS - 1;
elsif (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In the case we have to read 8 bytes
Cnt_Bytes_Rec <= NUMBYTES_READ_DATA -1;
else
Cnt_Bytes_Rec <= 0;
end if;
elsif Shift_Data_Reg = '1' then -- When shifting Data_Reg, decrement the counter
if Cnt_Bytes_Rec = 0 then
Cnt_Bytes_Rec <= 0; -- Stay at 0, reload at the next SPI transaction
else
Cnt_Bytes_Rec <= Cnt_Bytes_Rec - 1;
end if;
end if;
end if;
end process Count_Bytes_Rec;
-- Create the Sample_Rate_Div counter and the Sample_Rate_Tick signal
Count_Sample_Rate_Div: process (SYSCLK, Reset_Sample_Rate_Div, Sample_Rate_Div)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Sample_Rate_Div = '1' then
Sample_Rate_Div <= 0;
elsif Sample_Rate_Div = (UPDATE_DIV_RATE - 1) then
Sample_Rate_Div <= 0;
else
Sample_Rate_Div <= Sample_Rate_Div + 1;
end if;
end if;
end process Count_Sample_Rate_Div;
Sample_Rate_Tick <= '1' when Sample_Rate_Div = (UPDATE_DIV_RATE - 1) else '0';
-- Create the Cnt_Num_Reads counter, self-blocking
Count_Num_Reads: process (SYSCLK, Reset_Cnt_Num_Reads, CE_Cnt_Num_Reads, Cnt_Num_Reads)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Num_Reads = '1' then
Cnt_Num_Reads <= 0;
elsif CE_Cnt_Num_Reads = '1' then
if Cnt_Num_Reads = (NUM_READS - 1) then
Cnt_Num_Reads <= (NUM_READS - 1);
else
Cnt_Num_Reads <= Cnt_Num_Reads + 1;
end if;
end if;
end if;
end process Count_Num_Reads;
Cnt_Num_Reads_Done <= '1' when Cnt_Num_Reads = (NUM_READS - 1) else '0';
-- Create the Cnt_SS_Inactive counter, also self_blocking
Count_SS_Inactive: process (SYSCLK, RESET, Reset_Cnt_SS_Inactive, Cnt_SS_Inactive)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' or Reset_Cnt_SS_Inactive = '1' then
Cnt_SS_Inactive <= 0;
elsif Cnt_SS_Inactive = (SS_INACTIVE_CLOCKS - 1) then
Cnt_SS_Inactive <= (SS_INACTIVE_CLOCKS - 1);
else
Cnt_SS_Inactive <= Cnt_SS_Inactive + 1;
end if;
end if;
end process Count_SS_Inactive;
Cnt_SS_Inactive_done <= '1' when Cnt_SS_Inactive = (SS_INACTIVE_CLOCKS - 1) else '0';
-- SPI Send/Receive State Machine internal condition signals
-- SPI_RnW will be controlled according to the states of the Adxl 362 Control state machine
Set_SPI_RnW: process (SYSCLK, StC_Adxl_Ctrl)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if (StC_Adxl_Ctrl = stAdxlRead_Status)
or (StC_Adxl_Ctrl = stAdxlRead_Data) then
SPI_RnW <= '1';
else
SPI_RnW <= '0';
end if;
end if;
end process Set_SPI_RnW;
-- SPI Send/Receive State machine internal condition signals
SPI_WR_Done <= '1' when Cnt_Bytes_Sent = 0 AND Done = '1' else '0';
SPI_RD_Done <= '1' when Cnt_Bytes_Rec = 0 AND Done = '1' else '0';
-- Spi Send/Receive State Machine register process
Register_StC_Spi_SendRec: process (SYSCLK, RESET, StN_Spi_SendRec)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Spi_SendRec <= stSpiSendRecIdle;
else
StC_Spi_SendRec <= StN_Spi_SendRec;
end if;
end if;
end process Register_StC_Spi_SendRec;
-- Spi Send/Receive State Machine transitions process
Cmb_StC_Spi_SendRec: process (StC_Spi_SendRec, StartSpiSendRec, StartSpiSendRec,
SPI_WR_Done, SPI_RD_Done, SPI_RnW, Done)
begin
StN_Spi_SendRec <= StC_Spi_SendRec; -- Default: Stay in the current state
case (StC_Spi_SendRec) is
when stSpiSendRecIdle => if (StartSpiSendRec = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; end if;
when stSpiPrepareCmd => StN_Spi_SendRec <= stSpiSendStartW;
when stSpiSendStartW => StN_Spi_SendRec <= stSpiWaitOnDoneW;
when stSpiWaitOnDoneW => if (SPI_RnW = '1') then -- in the case of a read command proceed to reading data, if writing is done
if (SPI_WR_Done = '1') then StN_Spi_SendRec <= stSpiSendStartR;
elsif (Done = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; -- Return to send the next command byte
end if;
else
if (SPI_WR_Done = '1') then StN_Spi_SendRec <= stSpiSendRecDone; -- Sending command bytes finished
elsif (Done = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; -- Return to send the next command byte
end if;
end if;
when stSpiSendStartR => StN_Spi_SendRec <= stSpiWaitOnDoneR; --Send Start command to the SPI interface and wait until reads a byte
when stSpiWaitOnDoneR => if (SPI_RD_Done = '1') then StN_Spi_SendRec <= stSpiSendRecDone; -- If all of the bytes were read
elsif (Done = '1') then StN_Spi_SendRec <= stSpiSendStartR; -- Return and send another Start command to read
end if; -- the next byte
when stSpiSendRecDone => StN_Spi_SendRec <= stSpiSendRecIdle;
when others => StN_Spi_SendRec <= stSpiSendRecIdle;
end case;
end process Cmb_StC_Spi_SendRec;
-- SPI Transaction State Machine register process
Register_StC_Spi_Trans: process (SYSCLK, RESET, StN_Spi_Trans)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Spi_Trans <= stSpiTransIdle;
else
StC_Spi_Trans <= StN_Spi_Trans;
end if;
end if;
end process Register_StC_Spi_Trans;
-- SPI Transaction State Machine transitions process
Cmb_StC_Spi_Trans: process (StC_Spi_Trans, StartSpiTr, Cnt_SS_Inactive_done, SPI_SendRec_Done)
begin
StN_Spi_Trans <= StC_Spi_Trans; -- Default: Stay in the current state
case (StC_Spi_Trans) is
when stSpiTransIdle => if (StartSpiTr = '1') then StN_Spi_Trans <= stSpiPrepAndSendCmd; end if; -- Start SPI Transaction
when stSpiPrepAndSendCmd => StN_Spi_Trans <= stSpiWaitonDoneSR; -- Load Cmd_Reg, the Cnt_Bytes_Sent and Cnt_Bytes_Rec counters and send
-- the Start command to the Spi Send/Receive state machine
when stSpiWaitonDoneSR => if (SPI_SendRec_Done = '1') then StN_Spi_Trans <= stSpiWaitForSsInact; end if; -- SPI Send/Receive done,
-- Discativate SS for SS_INACTIVE_CLOCKS
when stSpiWaitForSsInact => if (Cnt_SS_Inactive_done = '1') then StN_Spi_Trans <= stSpiTransDone; end if; -- SS_INACTIVE_CLOCKS passed, go to
-- the Done state
when stSpiTransDone => StN_Spi_Trans <= stSpiTransIdle;
when others => StN_Spi_Trans <= stSpiTransIdle;
end case;
end process Cmb_StC_Spi_Trans;
-- The Status Register read will be on Data_Reg(0), bit 0 shows if new data is ready
-- Adxl_Data_Ready and Adxl_Conf_Err will be tested in the ADXL 362 Control State Machine, in the stAdxlRead_Status state
Adxl_Data_Ready <= Data_Reg(0)(0);
Adxl_Conf_Err <= Data_Reg(0)(7);
-- ADXL 362 Control State Machine register process
Register_StC_Adxl_Ctrl: process (SYSCLK, RESET, StN_Adxl_Ctrl)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Adxl_Ctrl <= stAdxlCtrlIdle;
else
StC_Adxl_Ctrl <= StN_Adxl_Ctrl;
end if;
end if;
end process Register_StC_Adxl_Ctrl;
-- ADXL 362 Control State Machine Transitions process
Cmb_StC_Adxl_Ctrl: process (StC_Adxl_Ctrl, Cnt_SS_Inactive_done, SPI_Trans_Done, Sample_Rate_Tick,
Cmd_Reg_Addr_Done, Adxl_Data_Ready, Adxl_Conf_Err, Cnt_Num_Reads_Done)
begin
StN_Adxl_Ctrl <= StC_Adxl_Ctrl; -- Default: Stay in the current state
case (StC_Adxl_Ctrl) is
when stAdxlCtrlIdle => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlSendResetCmd; end if; -- wait for some clock periods
-- before start
when stAdxlSendResetCmd => if (SPI_Trans_Done = '1') then StN_Adxl_Ctrl <= stAdxlWaitResetDone; end if; -- Send the Reset command to the ADXL 362
when stAdxlWaitResetDone => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlConf_Remaining; end if; -- wait for about 1mS for the
-- ADXL 362 to initialize
when stAdxlConf_Remaining => if ( Cmd_Reg_Addr_Done = '1' AND SPI_Trans_Done = '1') then -- all of the configuration register data were written
StN_Adxl_Ctrl <= stAdxlWaitSampleRateTick; -- into the ADXL 362
end if;
when stAdxlWaitSampleRateTick => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlRead_Status; end if; -- Read and check the
--status register
when stAdxlRead_Status => if SPI_Trans_Done = '1' then
if Adxl_Conf_Err = '1' then StN_Adxl_Ctrl <= stAdxlCtrlIdle; -- if error ocurred in configuration, go to the ilde state
-- and send reset command again
elsif Adxl_Data_Ready = '1' then StN_Adxl_Ctrl <= stAdxlRead_Data; -- If data is available, start data read
end if;
end if;
when stAdxlRead_Data => if (SPI_Trans_Done = '1') then StN_Adxl_Ctrl <= stAdxlFormatandSum; end if; -- If a set of data is read,
-- add it to the accumulators
when stAdxlFormatandSum => if (Cnt_Num_Reads_Done = '1') then
StN_Adxl_Ctrl <= stAdxlRead_Done; -- done 16 reads, go to the Done state
else
StN_Adxl_Ctrl <= stAdxlRead_Status; -- Proceed to the next read
end if;
when stAdxlRead_Done => StN_Adxl_Ctrl <= stAdxlWaitSampleRateTick; -- Wait for the next Sample_Rate_Tick, in an infinite loop
when others => StN_Adxl_Ctrl <= stAdxlCtrlIdle;
end case;
end process Cmb_StC_Adxl_Ctrl;
-- Create the accumulators
-- Data_Reg is shifted from 0 to 7, it means that after reading a set of data, Data_Reg will contain
-- Data_Reg(7) = XDATA_L,
-- Data_Reg(6) = XDATA_H,
-- Data_Reg(5) = YDATA_L,
-- Data_Reg(4) = YDATA_H,
-- Data_Reg(3) = ZDATA_L,
-- Data_Reg(2) = ZDATA_H,
-- Data_Reg(1) = TEMP_L,
-- Data_Reg(0) = TEMP_H
Sum_Data: process (SYSCLK, RESET, Data_Ready_1, Enable_Sum, Data_Reg,
ACCEL_X_SUM, ACCEL_Y_SUM, ACCEL_Z_SUM, ACCEL_TMP_SUM)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if (RESET = '1' OR Data_Ready_1 = '1') then
ACCEL_X_SUM <= (others => '0');
ACCEL_Y_SUM <= (others => '0');
ACCEL_Z_SUM <= (others => '0');
ACCEL_TMP_SUM <= (others => '0');
elsif Enable_Sum = '1' then
ACCEL_X_SUM <= ACCEL_X_SUM + (Data_Reg(6)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(7));
ACCEL_Y_SUM <= ACCEL_Y_SUM + (Data_Reg(4)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(5));
ACCEL_Z_SUM <= ACCEL_Z_SUM + (Data_Reg(2)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(3));
ACCEL_TMP_SUM <= ACCEL_TMP_SUM + (Data_Reg(0)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(1));
end if;
end if;
end process Sum_Data;
-- Register the output data
Register_Output_Data: process (SYSCLK, RESET, Data_Ready_1, ACCEL_X_SUM,
ACCEL_Y_SUM, ACCEL_Z_SUM, ACCEL_TMP_SUM)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
ACCEL_X <= (others => '0');
ACCEL_Y <= (others => '0');
ACCEL_Z <= (others => '0');
ACCEL_TMP <= (others => '0');
elsif Data_Ready_1 = '1' then -- Divide by NUM_READS to create the average and set the output data
ACCEL_X <= ACCEL_X_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS)); -- 12 bits
ACCEL_Y <= ACCEL_Y_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
ACCEL_Z <= ACCEL_Z_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
ACCEL_TMP <= ACCEL_TMP_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
end if;
end if;
end process Register_Output_Data;
-- Pipe Data_Ready from Data_Ready_1
-- to have stable output data when Data_Ready becomes active
Pipe_Data_Ready: process (SYSCLK, RESET, Data_Ready_1)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
Data_Ready <= '0';
else
Data_Ready <= Data_Ready_1;
end if;
end if;
end process Pipe_Data_Ready;
end Behavioral;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_0_0/src/c_sub/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd
|
8
|
8572
|
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iprappCgQF3yozwJUavmi37vBhy4iqlSLwyJYo+30Byi9j7jyF+L6rCC7GWsSAA7FkHGq4YHn0YV
sbvGSqGf7/xU+1DoUJxnKllPZB8LMyciBFIs6mlGaVLU3rs5rcLJsv81Ruu+AZwE
`protect end_protected
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.1/ml605/ml605_light/pcores/dcr_v29_v9_00_a/hdl/vhdl/dcr_v29.vhd
|
7
|
12890
|
-------------------------------------------------------------------------------
-- $Id: dcr_v29.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- dcr_v29.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dcr_v29.vhd
-- Version: v1.00b
-- Description: IBM DCR (Device Control Register) Bus implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- dcr_v29.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 4-18-02 First Version
-- ALS 4-29-02
-- ALS 4-01-03 Put in work-around for 1 DCR Slave problem with
-- NGDBUILD
-- GAB 10-05-09 Removed reference to proc_common_v1_00_b and pulled
-- or_gate and or_muxcy into this dcr library.
-- Updated copyright header
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- Removed 10/5/09
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DCR_NUM_SLAVES -- number of DCR slaves
-- C_DCR_DWIDTH -- width of DCR data bus
-- C_DCR_AWIDTH -- width of DCR address bus
-- C_USE_LUT_OR -- use LUTs to implement BUS ORs instead
-- -- of carry-chain implementation
--
-- Definition of Ports:
-- -- Master interface
-- M_dcrABus -- master dcr address bus output
-- M_dcrDBus -- master dcr data bus output
-- M_dcrRead -- master dcr read output
-- M_dcrWrite -- master dcr write output
-- DCR_M_DBus -- master dcr data bus input
-- DCR_Ack -- master dcr ack input
--
-- -- Slave interface
-- -- Note: All slave signals are concatenated together to form a
-- -- single bus. A particular slave's connection must be indexed
-- -- into the bus
-- DCR_ABus -- slave address bus input
-- DCR_Sl_DBus -- slave data bus input
-- DCR_Read -- slave dcr read input
-- DCR_Write -- slave dcr write input
-- Sl_dcrDBus -- slave data bus output
-- Sl_dcrAck -- slave dcr ack output
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity dcr_v29 is
generic (
C_DCR_NUM_SLAVES : integer := 4;
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_USE_LUT_OR : integer := 1
);
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
end entity dcr_v29;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of dcr_v29 is
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
-- internal version of DCR_Ack
signal m_dcrack_i : std_logic_vector(0 to 0);
-- dummy signal for NGDBUILD workaround which requires at least one component
-- in the NGC file when C_DCR_NUM_SLAVES=1
signal dummy : std_logic;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- Replaced with direct instantiation 10/5/09
--component or_gate is
-- generic (
-- C_OR_WIDTH : natural range 1 to 32;
-- C_BUS_WIDTH : natural range 1 to 64;
-- C_USE_LUT_OR : boolean := TRUE
-- );
-- port (
-- A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
-- Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
-- );
--end component or_gate;
-- dummy buffer for NGDBUILD workaround
component BUF
port (
O : out std_logic;
I : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- architecture imp
-----------------------------------------------------------------------------
-- Instantiation of Dummy buffer to get through NGDBUILD
-----------------------------------------------------------------------------
DUMMY_BUF_I: BUF
port map (O => dummy,
I => '1'
);
-----------------------------------------------------------------------------
-- Send the Master's Address bus and read/write signals to the slaves
-----------------------------------------------------------------------------
ABUS_RW_GEN: for i in 0 to C_DCR_NUM_SLAVES-1 generate
DCR_Read(i) <= M_dcrRead;
DCR_Write(i) <= M_dcrWrite;
DCR_ABus(i*C_DCR_AWIDTH to i*C_DCR_AWIDTH+C_DCR_AWIDTH-1) <= M_dcrABus;
end generate ABUS_RW_GEN;
-----------------------------------------------------------------------------
-- Daisy chain the DCR Data bus from the Master to Slave 0, then Slave 1, etc.
-- and then back to the Master
-----------------------------------------------------------------------------
DCR_Sl_DBus(0 to C_DCR_DWIDTH-1) <= M_dcrDBus;
DBUS_DCHAIN: for i in 1 to C_DCR_NUM_SLAVES-1 generate
DCR_Sl_DBus(i*C_DCR_DWIDTH to i*C_DCR_DWIDTH+C_DCR_DWIDTH-1)
<= Sl_dcrDBus((i-1)*C_DCR_DWIDTH to (i-1)*C_DCR_DWIDTH+C_DCR_DWIDTH-1);
end generate;
DCR_M_DBus <= Sl_dcrDBus((C_DCR_NUM_SLAVES-1)*C_DCR_DWIDTH to
(C_DCR_NUM_SLAVES-1)*C_DCR_DWIDTH+C_DCR_DWIDTH-1);
-----------------------------------------------------------------------------
-- OR the slave's dcrAck signals to generate the Master's dcrAck input
-----------------------------------------------------------------------------
M_DCRACK_OR_I: entity dcr_v29_v9_00_a.or_gate
generic map ( C_OR_WIDTH => C_DCR_NUM_SLAVES,
C_BUS_WIDTH => 1,
C_USE_LUT_OR => C_USE_LUT_OR /= 0
)
port map (
A => Sl_dcrAck,
Y => m_dcrack_i
);
DCR_Ack <= m_dcrack_i(0);
end imp;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/command_fifo.vhd
|
4
|
28636
|
-------------------------------------------------------------------------------
-- $Id: command_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename:
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
use UNISIM.vcomponents.all;
entity command_fifo is
port (
Clk : in std_logic;
Reset : in std_logic;
NextCommand : in std_logic;
CommandNum : out std_logic_vector(8 downto 0);
Data : out std_logic_vector(15 downto 0);
Address : out std_logic_vector(6 downto 0);
ValidCommand: out std_logic
);
end entity command_fifo;
-- Commands for AC97:
-- WriteAC97Reg(0x0,0x0); // reset registers
-- WriteAC97Reg(0x2,0x808); // master volume (0db gain)
-- WriteAC97Reg(0xa,0x8000); // mute PC beep
-- WriteAC97Reg(0x4,0x808); // headphone vol (aux out)
-- WriteAC97Reg(0x18,0x808); // pcmoutvol (amp out line)
-- WriteAC97Reg(0x1a,0x404); // record source (line in for left and right)
-- WriteAC97Reg(0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
-- WriteAC97Reg(0x20,0x1); // bypass 3d sound
-- 80000000
-- 80020808
-- 800a8000
-- 80040808
-- 80180808
-- 801a0404
-- 801c0008
-- 80200001
-- 80200001801c0008801a04048018080880040808800a80008002080880000000
architecture IMP of command_fifo is
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0a : string;
attribute INIT_0b : string;
attribute INIT_0c : string;
attribute INIT_0d : string;
attribute INIT_0e : string;
attribute INIT_0f : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1a : string;
attribute INIT_1b : string;
attribute INIT_1c : string;
attribute INIT_1d : string;
attribute INIT_1e : string;
attribute INIT_1f : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2a : string;
attribute INIT_2b : string;
attribute INIT_2c : string;
attribute INIT_2d : string;
attribute INIT_2e : string;
attribute INIT_2f : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3a : string;
attribute INIT_3b : string;
attribute INIT_3c : string;
attribute INIT_3d : string;
attribute INIT_3e : string;
attribute INIT_3f : string;
attribute INIT_00 of u1 : label is
"80200001801c0008801a04048018080880040808800a80008002080880000000";
attribute INIT_01 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
component RAMB16_S36
generic (
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
signal xram_di : std_logic_vector(31 downto 0); -- BlockRAM data in (zero)
signal command_addr : unsigned(8 downto 0); -- BlockRAM data in (zero)
signal xram_addr : std_logic_vector(8 downto 0); -- BlockRAM data in (zero)
signal xram_dip : std_logic_vector(3 downto 0); -- BlockRAM data in (zero)
signal xram_dop : std_logic_vector(3 downto 0); -- BlockRAM data out
signal xram_en : std_logic; -- BlockRAM enable (always on)
signal xram_we : std_logic; -- BlockRAM write enable (zero)
signal xram_reset : std_logic; -- BlockRAM reset (zero)
signal xram_do : std_logic_vector(31 downto 0);
begin
-- address (need to define)
block_ram_address_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
command_addr <= (others => '0');
elsif NextCommand = '1' then
command_addr <= command_addr + 1;
end if;
end if;
end process;
-- Define input signals to BlockRam
xram_di <= (others => '0'); -- no data in
xram_dip <= (others => '0'); -- 2-bit data (not used)
xram_en <= '1'; -- always enabled
xram_we <= '0'; -- do not need to write
xram_reset <= '0';
Data <= xram_do(15 downto 0);
Address <= xram_do(22 downto 16);
ValidCommand <= xram_do(31);
-- Instance the BlockRam
u1: RAMB16_S36
--translate_off
-- Note that the these generic map values are used for simulation
-- only. To insure that the simulation matches the actual ram values,
-- make sure that the attributes used above are the same as the
-- generics used below.
generic map (
INIT_00 =>
X"80200001801c0008801a04048018080880040808800a80008002080880000000",
INIT_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f =>
X"0000000000000000000000000000000000000000000000000000000000000000"
)
--translate_on
port map(
di => xram_di,
dip => xram_dip,
addr => xram_addr,
do => xram_do,
dop => xram_dop,
clk => clk,
SSR => xram_reset,
EN => xram_en,
WE => xram_we
);
xram_addr <= CONV_STD_LOGIC_VECTOR(command_addr, command_addr'length);
CommandNum <= xram_addr;
end architecture IMP;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DRSCFIFO288x16WC/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd
|
61
|
90319
|
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yEb1I02GVBeGWcCVe70WVVag0OriQjdMQ1PU1JksEmhlpr/IPU9R9pgxZwnHhSxyGjUhzi8OhbaR
NkbXEf7dL7aWBbwCPEqp9tY182P9NktS73S8iWb3TjOwJbTBGio/qYCF9hx+0dFlAIZ7WdeRkJ0h
RddKyuC17GnR+nsmQ0u4WLIOxpNNtEHwC9LuHmFdIkx61TU1+dJBDEhSTJL8q6rO57QIyBNR+mR8
3OGzzhA0fHEhyRESof6kKJ1Yv4Wx1uUcE6kUW/RW1igEbEOD8KZO3+cT3jURspoi4M/KPFkW8gOH
S/3h7ZRulqTCQLljS6kXQNlFiOj3aFVC4HVWiK1uVdt1SapBpzYxclHy0BkV0IzfdM8SleBNDM/F
2nzxOhdC9mwr9QyKDGRfaS/Z/umejoprjfY=
`protect end_protected
|
gpl-3.0
|
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S36_S144.vhd
|
1
|
7433
|
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S36_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (36 and --
-- 128) made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S36_S144 is
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S36_S144;
architecture BRAM_S36_S144_arch of BRAM_S36_S144 is
component BRAM_S18_S72
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
signal doa1 : std_logic_vector (15 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (15 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (15 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (15 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipa1: std_logic_vector (1 downto 0);
signal dipa2: std_logic_vector (1 downto 0);
signal dopa1: std_logic_vector (1 downto 0);
signal dopa2: std_logic_vector (1 downto 0);
signal dipb1: std_logic_vector (7 downto 0);
signal dipb2: std_logic_vector (7 downto 0);
signal dopb1: std_logic_vector (7 downto 0);
signal dopb2: std_logic_vector (7 downto 0);
begin
dia1(15 downto 0) <= DIA(15 downto 0);
dia2(15 downto 0) <= DIA(31 downto 16);
dipa1(1 downto 0) <= DIPA(1 downto 0);
dipa2(1 downto 0) <= DIPA(3 downto 2);
DOA(15 downto 0) <= doa1;
DOA(31 downto 16) <= doa2;
DOPA(1 downto 0) <= dopa1;
DOPA(3 downto 2) <= dopa2;
dib1(15 downto 0) <= DIB(15 downto 0);
dib2(15 downto 0) <= DIB(31 downto 16);
dib1(31 downto 16) <= DIB(47 downto 32);
dib2(31 downto 16) <= DIB(63 downto 48);
dib1(47 downto 32) <= DIB(79 downto 64);
dib2(47 downto 32) <= DIB(95 downto 80);
dib1(63 downto 48) <= DIB(111 downto 96);
dib2(63 downto 48) <= DIB(127 downto 112);
DOB(15 downto 0) <= dob1(15 downto 0);
DOB(31 downto 16) <= dob2(15 downto 0);
DOB(47 downto 32) <= dob1(31 downto 16);
DOB(63 downto 48) <= dob2(31 downto 16);
DOB(79 downto 64) <= dob1(47 downto 32);
DOB(95 downto 80) <= dob2(47 downto 32);
DOB(111 downto 96) <= dob1(63 downto 48);
DOB(127 downto 112) <= dob2(63 downto 48);
dipb1(1 downto 0) <= DIPB(1 downto 0);
dipb2(1 downto 0) <= DIPB(3 downto 2);
dipb1(3 downto 2) <= DIPB(5 downto 4);
dipb2(3 downto 2) <= DIPB(7 downto 6);
dipb1(5 downto 4) <= DIPB(9 downto 8);
dipb2(5 downto 4) <= DIPB(11 downto 10);
dipb1(7 downto 6) <= DIPB(13 downto 12);
dipb2(7 downto 6) <= DIPB(15 downto 14);
DOPB(1 downto 0) <= dopb1(1 downto 0);
DOPB(3 downto 2) <= dopb2(1 downto 0);
DOPB(5 downto 4) <= dopb1(3 downto 2);
DOPB(7 downto 6) <= dopb2(3 downto 2);
DOPB(9 downto 8) <= dopb1(5 downto 4);
DOPB(11 downto 10) <= dopb2(5 downto 4);
DOPB(13 downto 12) <= dopb1(7 downto 6);
DOPB(15 downto 14) <= dopb2(7 downto 6);
bram1: BRAM_S18_S72
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S18_S72
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S36_S144_arch;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_fifo.vhd
|
4
|
12653
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_fifo.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-- TESTBENCH_ac97_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_fifo.vhd
--
-- Description: Simple testbench for ac97_fifo
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_fifo is
end TESTBENCH_ac97_fifo;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_fifo is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
-- IP Interface
signal Bus2IP_Addr : std_logic_vector(0 to 31);
signal Bus2IP_Clk : std_logic;
signal Bus2IP_CS : std_logic;
signal Bus2IP_Data : std_logic_vector(0 to 31);
signal Bus2IP_BE : std_logic_vector(0 to 3);
signal Bus2IP_RdCE : std_logic;
signal Bus2IP_Reset : std_logic;
signal Bus2IP_WrCE : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal Interrupt : std_logic;
signal Bit_Clk : std_logic;
signal Sync : std_logic;
signal SData_Out : std_logic;
signal SData_In : std_logic;
signal AC97Reset_n : std_logic;
signal test_no : integer;
signal IP_READ : std_logic_vector(0 to 31);
signal sample : integer := 0;
begin -- behavioral
uut_1 : ac97_model
port map (
AC97Reset_n => ac97reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut : ac97_fifo
generic map (
C_INTR_LEVEL => 1,
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
Interrupt => Interrupt,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
clkgen_2: process
begin
Bus2IP_Clk<= '0';
wait for 5 ns;
Bus2IP_Clk<= '1';
wait for 5 ns;
end process;
-- simulate a reset
opb_rst_gen: process
begin
Bus2IP_Reset <= '1';
wait for 20 ns;
Bus2IP_Reset <= '0';
wait;
end process opb_rst_gen;
-- IP bus
IP_proc: process
begin
test_no <= 0;
Bus2IP_RdCE <= '0';
Bus2IP_WrCE <= '0';
Bus2IP_CS <= '0';
Bus2IP_ADDR <= (others => '0');
Bus2IP_DATA <= (others => '0');
IP_READ <= (others => '0');
-- skip some time slots before performing a bus cycle
for i in 100 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
-- Test 7. Reset CODEC
test_no <= 7;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000010", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000000", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Test 1. Wait until codec ready is found (ready status)
test_no <= 1;
while IP_READ(26) /= '1' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
for i in 50 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
end loop;
-- Test #2: Clear FIFO status & read status again
test_no <= 2;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #6: Write data into playback fifo
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 6;
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
-- Test #3: Read AC 97 register
wait until sync'event and sync='1';
test_no <= 3;
-- Write to AC97_CTRL_ADDR (perform a AC97 "read")
-- Address = "41" (lower 7 bits)
-- Read = 1 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_00C1", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- read from the status register until transfer is complete
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Now read the value of the data register returned
read_ip(Bus2IP_Clk, IP2Bus_Data, REG_DATA_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #4: Write AC 97 register
for i in 128 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 4;
write_ip(Bus2IP_Clk, REG_DATA_WRITE_OFFSET, X"0000_8001",
Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Write to AC97_CTRL_ADDR (perform a AC97 "write")
-- Address = "41" (lower 7 bits)
-- Read = 0 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_0041", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Test #5: Read Playback data
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 5;
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #8 - Interrupt
test_no <= 8;
-- Clear FIFO & read status
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Fill FIFO
for i in 512 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
-- Enable interrupts
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, ENABLE_PLAY_INT_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Wait until an interrupt occurs
wait until Interrupt'event and Interrupt = '1';
-- Wait for a few more samples
for i in 3 downto 0 loop
wait until sync'event and sync='1';
end loop;
-- Put some more data into the Fifo and make sure the interrupt goes away
for i in 8 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
wait;
end process;
end behavioral;
|
gpl-3.0
|
luebbers/reconos
|
demos/beat_tracker/hw/src/others/fft_transform.vhd
|
1
|
17668
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- -- --
-- FFT TRANSFORMATION OF 2048 SAMPLES (16 bit wide, signed) --
-- OUTPUT: 2048 FFT VALUES --
-- - real component (16 bit wide) --
-- - imaginary component (16 bit wide) --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity fft_transform is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end fft_transform;
architecture Behavioral of fft_transform is
-- fft component (uses radix-4 algorithm)
component xfft_v5_0
port (
clk : IN std_logic;
ce : IN std_logic;
sclr : IN std_logic;
start : IN std_logic;
xn_re : IN std_logic_vector(15 downto 0);
xn_im : IN std_logic_vector(15 downto 0);
fwd_inv : IN std_logic;
fwd_inv_we : IN std_logic;
scale_sch : IN std_logic_vector(13 downto 0);
scale_sch_we : IN std_logic;
rfd : OUT std_logic;
xn_index : OUT std_logic_vector(6 downto 0);
busy : OUT std_logic;
edone : OUT std_logic;
done : OUT std_logic;
dv : OUT std_logic;
xk_index : OUT std_logic_vector(6 downto 0);
xk_re : OUT std_logic_vector(15 downto 0);
xk_im : OUT std_logic_vector(15 downto 0));
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- signals for fft core
-- incoming signals
signal ce : std_logic := '0';
signal sclr : std_logic := '0';
signal start : std_logic := '0';
signal xn_re : std_logic_vector(15 downto 0) := (others => '0');
signal xn_im : std_logic_vector(15 downto 0) := (others => '0');
signal fwd_inv : std_logic := '1';
signal fwd_inv_we : std_logic := '0';
signal scale_sch : std_logic_vector(13 downto 0) := "01101010101010";
signal scale_sch_we : std_logic := '0';
--outgoing signals
signal rfd : std_logic;
signal xn_index : std_logic_vector(6 downto 0);
signal busy : std_logic;
signal edone : std_logic;
signal done : std_logic;
signal dv : std_logic;
signal xk_index : std_logic_vector(6 downto 0);
signal xk_re : std_logic_vector(15 downto 0);
signal xk_im : std_logic_vector(15 downto 0);
-- states
type t_state is
(
init,
wait_for_message,
wait_for_message_2,
read_input,
read_input_2,
read_input_3,
read_input_4,
read_input_5,
read_input_6,
read_input_dec,
make_fft,
write_output,
write_output_2,
write_output_3,
write_output_4,
write_output_5,
write_output_6,
write_output_dec,
write_output_get,
write_output_wait,
write_output_write,
write_output_write_done,
send_message
);
-- current state
signal state : t_state := init;
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal input_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal output_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_input_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal current_output_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_in : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_out : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal counter : std_logic_vector(0 to 6) := (others => '0');
signal my_xn_index : std_logic_vector(6 downto 0);
signal address : std_logic_vector(0 to C_BURST_AWIDTH-1);
signal local_ram_address_in_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal fft_en : std_logic := '0'; -- handshake signals
signal fft_done : std_logic := '0';
signal o_RAMAddr_fft : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMAddr_fsm : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal o_RAMData_fft : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMData_fsm : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
signal o_RAMWE_fft : std_logic := '0';
signal o_RAMWE_fsm : std_logic := '0';
-- 1st 16 bits: real component, 2nd 16 bits: imaginary component
--type t_ram is array (1023 downto 0) of std_logic_vector(31 downto 0);
--signal fft_ram : t_ram; -- samples memory
begin
-- fft core
my_fft_core : xfft_v5_0
port map (
clk => clk,
ce => ce,
sclr => sclr,
start => start,
xn_re => xn_re,
xn_im => xn_im,
fwd_inv => fwd_inv,
fwd_inv_we => fwd_inv_we,
scale_sch => scale_sch,
scale_sch_we => scale_sch_we,
rfd => rfd,
xn_index => xn_index,
busy => busy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im
);
-- clock for burst ram
o_RAMClk <= clk;
-- switch for o_RAMAddr
o_RAMAddr <= o_RAMAddr_fft(0 to C_BURST_AWIDTH-2) & not o_RAMAddr_fft(C_BURST_AWIDTH-1)
when (fft_en = '1') else o_RAMAddr_fsm(0 to C_BURST_AWIDTH-2) & not o_RAMAddr_fsm(C_BURST_AWIDTH-1);
o_RAMData <= o_RAMData_fft when (fft_en = '1') else o_RAMData_fsm;
o_RAMWE <= o_RAMWE_fft when (fft_en = '1') else o_RAMWE_fsm;
fft_proc : process(clk, reset, fft_en)
variable step : natural range 0 to 9;
begin
if (reset='1' or fft_en='0') then
fft_done <= '0';
start <= '0';
o_RAMWE_fft <= '0';
xn_im <= (others=>'0');
xn_re <= (others=>'0');
ce <= '0';
fwd_inv <= '1';
sclr <= '1';
step := 0;
elsif (rising_edge(clk)) then
case step is
-- fill fft core with data
when 0 => -- set start signal
sclr <= '0';
ce <= '1';
fwd_inv <= '1';
fwd_inv_we <= '1';
o_RAMWE_fft <= '0';
o_RAMAddr_fft <= (others => '0');
address <= (others => '0');
xn_im <= (others=>'0');
step := step + 1;
when 1 => -- set start signal
start <= '1';
fwd_inv_we <= '0';
o_RAMWE_fft <= '0';
--if (rfd = '1') then
my_xn_index <= xn_index;
step := step + 1;
--end if;
when 2 => -- start filling the incoming data pipeline
-- (read left sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 3 => -- start filling the incoming data pipeline
-- (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
my_xn_index <= xn_index + 1;
step := step + 1;
when 4 => -- samples are arriving (read left sample (16 of 32 bits))
start <= '0';
xn_re(15 downto 0) <= i_RAMData(16)&i_RAMData(17)&i_RAMData(18)&i_RAMData(19)&i_RAMData(20)&i_RAMData(21)&i_RAMData(22)&i_RAMData(23)&i_RAMData(24)&i_RAMData(25)&i_RAMData(26)&i_RAMData(27)&i_RAMData(28)&i_RAMData(29)&i_RAMData(30)&i_RAMData(31);
my_xn_index <= xn_index + 1;
o_RAMAddr_fft <= address + 1;
address <= address + 1;
step := step + 1;
when 5 => -- samples are arriving (read right sample (16 of 32 bits));
xn_re(15 downto 0) <= i_RAMData(0)&i_RAMData(1)&i_RAMData(2)&i_RAMData(3)&i_RAMData(4)&i_RAMData(5)&i_RAMData(6)&i_RAMData(7)&i_RAMData(8)&i_RAMData(9)&i_RAMData(10)&i_RAMData(11)&i_RAMData(12)&i_RAMData(13)&i_RAMData(14)&i_RAMData(15);
if (busy='0') then
my_xn_index <= xn_index + 1;
step := step - 1;
else
step := step + 1;
end if;
-- wait for results
when 6 =>
if (edone = '1') then
o_RAMAddr_fft <= address - 1;
address <= address - 1;
start <= '1';
o_RAMWE_fft <= '0';
step := step + 1;
end if;
-- get data and write them back
when 7 =>
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
o_RAMWE_fft <= '1';
if (busy='1') then
step := step + 1;
end if;
when 8 =>
--o_RAMData_fft(0 to 31) <= xk_re(15 downto 0) & xk_im(15 downto 0);
o_RAMData_fft(0 to 31) <= xk_re(15)&xk_re(14)&xk_re(13)&xk_re(12)&xk_re(11)&xk_re(10)&xk_re(9)&xk_re(8)&xk_re(7)&xk_re(6)&xk_re(5)&xk_re(4)&xk_re(3)&xk_re(2)&xk_re(1)&xk_re(0)&xk_im(15)&xk_im(14)&xk_im(13)&xk_im(12)&xk_im(11)&xk_im(10)&xk_im(9)&xk_im(8)&xk_im(7)&xk_im(6)&xk_im(5)&xk_im(4)&xk_im(3)&xk_im(2)&xk_im(1)&xk_im(0);
--o_RAMAddr_fft(0 to 11) <= "0" & xk_index(10 downto 0);
o_RAMAddr_fft(0 to 11) <= "00000"&xk_index(6)&xk_index(5)&xk_index(4)&xk_index(3)&xk_index(2)&xk_index(1)&xk_index(0);
--o_RAMWE_fft <= '1';
if (dv='0') then
o_RAMWE_fft <= '0';
step := step + 1;
else
o_RAMWE_fft <= '1';
end if;
-- finish fft process
when 9 =>
o_RAMWE_fft <= '0';
start <= '0';
sclr <= '1';
fft_done <= '1';
end case;
end if;
end process;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
fsm_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
variable success : boolean;
variable next_state : t_state := wait_for_message;
begin
if (reset = '1') then
reconos_reset( o_osif, i_osif );
state <= init;
o_RAMAddr_fsm <= (others=>'0');
o_RAMWE_fsm <= '0';
next_state := wait_for_message;
done := false;
elsif (rising_edge(clk)) then
reconos_begin( o_osif, i_osif );
if (reconos_ready( i_osif )) then
-- Transition to next state
case (state) is
-- 1. read information struct
when init =>
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
next_state := wait_for_message;
-- 2. wait for messages (input/output addresses) (do a fft)
when wait_for_message =>
reconos_mbox_get_s(done,success,o_osif,i_osif,C_MB_START,input_address);
counter <= (others => '0');
local_ram_address_in <= (others=>'0');
local_ram_address_out <= (others=>'0');
local_ram_address_in_if <= (others=>'0');
next_state := wait_for_message_2;
when wait_for_message_2 =>
reconos_mbox_get_s(done,success,o_osif,i_osif,C_MB_START,output_address);
current_input_address <= input_address;
next_state := read_input;
-- 3. read input samples from input_address (only real components expected)
when read_input =>
--reconos_read_burst(done,o_osif,i_osif,local_ram_address_in,current_input_address);
--next_state := read_input_dec;
next_state := read_input_2;
when read_input_2 =>
reconos_read_s(done,o_osif,i_osif,current_input_address,ram_data);
next_state := read_input_3;
when read_input_3 =>
-- wait
next_state := read_input_4;
when read_input_4 =>
-- wait
next_state := read_input_5;
when read_input_5 =>
-- write value to local ram
o_RAMWE_fsm <= '1';
o_RAMData_fsm <= ram_data;
o_RAMAddr_fsm <= local_ram_address_in_if;
next_state := read_input_6;
when read_input_6 =>
-- wait
o_RAMWE_fsm <= '0';
--local_ram_address_in <= local_ram_address_in + 4;
current_input_address <= current_input_address + 4;
local_ram_address_in_if <= local_ram_address_in_if + 1;
if (counter < 63) then
counter <= counter + 1;
next_state := read_input_2;
else
fft_en <= '1';
next_state := make_fft;
-- TODO: CHANGE CHANGE CHANGE: Remove again
--counter <= (others => '0');
--current_output_address <= output_address;
--next_state := write_output;
end if;
when read_input_dec =>
if (counter < 3) then
counter <= counter + 1;
local_ram_address_in <= local_ram_address_in + 128;
current_input_address <= current_input_address + 128;
next_state := read_input;
else
next_state := make_fft;
fft_en <= '1';
-- CHANGE CHANGE CHANGE - DEBUG
--counter <= (others => '0');
--current_output_address <= output_address;
--next_state := write_output;
end if;
--next_state := read_input_2;
-- 4. make fft for samples
when make_fft =>
if (fft_done = '1') then -- TODO CHANGE CHANGE CHANGE
current_output_address <= output_address;
local_ram_address_if <= (others => '0');
fft_en <= '0';
counter <= (others => '0');
next_state := write_output;
end if;
-- 5. write fft results to output_address
when write_output =>
--reconos_write_burst(done,o_osif,i_osif,local_ram_address_out,current_output_address);
--next_state := write_output_dec;
next_state := write_output_2;
when write_output_dec =>
if (counter < 3) then
counter <= counter + 1;
current_output_address <= current_output_address + 128;
local_ram_address_out <= local_ram_address_out + 128;
next_state := write_output;
else
next_state := send_message;
end if;
--next_state := write_output_2;
when write_output_2 =>
o_RAMAddr_fsm <= (others=>'0');
next_state := write_output_3;
when write_output_3 =>
-- wait
next_state := write_output_4;
when write_output_4 =>
reconos_write(done,o_osif,i_osif,current_output_address, i_RAMData);
next_state := write_output_5;
when write_output_5 =>
-- wait
next_state := write_output_6;
when write_output_6 =>
if (counter < 127) then
o_RAMAddr_fsm <= o_RAMAddr_fsm + 1;
counter <= counter + 1;
current_output_address <= current_output_address + 4;
next_state := write_output_3;
else
next_state := send_message;
end if;
-- 6. send message (work done)
when send_message =>
reconos_mbox_put(done,success,o_osif,i_osif,C_MB_DONE,input_address);
next_state := wait_for_message;
when others =>
next_state := wait_for_message;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
core/pcores/plb_osif_v2_01_a/hdl/vhdl/bus_master.vhd
|
2
|
8968
|
--!
--! \file bus_master.vhd
--!
--! PLB bus master logic for ReconOS OSIF (user_logic)
--!
--! \author Enno Luebbers <[email protected]>
--! \date 07.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 07.08.2006 Enno Luebbers File created
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity bus_master is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_BURST_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_BURSTLEN_WIDTH : integer := 5
);
port (
clk : in std_logic;
reset : in std_logic; -- high active synchronous
-- PLB bus master signals
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- user interface
i_my_addr : in std_logic_vector(0 to C_AWIDTH-1);
i_target_addr : in std_logic_vector(0 to C_AWIDTH-1);
i_read_req : in std_logic; -- single word
i_write_req : in std_logic; -- single word
i_burst_read_req : in std_logic; -- 128x64Bit burst
i_burst_write_req : in std_logic; -- 128x64Bit burst
i_burst_length : in std_logic_vector(0 to 4); -- number of burst beats (n x 64 bits)
o_busy : out std_logic;
o_read_done : out std_logic;
o_write_done : out std_logic
);
end bus_master;
architecture behavioral of bus_master is
-- signals for master control state machine
type plb_master_state_t is (IDLE, READ, WRITE);
signal plb_master_state : plb_master_state_t := IDLE;
signal mst_sm_rd_req : std_logic;
signal mst_sm_wr_req : std_logic;
signal mst_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
begin
-- connect common bus signalling
IP2Bus_Addr <= i_target_addr;
IP2IP_Addr <= mst_ip2ip_addr;
IP2Bus_MstBusLock <= '0'; -- FIXME: no atomic (locked) transactions
IP2Bus_MstRdReq <= mst_sm_rd_req;
IP2Bus_MstWrReq <= mst_sm_wr_req;
-- we are busy, when there are no pending and no running requests.
-- NOTE: incoming requests while non-idle are ignored.
o_busy <= '0' when (
(plb_master_state = IDLE) and
((i_read_req or i_write_req or i_burst_read_req or i_burst_write_req) = '0')
)
else '1';
-------------------------------------------------------------------
-- PLB master state machine
--
-- FIXME: are the mst_sm_*_req signals set right, or does this
-- cause too complicated logic?
-------------------------------------------------------------------
plb_master : process(clk, reset)
begin
if reset = '1' then
plb_master_state <= IDLE;
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
o_read_done <= '0';
o_write_done <= '0';
IP2Bus_MstBE <= "00000000"; -- 0 Bit
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= (others => '0');
elsif rising_edge(clk) then
o_read_done <= '0';
o_write_done <= '0';
case plb_master_state is
when IDLE =>
if i_read_req = '1' then
plb_master_state <= READ;
mst_sm_rd_req <= '1';
-- single
if i_target_addr(29) = '0' then -- align word access
IP2Bus_MstBE <= "11110000"; -- 32 Bit
else
IP2Bus_MstBE <= "00001111"; -- 32 Bit
end if;
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= i_my_addr OR C_SLAVE_BASEADDR;
elsif i_write_req = '1' then
plb_master_state <= WRITE;
mst_sm_wr_req <= '1';
-- single
if i_target_addr(29) = '0' then -- align word access
IP2Bus_MstBE <= "11110000"; -- 32 Bit
else
IP2Bus_MstBE <= "00001111"; -- 32 Bit
end if;
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= i_my_addr OR C_SLAVE_BASEADDR;
elsif i_burst_read_req = '1' then
plb_master_state <= READ;
mst_sm_rd_req <= '1';
-- burst
IP2Bus_MstBE <= "11111111"; -- 64 Bit
IP2Bus_MstBurst <= '1'; -- burst
IP2Bus_MstNum <= "11111"; -- 16x64 Bit burst
-- IP2Bus_MstNum <= i_burst_length; -- n x 64 Bit burst, max 16
mst_ip2ip_addr <= i_my_addr OR C_BURST_BASEADDR;
elsif i_burst_write_req = '1' then
plb_master_state <= WRITE;
mst_sm_wr_req <= '1';
-- burst
IP2Bus_MstBE <= "11111111"; -- 64 Bit
IP2Bus_MstBurst <= '1'; -- burst
mst_ip2ip_addr <= i_my_addr OR C_BURST_BASEADDR;
IP2Bus_MstNum <= "11111"; -- 16x64 Bit burst
-- IP2Bus_MstNum <= i_burst_length; -- n x 64 Bit burst, max 16
end if;
when READ =>
if Bus2IP_MstLastAck = '1' or -- on completion or
Bus2IP_MstTimeout = '1' or -- on timeout or
Bus2IP_MstError = '1' then -- on error
o_read_done <= '1'; -- finish transaction
mst_sm_rd_req <= '0';
plb_master_state <= IDLE;
end if;
when WRITE =>
if Bus2IP_MstLastAck = '1' or -- on completion or
Bus2IP_MstTimeout = '1' or -- on timeout or
Bus2IP_MstError = '1' then -- on error
o_write_done <= '1';
mst_sm_wr_req <= '0'; -- finish transaction
plb_master_state <= IDLE;
end if;
when others =>
plb_master_state <= IDLE;
end case;
end if;
end process;
end behavioral;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/hdl/vhdl/icapCTRL.vhd
|
1
|
17851
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:05 07/20/2006
-- Design Name:
-- Module Name: icapCTRL - icapCTRL_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity icapCTRL is
generic (
C_FAMILY : string := "virtex5";
C_ICAP_DWIDTH : integer:= 32;
C_BURST_SIZE : natural := 16; -- Number of DWords
C_NUM_WIDTH : integer := 5;
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := b"10_0000_0000"; --DCR_BaseAddr
C_DCR_HIGHADDR : std_logic_vector(9 downto 0) := b"00_0000_0011"; --DCR_HighAddr, not used
C_COUNT_ADDR : std_logic_vector(31 downto 0) := X"00000010"
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic_vector(1 downto 0);
M_rdAddr_o : out std_logic_vector(31 downto 0);
M_rdReq_o : out std_logic;
M_rdNum_o : out std_logic_vector(C_NUM_WIDTH - 1 downto 0);
M_rdAccept_i : in std_logic;
M_rdData_i : in std_logic_vector(63 downto 0);
M_rdAck_i : in std_logic;
M_rdComp_i : in std_logic;
M_wrAddr_o : out std_logic_vector(31 downto 0);
M_wrReq_o : out std_logic;
M_wrNum_o : out std_logic_vector(C_NUM_WIDTH - 1 downto 0);
M_wrAccept_i : in std_logic;
M_wrData_o : out std_logic_vector(63 downto 0);
M_wrRdy_i : in std_logic;
M_wrAck_i : in std_logic;
M_wrComp_i : in std_logic;
BUSY : out std_ulogic;
O : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
CE : out std_ulogic;
I : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
WRITE : out std_ulogic;
Fifo_empty_o : out std_logic;
Fifo_full_o : out std_logic;
--- Interrupt
done_int : out std_logic;
--- DCR signals
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
---
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
DCR_ABus_o : out std_logic_vector(9 downto 0);
DCR_Write_o : out std_logic;
DCR_Din_o : out std_logic_vector(31 downto 0);
state_CS : out std_logic_vector(2 downto 0);
burst_counter_CS : out std_logic_vector(2 downto 0)
);
end icapCTRL;
architecture icapCTRL_rtl of icapCTRL is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then
return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
component ICAP_VIRTEX2
port (
BUSY : out std_ulogic;
O : out std_logic_vector(7 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(7 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX4
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX5
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component icapFIFO
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end component;
-- component DCR_control
-- generic(
-- ICAP_DCR_ADDR_L : std_logic_vector(9 downto 0) := b"10_0000_0000";
-- ICAP_DCR_ADDR_H : std_logic_vector(9 downto 0) := b"10_0000_0011"
-- );
-- port(
-- dcr_addr : in std_logic_vector(9 downto 0);
-- dcr_mrd : in std_logic;
-- dcr_mwr : in std_logic;
-- dcr_din : in std_logic_vector(31 downto 0);
-- ---
-- dcr_ack : out std_logic;
-- dcr_dout : out std_logic_vector(31 downto 0);
-- ---
-- start_w : out std_logic;
-- start_r : out std_logic;
-- addr : out std_logic_vector(31 downto 0);
-- ---
-- clk : in std_logic
-- );
-- end component;
type state_type is (IDLE, INIT, ACTIVE, BURSTING, WRITE_COUNT, DONE);
signal state : state_type;
--signal addr : std_logic_vector(14 downto 0);
--signal addr : std_logic_vector(13 downto 0);
signal addr : std_logic_vector(18-(log2(C_BURST_SIZE)) downto 0);
signal addr_tail : std_logic_vector(2+(log2(C_BURST_SIZE)) downto 0);
signal base_addr : std_logic_vector(31 downto 22);
signal base_lngth : std_logic_vector(15 downto 0);
signal icap_busy : std_logic;
signal icap_dout : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din_r : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_en_l : std_logic;
signal icap_rnw : std_logic;
signal fifo_rEn : std_logic;
signal fifo_wEn : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal count : std_logic_vector(31 downto 0);
signal debounce : std_logic_vector(1 downto 0);
signal dcr_reg : std_logic_vector(31 downto 0);
signal dcr_start_w : std_logic;
signal dcr_start_w_n : std_logic;
signal dcr_start_r : std_logic;
signal dcr_addr : std_logic_vector(31 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal done_int_i : std_logic;
signal state_sig : std_logic_vector(2 downto 0);
signal burst_counter : std_logic_vector(2 downto 0); -- range from 0 to 7, MPMC can acknowledge not more than 4 transfers at the same time
begin
-- ICAP_4 : ICAP_VIRTEX5
-- generic map (
-- ICAP_WIDTH => "X32") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- SWAP_BITS: process (icap_din) is
-- begin -- process Swap_bit_Order
-- for byte_i in 0 to 3 loop
-- for bit_i in 0 to 7 loop
-- icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
-- end loop; -- Bit
-- end loop; -- Byte
-- end process SWAP_BITS;
state_CS <= state_sig;
addr_tail <= (others => '0');
-- Make icap signals available to chipscope at output
BUSY <= icap_busy; -- Busy output
O <= icap_dout; -- 8-bit data output
CE <= icap_en_l; -- Clock enable input
I <= icap_din; -- 8-bit data input
WRITE <= icap_rnw; -- Write input
-- dcr interface instantiation
dcr_control: entity work.dcr_if
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR)
port map (
clk => clk,
rst => reset,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrAck => Sl_dcrAck_sig,
Sl_dcrDBus => Sl_dcrDBus,
ctrl_reg => ctrl_reg);
dcr_start_w <= Sl_dcrAck_sig and DCR_Write;
Sl_dcrAck <= Sl_dcrAck_sig;
-- Make DCR signals available to chipscope at output
DCR_ABus_o <= DCR_ABus;
DCR_Write_o <= DCR_Write;
DCR_Din_o <= ctrl_reg;
burst_counter_CS <= burst_counter;
Fifo_empty_o <= fifo_empty;
Fifo_full_o <= fifo_full;
-- -- WARNING!!!
-- -- The ICAP's data signals are reversed!
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
-- if virtex2P or Virtex2 use ICAP_Virtex2 and invert input bits
V2_GEN : if (C_FAMILY = "virtex2p" or C_FAMILY = "virtex2") generate
V2_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_0 : ICAP_VIRTEX2
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
-- WARNING!!!
-- The ICAP's data signals are reversed in V2P!
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V2_GEN_8;
end generate V2_GEN;
V4_GEN : if (C_FAMILY = "virtex4") generate
V4_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_1 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V4_GEN_8;
V4_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_2 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
icap_din_r <= icap_din;
end generate V4_GEN_32;
end generate V4_GEN;
V5_GEN : if (C_FAMILY = "virtex5") generate
V5_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_3 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V5_GEN_8;
V5_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_4 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
SWAP_BITS: process (icap_din) is
begin -- process Swap_bit_Order
for byte_i in 0 to 3 loop
for bit_i in 0 to 7 loop
icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
end loop; -- Bit
end loop; -- Byte
end process SWAP_BITS;
end generate V5_GEN_32;
end generate V5_GEN;
-- fifo_empty is active high. If Fifo is not empty (fifo_empty = '0') rnw and ce gow low!
icap_rnw <= fifo_empty;
icap_en_l <= fifo_empty;
fifo_rEn <= not icap_busy;
fifo_wEn <= M_rdAck_i when(state=BURSTING) else '0';
icapFIFO_0 : icapFIFO
generic map (
C_FIFO_DEPTH => 64,
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => C_ICAP_DWIDTH
)
port map (
clk => clk,
reset => reset,
wEn_i => fifo_wEn,
wData_i => M_rdData_i,
rEn_i => fifo_rEn,
rData_o => icap_din,
full_o => fifo_full,
empty_o => fifo_empty
);
-- process(state, debounce, addr, base_addr) begin
-- M_rdAddr_o <= base_addr & addr & b"0000000";
-- if(state=IDLE) then
-- if(debounce(0)='0') then
-- M_rdAddr_o <= C_CONFIG_ADDR_0;
-- else
-- M_rdAddr_o <= C_CONFIG_ADDR_1;
-- end if;
-- end if;
-- end process;
-- Generate the read address
--M_rdAddr_o <= base_addr & addr & b"0000000";
--M_rdAddr_o <= base_addr & addr & b"00000000";
M_rdAddr_o <= base_addr & addr & addr_tail;
done_int <= done_int_i;
-- delay start signal by one cycle
process(clk) begin
if(clk='1' and clk'event) then
dcr_start_w_n <= dcr_start_w;
end if;
end process;
--By Rehan -- modified to Generics by Florian, 01.07.2009
M_rdNum_o <= CONV_STD_LOGIC_VECTOR(C_BURST_SIZE,C_NUM_WIDTH);
process(state, fifo_full, fifo_empty, addr) begin
-- don't request data
M_rdReq_o <= '0';
M_wrReq_o <= '0';
-- if(state=IDLE) then
-- -- debounce is active low, when one of the switches is pressed debounce goes low.
-- --M_rdReq_o <= not debounce(0) or not debounce(1); -- is one of the switches pressed?
-- M_rdReq_o <= dcr_start_w;
-- M_rdNum_o <= "00001"; -- request one 64 bit word
-- els
--if(state=ACTIVE) then
if ((state=ACTIVE or state=BURSTING) and (addr /= base_lngth)) then
M_rdReq_o <= not fifo_full;
elsif(state=WRITE_COUNT) then
M_wrReq_o <= fifo_empty;
end if;
end process;
M_wrAddr_o <= C_COUNT_ADDR;
M_wrNum_o <= CONV_STD_LOGIC_VECTOR(1,C_NUM_WIDTH);
M_wrData_o(63 downto 32) <= (others=>'0');
M_wrData_o(31 downto 0) <= count;
process(clk) begin
if(clk='1' and clk'event) then
if(state=IDLE) then
count <= (others=>'0');
else
if(fifo_empty='0') then -- if Fifo is not empty increase counter
count <= count+1;
end if;
end if;
end if;
end process;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
state <= IDLE;
addr <= (others=>'0');
base_addr <= (others=>'0');
base_lngth <= (others=>'0');
dcr_reg <= (others => '0');
done_int_i <= '0';
state_sig <= (others=>'0');
burst_counter <= (others=>'0');
else
--collect all M_rdAccepts
if(M_rdAccept_i='1') then
addr <= addr + 1;
burst_counter <= burst_counter+1;
end if;
done_int_i <= '0';
case(state) is
when IDLE =>
state_sig <= "000";
burst_counter <= (others=>'0');
addr <= (others=>'0');
-- initialize base addr and base_lngth with the data from DCR bus once!
base_addr <= ctrl_reg(31 downto 22);
base_lngth <= ctrl_reg(15 downto 0);
if(dcr_start_w_n='1') then
state <= ACTIVE;
end if;
when ACTIVE =>
state_sig <= "001";
if(burst_counter>=1) then
state <= BURSTING;
end if;
when BURSTING =>
state_sig <= "010";
-- 15.07.09 mod. Florian, the burst_counter value is decreased after completion of the current
-- burst which is indicated by the assertion of M_rdComp. This means, that the final burst
-- is completed but the burst_counter value still remains 1 until the next clock cycle occurs.
if(M_rdComp_i='1') then
if(addr=base_lngth and burst_counter=1) then
burst_counter <= burst_counter-1;
state <= WRITE_COUNT;
else
burst_counter <= burst_counter-1;
state <= ACTIVE;
end if;
end if;
when WRITE_COUNT =>
state_sig <= "011";
--if(M_wrAccept_i='1') then
state <= DONE;
--end if;
when DONE =>
state_sig <= "100";
if(fifo_empty = '1' and dcr_start_w_n = '0') then
done_int_i <= '1';
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
end icapCTRL_rtl;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBSCFIFO80x64WC/synth/DPBSCFIFO80x64WC.vhd
|
8
|
38586
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO80x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO80x64WC;
ARCHITECTURE DPBSCFIFO80x64WC_arch OF DPBSCFIFO80x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO80x64WC_arch : ARCHITECTURE IS "DPBSCFIFO80x64WC,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "DPBSCFIFO80x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=80,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=80,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 80,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 80,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO80x64WC_arch;
|
gpl-3.0
|
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/AccelArithmetics.vhd
|
1
|
9819
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:45:49 03/05/2014
-- Design Name:
-- Module Name: AccelArithmetics - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module transforms the incoming acceleration data from the ADXL_Control module into a format
-- that is displayed on the VGA screen:
-- - The incoming ACCEL_X_IN, ACCEL_Y_IN and ACCEL_Z_IN data is on 2g scale (-2g to +2g) represented on
-- 12 bits two's complement
-- - The ACCEL_Y_IN data is inverted, according to the accelerometer layout position on the Nexys4 board
--
-- - Both ACCEL_X_IN and ACCEL_Y_IN are scaled and limited to ACC_X_Y_MIN - ACC_X_Y_MAX (by default 0-511),
-- meaning: -1g: ACC_X_Y_MIN, 0g: (ACC_X_Y_MAX - ACC_X_Y_MIN)/2, 1g: ACC_X_Y_MAX. In this case will be
-- -1g: 0, 0g: 255 and 1g: 511, corresponding to the accelerometer data display on the VGA screen of 512 * 512
-- pixels.
--
-- - The acceleration magnitude is calculated according to the formula SQRT (ACC_X^2 + ACC_Y^2 + ACC_Z^2). For square
-- root calculation, a Logicore Square Root component is used. Due to the scaling purposes on the screen, the result
-- of the square root calculation is also divided by four.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AccelArithmetics is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
ACC_X_Y_MAX : STD_LOGIC_VECTOR (9 downto 0) := "01" & X"FF"; -- 511 pixels, corresponding to +1g
ACC_X_Y_MIN : STD_LOGIC_VECTOR (9 downto 0) := (others => '0') -- corresponding to -1g
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data input signals
ACCEL_X_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z_IN : in STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : in STD_LOGIC;
-- Accelerometer data output signals to be sent to the VGA display
ACCEL_X_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_Y_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_MAG_OUT : out STD_LOGIC_VECTOR (11 downto 0)
);
end AccelArithmetics;
architecture Behavioral of AccelArithmetics is
-- convert ACCEL_X and ACCEL_Y data to unsigned and divide by 4
-- (scaled to 0-1023, with -2g=0, 0g=511, 2g=1023)
-- Then limit to -1g = 0, 0g = 255, 1g = 511
-- Use a Square Root Logicore component to calculate the magnitude
COMPONENT Square_Root
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF Square_Root : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF Square_Root : COMPONENT IS "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
constant SUM_FACTOR : std_logic_vector (12 downto 0) := '0' & X"7FF"; --2047
constant LOWER_ACC_BOUNDARY : std_logic_vector (9 downto 0) := "00" & X"FF"; -- 255
constant UPPER_ACC_BOUNDARY : std_logic_vector (9 downto 0) := "10" & X"FF"; -- 767
-- Invert Y axis data in order to display it on the screen correctly
signal ACCEL_Y_IN_INV : STD_LOGIC_VECTOR (11 downto 0);
signal ACCEL_X_SUM : std_logic_vector (12 downto 0) := (others => '0'); -- one more bit to keep the sign extension
signal ACCEL_Y_SUM : std_logic_vector (12 downto 0) := (others => '0');
signal ACCEL_X_SUM_SHIFTED : std_logic_vector (9 downto 0) := (others => '0'); -- Divide the sum by four
signal ACCEL_Y_SUM_SHIFTED : std_logic_vector (9 downto 0) := (others => '0');
signal ACCEL_X_CLIP : std_logic_vector (9 downto 0) := (others => '0');
signal ACCEL_Y_CLIP : std_logic_vector (9 downto 0) := (others => '0');
-- Calculate magnitude
-- Pipe Data_Ready
signal Data_Ready_0, Data_Ready_1 : std_logic := '0';
signal ACCEL_X_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_Y_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_Z_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_MAG_SQUARE : std_logic_vector (25 downto 0) := (others => '0');
signal ACCEL_MAG_SQRT: std_logic_vector (13 downto 0) := (others => '0');
signal m_axis_dout_tdata: std_logic_vector (15 downto 0);
begin
-- Invert Accel_Y data to display on the screen the box movement
-- on the Y axis according to the board movement
ACCEL_Y_IN_INV <= (NOT ACCEL_Y_IN) + X"001";
-- Add 2047 to the incoming acceleration data
-- Therefore ACCEL_X_SUM and ACCEL_Y_SUM will be scaled to
-- -2g = 0, -1g = 1023, 0g = 2047, 1g = 3071, 2g = 4095
Accel_Sum: process (SYSCLK, RESET, ACCEL_X_IN, ACCEL_Y_IN, Data_Ready)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
ACCEL_X_SUM <= (others => '0');
ACCEL_Y_SUM <= (others => '0');
elsif Data_Ready = '1' then
if ACCEL_X_IN(11) = '1' then -- if negative, keep the sign extension
ACCEL_X_SUM <= ('1' & ACCEL_X_IN) + SUM_FACTOR;
else
ACCEL_X_SUM <= ('0' & ACCEL_X_IN) + SUM_FACTOR;
end if;
if ACCEL_Y_IN_INV(11) = '1' then -- if negative, keep the sign extension
ACCEL_Y_SUM <= ('1' & ACCEL_Y_IN_INV) + SUM_FACTOR;
else
ACCEL_Y_SUM <= ('0' & ACCEL_Y_IN_INV) + SUM_FACTOR;
end if;
end if;
end if;
end process Accel_Sum;
-- Divide by four ACCEL_X_SUM and ACCEL_Y_SUM, therefore will be scaled to
-- -2g = 0, -1g = 255, 0g = 511, 1g = 767, 2g = 1023
ACCEL_X_SUM_SHIFTED <= ACCEL_X_SUM(11 downto 2);
ACCEL_Y_SUM_SHIFTED <= ACCEL_Y_SUM(11 downto 2);
-- Subtract 255 and limit to -1g = 0, 0g = 255, 1g = 511
Accel_Clip: process (SYSCLK, RESET, ACCEL_X_SUM, ACCEL_Y_SUM)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
ACCEL_X_CLIP <= (others => '0');
ACCEL_Y_CLIP <= (others => '0');
else -- If the sum is negative or < 255 (-1g)
if (ACCEL_X_SUM(12) = '1') or (unsigned(ACCEL_X_SUM_SHIFTED) < unsigned(LOWER_ACC_BOUNDARY)) then
ACCEL_X_CLIP <= ACC_X_Y_MIN ; -- Limit to 0
elsif (unsigned(ACCEL_X_SUM_SHIFTED) >= unsigned(UPPER_ACC_BOUNDARY)) then
ACCEL_X_CLIP <= ACC_X_Y_MAX; -- Limit to 511
else
ACCEL_X_CLIP <= ACCEL_X_SUM_SHIFTED - LOWER_ACC_BOUNDARY; -- subtract 255
end if;
-- If the sum is negative or < 255 (-1g)
if (ACCEL_Y_SUM(12) = '1') or (unsigned(ACCEL_Y_SUM_SHIFTED) < unsigned(LOWER_ACC_BOUNDARY)) then
ACCEL_Y_CLIP <= ACC_X_Y_MIN; -- Limit to 0
elsif (unsigned(ACCEL_Y_SUM_SHIFTED) >= unsigned(UPPER_ACC_BOUNDARY)) then
ACCEL_Y_CLIP <= ACC_X_Y_MAX; -- Limit to 511
else
ACCEL_Y_CLIP <= ACCEL_Y_SUM_SHIFTED - LOWER_ACC_BOUNDARY; -- subtract 255
end if;
end if;
end if;
end process Accel_Clip;
-- ACCEL_X_CLIP and ACCEL_Y_CLIP values (0-511) can be represented on 9 bits
ACCEL_X_OUT <= ACCEL_X_CLIP(8 downto 0);
ACCEL_Y_OUT <= ACCEL_Y_CLIP(8 downto 0);
-- Pipe Data_Ready
Pipe_Data_Ready : process (SYSCLK, RESET, Data_Ready, Data_Ready_0)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
Data_Ready_0 <= '0';
Data_Ready_1 <= '0';
else
Data_Ready_0 <= Data_Ready;
Data_Ready_1 <= Data_Ready_0;
end if;
end if;
end process Pipe_Data_Ready;
-- Calculate squares of the incoming acceleration values
Calculate_Square: process (SYSCLK, Data_Ready, ACCEL_X_IN, ACCEL_Y_IN, ACCEL_Z_IN)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if Data_Ready = '1' then
ACCEL_X_SQUARE <= ACCEL_X_IN * ACCEL_X_IN;
ACCEL_Y_SQUARE <= ACCEL_Y_IN * ACCEL_Y_IN;
ACCEL_Z_SQUARE <= ACCEL_Z_IN * ACCEL_Z_IN;
end if;
end if;
end process Calculate_Square;
-- Calculate the sum of the squares to determine the magnitude of the acceleration
Calculate_Square_Sum: process (SYSCLK, Data_Ready_0, ACCEL_X_SQUARE, ACCEL_Y_SQUARE, ACCEL_Z_SQUARE)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if Data_Ready_0 = '1' then
ACCEL_MAG_SQUARE <= ("00" & ACCEL_X_SQUARE) + ("00" & ACCEL_Y_SQUARE) + ("00" & ACCEL_Z_SQUARE);
end if;
end if;
end process Calculate_Square_Sum;
-- Calculate the square root to determine magnitude
Magnitude_Calculation : Square_Root
PORT MAP (
aclk => SYSCLK,
s_axis_cartesian_tvalid => Data_Ready_1,
s_axis_cartesian_tdata => ("000000" & ACCEL_MAG_SQUARE),
m_axis_dout_tvalid => open,
m_axis_dout_tdata => m_axis_dout_tdata
);
ACCEL_MAG_SQRT <= m_axis_dout_tdata (13 downto 0);
-- Also divide the square root by 4
ACCEL_MAG_OUT <= ACCEL_MAG_SQRT(13 downto 2);
end Behavioral;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBDCFIFO36x16DR/synth/DPBDCFIFO36x16DR.vhd
|
8
|
38573
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBDCFIFO36x16DR IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END DPBDCFIFO36x16DR;
ARCHITECTURE DPBDCFIFO36x16DR_arch OF DPBDCFIFO36x16DR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DPBDCFIFO36x16DR_arch : ARCHITECTURE IS "DPBDCFIFO36x16DR,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DPBDCFIFO36x16DR_arch: ARCHITECTURE IS "DPBDCFIFO36x16DR,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=36,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=36,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=3,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 36,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 36,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 3,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBDCFIFO36x16DR_arch;
|
gpl-3.0
|
iti-luebeck/RTeasy2
|
RTeasy/src/vhdltmpl/demux.vhd
|
2
|
2380
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END demux;
ARCHITECTURE recursive OF demux IS
SIGNAL subdemux_0_IN, subdemux_1_IN : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT demux
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
demux1to2: IF select_width=1 GENERATE
OUTPUT(line_width-1 DOWNTO 0) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="0" ELSE (OTHERS => default_out);
OUTPUT(2*line_width-1 DOWNTO line_width) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="1" ELSE (OTHERS => default_out);
END GENERATE;
demux1toN: IF select_width>1 GENERATE
subdemux_0: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_0_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**(select_width-1)*line_width-1 DOWNTO 0));
subdemux_1: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_1_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**select_width*line_width-1
DOWNTO 2**(select_width-1)*line_width));
subdemux_0_IN <= INPUT WHEN SEL(select_width-1)='0'
ELSE (OTHERS => default_out);
subdemux_1_IN <= INPUT WHEN SEL(select_width-1)='1'
ELSE (OTHERS => default_out);
END GENERATE;
END recursive;
|
gpl-3.0
|
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@m@i@p@s_@shifter/_primary.vhd
|
2
|
350
|
library verilog;
use verilog.vl_types.all;
entity MIPS_Shifter is
port(
Data_in : in vl_logic_vector(31 downto 0);
Count : in vl_logic_vector(4 downto 0);
Sel : in vl_logic_vector(1 downto 0);
Data_out : out vl_logic_vector(31 downto 0)
);
end MIPS_Shifter;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/thermal_sensor.vhd
|
1
|
3028
|
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 12:17:11 02/09/2011
-- Design Name:
-- Module Name: thermal_sensor - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex 6 ML605
-- Tool versions: 12.3
-- Description: thermal sensor: ring oscilator that can be used as a temperature sensor.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity thermal_sensor is
generic (C_COUNTER_WIDTH : integer := 18);
port ( -- clock
clk : in std_logic;
-- reset
rst : in std_logic;
-- enable ring oscilator
osc_en : in std_logic;
-- enable recording
rec_en : in std_logic;
-- data
data : out std_logic_vector(C_COUNTER_WIDTH - 1 downto 0);
-- debug output: ring oscillator output
osc_sig : out std_logic;
-- debug output: count signal
count_sig : out std_logic
);
end thermal_sensor;
architecture Behavioral of thermal_sensor is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
component ring_oscillator is
generic ( C_OSC_SIZE : integer := 11);
port ( rst : in std_logic;
osc_en : in std_logic;
osc_out : out std_logic);
end component;
signal osc_out : std_logic;
signal osc_out_old : std_logic;
signal osc_out_old_2 : std_logic;
signal rec_en_old : std_logic;
signal counter : std_logic_vector(C_COUNTER_WIDTH-1 downto 0);
begin
data <= counter;
-- ring oscillator
osc : component ring_oscillator
generic map (C_OSC_SIZE => 11)
port map ( rst => rst, osc_en => osc_en, osc_out => osc_out);
osc_sig <= osc_out;
-- process that counts the ring_oscilator and shift them out
count : process(clk, rst)
begin
if rst = '1' then
-- reset old signals and counter
rec_en_old <= rec_en;
osc_out_old <= osc_out;
osc_out_old_2 <= osc_out;
counter <= (others=>'0');
count_sig <= '0';
--counter <= b"00011100001111";
elsif rising_edge(clk) then
-- store old signals for rec_en and osc_out
rec_en_old <= rec_en;
osc_out_old <= osc_out;
osc_out_old_2 <= osc_out_old;
count_sig <= '0';
--counter <= b"10000000000001";--XXX
-- record a thermal measurement
if rec_en = '1' then
-- if the ring oscillator has a rising edge, increase counter by 1
--counter <= counter + 1;
--counter <= b"10000000000001";
if (osc_out_old='1' and osc_out_old_2='0') then
count_sig <= '1';
counter <= counter + 1;
end if;
-- reset counter if a new record has started
if rec_en_old = '0' then
counter <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/srl_fifo.vhd
|
4
|
7611
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : integer := 8;
C_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
FIFO_Level : out std_logic_vector(0 to 3);
Half_Full : out std_logic;
Half_Empty : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
-- pragma translate_off
Xon : boolean;
-- pragma translate_on
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
signal Addr : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
signal reset_int : std_logic;
begin -- architecture IMP
FIFO_Level <= Addr;
reset_int <= Clear_FIFO or Reset;
buffer_Full <= '1' when (Addr = "1111") else '0';
FIFO_Full <= buffer_Full;
Half_Full <= Addr(3);
Half_Empty <= not Addr(3);
buffer_Empty <= '1' when (Addr = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (reset_int = '1') then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(4) is not used anywhere
Used_MuxCY : if I < 3 generate
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => reset_int); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
end architecture IMP;
|
gpl-3.0
|
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@m@u@x8_1_32/_primary.vhd
|
1
|
723
|
library verilog;
use verilog.vl_types.all;
entity MUX8_1_32 is
port(
Sel : in vl_logic_vector(2 downto 0);
S0 : in vl_logic_vector(31 downto 0);
S1 : in vl_logic_vector(31 downto 0);
S2 : in vl_logic_vector(31 downto 0);
S3 : in vl_logic_vector(31 downto 0);
S4 : in vl_logic_vector(31 downto 0);
S5 : in vl_logic_vector(31 downto 0);
S6 : in vl_logic_vector(31 downto 0);
S7 : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
end MUX8_1_32;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
8
|
24071
|
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
8
|
24071
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16080)
`protect data_block
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|
gpl-3.0
|
luebbers/reconos
|
core/pcores/cpu_hwt_bram_logic_v1_00_a/hdl/vhdl/cpu_hwt_bram_logic.vhd
|
1
|
5620
|
--
-- \file cpu_hwt_bram_logic.vhd
--
-- BRAM control logic for CPU-HW threads
--
-- This BRAM is used to store the CPU reset vectors for switching software
-- threads.
--
-- \author Robert Meiche <[email protected]>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpu_hwt_bram_logic is
generic (
BRAM_DWIDTH : integer := 64;
BRAM_AWIDTH : integer := 32;
CPU_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
--CPU Ports
CPU0_boot_sect_ready : out std_logic;
CPU0_set_boot_sect : in std_logic;
CPU0_boot_sect_data : in std_logic_vector(CPU_DWIDTH-1 downto 0);
CPU1_boot_sect_ready : out std_logic;
CPU1_set_boot_sect : in std_logic;
CPU1_boot_sect_data : in std_logic_vector(CPU_DWIDTH-1 downto 0);
--BRAM Ports
BRAM_Rst : out std_logic;
BRAM_CLK : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to BRAM_DWIDTH/8-1); --Qualified WE
BRAM_Addr : out std_logic_vector(0 to BRAM_AWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to BRAM_DWIDTH-1);
BRAM_Din : in std_logic_vector(0 to BRAM_DWIDTH-1)
);
end cpu_hwt_bram_logic;
architecture synth of cpu_hwt_bram_logic is
signal write_bootcode : std_logic;
signal bram_boot_data : std_logic_vector(0 to CPU_DWIDTH-1);
signal bram_boot_addr : std_logic_vector(0 to BRAM_AWIDTH-1);
signal ready_sigs: std_logic_vector(0 to 1); --connects the ready signals
signal set_sigs: std_logic_vector(0 to 1); --connects the set signals
--------------- state machine states
type SM_TYPE is (IDLE, WRITE, READY, WAIT_UNTIL_SET_ZERO);
signal state : SM_TYPE;
begin
CPU0_boot_sect_ready <= ready_sigs(0);
CPU1_boot_sect_ready <= ready_sigs(1);
set_sigs <= CPU0_set_boot_sect & CPU1_set_boot_sect;
BRAM_Rst <= reset;
BRAM_CLK <= clk;
BRAMWRITE: process(clk)
begin
if rising_edge(clk) then
if write_bootcode = '1' then
BRAM_EN <= '1';
BRAM_WEN <= "00001111";
BRAM_Dout <= X"deadbeef" & bram_boot_data;
BRAM_Addr <= bram_boot_addr;
else
BRAM_EN <= '0';
BRAM_WEN <= "00000000";
BRAM_Dout <= (others =>'0');
BRAM_Addr <= (others =>'0');
end if; --write_bootcode
end if;
end process;
BRAM_LOGIC_SM: process(clk, reset)
variable bootcode : std_logic_vector(CPU_DWIDTH-1 downto 0);
variable whichCPU : integer;
begin
if reset = '1' then
bram_boot_addr <= (others =>'0');
bram_boot_data <= (others =>'0');
write_bootcode <= '0';
state <= IDLE;
elsif rising_edge(clk) then
case state is
when IDLE =>
write_bootcode <= '0';
if CPU0_set_boot_sect = '1' then
bootcode:= CPU0_boot_sect_data;
whichCPU:= 0;
state <= WRITE;
elsif CPU1_set_boot_sect = '1' then
bootcode:= CPU1_boot_sect_data;
whichCPU:= 1;
state <= WRITE;
end if;
when WRITE =>
write_bootcode <= '1';
bram_boot_data <= bootcode;
bram_boot_addr <= X"FFFFFFFC";
state <= READY;
when READY =>
write_bootcode <= '1';
ready_sigs(whichCPU) <= '1';
state <= WAIT_UNTIL_SET_ZERO;
when WAIT_UNTIL_SET_ZERO =>
write_bootcode <= '0';
--after the ready signal for the corresponding CPU is set, the state machine
--waits that the cpu set its set-signal back to zero (then the cpu has booted correctly
-- and another CPU can now have the bootaddress 0xFFFFFFFC)
if set_sigs(whichCPU) = '0' then
ready_sigs(whichCPU) <= '0';
state <= IDLE;
else
ready_sigs(whichCPU) <= '1';
state <= WAIT_UNTIL_SET_ZERO;
end if;
when others =>
state <= IDLE;
end case;
end if;
end process;
end synth;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_proc_sys_reset_0_0/synth/OpenSSD2_proc_sys_reset_0_0.vhd
|
4
|
6692
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_0_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_0_0_arch OF OpenSSD2_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF OpenSSD2_proc_sys_reset_0_0_arch : ARCHITECTURE IS "OpenSSD2_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF OpenSSD2_proc_sys_reset_0_0_arch: ARCHITECTURE IS "OpenSSD2_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_0_0_arch;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DRSCFIFO288x16WC/synth/DRSCFIFO288x16WC.vhd
|
8
|
38594
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DRSCFIFO288x16WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DRSCFIFO288x16WC;
ARCHITECTURE DRSCFIFO288x16WC_arch OF DRSCFIFO288x16WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DRSCFIFO288x16WC_arch : ARCHITECTURE IS "DRSCFIFO288x16WC,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "DRSCFIFO288x16WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=288,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=288,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=14,C_PROG_FULL_THRESH_NEGATE_VAL=13,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 288,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 288,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 14,
C_PROG_FULL_THRESH_NEGATE_VAL => 13,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DRSCFIFO288x16WC_arch;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DRSCFIFO288x16WC/synth/DRSCFIFO288x16WC.vhd
|
8
|
38594
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DRSCFIFO288x16WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DRSCFIFO288x16WC;
ARCHITECTURE DRSCFIFO288x16WC_arch OF DRSCFIFO288x16WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DRSCFIFO288x16WC_arch : ARCHITECTURE IS "DRSCFIFO288x16WC,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "DRSCFIFO288x16WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=288,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=288,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=14,C_PROG_FULL_THRESH_NEGATE_VAL=13,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 288,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 288,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 14,
C_PROG_FULL_THRESH_NEGATE_VAL => 13,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DRSCFIFO288x16WC_arch;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_if.vhd
|
7
|
11332
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
entity ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end entity ac97_if;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of ac97_if is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component ac97_core;
component ac97_command_rom is
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end component ac97_command_rom;
signal pcm_playback_accept_ac97clk : std_logic;
signal pcm_playback_accept_ClkIn_0 : std_logic;
signal pcm_playback_accept_ClkIn_1 : std_logic;
signal pcm_playback_accept_ClkIn : std_logic;
signal pcm_record_valid_ac97clk, pcm_record_valid_ClkIn_0, pcm_record_valid_ClkIn_1 : std_logic;
signal pcm_record_valid_ClkIn : std_logic;
signal command_addr : std_logic_vector(6 downto 0);
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal codec_rdy : std_logic;
signal debug_i : std_logic_vector(3 downto 0);
signal reg_write_strobe_ac97, reg_busy_ac97, reg_error_ac97 : std_logic;
signal get_next_command : std_logic;
signal valid_command : std_logic;
signal command_num : unsigned(3 downto 0) := "0000";
type read_access_states is (AC97_READY, WARM_START,
REVIEW_COMMAND,ISSUE_COMMAND,
WAIT_COMMAND, NEXT_COMMAND,
READ_COMMAND, DONE);
signal command_SM : read_access_states;
signal reset_counter : unsigned(10 downto 0) := (others => '0');
signal AC97Reset_n_i : std_logic := '0';
signal rom_data : std_logic_vector(24 downto 0);
signal command_addr_i : std_logic_Vector(3 downto 0);
signal start_frame_delay : natural range 0 to 3 := 0;
attribute rom_style: string;
--attribute rom_style of ac97_command_rom: entity is "distributed";
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Command loading
-----------------------------------------------------------------------------
load_commands_SM_PROCESS : process (AC97clk) is
begin
if AC97clk'event and AC97clk = '1' then
if Reset = '1' then
command_SM <= AC97_READY;
command_num <= "0000";
else
case command_SM is
-- Issue some reset?
when AC97_READY =>
-- wait until codec is ready
if codec_rdy = '1' then
command_SM <= REVIEW_COMMAND;
start_frame_delay <= 0;
end if;
when WARM_START =>
if pcm_playback_accept_ac97clk = '1' then
if start_frame_delay = 3 then
command_SM <= REVIEW_COMMAND;
else
start_frame_delay <= start_frame_delay + 1;
end if;
end if;
when REVIEW_COMMAND =>
-- if command is valid, go on to issue command. otherwise, go to
-- end state.
if valid_command = '1' then
command_SM <= ISSUE_COMMAND;
else
command_SM <= DONE;
end if;
when ISSUE_COMMAND =>
-- strobe is issued in output forming logic
command_SM <= WAIT_COMMAND;
when WAIT_COMMAND =>
if reg_busy_ac97 = '0' then
command_SM <= NEXT_COMMAND;
end if;
-- error processing?
when NEXT_COMMAND =>
command_SM <= READ_COMMAND;
command_num <= command_num + 1;
when READ_COMMAND =>
command_SM <= REVIEW_COMMAND;
when DONE =>
-- do nothing
when others => NULL;
end case;
end if;
end if;
end process;
reg_write_strobe_ac97 <= '1' when command_SM = ISSUE_COMMAND else
'0';
get_next_command <= '1' when command_SM = NEXT_COMMAND else
'0';
-- ClkIn processes
-- The AC97 reset signal needs to be driven by ClkIn
-- (AC97 clock does not operate when reset asserted)
reset_process : process (ClkIn) is
begin
if Reset = '1' then
reset_counter <= (others => '0');
AC97Reset_n_i <= '0';
elsif ClkIn'event and ClkIn='1' then
if reset_counter(10) = '1' then
AC97Reset_n_i <= '1';
else
reset_counter <= reset_counter+1;
AC97Reset_n_i <= '0';
end if;
end if;
end process;
AC97Reset_n <= AC97Reset_n_i;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_playback_accept_ClkIn_0 <= pcm_playback_accept_ac97clk; -- async
pcm_playback_accept_ClkIn_1 <= pcm_playback_accept_ClkIn_0;
pcm_playback_accept_ClkIn <= pcm_playback_accept_ClkIn_0 and not pcm_playback_accept_ClkIn_1;
end if;
end process;
PCM_Playback_Accept <= pcm_playback_accept_ClkIn;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_record_valid_ClkIn_0 <= pcm_record_valid_ac97clk; -- async
pcm_record_valid_ClkIn_1 <= pcm_record_valid_ClkIn_0;
pcm_record_valid_ClkIn <= pcm_record_valid_ClkIn_0 and not pcm_record_valid_ClkIn_1;
end if;
end process;
PCM_Record_Valid <= pcm_record_valid_ClkIn;
-----------------------------------------------------------------------------
-- Command ROM
-----------------------------------------------------------------------------
ROM : ac97_command_rom
port map (
ClkIn => AC97Clk,
ROMAddr => command_addr_i,
ROMData => rom_data
);
command_addr_i <= CONV_STD_LOGIC_VECTOR(command_num, 4);
write_data <= rom_data(15 downto 0);
command_addr <= rom_data(22 downto 16);
valid_command <= rom_data(24);
-- debug_i(0) <= codec_rdy;
-- debug_i(1) <= '1' when command_SM = DONE else
-- '0';
-- debug_i(2) <= AC97Reset_n_i;
-- debug_i(3) <= reg_error_ac97;
debug_i <= command_addr_i;
debug <= debug_i;
-----------------------------------------------------------------------------
-- Instantiating the core
-----------------------------------------------------------------------------
ac97_core_I : ac97_core
port map (
Reset => Reset,
AC97_Bit_Clk => AC97Clk,
AC97_Sync => Sync,
AC97_SData_Out => SData_Out,
AC97_SData_In => SData_In,
AC97_Reg_Addr => command_addr,
AC97_Reg_Write_Data => write_data,
AC97_Reg_Read_Data => open, -- No reading from AC97
AC97_Reg_Read_Strobe => '0', -- No reading from AC97
AC97_Reg_Write_Strobe => reg_write_strobe_ac97, -- do
AC97_Reg_Busy => reg_busy_ac97, -- do
AC97_Reg_Error => reg_error_ac97, -- do
AC97_Reg_Read_Data_Valid => open, -- No reading from AC97
PCM_Playback_Left => PCM_Playback_Left, -- async
PCM_Playback_Right => PCM_Playback_right, -- async
PCM_Playback_Left_Valid => '1',
PCM_Playback_Right_Valid => '1',
PCM_Playback_Left_Accept => pcm_playback_accept_ac97clk,
PCM_Playback_Right_Accept => open, -- use left_accept
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => pcm_record_valid_ac97clk,
PCM_Record_Right_Valid => open, -- use left_valid
CODEC_RDY => codec_rdy
);
-- leds(3) <= not codec_rdy; -- and (command_SM = DONE);
-- leds(2) <= '0' when command_SM = INIT else '1';
-- leds(1) <= '0';
-- leds(0) <= AC97Clk; -- '0' when command_SM = DONE else '1';
end architecture IMP;
|
gpl-3.0
|
luebbers/reconos
|
demos/beat_tracker/hw/src/framework/importance.vhd
|
1
|
27063
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (initialize, read_particle_address,
read_number_of_particles, read_particle_size, read_block_size,
wait_one_cycle, read_observation_size, needed_bursts, needed_bursts_2,
needed_reads_1, needed_reads_2, read_observation_address,
read_ref_data_address, wait_for_message,
calculate_remaining_observations_1, calculate_remaining_observations_2,
calculate_remaining_observations_3, calculate_remaining_observations_4,
calculate_remaining_observations_5, calculate_remaining_observations_6,
calculate_remaining_observations_7, calculate_remaining_observations_8,
calculate_remaining_observations_9, calculate_remaining_observations_10,
calculate_remaining_observations_11, calculate_remaining_observations_12,
load_observation,
load_burst_decision, load_burst, load_read_decision,
load_read, load_read_wait, write_to_ram, wait_after_write,
wait_after_write_2, wait_after_write_3, load_last_burst,
load_observation_data_decision, load_observation_data_decision_2,
load_observation_data_decision_3, load_observation_data_decision_4,
load_observation_data_decision_5, --load_observation_data_decision_6,
--load_observation_data_decision_7,
likelihood, likelihood_done, write_likelihood,
send_message, send_measurement_1, send_measurement_2
);
-- current state
signal state : t_state := initialize;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal temp5 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer;-- := 5;
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= initialize;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when initialize =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= read_particle_address;
-- CHANGE BACK (2 of 6) !!!
--state <= needed_bursts;
end if;
when read_particle_address =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= read_number_of_particles;
end if;
when read_number_of_particles =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= read_particle_size;
end if;
when read_particle_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= read_block_size;
end if;
when read_block_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= wait_one_cycle;
end if;
when wait_one_cycle =>
--! wait one cycle
state <= read_observation_size;
when read_observation_size =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= needed_bursts;
end if;
when needed_bursts =>
--! calculate needed bursts
--number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= needed_bursts_2;
when needed_bursts_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= needed_reads_1;
when needed_reads_1 =>
--! calculate number of reads (1 of 2)
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= needed_reads_2;
when needed_reads_2 =>
--! calculate number of reads (2 of 2)
--number_of_reads_remember <= number_of_reads_remember / 8;
number_of_reads_remember <= number_of_reads_remember / 4;
state <= read_observation_address;
when read_observation_address =>
--! read observation array address
reconos_read_s (done,o_osif,i_osif,information_struct+20,observation_array_start_address);
if done then
state <= read_ref_data_address;
end if;
-- CHANGE BACK (3 of 6) !!!
--observation_array_start_address <= X"10000000";
--state <= read_ref_data_address;
when read_ref_data_address =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
state <= wait_for_message;
end if;
-- CHANGE BACK (4 of 6) !!!
--reference_data_address <= X"10000040";
--state <= wait_for_message;
when wait_for_message =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
--observation_array_start_address <= X"10000000"; -- TODO: ONLY FOR SIMULATION
--reference_data_address <= X"20000000"; -- TODO: ONLY FOR SIMULATION
--observation_address <= local_ram_start_address_if + 14 + 2; -- TODO: ONLY FOR SIMULATION
--observation_size <= 56; -- TODO: ONLY FOR SIMULATION
--block_size <= 2; -- TODO: ONLY FOR SIMULATION
--number_of_bursts_remember <= 0; -- TODO: ONLY FOR SIMULATION
--number_of_reads_remember <= 14; -- TODO: ONLY FOR SIMULATION
state <= calculate_remaining_observations_1;
--state <= send_message;
end if;
when calculate_remaining_observations_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
temp <= 0;
state <= calculate_remaining_observations_2;
when calculate_remaining_observations_2 =>
--! wait
if (message2 > 0) then
temp <= temp + block_size;
state <= calculate_remaining_observations_3;
else
state <= calculate_remaining_observations_4;
end if;
when calculate_remaining_observations_3 =>
--! calculates particle array address and number of particles to sample
--temp <= message2 * block_size;
message2 <= message2 - 1;
state <= calculate_remaining_observations_2;
when calculate_remaining_observations_4 =>
--! wait
temp5 <= temp;
temp3 <= 0;
state <= calculate_remaining_observations_5;
when calculate_remaining_observations_5 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= calculate_remaining_observations_6;
when calculate_remaining_observations_6 =>
--! wait
state <= calculate_remaining_observations_7;
when calculate_remaining_observations_7 =>
--! calculate offset
--temp3 <= temp * observation_size;
if (temp5 > 0) then
temp3 <= temp3 + observation_size;
state <= calculate_remaining_observations_8;
else
state <= calculate_remaining_observations_9;
end if;
when calculate_remaining_observations_8 =>
--! wait
temp5 <= temp5 - 1;
state <= calculate_remaining_observations_7;
when calculate_remaining_observations_9 =>
--! calculates particle array address and number of particles to sample
remaining_observations <= N - temp;
state <= calculate_remaining_observations_10;
when calculate_remaining_observations_10 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
state <= calculate_remaining_observations_11;
when calculate_remaining_observations_11 =>
--! calculates particle array address and number of particles to sample
observation_array_address <= observation_array_start_address + temp3;
state <= calculate_remaining_observations_12;
when calculate_remaining_observations_12 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= load_observation;
when load_observation =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= load_burst_decision;
when load_burst_decision =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= load_burst;
number_of_bursts <= number_of_bursts - 1;
else
state <= load_read_decision;
end if;
when load_burst =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= load_burst_decision;
end if;
when load_read_decision =>
--! decision if a read into local ram is needed
o_RAMWEImportance <= '0';
if (number_of_reads > 0) then
state <= load_read;
--state <= load_last_burst;
elsif (second_run = '1') then
state <= likelihood;
else
second_run <= '1';
state <= load_observation_data_decision;
end if;
when load_last_burst =>
--! load last burst
-- reconos_read_burst_l(done,o_osif,i_osif,local_ram_address,load_address,number_of_reads);
-- if done then
-- local_ram_address <= local_ram_address + (number_of_reads * 8);
-- load_address <= load_address + (number_of_reads * 8);
-- local_ram_address_if <= local_ram_address_if + (number_of_reads * 2);
-- number_of_reads <= 0;
state <= load_read_decision;
--end if;
when load_read =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
number_of_reads <= number_of_reads - 1;
state <= load_read_wait;
end if;
when load_read_wait =>
--! wait
state <= write_to_ram;
when write_to_ram =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= wait_after_write;
when wait_after_write =>
-- wait
o_RAMWEImportance<= '0';
state <= wait_after_write_2;
when wait_after_write_2 =>
-- wait
state <= wait_after_write_3;
when wait_after_write_3 =>
-- wait
state <= load_read_decision;
when load_observation_data_decision =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= load_observation_data_decision_2;
when load_observation_data_decision_2 =>
--! wait
state <= load_observation_data_decision_3;
when load_observation_data_decision_3 =>
--! decide, if there is another observation to be handled, else post semaphore
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= load_observation_data_decision_4;
when load_observation_data_decision_4 =>
--! wait
state <= load_observation_data_decision_5;
when load_observation_data_decision_5 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= load_burst_decision;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= send_message;
end if;
when likelihood =>
--! start and run likelihood user process
--init <= '0';
--enable <= '1';
observation_loaded <= '1';
state <= likelihood_done;
when likelihood_done =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
--if (finished = '1') then
enable <= '0';
init <= '1';
state <= write_likelihood;
remaining_observations <= remaining_observations - 1;
--end if;
when write_likelihood =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address,
STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= load_observation_data_decision;
end if;
when send_message =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE,
STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= send_measurement_1;
end if;
when send_measurement_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
--time_measurement <= time_stop - time_start;
--state <= send_measurement_2;
--else
state <= wait_for_message;
--end if;
-- when send_measurement_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= wait_for_message;
-- end if;
when others =>
state <= wait_for_message;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
tests/automated/mbox/hw/hwthreads/mbox/hwt_mbox.vhd
|
1
|
2524
|
----------------------------------------------------------------------------------
-- Company:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_mbox is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end hwt_mbox;
architecture Behavioral of hwt_mbox is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
constant C_MBOX_GET : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_PUT : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_GET, STATE_PUT, STATE_INC);
-- do not rely on initial values here, they won't work with
-- partial reconfiguration
signal state : t_state;
signal value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET;
value <= X"00AFFE00";
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MBOX_GET, value);
if done and success then state <= STATE_INC; end if;
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, value);
if done and success then
state <= STATE_GET;
end if;
when STATE_INC =>
value <= value + 1;
state <= STATE_PUT;
when others => state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/framework/observation.vhd
|
1
|
42473
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- CHANGE 1 OF 7
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
constant C_MB_EXIT : std_logic_vector(0 to 31) := X"00000003";
-- states
type state_t is (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
); -- 51 states = 0x00 - 0x32
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21",
X"22",
X"23",
X"24",
X"25",
X"26",
X"27",
X"28",
X"29",
X"2A",
X"2B",
X"2C",
X"2D",
X"2E",
X"2F",
X"30",
X"31",
X"32",
X"33"
);
constant decode : decode_t := (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- := "00010000000000000000000000000000";
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
signal local_ram_cache_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := "00000000000000000001111110000000";
signal local_ram_cache_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := "011111100000";
signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 32;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic; -- := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data needed signal
signal input_data_needed : std_logic := '0';
-- word data enable
signal word_data_en : std_logic := '0';
-- word data address
signal word_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- word address
signal word_address : std_logic_vector(0 to 31) := (others => '0');
-- word_ack
signal word_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, input_data_needed=>input_data_needed,
word_data_en=>word_data_en, word_address=>word_address,
word_data=>word_data, word_data_ack=>word_data_ack,
init=>init, enable=>enable, finished=>finished);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- 1) read data from information struct
--
-- 2) receive message m
--
-- 3) set current address for input data
--
-- 4) load current particle (into local ram, starting address (others=>'0'))
--
-- 5) start user process for observation extraction
--
-- 6) wait for finished signal of user process
--
-- 7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- 8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- 9) send message m
--
-- 9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"0B0B0B0B");
resume_state_enc := (others => '0');
done := false;
success := false;
preempted := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
-- unpreempted
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
local_ram_cache_address <= "00000000000000000001111110000000";
local_ram_cache_address_if <= "011111100000";
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
parameter_loaded <= '0';
-- CHANGE CHANGE CHANGE
state <= STATE_READ_PARTICLE_ADDRESS;
--state <= STATE_WAIT_FOR_MESSAGE;
-- END OF CHANGE CHANGE CHANGE
-- CHANGE 2 OF 7
--state <= STATE_NEEDED_BURSTS;
-- END CHANGE
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
state <= STATE_LENGTH_LAST_BURST;
when STATE_LENGTH_LAST_BURST =>
--! calculate number of reads (1 of 2)
length_of_last_burst <= observation_size mod 128;
state <= STATE_LENGTH_LAST_BURST_2;
when STATE_LENGTH_LAST_BURST_2 =>
--! calculate number of reads (2 of 2)
length_of_last_burst <= length_of_last_burst / 8;
state <= STATE_READ_OBSERVATION_ARRAY_ADDRESS;
-- CHANGE 3 OF 7
--state <= STATE_WAIT_FOR_MESSAGE;
-- END CHANGE
when STATE_READ_OBSERVATION_ARRAY_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_INPUT_DATA_LINK_ADDRESS;
end if;
when STATE_READ_INPUT_DATA_LINK_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
--state <= STATE_WAIT_FOR_MESSAGE;
state <= STATE_READ_PARAMETER_SIZE;
end if;
when STATE_READ_PARAMETER_SIZE =>
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= STATE_COPY_PARAMETER;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_PARAMETER =>
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
state <= STATE_COPY_PARAMETER_ACK;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when STATE_COPY_PARAMETER_2 =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= STATE_COPY_PARAMETER;
when STATE_COPY_PARAMETER_ACK =>
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
if preempted then
preempted := false;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done then
if success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
parameter_loaded <= '0';
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
else
state <= STATE_EXIT;
end if;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
temp <= 0;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
--temp <= message2 * block_size; -- timing error for virtex 4 ("18 setup errors")
if (message2 > 0) then
temp <= temp + block_size;
message2 <= message2 - 1;
else
-- temp = (message-1) * block_size
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_6;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_6 =>
--! calculates particle array address and number of particles to sample
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_7;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_7 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_8;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_8 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_9;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_9 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= STATE_READ_INPUT_DATA_ADDRESS;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_INPUT_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
state <= STATE_READ_NEXT_PARTICLE;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= STATE_READ_NEXT_PARTICLE;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_NEXT_PARTICLE =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
-- CHANGE CHANGE CHANGE
reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, particle_array_address);
if done then
particle_array_address <= particle_array_address + particle_size;
-- CHANGE CHANGE CHANGE
state <= STATE_START_EXTRACT_OBSERVATION;
--state <= STATE_WRITE_OBSERVATION;
-- END OF CHANGE CHANGE CHANGE
end if;
-- END OF CHANGE CHANGE CHANGE
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_START_EXTRACT_OBSERVATION =>
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= STATE_START_EXTRACT_OBSERVATION_WAIT;
when STATE_START_EXTRACT_OBSERVATION_WAIT =>
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_EXTRACT_OBSERVATION =>
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= STATE_WRITE_OBSERVATION;
elsif input_data_needed = '1' then
state <= STATE_GET_INPUT_DATA;
end if;
when STATE_GET_INPUT_DATA =>
--! get input data at word_address (and write it into word_data)
enable <= '0';
cache_offset <= 0;
if (cache_min <= word_address) and (word_address < cache_max) then
-- cache hit
state <= STATE_CACHE_HIT;
--current_address <= cache_min;
current_address <= word_address - cache_min;
else
-- cache miss
state <= STATE_CACHE_MISS;
end if;
when STATE_CACHE_HIT =>
--! calculate the correct position in the local ram
cache_offset <= TO_INTEGER(UNSIGNED(current_address)) / 4;
state <= STATE_LOAD_WORD;
when STATE_CACHE_MISS =>
--! check if word address is double aligned
if (word_address(29) = '0') then
-- word address is double-word aligned (needed for read bursts)
cache_min <= word_address;
cache_max <= word_address + 128;
cache_offset <= 0;
else
-- word address is NOT double-word aligned => cache_min has to be adjusted
cache_min <= word_address - 4;
cache_max <= word_address + 124;
cache_offset <= 1;
end if;
state <= STATE_CACHE_MISS_2;
when STATE_CACHE_MISS_2 =>
--! reads 128 byte input burst into local ram cache
reconos_read_burst(done, o_osif, i_osif, local_ram_cache_address, cache_min);
if done then
state <= STATE_LOAD_WORD;
end if;
when STATE_LOAD_WORD =>
--! load word data
o_RAMAddrObservation <= local_ram_cache_address_if + cache_offset;
state <= STATE_LOAD_WORD_2;
when STATE_LOAD_WORD_2 =>
--! load word data (wait one cycle)
-- state <= STATE_LOAD_WORD_3;
--
--
-- when STATE_LOAD_WORD_3 =>
-- --! load word data (get word)
-- word_data <= i_RAMData;
state <= STATE_WRITE_WORD_BACK;
when STATE_WRITE_WORD_BACK =>
--! activate user process and transfer the word
enable <= '1';
word_data_en <= '1';
word_data <= i_RAMData;
state <= STATE_WRITE_WORD_ACK;
when STATE_WRITE_WORD_ACK =>
--! wait for acknowledgement
if word_data_ack = '1' then
word_data_en <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WRITE_OBSERVATION =>
--! write observation (init)
number_of_bursts <= number_of_bursts_remember;
local_ram_address <= local_ram_start_address;
--write_histo_en <= '1';
state <= STATE_WRITE_OBSERVATION_2;
when STATE_WRITE_OBSERVATION_2 =>
--! write observation (check burst number)
if number_of_bursts > 0 then
-- more full bursts needed
state <= STATE_WRITE_OBSERVATION_3;
number_of_bursts <= number_of_bursts - 1;
elsif length_of_last_burst > 0 then
-- last burst needed (not full)
temp4 <= length_of_last_burst * 8;
state <= STATE_WRITE_OBSERVATION_4;
else
-- no last burst needed (which is not full)
state <= STATE_MORE_PARTICLES;
end if;
when STATE_WRITE_OBSERVATION_3 =>
--! write observation (write bursts)
reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
if done then
observation_array_address <= observation_array_address + 128;
local_ram_address <= local_ram_address + 128;
state <= STATE_WRITE_OBSERVATION_2;
end if;
when STATE_WRITE_OBSERVATION_4 =>
--! write observation (write last burst)
reconos_write_burst_l(done, o_osif, i_osif, local_ram_address, observation_array_address, length_of_last_burst);
if done then
state <= STATE_MORE_PARTICLES;
observation_array_address <= observation_array_address + temp4;
local_ram_address <= local_ram_address + temp4;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_MORE_PARTICLES =>
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= STATE_MORE_PARTICLES_2;
when STATE_MORE_PARTICLES_2 =>
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= STATE_READ_NEXT_PARTICLE;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
state <= STATE_SEND_MEASUREMENT_1;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
reconos_mbox_tryget(done, success, o_osif, i_osif, C_MB_EXIT, message_var);
if done then
if success then
state <= STATE_EXIT;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
--reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
--if (done and success) then
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_0_0/src/c_sub/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
8
|
86039
|
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`protect end_protected
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_pr/pcores/dcr_v29_v9_00_a/hdl/vhdl/or_gate.vhd
|
7
|
9289
|
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 10-05-09 Removed reference to proc_common_v1_00_b and pulled
-- or_gate and or_muxcy into dcr library.
-- Updated copyright header
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Replaced with direct instantiation 10/5/09
--component or_muxcy
-- generic (
-- C_NUM_BITS : integer := 8
-- );
-- port (
-- In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
-- Or_out : out std_logic
-- );
--end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity dcr_v29_v9_00_a.or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/DRSCFIFO288x16WC/sim/DRSCFIFO288x16WC.vhd
|
6
|
33467
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DRSCFIFO288x16WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DRSCFIFO288x16WC;
ARCHITECTURE DRSCFIFO288x16WC_arch OF DRSCFIFO288x16WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 288,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 288,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 14,
C_PROG_FULL_THRESH_NEGATE_VAL => 13,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DRSCFIFO288x16WC_arch;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/DRSCFIFO288x16WC/sim/DRSCFIFO288x16WC.vhd
|
6
|
33467
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DRSCFIFO288x16WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DRSCFIFO288x16WC;
ARCHITECTURE DRSCFIFO288x16WC_arch OF DRSCFIFO288x16WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DRSCFIFO288x16WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(287 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(287 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 288,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 288,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 14,
C_PROG_FULL_THRESH_NEGATE_VAL => 13,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DRSCFIFO288x16WC_arch;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.2/ml605/ml605_light/pcores/plbv46_dcr_bridge_v9_00_a/hdl/vhdl/plbv46_dcr_bridge.vhd
|
7
|
24559
|
-------------------------------------------------------------------------------
-- plbv46_dcr_bridge - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2004, 2005, 2006, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: plbv46_dcr_bridge.vhd
-- Version: v1.01.a
-- Description: Top level of plbv46_dcr Bridge core
-- Instantiates plbv46_dcr_bridge_core and plbv46_slave_single v1.01.a
-- as Component and interfacing
--
-------------------------------------------------------------------------------
-- Structure:
-- plbv46_dcr_bridge.vhd
-- -- plbv46_dcr_bridge_core.vhd
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Author : SK
-- History :
-- ~~~~~~
-- SK 2006/09/19 -- Initial version.
-- ^^^^^^
-- ~~~~~~
-- SK 2008/12/15 -- Updated version v1_01_a, based upon v1_00_a core.
-- -- updated proc_common_v3_00_a and plbv46_slave_
-- -- single_v1_01_a core libraries.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Short Description of the plbv46_dcr_bridge.vhd code.
-- This file includes the interfacing of plbv46_dcr_bridge.vhd and
-- plbv46_single_slave_v1_00_a signals.
-------------------------------------------------------------------------------
-- Generic & Port Declarations
-------------------------------------------------------------------------------
------------------------------------------
-- == Definition of Generics ==
------------------------------------------
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_SPLB_AWIDTH -- PLBv46 address bus width
-- C_SPLB_DWIDTH -- PLBv46 data bus width
-- C_FAMILY -- Default family
-- C_SPLB_P2P -- Selects point-to-point or shared plb topology
-- C_SPLB_MID_WIDTH -- PLB Master ID Bus Width
-- C_SPLB_NUM_MASTERS -- Number of PLB Masters
-- C_SPLB_NATIVE_DWIDTH -- Width of the slave data bus
-- C_SPLB_SUPPORT_BURSTS -- Burst support
-- Definition of Ports:
-- ==
------------------------------------------
-- PLB_ABus -- Each master is required to provide a valid 32-bit
-- -- address when its request signal is asserted. The PLB
-- -- will then arbitrate the requests and allow the highest
-- -- priority masters address to be gated onto the PLB_ABus
-- PLB_PAValid -- This signal is asserted by the PLB arbiter in response
-- -- to the assertion of Mn_request and to indicate
-- -- that there is a valid primary address and transfer
-- -- qualifiers on the PLB outputs
-- PLB_masterID -- These signals indicate to the slaves the identification
-- -- of the master of the current transfer
-- PLB_RNW -- This signal is driven by the master and is used to
-- -- indicate whether the request is for a read or a write
-- -- transfer
-- PLB_BE -- These signals are driven by the master. For a non-line
-- -- and non-burst transfer they identify which
-- -- bytes of the target being addressed are to be read
-- -- from or written to. Each bit corresponds to a byte
-- -- lane on the read or write data bus
-- PLB_size -- The PLB_size(0:3) signals are driven by the master
-- -- to indicate the size of the requested transfer.
-- PLB_type -- The Mn_type signals are driven by the master and are
-- -- used to indicate to the slave, via the PLB_type
-- -- signals, the type of transfer being requested
-- PLB_wrDBus -- This data bus is used to transfer data between a
-- -- master and a slave during a PLB write transfer
------------------------------------------
-- == SLAVE DCR BRIDGE RESPONSE SIGNALS ==
------------------------------------------
-- Sl_addrAck -- This signal is asserted to indicate that the
-- -- slave has acknowledged the address and will
-- -- latch the address
-- Sl_SSize -- The Sl_SSize(0:1) signals are outputs of all
-- -- non 32-bit PLB slaves. These signals are
-- -- activated by the slave with the assertion of
-- -- PLB_PAValid or SAValid and a valid slave
-- -- address decode and must remain negated at
-- -- all other times.
-- Sl_wait -- This signal is asserted to indicate that the
-- -- slave has recognized the PLB address as a valid address
-- Sl_rearbitrate -- This signal is asserted to indicate that the
-- -- slave is unable to perform the currently
-- -- requested transfer and require the PLB arbiter
-- -- to re-arbitrate the bus
-- Sl_wrDAck -- This signal is driven by the slave for a write
-- -- transfer to indicate that the data currently on the
-- -- PLB_wrDBus bus is no longer required by the slave
-- -- i.e. data is latched
-- Sl_wrComp -- This signal is asserted by the slave to
-- -- indicate the end of the current write transfer.
-- Sl_rdDBus -- Slave read bus
-- Sl_rdDAck -- This signal is driven by the slave to indicate
-- -- that the data on the Sl_rdDBus bus is valid and
-- -- must be latched at the end of the current clock cycle
-- Sl_rdComp -- This signal is driven by the slave and is used
-- -- to indicate to the PLB arbiter that the read
-- -- transfer is either complete, or will be complete
-- -- by the end of the next clock cycle
-- Sl_MBusy -- These signals are driven by the slave and
-- -- are used to indicate that the slave is either
-- -- busy performing a read or a write transfer, or
-- -- has a read or write transfer pending
-- Sl_MWrErr -- These signals are driven by the slave and
-- -- are used to indicate that the slave has encountered an
-- -- error during a write transfer that was initiated
-- -- by this master
-- Sl_MRdErr -- These signals are driven by the slave and are
-- -- used to indicate that the slave has encountered an
-- -- error during a read transfer that was initiated
-- -- by this master
------------------------------------------
-- == SIGNALS FROM PLBV46DCR_CORE TO THE DCR SLAVE DEVICE -- ==
------------------------------------------
-- DCR_plbAck -- DCR Slave ACK in
-- DCR_plbDBusIn -- DCR to PLB data bus in
-- PLB_dcrRead -- PLB to DCR read out to slave
-- PLB_dcrWrite -- PLB to DCR write out to slave
-- PLB_dcrABus -- PLB to DCR address bus out to slave
-- PLB_dcrDBusOut -- PLB to DCR data bus out to slave
-- PLB_dcrClk -- DCR clock for the slave devices
-- PLB_dcrRst -- DCR reset for the slave devices
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.ipif_pkg.SLV64_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.calc_num_ce;
library plbv46_slave_single_v1_01_a;
library plbv46_dcr_bridge_v9_00_a;
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity plbv46_dcr_bridge is
generic (
C_FAMILY : STRING := "virtex5";
C_BASEADDR : STD_LOGIC_VECTOR := X"FFFFFFFF";
C_HIGHADDR : STD_LOGIC_VECTOR := X"00000000";
-- PLBv46 slave single block generics
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 32;
C_SPLB_P2P : integer range 0 to 1 := 0;
C_SPLB_MID_WIDTH : integer range 0 to 4 := 1;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 1;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_SUPPORT_BURSTS : integer range 0 to 1 := 0
);
port (
--PLBv46 SLAVE SINGLE INTERFACE
-- system signals
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
-- Bus slave signals
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
--slave DCR Bridge response signals
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Unused Bus slave signals
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
-- Unused Slave Response Signals
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- signals from plbv46_dcr_core to DCR slaves
DCR_plbAck : in STD_LOGIC;
DCR_plbDBusIn : in STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrRead : out STD_LOGIC;
PLB_dcrWrite : out STD_LOGIC;
PLB_dcrABus : out STD_LOGIC_VECTOR(0 to 9);
PLB_dcrDBusOut : out STD_LOGIC_VECTOR(0 to C_SPLB_NATIVE_DWIDTH-1);
PLB_dcrClk : out STD_LOGIC;
PLB_dcrRst : out STD_LOGIC
);
--fan-out attributes for XST
--fan-out attributes for MPD
-----------------------------------------------------------------------------
ATTRIBUTE CORE_STATE : string;
ATTRIBUTE CORE_STATE of plbv46_dcr_bridge : entity is "ACTIVE";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of plbv46_dcr_bridge : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of plbv46_dcr_bridge : entity is "BRIDGE";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of plbv46_dcr_bridge : entity is "HDL";
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of SPLB_Clk : signal is "10000";
ATTRIBUTE MAX_FANOUT of SPLB_Rst : signal is "10000";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of SPLB_Clk : signal is "Clk";
ATTRIBUTE SIGIS of SPLB_Rst : signal is "Rst";
ATTRIBUTE SIGIS of PLB_dcrClk : signal is "Clk";
ATTRIBUTE SIGVAL : string;
ATTRIBUTE SIGVAL of DCR_plbAck : signal is "DCR_Ack";
ATTRIBUTE SIGVAL of DCR_plbDBusIn : signal is "DCR_M_DBus";
ATTRIBUTE SIGVAL of PLB_dcrRead : signal is "M_dcrRead";
ATTRIBUTE SIGVAL of PLB_dcrWrite : signal is "M_dcrWrite";
ATTRIBUTE SIGVAL of PLB_dcrABus : signal is "M_dcrABus";
ATTRIBUTE SIGVAL of PLB_dcrDBusOut : signal is "M_dcrDBus";
ATTRIBUTE BUSIF : string;
ATTRIBUTE BUSIF of SPLB_Clk : signal is "SPLB";
ATTRIBUTE BUSIF of DCR_plbAck : signal is "MDCR";
ATTRIBUTE BUSIF of DCR_plbDBusIn : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrRead : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrWrite : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrABus : signal is "MDCR";
ATTRIBUTE BUSIF of PLB_dcrDBusOut : signal is "MDCR";
ATTRIBUTE BRIDGE_TO : string;
ATTRIBUTE BRIDGE_TO of C_BASEADDR : constant is "MDCR";
-----------------------------------------------------------------------------
end entity plbv46_dcr_bridge;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture implementation of plbv46_dcr_bridge is
-------------------------------------------------------------------------------
-- Constant Declarations
constant ZERO_PADS : std_logic_vector(0 to 31) := X"00000000";
-- Decoder address range definition constants starts
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_PADS & C_BASEADDR,
ZERO_PADS & C_HIGHADDR
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1
);
-- Decoder address range definition constants ends
-------------------------------------------------------------------------------
-- local signal declaration goes here
--bus2ip signals
signal bus2IP_Clk : std_logic;
signal bus2IP_Reset : std_logic;
signal bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1 );
signal bus2IP_BE : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 - 1 );
signal bus2IP_CS : std_logic_vector(0 to (ARD_ADDR_RANGE_ARRAY'LENGTH/2)-1);
signal bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal bus2IP_RNW : std_logic;
-- ip2bus signals
signal ip2Bus_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH - 1 );
signal ip2Bus_WrAck : std_logic;
signal ip2Bus_RdAck : std_logic;
signal ip2Bus_Error : std_logic;
-- end of local signal declaration
begin -- architecture implementation
----------------------------------
-- INSTANTIATE PLBv46 SLAVE SINGLE
----------------------------------
PLBv46_IPIF_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_BUS2CORE_CLK_RATIO => 1,
C_INCLUDE_DPHASE_TIMER => 1,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- System signals ---------------------------------------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
-- Bus Slave signals ------------------------------------------------
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
-- Slave Response Signals -------------------------------------------
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
-- IP Interconnect (IPIC) port signals ------------------------------
IP2Bus_Data => ip2Bus_Data,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_Error => ip2Bus_Error,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_RNW => bus2IP_RNW,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS,
Bus2IP_RdCE => bus2IP_RdCE,
Bus2IP_WrCE => bus2IP_WrCE,
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset
);
-- component plbv46_dcr_bridge_core interface starts here
plbv46_dcr_bridge_core_1 : entity plbv46_dcr_bridge_v9_00_a.plbv46_dcr_bridge_core
port map (
-- IP Interconnect (IPIC) port signals ----
Bus2IP_Clk => bus2IP_Clk,
Bus2IP_Reset => bus2IP_Reset,
Bus2IP_Addr => bus2IP_Addr,
Bus2IP_Data => bus2IP_Data,
Bus2IP_BE => bus2IP_BE,
Bus2IP_CS => bus2IP_CS(0),
Bus2IP_RdCE => bus2IP_RdCE(0),
Bus2IP_WrCE => bus2IP_WrCE(0),
IP2Bus_RdAck => ip2Bus_RdAck,
IP2Bus_WrAck => ip2Bus_WrAck,
IP2Bus_Error => ip2Bus_Error,
IP2Bus_Data => ip2Bus_Data,
-- signals from plbv46dcr_core --
DCR_plbDBusIn => DCR_plbDBusIn,
DCR_plbAck => DCR_plbAck,
PLB_dcrABus => PLB_dcrABus,
PLB_dcrDBusOut => PLB_dcrDBusOut,
PLB_dcrRead => PLB_dcrRead,
PLB_dcrWrite => PLB_dcrWrite,
PLB_dcrRst => PLB_dcrRst,
PLB_dcrClk => PLB_dcrClk
);
-- component interfacing ends here.
end architecture implementation;
|
gpl-3.0
|
luebbers/reconos
|
support/threads/dummy_ul.vhd
|
1
|
2810
|
--
-- \file dummy_ul.vhd
--
-- Dummy hardware thread
--
-- Does not do ANYTHING. What a life.
--
-- \author Enno Luebbers <[email protected]>
-- \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dummy_ul is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end dummy_ul;
architecture Behavioral of dummy_ul is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
type t_state is ( STATE_WAIT );
signal state : t_state := STATE_WAIT;
begin
state_proc: process( clk, reset )
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_WAIT;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_WAIT =>
-- wiggle pins to prevent being optimized away
o_RAMData <= not i_RAMData;
when others =>
state <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
makestuff/vhdl
|
analyzer/sevenseg.vhdl
|
1
|
2577
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sevenseg is
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
segs_out : out std_logic_vector(6 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end sevenseg;
architecture behavioural of sevenseg is
-- Refresh rate 50M/2^18 ~ 190Hz
-- Refresh rate 8M/2^16 ~ 122Hz
constant COUNTER_WIDTH : natural := 18;
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anode_select : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
begin
count_next <= count + 1;
anode_select <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Update counter, drive anodes_out and select bits to display for each 7-seg
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
case anode_select is
when "00" =>
anodes_out <= "0111";
nibble <= data_in(15 downto 12);
when "01" =>
anodes_out <= "1011";
nibble <= data_in(11 downto 8);
when "10" =>
anodes_out <= "1101";
nibble <= data_in(7 downto 4);
when others =>
anodes_out <= "1110";
nibble <= data_in(3 downto 0);
end case;
end if;
end process;
-- Decode selected nibble
with nibble select
segs_out <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end behavioural;
|
gpl-3.0
|
makestuff/vhdl
|
dpimext/topLevel.vhd
|
1
|
5845
|
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic;
led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0)
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
led <= iThisR3;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
sw when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBSCFIFO64x64WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBDCFIFO64x16DR/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DPBSCFIFO80x64WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_0_0/src/SDPRAM_9A16x9B16/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/c92452ce/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/src/DCDPRAM16x1280WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
85
|
19921
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j
VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv
I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9
yfNP8OseoF3PEoH5
`protect end_protected
|
gpl-3.0
|
luebbers/reconos
|
core/pcores/plb_osif_v2_01_a/hdl/vhdl/mem_plb34.vhd
|
1
|
13813
|
--!
--! \file mem_plb34.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_01_a;
use plb_osif_v2_01_a.all;
entity mem_plb34 is
generic
(
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_BURST_BASEADDR : std_logic_vector := X"00004000"; -- system memory base address for burst ram access
C_BURSTLEN_WIDTH : integer := 5
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to C_BURSTLEN_WIDTH-1); -- number of burst beats (n x 64 bits)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH - 1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_DataX : in std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_DataX : out std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity mem_plb34;
architecture arch of mem_plb34 is
---------
-- read/write acknowledge
---------
signal ram_IP2Bus_RdAck : std_logic;
signal ram_IP2Bus_WrAck : std_logic;
signal slv_IP2Bus_RdAck : std_logic;
signal slv_IP2Bus_WrAck : std_logic;
signal slv_rddata : std_logic_vector(0 to C_DWIDTH-1);
begin
-----------------------------------------------------------------------
-- bus_master_inst: bus master instantiation
--
-- The bus_master module is responsible for initiating a bus read or
-- write transaction through the IPIF master services. The actual
-- transaction will appear like a bus initiated slave request at the
-- IPIF slave attachment and is therefore handled by bus_slave_regs
-- or the bus2burst process.
-----------------------------------------------------------------------
bus_master_inst : entity plb_osif_v2_01_a.bus_master
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_SLAVE_BASEADDR => C_SLAVE_BASEADDR,
C_BURST_BASEADDR => C_BURST_BASEADDR,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
clk => clk,
reset => reset,
-- PLB bus master signals
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr,
-- user interface
i_target_addr => i_targetAddr,
i_my_addr => i_localAddr,
i_read_req => i_singleRdReq,
i_write_req => i_singleWrReq,
i_burst_read_req => i_burstRdReq,
i_burst_write_req => i_burstWrReq,
i_burst_length => i_burstLen,
o_busy => o_busy,
o_read_done => o_rdDone,
o_write_done => o_wrDone
);
-----------------------------------------------------------------------
-- bus_slave_regs_inst: PLB bus slave instatiation
--
-- Handles access to the shared memory register
-- Used for single word memory accesses
-- (e.g. reconos_read() and reconos_write())
-----------------------------------------------------------------------
bus_slave_regs_inst : entity plb_osif_v2_01_a.bus_slave_regs
generic map (
C_DWIDTH => C_DWIDTH,
C_NUM_REGS => C_NUM_CE-1
)
port map (
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
-- bus slave signals
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE(0 to (C_DWIDTH/8)-1),
Bus2IP_RdCE => Bus2IP_RdCE(0 to C_NUM_CE-2),
Bus2IP_WrCE => Bus2IP_WrCE(0 to C_NUM_CE-2),
IP2Bus_Data => slv_RdData,
IP2Bus_RdAck => slv_IP2Bus_RdAck,
IP2Bus_WrAck => slv_IP2Bus_WrAck,
-- user registers
slv_osif2bus_shm => i_singleData,
slv_bus2osif_shm => o_singleData
);
-- read/write acknowledge
IP2Bus_RdAck <= slv_IP2Bus_RdAck or ram_IP2Bus_RdAck;
IP2Bus_WrAck <= slv_IP2Bus_WrAck or ram_IP2Bus_WrAck;
-- no error handling / retry / timeout
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
-- multiplex data, if PLB connected
IP2Bus_Data <= i_burstData(0 to C_DWIDTH-1) when ram_IP2Bus_RdAck = '1' else slv_RdData;
IP2Bus_DataX <= i_burstData(C_DWIDTH to C_PLB_DWIDTH-1);
o_burstData <= Bus2IP_Data & Bus2IP_DataX;
-- burstWE <= ram_IP2Bus_WrAck and Bus2IP_WrReq;
o_burstBE <= Bus2IP_BE;
-------------------------------------------------------------------
-- bus2burst: handles bus accesses to burst memory
--
-- supports both single and burst accesses
-------------------------------------------------------------------
bus2burst : process(Bus2IP_Clk, Bus2IP_Reset)
type ram_state_t is (IDLE, BURST_READ, BURST_WRITE, SINGLE_READ);
variable ram_state : ram_state_t;
variable start_addr : std_logic_vector(0 to C_BURST_AWIDTH-1);
variable counter : natural := 0;
begin
if Bus2IP_Reset = '1' then
ram_state := IDLE;
start_addr := (others => '0');
counter := 0;
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
o_burstAddr <= (others => '0');
o_burstWE <= '0';
elsif rising_edge(Bus2IP_Clk) then
case ram_state is
when IDLE =>
counter := 0;
o_burstWE <= '0';
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
-- if Bus2IP_RdReq = '1' then
if Bus2IP_RdCE(1) = '1' and Bus2IP_RdReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_state := BURST_READ;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_state := SINGLE_READ;
end if;
-- elsif Bus2IP_WrReq = '1' then
elsif Bus2IP_WrCE(1) = '1'and Bus2IP_WrReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := BURST_WRITE;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := IDLE;
end if;
end if;
when BURST_READ =>
ram_IP2Bus_RdAck <= '1';
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_RdAck <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when BURST_WRITE =>
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_WrAck <= '0';
o_burstWE <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when SINGLE_READ =>
ram_IP2Bus_RdAck <= '1';
ram_state := IDLE;
end case;
end if;
end process;
end arch;
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/c_sub/synth/c_sub.vhd
|
8
|
6227
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0;
USE c_addsub_v12_0.c_addsub_v12_0;
ENTITY c_sub IS
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END c_sub;
ARCHITECTURE c_sub_arch OF c_sub IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF c_sub_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF c_sub_arch: ARCHITECTURE IS "c_addsub_v12_0,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF c_sub_arch : ARCHITECTURE IS "c_sub,c_addsub_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF c_sub_arch: ARCHITECTURE IS "c_sub,c_addsub_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=c_addsub,x_ipVersion=12.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_XDEVICEFAMILY=zynq,C_IMPLEMENTATION=0,C_A_WIDTH=15,C_B_WIDTH=15,C_OUT_WIDTH=15,C_CE_OVERRIDES_SCLR=0,C_A_TYPE=0,C_B_TYPE=0,C_LATENCY=0,C_ADD_MODE=1,C_B_CONSTANT=0,C_B_VALUE=000000000000000,C_AINIT_VAL=0,C_SINIT_VAL=0,C_CE_OVERRIDES_BYPASS=1,C_BYPASS_LOW=0,C_SCLR_OVERRIDES_SSET=1,C_HAS_C_IN=0,C_HAS_C_OUT=0,C_BORROW_LOW=1,C_HAS_CE=0,C_HAS_BYPASS=0,C_HAS_SCLR=0,C_HAS_SSET=0,C_HAS_SINIT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 15,
C_B_WIDTH => 15,
C_OUT_WIDTH => 15,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 1,
C_B_CONSTANT => 0,
C_B_VALUE => "000000000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END c_sub_arch;
|
gpl-3.0
|
luebbers/reconos
|
support/templates/coregen/burst_ram/burst_ram.vhd
|
1
|
5406
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2005 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file burst_ram.vhd when simulating
-- the core, burst_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY burst_ram IS
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic);
END burst_ram;
ARCHITECTURE burst_ram_a OF burst_ram IS
-- synopsys translate_off
component wrapped_burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_burst_ram use entity XilinxCoreLib.blkmemdp_v6_2(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_ywea_is_high => 1,
c_yena_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 64,
c_width_a => 32,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 0,
c_write_modea => 0,
c_has_rdyb => 0,
c_yuse_single_primitive => 0,
c_has_rdya => 0,
c_addra_width => 11,
c_addrb_width => 10,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_yydisable_warnings => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_default_data => 1,
c_has_web => 1,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 1,
c_has_dina => 1,
c_ymake_bmm => 0,
c_sim_collision_check => "NONE",
c_has_enb => 0,
c_has_ena => 0,
c_depth_b => 1024,
c_mem_init_file => "mif_file_16_1",
c_depth_a => 2048,
c_has_doutb => 1,
c_has_douta => 1,
c_yprimitive_type => "16kx1");
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_burst_ram
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
wea => wea,
web => web);
-- synopsys translate_on
END burst_ram_a;
|
gpl-3.0
|
luebbers/reconos
|
demos/mbox_demo/hw/src/threadB.vhd
|
1
|
7992
|
--
-- threadB.vhd
-- demo thread
-- Waiting on its local read FIFO, this thread will transfer 8 kB of data
-- from the FIFO to its burst RAM, and then burst that to a main memory
-- address determined by its init data.
-- Both transactions are timed, and sent to C_MBOX_GETTIME,
-- C_MBOX_WRITETIME respectively.
--
-- NOTE: These measurements may not be entirely accurate due to the bus load
-- incurred by the OS commands.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 15.10.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity threadB is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end threadB;
architecture Behavioral of threadB is
-- timer address (FIXME: hardcoded!)
constant TIMER_ADDR : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"50004000";
-- ReconOS resources used by this thread
constant C_MB_TRANSFER : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_GETTIME : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_WRITETIME : std_logic_vector(0 to 31) := X"00000002";
-- OS synchronization state machine states (TODO: measurements!)
type t_state is (
STATE_INIT,
STATE_GETTIME_START,
STATE_TRANSFER,
STATE_GETTIME_STOP,
STATE_WRITE,
STATE_WRITETIME_STOP,
STATE_POST_GETTIME_1,
STATE_POST_GETTIME_2,
STATE_POST_WRITETIME_1,
STATE_POST_WRITETIME_2,
STATE_ERROR
);
signal state : t_state := STATE_INIT;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- timing values
signal gettime : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
signal writetime : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
signal RAMAddr_d1 : std_logic_vector(0 to C_BURST_AWIDTH-1); -- delay by one
begin
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr_d1(0 to C_BURST_AWIDTH-2) & not RAMAddr_d1(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- delay RAM address
delay_proc : process(clk)
begin
if rising_edge(clk) then
RAMAddr_d1 <= RAMAddr;
end if;
end process;
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1; -- transfer 128 bytes at once
variable trans_counter : natural range 0 to 8192/4 - 1; -- transfer 4 bytes at once
-- timing values
variable writetime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable writetime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable gettime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable gettime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
address <= (others => '0');
state <= STATE_INIT;
o_RAMWE <= '0';
o_RAMData <= (others => '0');
burst_counter := 0;
trans_counter := 0;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
if done then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_GETTIME_START;
end if;
-- get start time of FIFO transfer
when STATE_GETTIME_START =>
gettime_1 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, gettime_1);
-- if done then
state <= STATE_TRANSFER;
-- end if;
-- transfer data across mailbox
-- this state also hides the RAM access timing, since this is a multi-cycle
-- command, and the "data" parameter is only transferred in the second cycle.
when STATE_TRANSFER =>
o_RAMWE <= '0';
if trans_counter = 0 then
gettime_1 := i_timeBase;
end if;
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_TRANSFER, o_RAMData);
if done then
if success then
o_RAMWE <= '1';
if trans_counter = 8192/4 - 1 then
burst_counter := 0;
state <= STATE_GETTIME_STOP;
else
RAMAddr <= RAMAddr + 1; -- note that this is delayed by one clock cycle
trans_counter := trans_counter + 1;
end if;
else -- no success
state <= STATE_ERROR;
end if;
end if;
-- get stop time of FIFO transfer
when STATE_GETTIME_STOP =>
o_RAMWE <= '0';
gettime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, gettime_2);
-- if done then
writetime_1 := gettime_2;
state <= STATE_WRITE;
-- end if;
-- write data from local burst RAM into main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_WRITETIME_STOP;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- get stop time of burst transfer
when STATE_WRITETIME_STOP =>
writetime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, writetime_2);
-- if done then
state <= STATE_POST_GETTIME_1;
-- end if;
-- write transfer time to mailbox
when STATE_POST_GETTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_GETTIME, gettime_1);
if done and success then
state <= STATE_POST_GETTIME_2;
end if;
when STATE_POST_GETTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_GETTIME, gettime_2);
if done and success then
state <= STATE_POST_WRITETIME_1;
end if;
-- write write time to mailbox
when STATE_POST_WRITETIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_WRITETIME, writetime_1);
if done and success then
state <= STATE_POST_WRITETIME_2;
end if;
when STATE_POST_WRITETIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_WRITETIME, writetime_2);
if done and success then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_TRANSFER;
end if;
when STATE_ERROR =>
reconos_thread_exit(o_osif, i_osif, X"00000" & RAMAddr);
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luebbers/reconos
|
core/pcores/plb_osif_v2_01_a/hdl/vhdl/fifo_mgr.vhd
|
3
|
3729
|
--!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <[email protected]>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 04.10.2007 Enno Luebbers File created
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fifo_mgr is
generic (
C_FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- local FIFO access signals
i_local_read_remove : in std_logic;
o_local_read_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_read_wait : out std_logic; -- either empty or busy
i_local_write_add : in std_logic;
i_local_write_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_write_wait : out std_logic; -- either full or busy
-- "real" FIFO access signals
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic
-- TODO: signal to communicate with the bus_slave_regs module
);
end fifo_mgr;
architecture behavioral of fifo_mgr is
signal local_read_remove_d1 : std_logic := '0';
begin
-- delay read_remove for 1 clock cycle
process(clk, reset)
begin
if reset = '1' then
local_read_remove_d1 <= '0';
elsif rising_edge(clk) then
local_read_remove_d1 <= i_local_read_remove;
end if;
end process;
-- for now, the FIFO manager only services local accesses.
-- so we just need to pass the local access signals straight
-- through to the "real" FIFOs
o_fifo_read_en <= local_read_remove_d1; -- hack to fit slow OSIF request/busy handshake
-- this will be obsoleted once we connect the HW
-- FIFO to the burst RAM interface (mq)
o_local_read_data <= i_fifo_read_data;
o_local_read_wait <= not i_fifo_read_ready;
o_fifo_write_en <= i_local_write_add;
o_fifo_write_data <= i_local_write_data;
o_local_write_wait <= not i_fifo_write_ready;
end behavioral;
|
gpl-3.0
|
luebbers/reconos
|
support/refdesigns/12.1/ml605/ml605_light/pcores/plbv46_dcr_bridge_v9_00_a/hdl/vhdl/plbv46_dcr_bridge_core.vhd
|
7
|
14236
|
-------------------------------------------------------------------------------
-- plbv46_dcr_bridge_core - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2006, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************--
--
-------------------------------------------------------------------------------
-- Filename: plbv46_dcr_bridge_core.vhd
-- Version: v1.01.a
-- Description: plbv46_dcr_bridge core
--
-------------------------------------------------------------------------------
-- Structure:
-- plbv46_dcr_bridge.vhd
-- -- plbv46_dcr_bridge_core.vhd
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : SK
-- History:
-- Initial version of plbv46_dcr_Bridge
-- ~~~~~~
-- SK 2006/09/19 -- Initial version
-- ^^^^^^
-- ~~~~~~
-- SK 2008/12/15 -- Updated version v1_01_a, based upon v1_00_a core.
-- -- updated proc_common_v3_00_a and plbv46_slave_
-- -- single_v1_01_a core libraries.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Definition of Ports:
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
----------------------------------------
-- IPIC INTERFACE
----------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Reset - IPIC reset
-- Bus2IP_CS - IPIC chip select signals
-- Bus2IP_RdCE - IPIC read transaction chip enables
-- Bus2IP_WrCE - IPIC write transaction chip enables
-- Bus2IP_Addr - IPIC address
-- Bus2IP_RNW - IPIC read/write indication
-- Bus2IP_BE - IPIC byte enables
-- Bus2IP_Data - IPIC write data
-- IP2Bus_Data - Read data from IP to IPIC interface
-- IP2Bus_WrAck - Write Data acknowledgment from IP to IPIC interface
-- IP2Bus_RdAck - Read Data acknowledgment from IP to IPIC interface
-- IP2Bus_Error - Error indication from IP to IPIC interface
----------------------------------------
-- PERIPHERAL INTERFACE
----------------------------------------
-- DCR_plbDBusIn - DCR data bus input
-- DCR_plbAck - DCR Ack signals
-- PLB_dcrABus - PLB address bus to DCR
-- PLB_dcrDBusOut - Data bus to the PLB
-- PLB_dcrRead - PLB read signal to DCR
-- PLB_dcrWrite - PLB write signal to DCR
-- PLB_dcrClk - PLB to DCR clk
-- PLB_dcrRst - PLB to DCR reset
-----------------------------------------------------------------------------
-- Definition of Generics
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned."+";
entity plbv46_dcr_bridge_core is
port (
-- PLBv46_IPIF Signals
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_CS : in std_logic;
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
-- DCR Master Signals
-- core signals
DCR_plbDBusIn : in std_logic_vector(0 to 31);
DCR_plbAck : in std_logic;
PLB_dcrABus : out std_logic_vector(0 to 9);
PLB_dcrDBusOut : out std_logic_vector(0 to 31);
PLB_dcrRead : out std_logic;
PLB_dcrWrite : out std_logic;
PLB_dcrClk : out std_logic;
PLB_dcrRst : out std_logic
);
end entity plbv46_dcr_bridge_core;
-------------------------------------------------------------------------------
architecture implemented of plbv46_dcr_bridge_core is
-------------------------------------------------------------------------------
-- local signal declaration section
signal plb_dcrRead_i : std_logic;
signal plb_dcrWrite_i : std_logic;
signal ip2Bus_RdAck_i : std_logic;
signal ip2Bus_WrAck_i : std_logic;
signal dcr_ack_posedge : std_logic;
signal dcr_plbAck_d1 : std_logic;
signal timeout : std_logic;
signal ip2Bus_Error_i : std_logic;
signal timeout_cnt : std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
begin -- architecture implemented
-------------------------------------------------------------------------------
--////////////////////////////////////////////////////////////////////////////
-- Main Body of Code
--////////////////////////////////////////////////////////////////////////////
-- NOTE: This design is supporting DCR reads and writes bridged from
-- PLBV46. Since DCR reads and writes are defined on words only, the
-- incoming PLBV46 reads and writes that are to be retargetted to the DCR bus
-- must also be for words only. If the PLBV46 byte enables do not correspond
-- to a word transfer, an error will be returned.
-- DCR signals just pass through from IPIF/PLBv46, but are renamed
-- to DCR names to help make it clear how to hook things up.
PLB_dcrClk <= Bus2IP_Clk;
PLB_dcrRst <= Bus2IP_Reset;
-------------------------------------------------------------------------------
-- PLB_DCRREAD_I_PROC
-- latch and hold read request strobe
-- synchronous reset (active high)
PLB_DCRREAD_I_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_RdAck_i = '1' or
Bus2IP_Reset = '1' or timeout = '1') then
plb_dcrRead_i <= '0';
elsif (Bus2IP_RdCE = '1' and DCR_plbAck = '0') then
plb_dcrRead_i <= '1';
end if;
end if;
end process PLB_DCRREAD_I_PROC;
PLB_dcrRead <= plb_dcrRead_i;
-------------------------------------------------------------------------------
-- PLB_DCRWRITE_I_PROC
-- latch and hold write request strobe
-- synchronous reset (active high)
PLB_DCRWRITE_I_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_WrAck_i = '1' or
Bus2IP_Reset = '1' or timeout = '1') then
plb_dcrWrite_i <= '0';
elsif (Bus2IP_WrCE = '1' and DCR_plbAck = '0')then
plb_dcrWrite_i <= '1';
end if;
end if;
end process PLB_DCRWRITE_I_PROC;
PLB_dcrWrite <= plb_dcrWrite_i;
-------------------------------------------------------------------------------
-- process REG_DCR_ABUS_PROC
-- DCR address bus is 10 bits and points to 32 bit words, so pick up the
-- corresponding address bits from PLBv46
REG_DCR_ABUS_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
PLB_dcrABus <= Bus2IP_Addr(20 to 29);
end if;
end process REG_DCR_ABUS_PROC;
-------------------------------------------------------------------------------
-- process DCR_DBUS_OUT_PROC
-- PLB_dcrDBusOut is set to 0xFFFF_FFFF during reads operations so it
-- will return 0xFFFF_FFFF when read times out. DCR specifies that timeout
-- errors are ignored back to the CPU so setting the default read to all
-- 1's will help identify timeouts. Data bus out drives 00000000 during
-- reset as required by DCR spec.
DCR_DBUS_OUT_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
PLB_dcrDBusOut <= (others => '0');
elsif (plb_dcrRead_i = '1' or Bus2IP_RdCE = '1') then
PLB_dcrDBusOut <= (others => '1');
else
PLB_dcrDBusOut <= Bus2IP_Data;
end if;
end if;
end process DCR_DBUS_OUT_PROC;
-------------------------------------------------------------------------------
-- connect input data lines to ip2bus_data, so that it will be returned to ipif
IP2Bus_Data <= DCR_plbDBusIn;
-------------------------------------------------------------------------------
-- process TIMOUT_CNT_PROC
-- Generate timeouts after 16 cycles. The timeout counter is enabled during
-- DCR operations and is reset during system reset or when an ack is sent
-- back to the IPIF. Note that an ack is sent back to the IPIF after a timeout
-- has been issued or if a DCR slave responds.
TIMOUT_CNT_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_RdAck_i = '1' or IP2Bus_WrAck_i = '1'
or Bus2IP_Reset = '1') then
timeout_cnt <= "0000";
elsif (plb_dcrRead_i = '1' or plb_dcrWrite_i = '1') then
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process TIMOUT_CNT_PROC;
-------------------------------------------------------------------------------
timeout <= '1' when timeout_cnt = "1111" else '0';
-------------------------------------------------------------------------------
-- process DCR_plbAck_PROC
-- detect only the posedge of DCR slave acks since the DCR slave may run
-- on a slower clock and thus its ack would be seen asserted for more than
-- 1 cycle
DCR_plbAck_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
dcr_plbAck_d1 <= DCR_plbAck;
end if;
end process DCR_plbAck_PROC;
dcr_ack_posedge <= DCR_plbAck and (not dcr_plbAck_d1);
-------------------------------------------------------------------------------
-- generate an ack back to the IPIF when a DCR slave responds or if a timeout
-- occurs
IP2Bus_RdAck_i <= plb_dcrRead_i and (dcr_ack_posedge or timeout);
IP2Bus_RdAck <= IP2Bus_RdAck_i;
IP2Bus_WrAck_i <= plb_dcrWrite_i and (dcr_ack_posedge or timeout);
IP2Bus_WrAck <= IP2Bus_WrAck_i;
-------------------------------------------------------------------------------
-- Generate a PLB error on DCR timeout or if less than a full
-- word of data is transferred (BE not 1111)
ip2Bus_Error_i <= '1' when (
(timeout = '1' and dcr_ack_posedge = '0')
or
((Bus2IP_BE /= "1111") and Bus2IP_CS = '1')
) else '0';
-------------------------------------------------------------------------------
--DCR_Error_REG_PROC
--this process is to register the error signal.
-----------------------------------------------
DCR_Error_REG_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
IP2Bus_Error <= ip2Bus_Error_i;
end if;
end process DCR_Error_REG_PROC;
-------------------------------------------------------------------------------
end architecture implemented;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/ip/clock/vhdl_sim/real_time_clock_tb.vhd
|
5
|
735
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_req := c_io_req_init;
signal resp : t_io_resp := c_io_resp_init;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_dut: entity work.real_time_clock
generic map (
g_freq => 100 )
port map (
clock => clock,
reset => reset,
req => req,
resp => resp );
end;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/ip/video/vhdl_sim/pll_tb.vhd
|
5
|
3453
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/ip/async_fifo/vhdl_source/gray_code_pkg.vhd
|
4
|
3209
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : gray_code_pkg
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: gray code package, only the functions needed for the
-- asynchronous fifo
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gray_code_pkg is
---------------------------------------------------------------------------
-- type
---------------------------------------------------------------------------
type t_gray is array (natural range <>) of std_logic;
---------------------------------------------------------------------------
-- conversion function
---------------------------------------------------------------------------
function to_unsigned (arg : t_gray) return unsigned;
---------------------------------------------------------------------------
-- arithmetic function
---------------------------------------------------------------------------
function increment (arg : t_gray) return t_gray;
end gray_code_pkg;
-------------------------------------------------------------------------------
-- package body
-------------------------------------------------------------------------------
package body gray_code_pkg is
function to_unsigned (arg : t_gray) return unsigned is
variable mybin : unsigned(arg'range);
variable temp : std_logic;
begin
for i in arg'low to arg'high-1 loop
temp := '0';
for j in i+1 to arg'high loop
temp := temp xor arg(j);
end loop;
mybin(i) := arg(i) xor temp;
end loop;
mybin(mybin'high) := arg(arg'high);
return mybin;
end to_unsigned;
function increment (arg : t_gray) return t_gray is
alias xarg : t_gray((arg'length-1) downto 0) is arg;
variable grayinc : t_gray(xarg'range);
variable temp : std_logic;
begin
for i in xarg'range loop
-- rule: high downto i: xnor
-- i-1: and
-- i-2 downto 0: and not
temp := '0';
if i = xarg'high then
temp := xarg(i) xor xarg(i-1);
else
for j in i to arg'high loop
temp := temp xor xarg(j);
end loop;
temp := not(temp);
if i >= 1 then
temp := temp and xarg(i-1);
end if;
end if;
if i >= 2 then
for j in 0 to i-2 loop
temp := temp and not(xarg(j));
end loop;
end if;
grayinc(i) := xarg(i) xor temp;
end loop;
return grayinc;
end increment;
end;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/ip/video/vhdl_source/char_generator_timing.vhd
|
5
|
9039
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_timing.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.char_generator_pkg.all;
entity char_generator_timing is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
h_sync : in std_logic;
v_sync : in std_logic;
control : in t_chargen_control;
screen_addr : out unsigned(10 downto 0);
screen_data : in std_logic_vector(7 downto 0);
char_addr : out unsigned(10 downto 0);
char_data : in std_logic_vector(7 downto 0);
sync_n : out std_logic;
clock_en : out std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic );
end entity;
architecture gideon of char_generator_timing is
signal clock_div : integer range 0 to g_divider-1;
signal clock_en_i : std_logic;
signal force_sync : std_logic;
signal x_counter : unsigned(10 downto 0) := (others => '0');
signal y_counter : unsigned(8 downto 0) := (others => '0');
signal pointer : unsigned(10 downto 0) := (others => '0');
signal char_x : unsigned(6 downto 0) := (others => '0');
signal char_y : unsigned(3 downto 0) := (others => '0');
signal char_y_d : unsigned(3 downto 0) := (others => '0');
signal pixel_count : unsigned(2 downto 0) := (others => '0');
signal remaining_lines : unsigned(4 downto 0) := (others => '0');
signal h_sync_c : std_logic;
signal h_sync_d : std_logic;
signal v_sync_c : std_logic;
type t_state is (idle, active_line, draw);
signal state : t_state;
type t_line_type is (normal, half, serration);
signal line_type : t_line_type;
-- pipeline
signal active_d1 : std_logic;
signal pixel_sel_d1 : unsigned(2 downto 0);
signal active_d2 : std_logic;
signal pixel_sel_d2 : unsigned(2 downto 0);
begin
clock_en <= clock_en_i;
process(clock)
begin
if rising_edge(clock) then
h_sync_c <= h_sync;
h_sync_d <= h_sync_c;
v_sync_c <= v_sync;
-- force_sync <= '0';
-- if control.perform_sync='1' and v_sync_c='1' and h_sync_d='0' and h_sync_c='1' then
-- y_counter <= (others => '0');
-- x_counter <= (others => '0');
-- end if;
-- -- x/y counters, zonder gehinderd door enige sync-kennis
-- if clock_en_i = '1' then
-- if x_counter = control.clocks_per_line-1 then
-- x_counter <= (others => '0');
-- if y_counter = 311 then
-- y_counter <= (others => '0');
-- force_sync <= '1';
-- else
-- y_counter <= y_counter + 1;
-- end if;
-- else
-- x_counter <= x_counter + 1;
-- end if;
-- end if;
if h_sync_c='1' and h_sync_d='0' then -- rising_edge
x_counter <= (others => '0');
if v_sync_c='1' then
y_counter <= (others => '0');
else
y_counter <= y_counter + 1;
end if;
clock_en_i <= '0';
clock_div <= g_divider-1;
elsif clock_div = 0 then
x_counter <= x_counter + 1;
clock_en_i <= '1';
clock_div <= g_divider-1;
else
clock_en_i <= '0';
clock_div <= clock_div - 1;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if clock_en_i='1' then
line_type <= normal;
if (y_counter < 3) or (y_counter > 305) then
line_type <= half;
end if;
if (y_counter > 308) then
line_type <= serration;
end if;
if x_counter=0 then
sync_n <= '0';
else
case line_type is
when normal =>
if x_counter = 64 then
sync_n <= '1';
end if;
when half =>
if x_counter = 32 then
sync_n <= '1';
elsif x_counter = 448 then
sync_n <= '0';
elsif x_counter = 480 then
sync_n <= '1';
end if;
when serration =>
if x_counter = 416 then
sync_n <= '1';
elsif x_counter = 448 then
sync_n <= '0';
elsif x_counter = 864 then
sync_n <= '1';
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if clock_en_i='1' then
active_d1 <= '0';
char_y_d <= char_y;
case state is
when idle =>
pointer <= control.pointer;
char_y <= (others => '0');
remaining_lines <= control.active_lines;
if y_counter = control.y_on then
state <= active_line;
end if;
when active_line =>
char_x <= (others => '0');
pixel_count <= control.char_width;
if remaining_lines = 0 then
state <= idle;
elsif x_counter = control.x_on then
state <= draw;
end if;
when draw =>
if pixel_count = 1 then
pixel_count <= control.char_width;
char_x <= char_x + 1;
if char_x = control.chars_per_line-1 then
state <= active_line;
char_x <= (others => '0');
if char_y = control.char_height-1 then
pointer <= pointer + control.chars_per_line;
char_y <= (others => '0');
remaining_lines <= remaining_lines - 1;
else
char_y <= char_y + 1;
end if;
end if;
else
pixel_count <= pixel_count - 1;
end if;
active_d1 <= '1';
when others =>
null;
end case;
-- pipeline forwards
pixel_sel_d1 <= pixel_count - 1;
pixel_sel_d2 <= pixel_sel_d1;
active_d2 <= active_d1;
-- pixel output
pixel_active <= active_d2;
pixel_data <= active_d2 and char_data(to_integer(pixel_sel_d2));
if force_sync='1' then
state <= idle;
end if;
end if;
if reset='1' then
state <= idle;
end if;
end if;
end process;
screen_addr <= pointer + char_x;
char_addr <= unsigned(screen_data) & char_y_d(2 downto 0) when char_y_d(3)='0' else
screen_data(7) & "0000000000";
end architecture;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/io/spi/vhdl_source/spi.vhd
|
5
|
4344
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/high_pass.vhd
|
5
|
1274
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity high_pass is
generic (
g_width : natural := 12 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
x : in signed(g_width-1 downto 0);
q : out signed(g_width downto 0) );
end high_pass;
architecture gideon of high_pass is
signal z : signed(g_width downto 0);
signal count : integer range 0 to 3;
begin
process(clock)
variable z_half : signed(g_width downto 0);
begin
if rising_edge(clock) then
z_half := (z(z'high) & z(z'high downto 1));
if enable='1' then
z <= sum_limit((x(x'high) & x), z_half); -- z=x+(z/2)
q <= sub_limit((x(x'high) & x), z_half); -- q=x-(z/2)
end if;
-- z <= extend(x, g_width+1);
-- q <= extend(x, g_width+1) - z;
if reset='1' then
z <= (others => '0');
q <= (others => '0');
count <= 0;
end if;
end if;
end process;
end gideon;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/my_math_pkg.vhd
|
6
|
4097
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_math_pkg is
function sum_limit(i1, i2 : signed) return signed;
function sub_limit(i1, i2 : signed) return signed;
function sum_limit(i1, i2 : unsigned) return unsigned;
function extend(x : signed; len : natural) return signed;
function extend(x : unsigned; len : natural) return unsigned;
function left_align(x : signed; len : natural) return signed;
function left_scale(x : signed; sh : natural) return signed;
-- function shift_right(x : signed; positions: natural) return signed;
end;
package body my_math_pkg is
function sum_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 + i2;
if (i1(i1'left) = i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sub_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 - i2;
if (i1(i1'left) /= i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sum_limit(i1, i2 : unsigned) return unsigned is
variable o : unsigned(i1'length downto 0);
begin
o := ('0' & i1) + i2;
if o(o'left)='1' then
o := (others => '1');
end if;
return o(i1'length-1 downto 0);
end function;
function extend(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
alias a : signed(x'length-1 downto 0) is x;
begin
ret := (others => x(x'left));
ret(a'range) := a;
return ret;
end function extend;
function extend(x : unsigned; len : natural) return unsigned is
variable ret : unsigned(len-1 downto 0);
alias a : unsigned(x'length-1 downto 0) is x;
begin
ret := (others => '0');
ret(a'range) := a;
return ret;
end function extend;
function left_align(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
begin
ret := (others => '0');
ret(len-1 downto len-x'length) := x;
return ret;
end function left_align;
function left_scale(x : signed; sh : natural) return signed is
alias a : signed(x'length-1 downto 0) is x;
variable ret : signed(x'length-(1+sh) downto 0);
variable top : signed(sh downto 0);
begin
if sh=0 then
return x;
end if;
top := a(a'high downto a'high-sh);
if (top = -1) or (top = 0) then -- can shift without getting punished!
ret := a(ret'range);
elsif a(a'high)='1' then -- negative and can't shift, so max neg:
ret := (others => '0');
ret(ret'high) := '1';
else -- positive and can't shift, so max pos
ret := (others => '1');
ret(ret'high) := '0';
end if;
return ret;
end function left_scale;
-- function shift_right(x : signed; positions: natural) return signed is
-- alias a : signed(x'length-1 downto 0) is x;
-- variable ret : signed(x'length-1 downto 0);
-- begin
-- ret := (others => x(x'left));
-- ret(a'left-positions downto 0) := a(a'left downto positions);
-- return ret;
-- end function shift_right;
end;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/ip/fall_through/vhdl_source/fall_through_add_on.vhd
|
5
|
2208
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : fall_through_add_on
-------------------------------------------------------------------------------
-- Description: fall_through_add_on, one position deep fifo-add-on
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity fall_through_add_on is
generic (
g_data_width : natural := 32);
port (
clock : in std_logic;
reset : in std_logic;
-- fifo side
rd_dout : in std_logic_vector(g_data_width - 1 downto 0);
rd_empty : in std_logic;
rd_en : out std_logic;
-- consumer side
data_out : out std_logic_vector(g_data_width - 1 downto 0);
data_valid : out std_logic;
data_next : in std_logic);
end fall_through_add_on;
architecture structural of fall_through_add_on is
type t_state is (empty, full);
signal state : t_state;
begin -- structural
fsm : process (clock)
begin -- process fsm
if clock'event and clock = '1' then -- rising clock edge
case state is
when empty =>
if rd_empty = '0' then
state <= full;
end if;
when full =>
if data_next = '1' and rd_empty = '1' then
state <= empty;
end if;
when others => null;
end case;
if reset = '1' then -- synchronous reset (active high)
state <= empty;
end if;
end if;
end process fsm;
data_valid <= '1' when state = full else
'0';
rd_en <= '1' when ((state = empty and rd_empty = '0') or
(state = full and rd_empty = '0' and data_next = '1')) else
'0';
data_out <= rd_dout;
end structural;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/io/mem_ctrl/vhdl_source/ext_mem_test_v6.vhd
|
5
|
4298
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v6 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_16_req;
resp : in t_mem_burst_16_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_v6 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(15 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 15) := (
X"1234", X"5678", X"9ABC", X"DEF0", -- 0
X"DEAD", X"BEEF", X"C0ED", X"BABE", -- 100
X"00FF", X"00FF", X"00FF", X"00FF", -- 64K
X"55AA", X"55AA", X"3366", X"CC99" ); -- 0, etc
-- constant c_read_data : t_datas(0 to 15) := (
-- X"1234", X"5678", X"9ABC", X"DEF0",
-- X"DEAD", X"BEEF", X"C0ED", X"BABE",
-- X"00FF", X"00FF", X"00FF", X"00FF",
-- X"55AA", X"55AA", X"3366", X"CC99" );
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_16_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/cpu_unit/vhdl_source/dm_cache_custom.vhd
|
5
|
19631
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dm_cache_custom is
generic (
-- g_allocate_on_write : boolean := true;
-- g_write_through : boolean := false;
g_write_support : boolean := true;
g_early_resume : boolean := false;
g_init_file : string := "none";
g_address_width : natural := 24;
g_data_width : natural := 32;
g_id_width : natural := 8;
g_cache_size_bits : natural := 11;
g_line_size_bits : natural := 1 ); -- 2K*32 BL=2
port (
clock : in std_logic;
reset : in std_logic;
client_request : in std_logic;
client_req_id : in std_logic_vector(g_id_width-1 downto 0);
client_rwn : in std_logic;
client_address : in unsigned(g_address_width-1 downto 0);
client_wdata : in std_logic_vector(g_data_width-1 downto 0);
client_byte_en : in std_logic_vector((g_data_width/8)-1 downto 0);
client_rdata : out std_logic_vector(g_data_width-1 downto 0);
client_rack : out std_logic;
client_rack_id : out std_logic_vector(g_id_width-1 downto 0);
client_dack_id : out std_logic_vector(g_id_width-1 downto 0);
mem_request : out std_logic;
mem_read_writen : out std_logic;
mem_address : out unsigned(g_address_width-1 downto 0);
mem_wdata : out std_logic_vector(g_data_width-1 downto 0);
mem_data_push : out std_logic;
mem_data_pop : out std_logic;
mem_rdata : in std_logic_vector(g_data_width-1 downto 0);
mem_ready : in std_logic; -- can accept requests
mem_rdata_av : in std_logic; -- indicates if there is data in read fifo
hit_count : out unsigned(31 downto 0);
miss_count : out unsigned(31 downto 0) );
end dm_cache_custom;
architecture gideon of dm_cache_custom is
constant c_tag_size_bits : integer := g_cache_size_bits - g_line_size_bits;
constant c_tag_width : natural := 2 + g_address_width - g_cache_size_bits;
function cache_index_of(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_cache_size_bits-1 downto 0);
end function;
function tag_index_of(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_cache_size_bits-1 downto g_line_size_bits);
end function;
function get_addr_high(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_address_width-1 downto g_cache_size_bits);
end function;
type t_tag is record
address_high : unsigned(g_address_width-1 downto g_cache_size_bits);
dirty : std_logic;
valid : std_logic;
end record;
constant c_tag_pre_init : t_tag := (
address_high => to_unsigned(0, g_address_width - g_cache_size_bits),
dirty => '1',
valid => '1' );
function tag_pack(t : t_tag) return std_logic_vector is
variable ret : std_logic_vector(c_tag_width-1 downto 0);
begin
ret := t.dirty & t.valid & std_logic_vector(t.address_high);
return ret;
end function;
function tag_unpack(v : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.dirty := v(v'high);
ret.valid := v(v'high-1);
ret.address_high := unsigned(v(v'high-2 downto 0));
return ret;
end function;
signal any_request : std_logic := '0';
signal read_request : std_logic := '0';
signal read_request_d : std_logic := '0';
signal write_request : std_logic := '0';
signal write_request_d : std_logic := '0';
signal ready : std_logic := '0';
signal read_la : std_logic := '0';
signal write_la : std_logic := '0';
signal tag_la : std_logic_vector(g_id_width-1 downto 0);
signal do_query_d : std_logic;
signal rd_address : unsigned(g_address_width-1 downto 0);
signal wr_address : unsigned(g_address_width-1 downto 0);
signal cache_rd_index : unsigned(g_cache_size_bits-1 downto 0);
signal cache_wr_index : unsigned(g_cache_size_bits-1 downto 0);
signal cache_wdata : std_logic_vector(g_data_width-1 downto 0);
signal cache_byte_en : std_logic_vector(client_byte_en'range);
signal cache_data_out : std_logic_vector(g_data_width-1 downto 0) := (others => '0');
signal cache_rdata : std_logic_vector(g_data_width-1 downto 0);
signal cache_we : std_logic;
signal cache_b_en : std_logic;
signal cache_rd_en : std_logic;
signal tag_rd_index : unsigned(g_cache_size_bits-1 downto g_line_size_bits);
signal tag_wr_index : unsigned(g_cache_size_bits-1 downto g_line_size_bits);
signal tag_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal rd_tag : t_tag;
signal wr_tag : t_tag;
signal fill_tag : t_tag;
signal last_write_tag : t_tag;
signal hit_i : std_logic := '0';
signal cache_miss : std_logic := '0';
signal cache_hit : std_logic := '0';
signal old_address : unsigned(g_address_width-1 downto 0);
signal address_la : unsigned(g_address_width-1 downto 0);
-- back office
signal fill_high : unsigned(g_address_width-1 downto g_line_size_bits) := (others => '0');
signal fill_address : unsigned(g_address_width-1 downto 0) := (others => '0');
signal fill_valid : std_logic;
signal fill_data : std_logic_vector(g_data_width-1 downto 0);
signal burst_count : unsigned(g_line_size_bits-1 downto 0);
signal burst_count_d : unsigned(g_line_size_bits-1 downto 0);
type t_state is (idle, check_dirty, fill, deferred);
signal state : t_state;
signal dirty_d : std_logic;
-- signals related to delayed write register
signal last_write_address : unsigned(g_address_width-1 downto 0);
signal last_write_data : std_logic_vector(g_data_width-1 downto 0);
signal last_write_byte_en : std_logic_vector(client_byte_en'range);
signal last_write_valid : std_logic;
signal store_reg : std_logic := '0';
signal store_after_fill : std_logic := '0';
-- memory interface
signal mem_busy : std_logic := '0';
signal need_mem_access : std_logic := '0';
signal mem_req_i : std_logic;
signal mem_rwn : std_logic;
signal mem_addr_i : unsigned(g_address_width-1 downto 0);
signal mem_wrfifo_put : std_logic;
signal mem_rdfifo_get : std_logic;
signal helper_data_to_ram : std_logic_vector(g_data_width-1 downto 0);
signal helper_data_from_ram : std_logic_vector(g_data_width-1 downto 0);
-- statistics
signal hit_count_i : unsigned(31 downto 0) := (others => '0');
signal miss_count_i : unsigned(31 downto 0) := (others => '0');
begin
any_request <= client_request and ready;
read_request <= client_request and client_rwn and ready;
write_request <= client_request and not client_rwn and ready;
ready <= '1' when mem_busy='0' and need_mem_access='0' else '0';
need_mem_access <= cache_miss;
process(clock)
begin
if rising_edge(clock) then
read_request_d <= read_request;
write_request_d <= write_request;
do_query_d <= '0';
if ready='1' then
do_query_d <= client_request;
tag_la <= client_req_id;
address_la <= client_address;
read_la <= client_request and client_rwn;
write_la <= client_request and not client_rwn;
end if;
end if;
end process;
-- main address multiplexer
rd_address <= client_address;
wr_address <= fill_address when (mem_rdfifo_get='1' or dirty_d='1') else
last_write_address;
cache_rd_index <= cache_index_of(rd_address);
cache_wr_index <= cache_index_of(wr_address);
cache_wdata <= fill_data when mem_rdfifo_get='1' else
last_write_data;
cache_byte_en <= (others => '1') when mem_rdfifo_get='1' else
last_write_byte_en;
wr_tag <= fill_tag when mem_rdfifo_get='1' else
last_write_tag;
cache_we <= mem_rdfifo_get or store_reg;
cache_b_en <= cache_we or dirty_d; -- dirty_d is set during fill operation and causes read enable here
cache_rd_en <= client_request and ready;
fill_tag.address_high <= get_addr_high(fill_address);
fill_tag.dirty <= '0';
fill_tag.valid <= '1';
last_write_tag.address_high <= get_addr_high(last_write_address);
last_write_tag.dirty <= '1';
last_write_tag.valid <= last_write_valid;
r_write_byte_en: if g_write_support generate
i_cache_ram: entity work.dpram_rdw_byte
generic map (
g_rdw_check => g_early_resume,
g_width_bits => g_data_width,
g_depth_bits => g_cache_size_bits,
g_init_file => g_init_file,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => cache_wdata,
b_byte_en => cache_byte_en,
b_en => cache_b_en,
b_we => cache_we );
end generate;
r_write_fill_only: if not g_write_support generate
i_cache_ram_nobe: entity work.dpram_rdw
generic map (
g_rdw_check => g_early_resume,
g_width_bits => g_data_width,
g_depth_bits => g_cache_size_bits,
g_init_value => X"00000000",
g_init_file => g_init_file,
g_init_width => g_data_width/8,
g_init_offset => 0,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => fill_data,
b_en => cache_b_en,
b_we => mem_rdfifo_get );
end generate;
tag_rd_index <= tag_index_of(rd_address);
tag_wr_index <= tag_index_of(wr_address);
rd_tag <= tag_unpack(tag_rdata);
tag_wdata <= tag_pack(wr_tag);
i_tag_ram: entity work.dpram_rdw
generic map (
g_rdw_check => g_early_resume,
g_width_bits => c_tag_width,
g_init_value => tag_pack(c_tag_pre_init),
g_depth_bits => c_tag_size_bits )
port map (
clock => clock,
a_address => tag_rd_index,
a_rdata => tag_rdata,
a_en => cache_rd_en,
b_address => tag_wr_index,
b_wdata => tag_wdata,
b_en => cache_we,
b_we => cache_we );
hit_i <= '1' when rd_tag.valid='1' and (rd_tag.address_high = get_addr_high(address_la)) else '0';
cache_hit <= hit_i and do_query_d;
cache_miss <= not hit_i and do_query_d;
old_address <= rd_tag.address_high & address_la(g_cache_size_bits-1 downto 0); -- recombine
-- handle writes
process(clock)
begin
if rising_edge(clock) then
if client_request='1' and client_rwn='0' and ready='1' then
last_write_data <= client_wdata;
last_write_byte_en <= client_byte_en;
last_write_address <= client_address;
last_write_valid <= '1';
elsif store_reg='1' then
last_write_valid <= '0';
end if;
end if;
end process;
store_reg <= '1' when (last_write_valid='1' and (cache_hit='1' or store_after_fill='1')) else
'0';
-- end handle writes
-- read data multiplexer
fill_valid <= mem_rdata_av;
fill_data <= mem_rdata;
client_rack <= client_request and ready;
client_rack_id <= client_req_id when client_request='1' and ready='1' else (others => '0');
process(cache_hit, cache_rdata, read_request_d, tag_la,
fill_data, fill_valid, burst_count, read_la, address_la)
begin
client_dack_id <= (others => '0');
if cache_hit='1' then
client_rdata <= cache_rdata;
if read_request_d='1' then
client_dack_id <= tag_la;
end if;
else
client_rdata <= fill_data;
-- Generate dack when correct word passes by (not necessary, but will increase performance)
-- (In this setup it is necessary, because there is no other cause to let the client continue,
-- as 'hit' will not automatically become '1', as we already acknowledged the request itself.)
if fill_valid='1' and burst_count = address_la(burst_count'range) and read_la='1' then
client_dack_id <= tag_la;
end if;
end if;
end process;
-- end read data multiplexer
p_cache_control: process(clock)
begin
if rising_edge(clock) then
burst_count_d <= burst_count;
store_after_fill <= '0';
mem_req_i <= '0';
if cache_miss='1' then
miss_count_i <= miss_count_i + 1;
end if;
if cache_hit='1' then
hit_count_i <= hit_count_i + 1;
end if;
case state is
when idle =>
-- There are a few scenarios that could cause a miss:
-- Read miss: last_write_register is not valid, because it should already have been written in the cache!
-- Write miss: last_write_register is always valid, since it was just set. In this scenario the last write register
-- holds data that still needs to be written to the cache, BUT couldn't do it because of the miss. The data in the cache
-- that is flushed to DRAM is never the data in the register, otherwise it would have been a hit. The fill cycle that
-- follows will check dirty, do a write out of the dirty data from cache, and then fills the cacheline with data from
-- the DRAM, and then will issue the command to store the register. Obviously this immediately sets the line to dirty.
if cache_miss='1' then
if mem_ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_addr_i <= address_la;
state <= check_dirty;
else
state <= deferred;
end if;
end if;
dirty_d <= rd_tag.dirty and cache_miss; -- dirty will be our read enable from cache :)
--fill_high <= old_address(old_address'high downto g_line_size_bits); -- high bits don't matter here (this is correct!)
--fill_high <= address_la(old_address'high downto g_line_size_bits); -- high bits don't matter here (optimization!!)
when deferred =>
if mem_ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_addr_i <= address_la;
state <= check_dirty;
end if;
when check_dirty => -- sequences through 'line_size' words
mem_addr_i <= old_address;
mem_rwn <= '0'; -- write
if dirty_d='0' then
--fill_high <= address_la(address_la'high downto g_line_size_bits); -- high bits do matter here
state <= fill;
else -- dirty_d='1'
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
mem_req_i <= '1'; -- issue the write request to memctrl
dirty_d <= '0';
--fill_high <= address_la(address_la'high downto g_line_size_bits); -- high bits do matter here
state <= fill;
end if;
end if;
when fill =>
if mem_rdata_av='1' then
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
state <= idle;
store_after_fill <= last_write_valid; -- this will occur during idle
end if;
end if;
-- asynchronously: mem_rdfifo_get <= '1' when state = fill and mem_rdata_av='1'.
when others =>
null;
end case;
mem_wrfifo_put <= dirty_d; -- latency of blockram
if reset='1' then
burst_count <= (others => '0');
dirty_d <= '0';
state <= idle;
mem_rwn <= '1';
mem_req_i <= '0';
end if;
end if;
end process;
mem_rdfifo_get <= '1' when state = fill and mem_rdata_av='1' else '0';
-- index to the cache for back-office operations (line in, line out)
fill_high <= address_la(old_address'high downto g_line_size_bits);
fill_address <= fill_high & burst_count;
mem_busy <= '1' when (state/= idle) else '0';
mem_request <= mem_req_i;
mem_read_writen <= mem_rwn;
mem_address <= mem_addr_i(mem_address'high downto g_line_size_bits) & to_unsigned(0, g_line_size_bits);
mem_wdata <= cache_data_out;
mem_data_pop <= mem_rdfifo_get;
mem_data_push <= mem_wrfifo_put;
helper_data_to_ram <= cache_data_out when mem_wrfifo_put='1' else (others => 'Z');
helper_data_from_ram <= mem_rdata when mem_rdfifo_get='1' else (others => 'Z');
hit_count <= hit_count_i;
miss_count <= miss_count_i;
end gideon;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
target/simulation/packages/vhdl_source/tl_string_util_pkg.vhd
|
5
|
33938
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION B.V., GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Style guide example package
-- Author : Jonathan Hofman ([email protected]) (import only)
-------------------------------------------------------------------------------
-- Description: This file contains type definitions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package tl_string_util_pkg is
-------------------------------------------------------------------------------
-- functions origination from file_io_package (depricated)
-------------------------------------------------------------------------------
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character; -- depricated
function hex_to_nibble(c : character) return std_logic_vector; -- depricated
function is_hex_char(c : character) return boolean; -- depricated
function vec_to_hex(vec : std_logic_vector; len : integer) return string; -- depricated
procedure write_string(variable my_line : inout line; s : string); -- depricated
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts std_logic into a character
---------------------------------------------------------------------------
function chr(sl: std_logic) return character;
---------------------------------------------------------------------------
-- converts a nible into a hex character
---------------------------------------------------------------------------
function hchr(slv: std_logic_vector) return character;
function hchr(slv: unsigned) return character;
---------------------------------------------------------------------------
-- converts std_logic into a string (1 to 1)
---------------------------------------------------------------------------
function str(sl: std_logic) return string;
---------------------------------------------------------------------------
-- converts std_logic_vector into a string (binary base)
---------------------------------------------------------------------------
function str(slv: std_logic_vector) return string;
---------------------------------------------------------------------------
-- converts boolean into a string
---------------------------------------------------------------------------
function str(b: boolean) return string;
---------------------------------------------------------------------------
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
---------------------------------------------------------------------------
function chr(int: integer) return character;
---------------------------------------------------------------------------
-- converts integer into string using specified base
---------------------------------------------------------------------------
function str(int: integer; base: integer) return string;
---------------------------------------------------------------------------
-- converts to string, using base 10
---------------------------------------------------------------------------
function str(int: integer) return string;
---------------------------------------------------------------------------
-- convert into a string in hex format
---------------------------------------------------------------------------
function hstr(slv: std_logic_vector) return string;
function hstr(uns: unsigned) return string;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts a character into std_logic
---------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic;
---------------------------------------------------------------------------
-- converts a hex character into std_logic_vector
---------------------------------------------------------------------------
function hchr_to_std_logic_vector(c: character) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a string into a specific type
---------------------------------------------------------------------------
function to_std_logic_vector(s: string) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a hex string into a specific type
---------------------------------------------------------------------------
function hstr_to_std_logic_vector( str : string; len: integer) return std_logic_vector;
function hstr_to_integer( str : string ) return integer;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- convert to upper case
---------------------------------------------------------------------------
function to_upper(c: character) return character;
function to_upper(s: string) return string;
---------------------------------------------------------------------------
-- convert to lower case
---------------------------------------------------------------------------
function to_lower(c: character) return character;
function to_lower(s: string) return string;
---------------------------------------------------------------------------
-- check if it is an hex character
---------------------------------------------------------------------------
function is_hchr(c : character) return boolean;
function resize(s: string; size: natural; default: character := ' ') return string;
---------------------------------------------------------------------------
-- Compare function for strings that correctly handles terminators (NUL)
---------------------------------------------------------------------------
function strcmp(a: string; b: string) return boolean;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- print
---------------------------------------------------------------------------
-- print string to a file and start new line, if no file is specified the
-- print function will print to stdout
---------------------------------------------------------------------------
procedure print(text: string);
procedure print(active: boolean; text: string);
procedure print(file out_file: TEXT; new_string: in string);
procedure print(file out_file: TEXT; char: in character);
---------------------------------------------------------------------------
-- read variable length string from input file
---------------------------------------------------------------------------
procedure str_read(file in_file: TEXT; res_string: out string);
-------------------------------------------------------------------------------
-- character manipulation
-------------------------------------------------------------------------------
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector;
end tl_string_util_pkg;
package body tl_string_util_pkg is
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character is
variable r : character := '?';
begin
case nibble is
when "0000" => r := '0';
when "0001" => r := '1';
when "0010" => r := '2';
when "0011" => r := '3';
when "0100" => r := '4';
when "0101" => r := '5';
when "0110" => r := '6';
when "0111" => r := '7';
when "1000" => r := '8';
when "1001" => r := '9';
when "1010" => r := 'A';
when "1011" => r := 'B';
when "1100" => r := 'C';
when "1101" => r := 'D';
when "1110" => r := 'E';
when "1111" => r := 'F';
when others => r := 'X';
end case;
return r;
end nibble_to_hex;
function hex_to_nibble(c : character) return std_logic_vector is
variable z : std_logic_vector(3 downto 0);
begin
case c is
when '0' => z := "0000";
when '1' => z := "0001";
when '2' => z := "0010";
when '3' => z := "0011";
when '4' => z := "0100";
when '5' => z := "0101";
when '6' => z := "0110";
when '7' => z := "0111";
when '8' => z := "1000";
when '9' => z := "1001";
when 'A' => z := "1010";
when 'B' => z := "1011";
when 'C' => z := "1100";
when 'D' => z := "1101";
when 'E' => z := "1110";
when 'F' => z := "1111";
when 'a' => z := "1010";
when 'b' => z := "1011";
when 'c' => z := "1100";
when 'd' => z := "1101";
when 'e' => z := "1110";
when 'f' => z := "1111";
when others => z := "XXXX";
end case;
return z;
end hex_to_nibble;
function is_hex_char(c : character) return boolean is
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7' => return true;
when '8'|'9'|'A'|'B'|'C'|'D'|'E'|'F' => return true;
when 'a'|'b'|'c'|'d'|'e'|'f' => return true;
when others => return false;
end case;
return false;
end is_hex_char;
procedure vec_to_hex(vec : std_logic_vector; str : out string) is
variable temp_vec : std_logic_vector(str'length * 4 downto 1) := (others => '0');
variable j : integer;
variable my_vec : std_logic_vector(vec'range);
variable len, my_low, my_high : integer;
begin
my_vec := vec;
len := str'length;
my_low := vec'low;
my_high := vec'high;
if vec'length < temp_vec'length then
temp_vec(vec'length downto 1) := vec;
else
temp_vec := vec(vec'low + temp_vec'length - 1 downto vec'low);
end if;
for i in str'range loop
j := (str'right - i) * 4;
str(i) := nibble_to_hex(temp_vec(j+4 downto j+1));
end loop;
end vec_to_hex;
function vec_to_hex(vec : std_logic_vector; len : integer) return string is
variable str : string(1 to len);
begin
vec_to_hex(vec, str);
return str;
end vec_to_hex;
procedure write_string(variable my_line : inout line; s : string) is
begin
write(my_line, s);
end write_string;
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
function hchr(slv: std_logic_vector) return character is
begin
return hchr(unsigned(slv));
end function;
function hchr(slv: unsigned) return character is
variable v_fourbit : unsigned(3 downto 0);
variable v_result : character;
begin
v_fourbit := resize(slv, 4);
case v_fourbit is
when "0000" => v_result := '0';
when "0001" => v_result := '1';
when "0010" => v_result := '2';
when "0011" => v_result := '3';
when "0100" => v_result := '4';
when "0101" => v_result := '5';
when "0110" => v_result := '6';
when "0111" => v_result := '7';
when "1000" => v_result := '8';
when "1001" => v_result := '9';
when "1010" => v_result := 'A';
when "1011" => v_result := 'B';
when "1100" => v_result := 'C';
when "1101" => v_result := 'D';
when "1110" => v_result := 'E';
when "1111" => v_result := 'F';
when "ZZZZ" => v_result := 'z';
when "UUUU" => v_result := 'u';
when "XXXX" => v_result := 'x';
when others => v_result := '?';
end case;
return v_result;
end function;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
constant c_hexlen : integer := (slv'length + 3)/4;
alias slv_norm : std_logic_vector(slv'length - 1 downto 0) is slv;
variable v_longslv : std_logic_vector(c_hexlen * 4 - 1 downto 0) := (others => '0');
variable v_result : string(1 to c_hexlen);
variable v_fourbit : std_logic_vector(3 downto 0);
begin
v_longslv(slv_norm'range) := slv_norm;
for i in 0 to c_hexlen - 1 loop
v_fourbit := v_longslv(((i * 4) + 3) downto (i * 4));
case v_fourbit is
when "0000" => v_result(c_hexlen - i) := '0';
when "0001" => v_result(c_hexlen - i) := '1';
when "0010" => v_result(c_hexlen - i) := '2';
when "0011" => v_result(c_hexlen - i) := '3';
when "0100" => v_result(c_hexlen - i) := '4';
when "0101" => v_result(c_hexlen - i) := '5';
when "0110" => v_result(c_hexlen - i) := '6';
when "0111" => v_result(c_hexlen - i) := '7';
when "1000" => v_result(c_hexlen - i) := '8';
when "1001" => v_result(c_hexlen - i) := '9';
when "1010" => v_result(c_hexlen - i) := 'A';
when "1011" => v_result(c_hexlen - i) := 'B';
when "1100" => v_result(c_hexlen - i) := 'C';
when "1101" => v_result(c_hexlen - i) := 'D';
when "1110" => v_result(c_hexlen - i) := 'E';
when "1111" => v_result(c_hexlen - i) := 'F';
when "ZZZZ" => v_result(c_hexlen - i) := 'z';
when "UUUU" => v_result(c_hexlen - i) := 'u';
when "XXXX" => v_result(c_hexlen - i) := 'x';
when others => v_result(c_hexlen - i) := '?';
end case;
end loop;
return v_result;
end hstr;
-- converts an unsigned into a hex string.
function hstr(uns : unsigned) return string is
begin
return hstr(std_logic_vector(uns));
end;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' => sl := 'U';
when 'X' => sl := 'X';
when '0' => sl := '0';
when '1' => sl := '1';
when 'Z' => sl := 'Z';
when 'W' => sl := 'W';
when 'L' => sl := 'L';
when 'H' => sl := 'H';
when '-' => sl := '-';
when others => sl := 'X';
end case;
return sl;
end to_std_logic;
function hchr_to_std_logic_vector(c: character) return std_logic_vector is
variable v_result : std_logic_vector(3 downto 0);
begin
case c is
when '0' => v_result := "0000";
when '1' => v_result := "0001";
when '2' => v_result := "0010";
when '3' => v_result := "0011";
when '4' => v_result := "0100";
when '5' => v_result := "0101";
when '6' => v_result := "0110";
when '7' => v_result := "0111";
when '8' => v_result := "1000";
when '9' => v_result := "1001";
when 'a' => v_result := "1010";
when 'b' => v_result := "1011";
when 'c' => v_result := "1100";
when 'd' => v_result := "1101";
when 'e' => v_result := "1110";
when 'f' => v_result := "1111";
when 'A' => v_result := "1010";
when 'B' => v_result := "1011";
when 'C' => v_result := "1100";
when 'D' => v_result := "1101";
when 'E' => v_result := "1110";
when 'F' => v_result := "1111";
when others => v_result := "XXXX";
assert FALSE
report "Illegal character "& c & "in hex string! "
severity warning;
end case;
return v_result;
end function;
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
function hstr_to_integer(str: string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in 1 to len loop
case to_lower(str(i)) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'a' => digit := 10;
when 'b' => digit := 11;
when 'c' => digit := 12;
when 'd' => digit := 13;
when 'e' => digit := 14;
when 'f' => digit := 15;
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hstr_to_std_logic_vector(str: string; len: integer) return std_logic_vector is
variable digit : std_logic_vector(3 downto 0);
variable result : std_logic_vector((str'length * 4) - 1 downto 0);
begin
-- we can not use hstr_to_integer and then convert to hex, because the integer range is
-- limited
for i in str'range loop
case to_lower(str(str'length - i + 1)) is
when '0' => digit := "0000";
when '1' => digit := "0001";
when '2' => digit := "0010";
when '3' => digit := "0011";
when '4' => digit := "0100";
when '5' => digit := "0101";
when '6' => digit := "0110";
when '7' => digit := "0111";
when '8' => digit := "1000";
when '9' => digit := "1001";
when 'a' => digit := "1010";
when 'b' => digit := "1011";
when 'c' => digit := "1100";
when 'd' => digit := "1101";
when 'e' => digit := "1110";
when 'f' => digit := "1111";
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity error;
end case;
result((i * 4) - 1 downto (i - 1) * 4) := digit;
end loop;
return result(len - 1 downto 0);
end;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
function is_hchr(c : character) return boolean is
variable v_result : boolean;
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|
'8'|'9'|'A'|'B'|'C'|'D'|'E'|'F'|
'a'|'b'|'c'|'d'|'e'|'f' => v_result := true;
when others => v_result := false;
end case;
return v_result;
end function;
function strcmp(a: string; b: string) return boolean is
variable r : boolean := true;
begin
for i in a'range loop
if i > b'right then
if a(i) /= NUL then -- b is shorter and a doesn't terminate here.
return false;
else
return true; -- b is shorter, but a does terminate here
end if;
end if;
if a(i) /= b(i) then -- characters are not the same
return false;
end if;
if a(i) = NUL and b(i) = NUL then -- a and b have a string terminator at the same place
-- and previous characters were all the same
return true;
end if;
end loop;
-- if b is longer, then check if b has a terminator
if (b'right > a'right) then
if b(a'right + 1) /= NUL then
return false;
end if;
end if;
return true;
end strcmp;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
procedure print(file out_file: TEXT; new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
procedure print(file out_file: TEXT; char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
procedure str_read(file in_file: TEXT; res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT; new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(character'pos(my_char), 8));
end;
function resize(s: string; size: natural; default: character := ' ') return string is
variable result: string(1 to size) := (others => default);
begin
if s'length > size then
result := s(result'range);
else
result(s'range) := s;
end if;
return result;
end function;
end tl_string_util_pkg;
|
gpl-3.0
|
davidhorrocks/1541UltimateII
|
fpga/cart_slot/vhdl_sim/harness_reu.vhd
|
5
|
2141
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp;
signal phi2_tick : std_logic := '0';
signal reu_dma_n : std_logic := '1';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_reu: entity work.reu
generic map (
g_ram_tag => X"10",
g_extended => false,
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp,
-- system interface
phi2_tick => phi2_tick,
reu_dma_n => reu_dma_n,
size_ctrl => "111",
enable => '1',
-- memory interface
mem_req => mem_req,
mem_resp => mem_resp,
dma_req => dma_req,
dma_resp => dma_resp );
i_slot_master: entity work.slot_bus_master_bfm
generic map (
g_name => "slot master" )
port map (
clock => clock,
req => slot_req,
resp => slot_resp );
i_c64_memory: entity work.dma_bus_slave_bfm
generic map (
g_name => "c64_memory",
g_latency => 4 )
port map (
clock => clock,
req => dma_req,
resp => dma_resp );
i_reu_memory: entity work.mem_bus_slave_bfm
generic map (
g_name => "reu_memory",
g_latency => 2 )
port map (
clock => clock,
req => mem_req,
resp => mem_resp );
end harness;
|
gpl-3.0
|
sbourdeauducq/dspunit
|
top/dspunit.vhd
|
2
|
20739
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dspunit is
port (
--@inputs
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
--@outputs;
-- memory 0
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
-- memory 1
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
-- memory 2
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
-- cmd registers
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end dspunit;
--=----------------------------------------------------------------------------
architecture archi_dspunit of dspunit is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspalu_acc
generic (
sig_width : integer;
acc_width : integer
);
port (
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : in std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end component;
component dsp_cmdregs
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end component;
component cpflip
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component cpmem
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component fft
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
shift_flags_reg : in std_logic_vector((cmdreg_width - 1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector(sig_width downto 0);
result2 : in std_logic_vector(sig_width downto 0);
lut_out : in std_logic_vector((lut_out_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component dotcmul
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
length_kern_reg : in std_logic_vector((cmdreg_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((sig_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component dsplut
port (
clk : in std_logic;
lut_in : in std_logic_vector((lut_in_width - 1) downto 0);
lut_select : in std_logic_vector((lut_sel_width - 1) downto 0);
lut_out : out std_logic_vector((lut_out_width - 1) downto 0)
);
end component;
component dotopnorm
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_params : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((2*sig_width - 1) downto 0);
cmp_greater : in std_logic;
dsp_bus : out t_dsp_bus
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
component dotdiv
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
num_shift : in std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
div_q : in std_logic_vector((sig_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clr_acc : std_logic;
signal s_alu_result1 : std_logic_vector((sig_width - 1) downto 0);
signal s_alu_result_acc1 : std_logic_vector((acc_width - 1) downto 0);
signal s_alu_result2 : std_logic_vector((sig_width - 1) downto 0);
signal s_alu_result_acc2 : std_logic_vector((acc_width - 1) downto 0);
signal s_opflag_select : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select : std_logic_vector((opcode_width - 1) downto 0);
signal s_offset_0 : unsigned((cmdreg_width - 1) downto 0);
signal s_offset_1 : unsigned((cmdreg_width - 1) downto 0);
signal s_offset_2 : unsigned((cmdreg_width - 1) downto 0);
signal s_length0 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_length1 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_length2 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_gcount : unsigned(15 downto 0);
signal s_dsp_bus : t_dsp_bus;
signal s_op_cpflip_en : std_logic;
signal s_dsp_bus_cpflip : t_dsp_bus;
signal s_op_cpmem_en : std_logic;
signal s_dsp_bus_cpmem : t_dsp_bus;
signal s_op_fft_en : std_logic;
signal s_op_dotcmul_en : std_logic;
signal s_dsp_bus_fft : t_dsp_bus;
signal s_dsp_bus_dotcmul : t_dsp_bus;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_alu_cmp_reg : std_logic_vector((acc_width - 1) downto 0);
signal s_alu_cmp_out : std_logic;
signal s_cmp_greater : std_logic;
signal s_dsp_bus_dotopnorm : t_dsp_bus;
signal s_op_dotopnorm_en : std_logic;
signal s_dsp_bus_dotdiv : t_dsp_bus;
signal s_op_dotdiv_en : std_logic;
signal s_chain_acc : std_logic;
signal s_div_q : std_logic_vector((sig_width - 1) downto 0);
signal s_div_r : std_logic_vector((2*sig_width - 3) downto 0);
begin -- archs_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspalu_acc_1 : dspalu_acc
generic map (
sig_width => sig_width,
acc_width => acc_width)
port map (
a1 => s_dsp_bus.mul_in_a1,
b1 => s_dsp_bus.mul_in_b1,
a2 => s_dsp_bus.mul_in_a2,
b2 => s_dsp_bus.mul_in_b2,
clk => clk,
clr_acc => s_clr_acc,
acc_mode1 => s_dsp_bus.acc_mode1,
acc_mode2 => s_dsp_bus.acc_mode2,
alu_select => s_dsp_bus.alu_select,
cmp_mode => s_dsp_bus.cmp_mode,
cmp_pol => s_dsp_bus.cmp_pol,
cmp_store => s_dsp_bus.cmp_store,
chain_acc => s_chain_acc,
result1 => s_alu_result1,
result_acc1 => s_alu_result_acc1,
result2 => s_alu_result2,
result_acc2 => s_alu_result_acc2,
cmp_reg => s_alu_cmp_reg,
cmp_greater => s_cmp_greater,
cmp_out => s_alu_cmp_out);
dsp_cmdregs_1 : dsp_cmdregs
port map (
clk => clk,
clk_cpu => clk_cpu,
reset => reset,
op_done => s_dsp_bus.op_done,
addr_cmdreg => addr_cmdreg,
data_in_cmdreg => data_in_cmdreg,
wr_en_cmdreg => wr_en_cmdreg,
data_out_cmdreg => data_out_cmdreg,
offset_0 => s_offset_0,
offset_1 => s_offset_1,
offset_2 => s_offset_2,
length0 => s_length0,
length1 => s_length1,
length2 => s_length2,
opflag_select => s_opflag_select,
opcode_select => s_opcode_select,
irq => irq,
debug => open);
dsplut_1 : dsplut
port map (
clk => clk,
lut_in => s_dsp_bus.lut_in,
lut_select => s_dsp_bus.lut_select,
lut_out => s_lut_out);
cpflip_1 : cpflip
port map (
clk => clk,
op_en => s_op_cpflip_en,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
dsp_bus => s_dsp_bus_cpflip);
cpmem_1 : cpmem
port map (
clk => clk,
op_en => s_op_cpmem_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
opflag_select => s_opflag_select,
dsp_bus => s_dsp_bus_cpmem);
fft_1 : fft
port map (
clk => clk,
op_en => s_op_fft_en,
data_in_m0 => data_in_m0,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
shift_flags_reg => s_length1, --s_dsp_cmdregs(DSPADDR_LENGTH1),
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 1) downto (sig_width - 1)),
result2 => s_alu_result_acc2((2*sig_width - 1) downto (sig_width - 1)),
lut_out => s_lut_out,
dsp_bus => s_dsp_bus_fft);
dotcmul_1 : dotcmul
port map (
clk => clk,
op_en => s_op_dotcmul_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
length_kern_reg => s_length1, --s_dsp_cmdregs(DSPADDR_LENGTH1),
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 1) downto sig_width),
result2 => s_alu_result_acc2((2*sig_width - 1) downto sig_width),
dsp_bus => s_dsp_bus_dotcmul);
dotopnorm_1 : dotopnorm
port map (
clk => clk,
op_en => s_op_dotopnorm_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0,
offset_params => s_length1,
offset_result => s_length2,
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 2) downto (sig_width - 1)),
result2 => s_alu_result_acc2((acc_width - 1) downto (acc_width - 2*sig_width)),
cmp_greater => s_cmp_greater,
dsp_bus => s_dsp_bus_dotopnorm);
dspdiv_1 : dspdiv
generic map (
sig_width => sig_width)
port map (
num => s_dsp_bus.div_num,
den => s_dsp_bus.div_den,
clk => clk,
q => s_div_q,
r => s_div_r);
dotdiv_1 : dotdiv
port map (
clk => clk,
op_en => s_op_dotdiv_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0,
offset_result => s_length1,
num_shift => s_length2,
opflag_select => s_opflag_select,
div_q => s_div_q,
dsp_bus => s_dsp_bus_dotdiv);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Global counter
-------------------------------------------------------------------------------
p_count : process (clk)
begin -- process p_count
if rising_edge(clk) then -- rising clock edge
if s_dsp_bus.gcounter_reset = '1' then
s_gcount <= (others => '0');
else
s_gcount <= s_gcount + 1;
end if;
end if;
end process p_count;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- reading of config registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- multiplexer of the dsp unit bus
-------------------------------------------------------------------------------
s_op_cpflip_en <= '1' when s_opcode_select = opcode_cpflip else '0';
s_op_cpmem_en <= '1' when s_opcode_select = opcode_cpmem else '0';
s_op_fft_en <= '1' when s_opcode_select = opcode_fft else '0';
s_op_dotcmul_en <= '1' when s_opcode_select = opcode_dotcmul else '0';
s_op_dotopnorm_en <= '1' when s_opcode_select = opcode_dotopnorm else '0';
s_op_dotdiv_en <= '1' when s_opcode_select = opcode_dotdiv else '0';
s_dsp_bus <=
s_dsp_bus_cpflip when s_opcode_select = opcode_cpflip else
s_dsp_bus_cpmem when s_opcode_select = opcode_cpmem else
s_dsp_bus_fft when s_opcode_select = opcode_fft else
s_dsp_bus_dotcmul when s_opcode_select = opcode_dotcmul else
s_dsp_bus_dotopnorm when s_opcode_select = opcode_dotopnorm else
s_dsp_bus_dotdiv when s_opcode_select = opcode_dotdiv else
c_dsp_bus_init;
-------------------------------------------------------------------------------
-- bus to output ports
-------------------------------------------------------------------------------
-- memory 0
data_out_m0 <= s_dsp_bus.data_out_m0;
addr_r_m0 <= std_logic_vector(s_dsp_bus.addr_r_m0 + s_offset_0);
addr_w_m0 <= std_logic_vector(s_dsp_bus.addr_w_m0 + s_offset_0);
wr_en_m0 <= s_dsp_bus.wr_en_m0;
c_en_m0 <= s_dsp_bus.c_en_m0;
-- memory 1
data_out_m1 <= s_dsp_bus.data_out_m1;
addr_m1 <= std_logic_vector(s_dsp_bus.addr_m1 + s_offset_1);
wr_en_m1 <= s_dsp_bus.wr_en_m1;
c_en_m1 <= s_dsp_bus.c_en_m1;
-- memory 2
data_out_m2 <= s_dsp_bus.data_out_m2;
addr_m2 <= std_logic_vector(s_dsp_bus.addr_m2 + s_offset_2);
wr_en_m2 <= s_dsp_bus.wr_en_m2;
c_en_m2 <= s_dsp_bus.c_en_m2;
op_done <= s_dsp_bus.op_done;
s_clr_acc <= not reset;
end archi_dspunit;
-------------------------------------------------------------------------------
|
gpl-3.0
|
sbourdeauducq/dspunit
|
sim/bench_div.vhd
|
2
|
4333
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=3000ns
-->SIMSAVFILE=dspdiv.sav
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity bench_div is
end bench_div;
--=----------------------------------------------------------------------------
architecture archi_bench_div of bench_div is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_sig_width : integer := 16;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_num : std_logic_vector((2*c_sig_width - 1) downto 0);
signal s_den : std_logic_vector((c_sig_width - 1) downto 0);
signal s_q : std_logic_vector((c_sig_width - 1) downto 0);
signal s_r : std_logic_vector((2*c_sig_width - 3) downto 0);
begin -- archs_bench_div
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspdiv_1 : dspdiv
generic map (
sig_width => c_sig_width)
port map (
num => s_num,
den => s_den,
clk => s_clk,
q => s_q,
r => s_r);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_num <= x"00050000", x"05000000" after 21 ns, x"00050000" after 31 ns;
s_den <= x"0406", x"0400" after 11 ns, x"FBFA" after 41 ns, x"0400" after 51 ns;
-- s_num <= x"00050000",x"00050000" after 11 ns, x"FFFB0000" after 21 ns;
-- s_den <= x"0406",x"FC00" after 31 ns;
end archi_bench_div;
-------------------------------------------------------------------------------
|
gpl-3.0
|
JL-Grande/Ascensor_SED
|
ASCENSOR/dec_flechas.vhd
|
1
|
486
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dec_flechas is
Port ( action : in STD_LOGIC_VECTOR (1 DOWNTO 0);
led_flechas : out STD_LOGIC_VECTOR (6 downto 0);
flecha_ctrl : out STD_LOGIC);
end dec_flechas;
architecture dataflow of dec_flechas is
begin
flecha_ctrl <= '0';
WITH action SELECT
led_flechas <= "0011101" WHEN "11", --Subiendo
"1100011" WHEN "00", --Bajando
"1111110" WHEN others; --Parado
END ARCHITECTURE dataflow;
|
gpl-3.0
|
JL-Grande/Ascensor_SED
|
ASCENSOR/dec_piso_seleccion.vhd
|
1
|
665
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity dec_piso_seleccion is
Port ( piso_code : in STD_LOGIC_VECTOR (1 downto 0);
piso0 : out STD_LOGIC;
piso1 : out STD_LOGIC;
piso2 : out STD_LOGIC);
end entity dec_piso_seleccion;
architecture dataflow of dec_piso_seleccion is
begin
WITH piso_code SELECT
piso0 <= '1' WHEN "01",
'0' WHEN others;
WITH piso_code SELECT
piso1 <= '1' WHEN "10",
'0' WHEN others;
WITH piso_code SELECT
piso2 <= '1' WHEN "11",
'0' WHEN others;
end architecture dataflow;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/cart_slot/vhdl_source/reu_pkg.vhd
|
4
|
1402
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/zpu/vhdl_source/zpu.vhd
|
5
|
8493
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/6502/vhdl_sim/tb_data_oper.vhd
|
5
|
4942
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
gpl-3.0
|
emabello42/FREAK-on-FPGA
|
embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/example_design/ROM_GAUSS_COE_exdes.vhd
|
1
|
4502
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_GAUSS_COE_exdes is
PORT (
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
end ROM_GAUSS_COE_exdes;
architecture xilinx of ROM_GAUSS_COE_exdes is
SIGNAL CLK_i : std_logic;
component ROM_GAUSS_COE is
PORT (
CLK : IN STD_LOGIC;
WE : IN STD_LOGIC;
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_GAUSS_COE
port map (
CLK => CLK_i,
WE => WE,
SPO => SPO,
A => A,
D => D
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/ulpi_bus.vhd
|
1
|
8362
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
operational : in std_logic := '1';
-- chirp interface
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
signal bus_has_our_data : std_logic;
type t_state is ( idle, chirp, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1 and operational;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d3;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif do_chirp='1' then
if ULPI_DIR='0' then
ulpi_last <= '0';
state <= chirp;
end if;
ulpi_data_out <= X"40"; -- PIDless packet
elsif tx_valid = '1' and tx_start = '1' then
if ULPI_DIR='0' then
ulpi_last <= tx_last;
state <= transmit;
end if;
ulpi_data_out <= tx_data;
end if;
when chirp =>
if ULPI_NXT = '1' then
if do_chirp = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= (others => chirp_data);
end if;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
when writing_data =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= X"00";
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '1';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write, bus_has_our_data)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start; -- first byte is transferred to register
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and bus_has_our_data and tx_valid and not ulpi_last; -- phy accepted this data.
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when bus_has_our_data = '1' else (others => 'Z');
bus_has_our_data <= '1' when ULPI_DIR='0' and ulpi_dir_d1='0' else '0';
end gideon;
|
gpl-3.0
|
emabello42/FREAK-on-FPGA
|
embeddedretina_ise/ROM_PAIRS.vhd
|
1
|
10417
|
--Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:14:30 05/16/2014
-- Design Name:
-- Module Name: ROM_PAIRS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ROM_PAIRS is
port(
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
points1 : out T_POINT_INDEX;
points2 : out T_POINT_INDEX
);
end ROM_PAIRS;
architecture Behavioral of ROM_PAIRS is
constant sROM_PAIRS : T_ROM_PAIRS :=
(
0 => (28,26), 1 => (29,25), 2 => (40,38), 3 => (32,15), 4 => (19,10), 5 => (10,7), 6 => (25,11), 7 => (42,13), 8 => (39,33), 9 => (33,15), 10 => (38,16), 11 => (21,20), 12 => (29,11), 13 => (20,15), 14 => (5,1), 15 => (33,32), 16 => (17,13), 17 => (23,12), 18 => (9,3), 19 => (25,6), 20 => (18,12), 21 => (41,37), 22 => (22,19), 23 => (4,2), 24 => (11,6), 25 => (6,0), 26 => (11,0), 27 => (38,14), 28 => (9,8), 29 => (29,6), 30 => (34,31), 31 => (16,14), 32 => (39,20), 33 => (37,29), 34 => (36,30), 35 => (40,2), 36 => (35,30), 37 => (31,22), 38 => (33,21), 39 => (32,20), 40 => (23,18), 41 => (36,35), 42 => (39,21), 43 => (28,14), 44 => (19,7), 45 => (40,16), 46 => (39,32), 47 => (8,3), 48 => (37,6), 49 => (41,25), 50 => (33,20), 51 => (40,14), 52 => (37,11), 53 => (36,24), 54 => (22,10), 55 => (41,11), 56 => (21,15), 57 => (22,7), 58 => (41,29), 59 => (13,5), 60 => (37,25), 61 => (31,19), 62 => (41,6), 63 => (38,4), 64 => (16,2), 65 => (32,21), 66 => (34,22), 67 => (38,28), 68 => (26,3), 69 => (26,14), 70 => (34,10), 71 => (31,10), 72 => (28,16), 73 => (31,7), 74 => (34,19), 75 => (28,3), 76 => (17,1), 77 => (14,2), 78 => (28,2), 79 => (26,2), 80 => (35,24), 81 => (38,26), 82 => (40,28), 83 => (21,8), 84 => (21,3), 85 => (30,24), 86 => (17,5), 87 => (40,26), 88 => (26,16), 89 => (14,4), 90 => (28,4), 91 => (34,7), 92 => (16,4), 93 => (39,9), 94 => (20,3), 95 => (39,8), 96 => (38,3), 97 => (41,23), 98 => (13,1), 99 => (20,9), 100 => (25,17), 101 => (26,4), 102 => (39,27), 103 => (20,8), 104 => (14,9), 105 => (31,1), 106 => (35,18), 107 => (13,0), 108 => (34,1), 109 => (40,3), 110 => (37,23), 111 => (17,0), 112 => (41,18), 113 => (14,3), 114 => (17,6), 115 => (18,11), 116 => (37,13), 117 => (21,9), 118 => (29,13), 119 => (27,15), 120 => (29,12), 121 => (29,17), 122 => (12,11), 123 => (13,11), 124 => (32,27), 125 => (23,6), 126 => (37,17), 127 => (25,12), 128 => (33,27), 129 => (6,5), 130 => (31,5), 131 => (37,18), 132 => (16,3), 133 => (30,23), 134 => (30,18), 135 => (41,13), 136 => (12,6), 137 => (15,8), 138 => (23,0), 139 => (15,3), 140 => (25,13), 141 => (7,4), 142 => (18,0), 143 => (36,18), 144 => (29,5), 145 => (35,12), 146 => (35,23), 147 => (16,8), 148 => (25,5), 149 => (22,1), 150 => (25,1), 151 => (13,6), 152 => (11,1), 153 => (23,11), 154 => (27,20), 155 => (10,1), 156 => (29,1), 157 => (27,9), 158 => (9,2), 159 => (14,8), 160 => (19,5), 161 => (38,7), 162 => (15,9), 163 => (34,17), 164 => (12,0), 165 => (27,21), 166 => (36,23), 167 => (16,9), 168 => (27,8), 169 => (29,18), 170 => (18,6), 171 => (41,1), 172 => (5,0), 173 => (25,23), 174 => (28,15), 175 => (3,2), 176 => (26,15), 177 => (42,30), 178 => (4,3), 179 => (40,10), 180 => (10,2), 181 => (1,0), 182 => (19,4), 183 => (26,21), 184 => (22,5), 185 => (7,5), 186 => (19,1), 187 => (17,11), 188 => (34,13), 189 => (34,0), 190 => (8,4), 191 => (24,18), 192 => (29,23), 193 => (38,21), 194 => (39,14), 195 => (28,20), 196 => (40,7), 197 => (24,12), 198 => (24,23), 199 => (39,28), 200 => (34,4), 201 => (39,26), 202 => (38,19), 203 => (39,16), 204 => (21,14), 205 => (31,0), 206 => (38,20), 207 => (32,2), 208 => (31,2), 209 => (22,4), 210 => (16,7), 211 => (40,22), 212 => (30,11), 213 => (22,2), 214 => (33,16), 215 => (31,17), 216 => (40,20), 217 => (25,18), 218 => (6,1), 219 => (33,4), 220 => (40,21), 221 => (30,6), 222 => (33,26), 223 => (19,2), 224 => (11,5), 225 => (33,2), 226 => (38,10), 227 => (31,4), 228 => (8,2), 229 => (21,2), 230 => (36,0), 231 => (42,38), 232 => (18,17), 233 => (23,13), 234 => (40,19), 235 => (13,10), 236 => (10,4), 237 => (32,16), 238 => (28,21), 239 => (7,2), 240 => (32,4), 241 => (15,2), 242 => (32,28), 243 => (13,12), 244 => (20,4), 245 => (17,7), 246 => (16,15), 247 => (20,2), 248 => (20,16), 249 => (26,20), 250 => (17,12), 251 => (12,5), 252 => (15,14), 253 => (14,10), 254 => (34,2), 255 => (42,9), 256 => (18,5), 257 => (23,1), 258 => (21,4), 259 => (24,0), 260 => (30,29), 261 => (26,7), 262 => (38,22), 263 => (19,17), 264 => (28,7), 265 => (7,3), 266 => (31,11), 267 => (9,4), 268 => (22,0), 269 => (35,25), 270 => (19,0), 271 => (23,5), 272 => (12,1), 273 => (15,4), 274 => (41,24), 275 => (22,13), 276 => (19,16), 277 => (28,10), 278 => (37,35), 279 => (37,24), 280 => (10,5), 281 => (4,1), 282 => (41,30), 283 => (31,14), 284 => (10,3), 285 => (32,26), 286 => (7,1), 287 => (18,1), 288 => (5,2), 289 => (36,29), 290 => (38,33), 291 => (36,25), 292 => (34,16), 293 => (38,34), 294 => (41,10), 295 => (40,31), 296 => (19,3), 297 => (7,0), 298 => (22,6), 299 => (26,10), 300 => (27,2), 301 => (22,3), 302 => (10,8), 303 => (23,17), 304 => (11,7), 305 => (19,11), 306 => (10,0), 307 => (19,6), 308 => (22,14), 309 => (40,32), 310 => (37,7), 311 => (27,4), 312 => (33,28), 313 => (35,17), 314 => (18,13), 315 => (20,14), 316 => (10,9), 317 => (22,17), 318 => (27,14), 319 => (21,16), 320 => (22,11), 321 => (30,17), 322 => (37,34), 323 => (37,19), 324 => (34,12), 325 => (5,4), 326 => (41,22), 327 => (31,16), 328 => (31,3), 329 => (40,1), 330 => (34,3), 331 => (29,10), 332 => (19,8), 333 => (28,27), 334 => (8,7), 335 => (40,39), 336 => (35,13), 337 => (35,29), 338 => (27,16), 339 => (14,7), 340 => (36,13), 341 => (30,13), 342 => (2,1), 343 => (30,25), 344 => (37,10), 345 => (30,5), 346 => (22,9), 347 => (16,10), 348 => (17,10), 349 => (19,13), 350 => (19,14), 351 => (29,24), 352 => (11,10), 353 => (40,27), 354 => (27,26), 355 => (13,4), 356 => (16,1), 357 => (38,5), 358 => (22,8), 359 => (25,10), 360 => (17,2), 361 => (35,1), 362 => (38,27), 363 => (34,14), 364 => (31,12), 365 => (41,31), 366 => (40,17), 367 => (22,16), 368 => (7,6), 369 => (13,7), 370 => (34,25), 371 => (25,7), 372 => (39,38), 373 => (26,1), 374 => (31,29), 375 => (41,36), 376 => (25,24), 377 => (41,7), 378 => (14,5), 379 => (39,7), 380 => (5,3), 381 => (28,19), 382 => (16,5), 383 => (37,22), 384 => (37,36), 385 => (14,1), 386 => (24,17), 387 => (38,13), 388 => (24,1), 389 => (17,4), 390 => (15,7), 391 => (3,1), 392 => (13,2), 393 => (41,35), 394 => (41,19), 395 => (2,0), 396 => (29,7), 397 => (26,22), 398 => (34,23), 399 => (31,28), 400 => (24,13), 401 => (37,30), 402 => (6,4), 403 => (39,10), 404 => (28,1), 405 => (12,10), 406 => (12,7), 407 => (15,10), 408 => (4,0), 409 => (34,29), 410 => (19,12), 411 => (38,31), 412 => (20,7), 413 => (31,18), 414 => (21,7), 415 => (26,19), 416 => (26,5), 417 => (28,22), 418 => (19,15), 419 => (22,12), 420 => (34,26), 421 => (21,10), 422 => (40,0), 423 => (20,10), 424 => (40,13), 425 => (22,15), 426 => (41,4), 427 => (9,5), 428 => (38,32), 429 => (34,18), 430 => (13,3), 431 => (38,0), 432 => (25,22), 433 => (39,19), 434 => (38,17), 435 => (17,3), 436 => (31,15), 437 => (31,25), 438 => (14,0), 439 => (40,34), 440 => (40,33), 441 => (18,10), 442 => (17,16), 443 => (31,23), 444 => (39,22), 445 => (23,10), 446 => (29,19), 447 => (29,4), 448 => (34,15), 449 => (16,0), 450 => (25,19), 451 => (37,2), 452 => (17,14), 453 => (18,7), 454 => (25,2), 455 => (31,26), 456 => (32,19), 457 => (23,7), 458 => (17,9), 459 => (29,22), 460 => (14,6), 461 => (22,20), 462 => (28,17), 463 => (23,19), 464 => (22,21), 465 => (6,3), 466 => (15,1), 467 => (27,7), 468 => (41,34), 469 => (31,20), 470 => (17,8), 471 => (33,22), 472 => (16,11), 473 => (16,13), 474 => (28,0), 475 => (12,2), 476 => (14,11), 477 => (14,13), 478 => (11,3), 479 => (27,10), 480 => (23,22), 481 => (20,19), 482 => (37,31), 483 => (34,21), 484 => (26,13), 485 => (39,1), 486 => (34,28), 487 => (26,0), 488 => (29,2), 489 => (21,19), 490 => (8,0), 491 => (25,4), 492 => (20,1), 493 => (19,18), 494 => (15,5), 495 => (16,6), 496 => (31,21), 497 => (21,1), 498 => (33,19), 499 => (33,5), 500 => (12,4), 501 => (21,5), 502 => (37,4), 503 => (22,18), 504 => (9,0), 505 => (34,20), 506 => (28,11), 507 => (35,10), 508 => (26,6), 509 => (32,22), 510 => (30,7), 511 => (41,2)
);
begin
rom: process(clk)
variable pointIndex1: integer range 0 to 42 := 0;
variable pointIndex2: integer range 0 to 42 := 0;
begin
if rising_edge(clk) then
for i in 0 to 15 loop
pointIndex1 := sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(0);
pointIndex2 := sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(1);
points1(i) <= std_logic_vector(to_unsigned(pointIndex1, points1(0)'length)) ;
points2(i) <= std_logic_vector(to_unsigned(pointIndex2, points2(0)'length)) ;
end loop;
end if;
--sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(0);
end process rom;
end Behavioral;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/1541/vhdl_source/gcr_encoder.vhd
|
5
|
1636
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/usb/vhdl_source/usb_host_io.vhd
|
3
|
15325
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_io is
generic (
g_simulation : boolean := false );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_host_io;
architecture wrap of usb_host_io is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(10 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic;
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
-- signal reset_pkt : std_logic;
-- signal reset_valid : std_logic;
-- signal reset_last : std_logic;
-- signal reset_data : std_logic_vector(7 downto 0);
signal send_reset_data : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal reset_done : std_logic;
signal sof_enable : std_logic;
signal scan_enable : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal abort : std_logic;
signal sys_addr_i : std_logic_vector(sys_io_req.address'range);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic_vector(2 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_read : std_logic;
signal sys_cmd_write : std_logic;
signal sys_cmd_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_full : std_logic;
signal sys_cmd_count : std_logic_vector(2 downto 0);
signal sys_resp_get : std_logic;
signal sys_resp_data : std_logic_vector(8 downto 0);
signal sys_resp_empty : std_logic;
signal cmd_get : std_logic;
signal cmd_empty : std_logic;
signal cmd_data : std_logic_vector(7 downto 0);
signal resp_put : std_logic;
signal resp_full : std_logic;
signal resp_data : std_logic_vector(8 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to bus reset unit
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to read/write registers and reset packets
send_reset_data => send_reset_data,
reset_data => reset_data(0),
reset_last => reset_last );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
generic map (
g_simulation => g_simulation )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Command / response interface
cmd_get => cmd_get,
cmd_empty => cmd_empty,
cmd_data => cmd_data,
resp_put => resp_put,
resp_full => resp_full,
resp_data => resp_data,
-- status
status => status,
usb_busy => usb_busy,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_rdata => rx_data,
reg_wdata => reg_wdata,
reg_address => reg_addr,
reg_ack => reg_ack,
-- interface to packet transmitter
send_packet => send_reset_data,
user_data => reset_data,
user_last => reset_last,
user_valid => open );
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => sys_cmd_write,
wr_din => sys_io_req.data,
wr_flush => '0',
wr_count => sys_cmd_count,
wr_full => open,
wr_almost_full => sys_cmd_full,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => ulpi_clock,
rd_reset => ulpi_reset,
rd_en => cmd_get,
rd_dout => cmd_data,
rd_count => open,
rd_empty => cmd_empty,
rd_almost_empty => open,
rd_error => open );
i_resp_fifo: entity work.async_fifo
generic map (
g_data_width => 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => resp_put,
wr_din => resp_data,
wr_flush => '0',
wr_count => open,
wr_full => resp_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => sys_resp_get,
rd_dout => sys_resp_data,
rd_count => open,
rd_empty => sys_resp_empty,
rd_almost_empty => open,
rd_error => open );
-- BUS INTERFACE --
-- command / response output word generator
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_resp_get <= '0';
case sys_io_req.address(1 downto 0) is
when "00" =>
sys_cmd_rdata <= sys_resp_data(7 downto 0);
when "01" =>
sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8);
when "10" =>
sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count;
when "11" =>
sys_cmd_rdata <= X"00";
sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one
when others =>
null;
end case;
end if;
end process;
sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range));
sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12);
sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11);
sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11);
sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11);
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp.ack <= sys_io_req.read or sys_io_req.write;
sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11));
end if;
end process;
with sys_sel_d select sys_io_resp.data <=
sys_buf_rdata when "110" | "111",
sys_descr_rdata when "100",
sys_cmd_rdata when "101",
X"00" when others;
end wrap;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/cpu_unit/mblite/hw/core/execute.vhd
|
1
|
11793
|
----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
break_in_progress : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i, r, reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable special_reg : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
if exec_i.ctrl_wrb.reg_d = "00000" then
v.ctrl_wrb.reg_write := '0';
end if;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- In case more than just one special register needs to be supported, a multiplexer can be made here. For now, just MSR.
special_reg := (31 => reg.carry,
3 => reg.break_in_progress,
2 => reg.carry,
1 => r.interrupt_enable,
others => '0' );
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_SPR => alu_src_a := special_reg;
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
report "Invalid ALU operation" severity FAILURE;
end case;
if reg.flush_ex = '0' then
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
-- MSR operations
case exec_i.ctrl_ex.msr_op is
when MSR_SET_I =>
v.interrupt_enable := '1';
when MSR_CLR_I =>
v.interrupt_enable := '0';
when LOAD_MSR =>
v_reg.break_in_progress := dat_a(3);
v_reg.carry := dat_a(2);
v.interrupt_enable := dat_a(1);
when MSR_SET =>
v_reg.break_in_progress := exec_i.imm(3) or reg.break_in_progress;
v_reg.carry := exec_i.imm(2) or reg.carry;
v.interrupt_enable := exec_i.imm(1) or r.interrupt_enable;
when MSR_CLR =>
v_reg.break_in_progress := not exec_i.imm(3) and reg.break_in_progress;
v_reg.carry := not exec_i.imm(2) and reg.carry;
v.interrupt_enable := not exec_i.imm(1) and r.interrupt_enable;
when others =>
null;
end case;
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
-- Handle CMPU and CMP
if ( exec_i.ctrl_ex.operation = "11" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := not result_add(CFG_DMEM_WIDTH); -- unsigned = bit 32 of result
elsif ( exec_i.ctrl_ex.operation = "01" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := (result_add(CFG_DMEM_WIDTH) xor alu_src_a(CFG_DMEM_WIDTH-1) xor alu_src_b(CFG_DMEM_WIDTH-1)); -- signed
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.interrupt_enable <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.break_in_progress <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/sid6581/vhdl_source/sid_ctrl.vhd
|
6
|
1641
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_ctrl is
generic (
g_num_voices : natural := 8 );
port (
clock : in std_logic;
reset : in std_logic;
start_iter : in std_logic;
voice_osc : out unsigned(3 downto 0);
enable_osc : out std_logic );
end sid_ctrl;
architecture gideon of sid_ctrl is
signal voice_cnt : unsigned(3 downto 0);
signal enable : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
voice_cnt <= X"0";
enable <= '0';
elsif start_iter='1' then
voice_cnt <= X"0";
enable <= '1';
elsif voice_cnt = g_num_voices-1 then
voice_cnt <= X"0";
enable <= '0';
elsif enable='1' then
voice_cnt <= voice_cnt + 1;
enable <= '1';
end if;
end if;
end process;
voice_osc <= voice_cnt;
enable_osc <= enable;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v7.vhd
|
5
|
21232
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v7 is
generic (
g_simulation : boolean := false;
g_read_fifo : boolean := false;
q_tcko_data : time := 100 ps;
A_Width : integer := 13;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
req : in t_mem_burst_32_req;
resp : out t_mem_burst_32_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_A : out std_logic_vector(A_Width-1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v7;
architecture Gideon of ext_mem_ctrl_v7 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002B", "000" ), -- mode register, burstlen=8, writelen=8, CAS lat = 2, interleaved
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ) );
type t_ints is array(natural range <>) of integer;
constant c_delays : t_ints(0 to 15) := (
2, 4, 2, 3, -- R2R (other row&other bank, other row, other bank, same row+bank)
4, 5, 4, 5, -- R2W
2, 5, 2, 3, -- W2R
2, 4, 2, 3 );-- W2W
type t_state is (boot, init, idle, sd_cas );
signal state : t_state;
signal sdram_d_o : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal sdram_d_t : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal wdata_tri : std_logic_vector(8 downto 0) := (others => '1');
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal mem_a_i : std_logic_vector(SDRAM_A'range) := (others => '0');
signal mem_ba_i : std_logic_vector(SDRAM_BA'range) := (others => '0');
signal cs_n_i : std_logic := '1';
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal do_refresh_d : std_logic := '0';
signal trigger_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_out : std_logic_vector(15 downto 0) := (others => '0');
signal wdata : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_i : std_logic_vector(35 downto 0) := (others => '0');
signal wdata_av : std_logic;
signal fifo_wdata_in : std_logic_vector(35 downto 0);
signal wdqm : std_logic_vector(1 downto 0);
signal dqm_override : std_logic := '1';
-- signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(5 downto 0) := "000000";
signal burst_start : std_logic_vector(5 downto 0) := "000000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal same_bank : std_logic;
signal last_row : std_logic_vector(12 downto 0) := "0101011010101";
signal addr_row : std_logic_vector(12 downto 0);
signal same_row : std_logic;
signal addr_column : std_logic_vector(9 downto 0);
signal next_activate : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal rwn_i : std_logic := '1';
signal tag_fifo : std_logic_vector(7 downto 0);
signal rdata_tag : std_logic_vector(7 downto 0);
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic := '0'; -- forced low for when there is no fifo
signal push_cmd : std_logic;
signal push_read_cmd : std_logic;
signal crazy_index_slv : std_logic_vector(3 downto 0);
signal crazy_index : integer range 0 to 15;
signal wtoggle : std_logic;
signal wdata_get : std_logic;
begin
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av and not do_refresh_d;
push_cmd <= req.request and not cmd_af;
push_read_cmd <= push_cmd and req.read_writen;
resp.ready <= not cmd_af;
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(address_fifo'length);
addr_bank <= address_fifo(14 downto 13);
addr_row <= address_fifo(24 downto 15) & address_fifo(12 downto 10);
addr_column <= address_fifo( 9 downto 0);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_tag_fifo: entity work.srl_fifo
generic map (
Width => 8,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => burst_start(1),
PutElement => push_read_cmd,
FlushFifo => '0',
DataIn => req.request_tag,
DataOut => tag_fifo,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => open );
rdata_out <= rdata_lo & rdata_hi;
b_read: block
signal rtoggle : std_logic;
signal rsp_data : std_logic_vector(31 downto 0);
signal rsp_data_tag : std_logic_vector(7 downto 0);
signal rsp_rdata_av : std_logic;
begin
-- data compacter 16->32
process(clock)
begin
if rising_edge(clock) then
-- handle reads
rsp_rdata_av <= '0';
if dack(0)='1' then
rtoggle <= not rtoggle;
if rtoggle='1' then
rsp_data(31 downto 16) <= rdata_out;
rsp_data_tag <= rdata_tag;
rsp_rdata_av <= '1';
else
rsp_data(15 downto 0) <= rdata_out;
end if;
end if;
-- reset
if reset='1' then
rtoggle <= '0';
rsp_data <= (others => '0');
rsp_data_tag <= (others => '0');
end if;
end if;
end process;
r_no_read_fifo: if not g_read_fifo generate
resp.rdata_av <= rsp_rdata_av;
resp.data <= rsp_data;
resp.data_tag <= rsp_data_tag;
end generate;
r_read_fifo: if g_read_fifo generate
i_read_fifo: entity work.srl_fifo
generic map (
Width => 40,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => rsp_rdata_av,
FlushFifo => '0',
DataIn(39 downto 32) => rsp_data_tag,
DataIn(31 downto 0) => rsp_data,
DataOut(39 downto 32) => resp.data_tag,
DataOut(31 downto 0) => resp.data,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => resp.rdata_av );
end generate;
end block;
fifo_wdata_in <= req.byte_en & req.data;
i_write_fifo: entity work.SRL_fifo
generic map (
Width => (c_data_width*9)/8,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => wdata_get,
PutElement => req.data_push,
FlushFifo => '0',
DataIn => fifo_wdata_in,
DataOut => wdata_i,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => wdata_av );
process(clock)
begin
if rising_edge(clock) then
if dnext(0)='1' then
wtoggle <= not wtoggle;
end if;
if reset='1' then
wtoggle <= '0';
end if;
end if;
end process;
wdata_get <= dnext(0) and wtoggle;
wdata(15 downto 0) <= wdata_i(15 downto 0) after 1 ns when wtoggle='0' else wdata_i(31 downto 16) after 1 ns;
wdata(17 downto 16) <= wdata_i(33 downto 32) after 1 ns when wtoggle='0' else wdata_i(35 downto 34) after 1 ns;
wdqm <= (others => '1') when dqm_override='1' else
(others => '0') when dnext(0)='0' else not wdata(17 downto 16);
same_row <= '1' when addr_row = last_row else '0';
same_bank <= '1' when addr_bank = last_bank else '0';
crazy_index_slv <= not rwn_i & not rwn_fifo & same_row & same_bank;
crazy_index <= to_integer(unsigned(crazy_index_slv));
trigger_refresh <= do_refresh_d and not (inhibit_d or inhibit);
process(clock)
procedure send_refresh_cmd is
begin
if next_delay = 0 then
do_refresh <= '0';
do_refresh_d <= '0';
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
col_addr <= addr_column;
last_bank <= addr_bank;
last_row <= addr_row;
mem_a_i(addr_row'range) <= addr_row;
mem_ba_i <= addr_bank;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
end procedure;
procedure issue_read_or_write is
begin
mem_a_i(9 downto 0) <= col_addr;
do_refresh_d <= do_refresh;
if req_i='0' or do_refresh='1' then
if rwn_i='0' then
next_delay <= 5;
else
next_delay <= 4;
end if;
mem_a_i(10) <= '1'; -- auto precharge
next_activate <= '1';
else
next_delay <= c_delays(crazy_index);
mem_a_i(10) <= not (same_row and same_bank); -- do not AP when we'll continue in same row
next_activate <= not (same_row and same_bank); -- only activate next time if we also AP.
end if;
if delay=0 then
if rwn_i='0' then
if wdata_av='1' then
wdata_tri(7 downto 0) <= (others => '0') after 1 ns;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
dnext <= "1111" after 1 ns;
state <= idle;
end if;
else
if rdata_af='0' then
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
dack(dack'high downto dack'high-3) <= (others => '1');
burst_start(2) <= '1';
state <= idle;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
cs_n_i <= '1' after 1 ns;
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
if burst_start(1)='1' then
rdata_tag <= tag_fifo;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
wdata_tri <= "11" & wdata_tri(wdata_tri'high downto 2) after 1 ns;
dack <= '0' & dack(dack'high downto 1);
burst_start <= '0' & burst_start(burst_start'high downto 1);
dnext <= '0' & dnext(dnext'high downto 1) after 1 ns;
case state is
when boot =>
enable_sdram <= '1';
if g_simulation then
state <= init;
elsif refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
mem_ba_i <= (others => '0'); -- for DDR and such, maybe the upper 2/3 bits
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if next_delay = 0 then
next_delay <= 7;
cs_n_i <= '0' after 1 ns;
if init_cnt = c_init_array'high then
state <= idle;
dqm_override <= '0';
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' then
if next_activate='1' and next_delay=0 then
accept_req;
elsif next_activate='0' and next_delay=1 then
rwn_i <= rwn_fifo;
col_addr <= addr_column;
state <= sd_cas;
end if;
else
do_refresh_d <= do_refresh;
end if;
end if;
when sd_cas =>
issue_read_or_write;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
rdata_tag <= (others => '0');
dqm_override <= '1';
state <= boot;
wdata_tri <= (others => '0');
delay <= 0;
next_delay <= 0;
do_refresh <= '0';
do_refresh_d <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
next_activate <= '1';
rwn_i <= '1';
end if;
end if;
end process;
-- Generate rack; the signal that indicates that a request is going to be issued
-- and thus taken from the command fifo.
process(state, trigger_refresh, inhibit, req_i, next_delay, next_activate)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
null;
elsif inhibit='0' and req_i='1' then
if next_activate='1' and next_delay = 0 then
rack <= '1';
elsif next_activate='0' and next_delay = 1 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
SDRAM_A <= mem_a_i;
SDRAM_BA <= mem_ba_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_dout: entity work.my_ioddr
port map (
pin => SDRAM_DQ(i),
clock => clock,
D0 => wdata(8+i),
D1 => wdata(i),
T0 => wdata_tri(1),
T1 => wdata_tri(0),
Q0 => rdata_hi(i),
Q1 => rdata_lo(i) );
end generate;
select_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
i_dqm_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => wdqm(1),
D1 => wdqm(0),
R => '0',
S => '0' );
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/itu/vhdl_source/itu.vhd
|
3
|
10344
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.itu_pkg.all;
entity itu is
generic (
g_version : unsigned(7 downto 0) := X"FE";
g_uart : boolean := true;
g_frequency : integer := 50_000_000;
g_edge_init : std_logic_vector(7 downto 0) := "00000001";
g_capabilities : std_logic_vector(31 downto 0) := X"5555AAAA";
g_edge_write : boolean := true;
g_baudrate : integer := 115_200;
g_timer_rate : integer := 200_000 ); -- 5µs (should not result in more than 8 bits div)
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq_timer_tick : in std_logic := '0';
irq_in : in std_logic_vector(7 downto 2);
uart_txd : out std_logic;
uart_rxd : in std_logic := '1';
uart_rts : out std_logic;
uart_cts : in std_logic := '1' );
end itu;
architecture gideon of itu is
constant c_timer_div : integer := g_frequency / g_timer_rate;
constant c_baud_div : integer := g_frequency / g_baudrate;
constant c_ms_div : integer := g_timer_rate / 1000;
signal imask : std_logic_vector(7 downto 0);
signal iedge : std_logic_vector(7 downto 0) := g_edge_init;
signal timer : unsigned(7 downto 0);
signal timer_tick : std_logic;
signal timer_div : integer range 0 to c_timer_div - 1;
signal irq_timer_val : unsigned(15 downto 0);
signal irq_timer_cnt : unsigned(23 downto 0);
signal irq_timer_en : std_logic;
signal irq_timer_select : std_logic;
signal irq_en : std_logic;
signal irq_c : std_logic_vector(7 downto 0);
signal irq_d : std_logic_vector(7 downto 0);
signal irq_edge_flag : std_logic_vector(7 downto 0);
signal irq_active : std_logic_vector(7 downto 0);
signal uart_irq : std_logic := '0';
signal io_req_it : t_io_req;
signal io_resp_it : t_io_resp;
signal io_req_uart : t_io_req;
signal io_resp_uart : t_io_resp;
signal io_req_ms : t_io_req;
signal io_resp_ms : t_io_resp;
signal ms_timer_presc : integer range 0 to c_ms_div-1 := 0;
signal ms_timer : unsigned(15 downto 0) := (others => '0');
begin
process(clock)
variable new_irq_edge_flag : std_logic_vector(irq_edge_flag'range);
begin
if rising_edge(clock) then
if timer_div = 0 then
timer_div <= c_timer_div - 1;
timer_tick <= '1';
else
timer_div <= timer_div - 1;
timer_tick <= '0';
end if;
if timer_tick='1' then
if timer /= X"00" then
timer <= timer - 1;
end if;
if ms_timer_presc = 0 then
ms_timer <= ms_timer + 1;
ms_timer_presc <= c_ms_div - 1;
else
ms_timer_presc <= ms_timer_presc - 1;
end if;
end if;
irq_c(7 downto 2) <= irq_in(7 downto 2);
irq_c(1) <= uart_irq;
irq_c(0) <= '0';
if irq_timer_en='1' then
if irq_timer_cnt = 0 then
irq_c(0) <= '1';
if irq_timer_select='1' then
irq_timer_cnt <= X"00" & irq_timer_val;
else
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
elsif irq_timer_select='0' or irq_timer_tick='1' then
irq_timer_cnt <= irq_timer_cnt - 1;
end if;
end if;
irq_d <= irq_c;
io_resp_it <= c_io_resp_init;
new_irq_edge_flag := irq_edge_flag;
if io_req_it.write='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
irq_en <= io_req_it.data(0);
when c_itu_irq_enable =>
imask <= imask or io_req_it.data;
when c_itu_irq_disable =>
imask <= imask and not io_req_it.data;
when c_itu_irq_edge =>
if g_edge_write then
iedge <= io_req_it.data;
end if;
when c_itu_irq_clear =>
new_irq_edge_flag := new_irq_edge_flag and not io_req_it.data;
when c_itu_timer =>
timer <= unsigned(io_req_it.data);
when c_itu_irq_timer_en =>
irq_timer_en <= io_req_it.data(0);
irq_timer_select <= io_req_it.data(1);
if irq_timer_en='0' then
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
when c_itu_irq_timer_lo =>
irq_timer_val(7 downto 0) <= unsigned(io_req_it.data);
when c_itu_irq_timer_hi =>
irq_timer_val(15 downto 8) <= unsigned(io_req_it.data);
when others =>
null;
end case;
elsif io_req_it.read='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
io_resp_it.data(0) <= irq_en;
when c_itu_irq_enable =>
io_resp_it.data <= imask;
when c_itu_irq_edge =>
io_resp_it.data <= iedge;
when c_itu_irq_active =>
io_resp_it.data <= irq_active;
when c_itu_timer =>
io_resp_it.data <= std_logic_vector(timer);
when c_itu_irq_timer_en =>
io_resp_it.data(0) <= irq_timer_en;
io_resp_it.data(1) <= irq_timer_select;
when c_itu_irq_timer_lo =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(7 downto 0));
when c_itu_irq_timer_hi =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(15 downto 8));
when c_itu_fpga_version =>
io_resp_it.data <= std_logic_vector(g_version);
when c_itu_capabilities0 =>
io_resp_it.data <= g_capabilities(31 downto 24);
when c_itu_capabilities1 =>
io_resp_it.data <= g_capabilities(23 downto 16);
when c_itu_capabilities2 =>
io_resp_it.data <= g_capabilities(15 downto 8);
when c_itu_capabilities3 =>
io_resp_it.data <= g_capabilities( 7 downto 0);
when others =>
null;
end case;
end if;
io_resp_ms <= c_io_resp_init;
if io_req_ms.write='1' then
io_resp_ms.ack <= '1';
elsif io_req_ms.read='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_ms_timer_lo =>
io_resp_ms.data <= std_logic_vector(ms_timer(7 downto 0));
when c_itu_ms_timer_hi =>
io_resp_ms.data <= std_logic_vector(ms_timer(15 downto 8));
when others =>
null;
end case;
end if;
for i in 0 to 7 loop
if iedge(i)='1' then
if irq_c(i)='1' and irq_d(i)='0' then
new_irq_edge_flag(i) := '1';
end if;
end if;
end loop;
irq_edge_flag <= new_irq_edge_flag;
io_resp_it.irq <= '0';
if irq_en = '1' then
if (irq_active and imask) /= X"00" then
io_resp_it.irq <= '1';
end if;
end if;
if reset='1' then
irq_en <= '1';
imask <= (others => '0');
iedge <= g_edge_init;
timer <= (others => '0');
irq_timer_en <= '0';
irq_timer_val <= X"8000";
irq_timer_cnt <= (others => '0');
ms_timer <= (others => '0');
end if;
end if;
end process;
irq_active <= irq_edge_flag or (irq_c and not iedge);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_it,
reqs(1) => io_req_uart,
reqs(2) => io_req_ms,
resps(0) => io_resp_it,
resps(1) => io_resp_uart,
resps(2) => io_resp_ms );
r_uart: if g_uart generate
uart: entity work.uart_peripheral_io
generic map (
g_divisor => c_baud_div )
port map (
clock => clock,
reset => reset,
io_req => io_req_uart,
io_resp => io_resp_uart,
rts => uart_rts,
cts => uart_cts,
txd => uart_txd,
rxd => uart_rxd );
end generate;
no_uart: if not g_uart generate
process(clock)
begin
if rising_edge(clock) then
io_resp_uart <= c_io_resp_init;
io_resp_uart.ack <= io_req_uart.read or io_req_uart.write;
end if;
end process;
end generate;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/my_math_pkg.vhd
|
6
|
4097
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_math_pkg is
function sum_limit(i1, i2 : signed) return signed;
function sub_limit(i1, i2 : signed) return signed;
function sum_limit(i1, i2 : unsigned) return unsigned;
function extend(x : signed; len : natural) return signed;
function extend(x : unsigned; len : natural) return unsigned;
function left_align(x : signed; len : natural) return signed;
function left_scale(x : signed; sh : natural) return signed;
-- function shift_right(x : signed; positions: natural) return signed;
end;
package body my_math_pkg is
function sum_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 + i2;
if (i1(i1'left) = i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sub_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 - i2;
if (i1(i1'left) /= i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sum_limit(i1, i2 : unsigned) return unsigned is
variable o : unsigned(i1'length downto 0);
begin
o := ('0' & i1) + i2;
if o(o'left)='1' then
o := (others => '1');
end if;
return o(i1'length-1 downto 0);
end function;
function extend(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
alias a : signed(x'length-1 downto 0) is x;
begin
ret := (others => x(x'left));
ret(a'range) := a;
return ret;
end function extend;
function extend(x : unsigned; len : natural) return unsigned is
variable ret : unsigned(len-1 downto 0);
alias a : unsigned(x'length-1 downto 0) is x;
begin
ret := (others => '0');
ret(a'range) := a;
return ret;
end function extend;
function left_align(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
begin
ret := (others => '0');
ret(len-1 downto len-x'length) := x;
return ret;
end function left_align;
function left_scale(x : signed; sh : natural) return signed is
alias a : signed(x'length-1 downto 0) is x;
variable ret : signed(x'length-(1+sh) downto 0);
variable top : signed(sh downto 0);
begin
if sh=0 then
return x;
end if;
top := a(a'high downto a'high-sh);
if (top = -1) or (top = 0) then -- can shift without getting punished!
ret := a(ret'range);
elsif a(a'high)='1' then -- negative and can't shift, so max neg:
ret := (others => '0');
ret(ret'high) := '1';
else -- positive and can't shift, so max pos
ret := (others => '1');
ret(ret'high) := '0';
end if;
return ret;
end function left_scale;
-- function shift_right(x : signed; positions: natural) return signed is
-- alias a : signed(x'length-1 downto 0) is x;
-- variable ret : signed(x'length-1 downto 0);
-- begin
-- ret := (others => x(x'left));
-- ret(a'left-positions downto 0) := a(a'left downto positions);
-- return ret;
-- end function shift_right;
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/sid6581/vhdl_source/sid_io_regs.vhd
|
4
|
4237
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/sid6581/vhdl_source/sid_io_regs.vhd
|
4
|
4237
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/usb_cmd_io.vhd
|
2
|
4001
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_cmd_io
-- Date:2015-01-18
-- Author: Gideon
-- Description: I/O registers for controlling commands directly
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_cmd_pkg.all;
entity usb_cmd_io is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
connected : in std_logic;
operational : in std_logic;
speed : in std_logic_vector(1 downto 0);
cmd_req : out t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp );
end entity;
architecture arch of usb_cmd_io is
signal done_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if cmd_resp.done = '1' then
cmd_req.request <= '0';
done_latch <= '1';
end if;
io_resp <= c_io_resp_init;
if io_req.write = '1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"1" =>
cmd_req.request <= '1';
done_latch <= '0';
cmd_req.do_split <= io_req.data(7);
cmd_req.do_data <= io_req.data(6);
cmd_req.command <= c_usb_commands_decoded(to_integer(unsigned(io_req.data(2 downto 0))));
when X"6" => -- high of data buffer control
cmd_req.buffer_index <= unsigned(io_req.data(7 downto 6));
cmd_req.no_data <= io_req.data(5);
cmd_req.togglebit <= io_req.data(4);
cmd_req.data_length(9 downto 8) <= unsigned(io_req.data(1 downto 0));
when X"7" =>
cmd_req.data_length(7 downto 0) <= unsigned(io_req.data);
when X"A" =>
cmd_req.device_addr <= unsigned(io_req.data(6 downto 0));
when X"B" =>
cmd_req.endp_addr <= unsigned(io_req.data(3 downto 0));
when X"E" =>
cmd_req.split_hub_addr <= unsigned(io_req.data(6 downto 0));
when X"F" =>
cmd_req.split_port_addr <= unsigned(io_req.data(3 downto 0));
cmd_req.split_sc <= io_req.data(7);
cmd_req.split_sp <= io_req.data(6);
cmd_req.split_et <= io_req.data(5 downto 4);
when others =>
null;
end case;
elsif io_req.read = '1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"0" =>
io_resp.data(7) <= done_latch;
io_resp.data(6 downto 4) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
io_resp.data(2) <= cmd_resp.no_data;
io_resp.data(3) <= cmd_resp.togglebit;
io_resp.data(1 downto 0) <= std_logic_vector(cmd_resp.data_length(9 downto 8));
when X"1" =>
io_resp.data <= std_logic_vector(cmd_resp.data_length(7 downto 0));
when X"2" =>
io_resp.data(0) <= connected;
io_resp.data(1) <= operational;
io_resp.data(5 downto 4) <= speed;
when others =>
null;
end case;
end if;
if reset='1' then
done_latch <= '0';
cmd_req.request <= '0';
end if;
end if;
end process;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/noise_generator.vhd
|
5
|
2044
|
library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
polynom : in std_logic_vector(g_polynom'length-1 downto 0) := (others => '0');
q : out std_logic_vector(g_polynom'length-1 downto 0) );
end noise_generator;
architecture gideon of noise_generator is
signal c_poly : std_logic_vector(g_polynom'length-1 downto 0);
signal reg : std_logic_vector(g_polynom'length-1 downto 0);
begin
assert (g_type = "Fibonacci") or (g_type = "Galois")
report "Type of LFSR should be Fibonacci or Galois.."
severity failure;
c_poly <= g_polynom when g_fixed_polynom else polynom;
process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
if enable='1' then
if g_type = "Fibonacci" then
new_bit := '0';
for i in c_poly'range loop
if c_poly(i)='1' then
new_bit := new_bit xor reg(i);
end if;
end loop;
reg <= reg(reg'high-1 downto 0) & new_bit;
else -- "Galois", enforced by assert
if reg(reg'high)='1' then
reg <= (reg(reg'high-1 downto 0) & '0') xor c_poly;
else
reg <= reg(reg'high-1 downto 0) & '1';
end if;
end if;
end if;
if reset='1' then
reg <= g_seed;
end if;
end if;
end process;
q <= reg;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/usb_pkg.vhd
|
1
|
12129
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb_pkg is
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token ->
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake <-
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token ->
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_split(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic;
type t_token is record
device_addr : std_logic_vector(6 downto 0);
endpoint_addr : std_logic_vector(3 downto 0);
end record;
constant c_token_init : t_token := ( "0000000", "0000" );
constant c_token_undefined : t_token := ( "XXXXXXX", "XXXX" );
type t_split_token is record
hub_address : std_logic_vector(6 downto 0);
sc : std_logic;
port_address : std_logic_vector(6 downto 0);
s : std_logic; -- start/speed (isochronous out start split), for interrupt/control transfers: Speed. 0=full, 1=low
e : std_logic; -- end (isochronous out start split) 00=middle, 10=beginning, 01=end, 11=all
et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
constant c_split_token_init : t_split_token := (
hub_address => "0000000",
sc => '0',
port_address => "0000000",
s => '0',
e => '0',
et => "00" );
constant c_split_token_undefined : t_split_token := (
hub_address => "XXXXXXX",
sc => 'X',
port_address => "XXXXXXX",
s => 'X',
e => 'X',
et => "XX" );
constant c_split_token_bogus : t_split_token := (
hub_address => "0000001",
sc => '0',
port_address => "0000010",
s => '0',
e => '0',
et => "11" );
type t_usb_rx is record
receiving : std_logic;
valid_token : std_logic;
valid_split : std_logic;
valid_handsh : std_logic;
valid_packet : std_logic;
error : std_logic;
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
data_valid : std_logic;
data_start : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_usb_tx_req is record
send_token : std_logic;
send_split : std_logic;
send_handsh : std_logic;
send_packet : std_logic;
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
no_data : std_logic;
data : std_logic_vector(7 downto 0);
data_valid : std_logic;
data_last : std_logic;
end record;
type t_usb_tx_resp is record
request_ack : std_logic;
busy : std_logic;
data_wait : std_logic;
end record;
type t_usb_tx_req_array is array(natural range <>) of t_usb_tx_req;
-- function or_reduce(a : t_usb_tx_req_array) return t_usb_tx_req;
constant c_usb_rx_init : t_usb_rx := (
receiving => '0',
valid_token => '0',
valid_split => '0',
valid_handsh => '0',
valid_packet => '0',
error => '0',
pid => X"0",
token => c_token_init,
split_token => c_split_token_init,
data_valid => '0',
data_start => '0',
data => X"00" );
constant c_usb_tx_req_init : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '0',
pid => c_pid_reserved,
token => c_token_init,
split_token => c_split_token_init,
no_data => '0',
data => X"00",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_ack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_ack,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nak,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nyet : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nyet,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_stall : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_stall,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_data_out0 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data0,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_data_out1 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data1,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
function token_to_vector(t : t_token) return std_logic_vector;
function vector_to_token(v : std_logic_vector) return t_token;
function split_token_to_vector(t : t_split_token) return std_logic_vector;
function vector_to_split_token(v : std_logic_vector) return t_split_token;
end package;
package body usb_pkg is
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_split(i : std_logic_vector(3 downto 0)) return boolean is
begin
return (i = c_pid_split);
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused! HUB reply to CSPLIT
when others => return false;
end case;
return false;
end function;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic is
begin
return i(3);
end function;
function split_token_to_vector(t : t_split_token) return std_logic_vector is
variable ret : std_logic_vector(18 downto 0);
begin
ret(18 downto 17) := t.et;
ret(16) := t.e;
ret(15) := t.s;
ret(14 downto 8) := t.port_address;
ret(7) := t.sc;
ret(6 downto 0) := t.hub_address;
return ret;
end function;
function vector_to_split_token(v : std_logic_vector) return t_split_token is
variable va : std_logic_vector(18 downto 0);
variable ret : t_split_token;
begin
va := v;
ret.et := va(18 downto 17);
ret.e := va(16);
ret.s := va(15);
ret.port_address := va(14 downto 8);
ret.sc := va(7);
ret.hub_address := va(6 downto 0);
return ret;
end function;
-- Token conversion
function token_to_vector(t : t_token) return std_logic_vector is
variable ret : std_logic_vector(10 downto 0);
begin
ret := t.endpoint_addr & t.device_addr;
return ret;
end function;
function vector_to_token(v : std_logic_vector) return t_token is
alias va : std_logic_vector(10 downto 0) is v;
variable ret : t_token;
begin
ret.device_addr := va(6 downto 0);
ret.endpoint_addr := va(10 downto 7);
return ret;
end function;
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
target/simulation/packages/vhdl_source/tl_string_util_pkg.vhd
|
5
|
33938
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION B.V., GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Style guide example package
-- Author : Jonathan Hofman ([email protected]) (import only)
-------------------------------------------------------------------------------
-- Description: This file contains type definitions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package tl_string_util_pkg is
-------------------------------------------------------------------------------
-- functions origination from file_io_package (depricated)
-------------------------------------------------------------------------------
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character; -- depricated
function hex_to_nibble(c : character) return std_logic_vector; -- depricated
function is_hex_char(c : character) return boolean; -- depricated
function vec_to_hex(vec : std_logic_vector; len : integer) return string; -- depricated
procedure write_string(variable my_line : inout line; s : string); -- depricated
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts std_logic into a character
---------------------------------------------------------------------------
function chr(sl: std_logic) return character;
---------------------------------------------------------------------------
-- converts a nible into a hex character
---------------------------------------------------------------------------
function hchr(slv: std_logic_vector) return character;
function hchr(slv: unsigned) return character;
---------------------------------------------------------------------------
-- converts std_logic into a string (1 to 1)
---------------------------------------------------------------------------
function str(sl: std_logic) return string;
---------------------------------------------------------------------------
-- converts std_logic_vector into a string (binary base)
---------------------------------------------------------------------------
function str(slv: std_logic_vector) return string;
---------------------------------------------------------------------------
-- converts boolean into a string
---------------------------------------------------------------------------
function str(b: boolean) return string;
---------------------------------------------------------------------------
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
---------------------------------------------------------------------------
function chr(int: integer) return character;
---------------------------------------------------------------------------
-- converts integer into string using specified base
---------------------------------------------------------------------------
function str(int: integer; base: integer) return string;
---------------------------------------------------------------------------
-- converts to string, using base 10
---------------------------------------------------------------------------
function str(int: integer) return string;
---------------------------------------------------------------------------
-- convert into a string in hex format
---------------------------------------------------------------------------
function hstr(slv: std_logic_vector) return string;
function hstr(uns: unsigned) return string;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts a character into std_logic
---------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic;
---------------------------------------------------------------------------
-- converts a hex character into std_logic_vector
---------------------------------------------------------------------------
function hchr_to_std_logic_vector(c: character) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a string into a specific type
---------------------------------------------------------------------------
function to_std_logic_vector(s: string) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a hex string into a specific type
---------------------------------------------------------------------------
function hstr_to_std_logic_vector( str : string; len: integer) return std_logic_vector;
function hstr_to_integer( str : string ) return integer;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- convert to upper case
---------------------------------------------------------------------------
function to_upper(c: character) return character;
function to_upper(s: string) return string;
---------------------------------------------------------------------------
-- convert to lower case
---------------------------------------------------------------------------
function to_lower(c: character) return character;
function to_lower(s: string) return string;
---------------------------------------------------------------------------
-- check if it is an hex character
---------------------------------------------------------------------------
function is_hchr(c : character) return boolean;
function resize(s: string; size: natural; default: character := ' ') return string;
---------------------------------------------------------------------------
-- Compare function for strings that correctly handles terminators (NUL)
---------------------------------------------------------------------------
function strcmp(a: string; b: string) return boolean;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- print
---------------------------------------------------------------------------
-- print string to a file and start new line, if no file is specified the
-- print function will print to stdout
---------------------------------------------------------------------------
procedure print(text: string);
procedure print(active: boolean; text: string);
procedure print(file out_file: TEXT; new_string: in string);
procedure print(file out_file: TEXT; char: in character);
---------------------------------------------------------------------------
-- read variable length string from input file
---------------------------------------------------------------------------
procedure str_read(file in_file: TEXT; res_string: out string);
-------------------------------------------------------------------------------
-- character manipulation
-------------------------------------------------------------------------------
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector;
end tl_string_util_pkg;
package body tl_string_util_pkg is
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character is
variable r : character := '?';
begin
case nibble is
when "0000" => r := '0';
when "0001" => r := '1';
when "0010" => r := '2';
when "0011" => r := '3';
when "0100" => r := '4';
when "0101" => r := '5';
when "0110" => r := '6';
when "0111" => r := '7';
when "1000" => r := '8';
when "1001" => r := '9';
when "1010" => r := 'A';
when "1011" => r := 'B';
when "1100" => r := 'C';
when "1101" => r := 'D';
when "1110" => r := 'E';
when "1111" => r := 'F';
when others => r := 'X';
end case;
return r;
end nibble_to_hex;
function hex_to_nibble(c : character) return std_logic_vector is
variable z : std_logic_vector(3 downto 0);
begin
case c is
when '0' => z := "0000";
when '1' => z := "0001";
when '2' => z := "0010";
when '3' => z := "0011";
when '4' => z := "0100";
when '5' => z := "0101";
when '6' => z := "0110";
when '7' => z := "0111";
when '8' => z := "1000";
when '9' => z := "1001";
when 'A' => z := "1010";
when 'B' => z := "1011";
when 'C' => z := "1100";
when 'D' => z := "1101";
when 'E' => z := "1110";
when 'F' => z := "1111";
when 'a' => z := "1010";
when 'b' => z := "1011";
when 'c' => z := "1100";
when 'd' => z := "1101";
when 'e' => z := "1110";
when 'f' => z := "1111";
when others => z := "XXXX";
end case;
return z;
end hex_to_nibble;
function is_hex_char(c : character) return boolean is
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7' => return true;
when '8'|'9'|'A'|'B'|'C'|'D'|'E'|'F' => return true;
when 'a'|'b'|'c'|'d'|'e'|'f' => return true;
when others => return false;
end case;
return false;
end is_hex_char;
procedure vec_to_hex(vec : std_logic_vector; str : out string) is
variable temp_vec : std_logic_vector(str'length * 4 downto 1) := (others => '0');
variable j : integer;
variable my_vec : std_logic_vector(vec'range);
variable len, my_low, my_high : integer;
begin
my_vec := vec;
len := str'length;
my_low := vec'low;
my_high := vec'high;
if vec'length < temp_vec'length then
temp_vec(vec'length downto 1) := vec;
else
temp_vec := vec(vec'low + temp_vec'length - 1 downto vec'low);
end if;
for i in str'range loop
j := (str'right - i) * 4;
str(i) := nibble_to_hex(temp_vec(j+4 downto j+1));
end loop;
end vec_to_hex;
function vec_to_hex(vec : std_logic_vector; len : integer) return string is
variable str : string(1 to len);
begin
vec_to_hex(vec, str);
return str;
end vec_to_hex;
procedure write_string(variable my_line : inout line; s : string) is
begin
write(my_line, s);
end write_string;
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
function hchr(slv: std_logic_vector) return character is
begin
return hchr(unsigned(slv));
end function;
function hchr(slv: unsigned) return character is
variable v_fourbit : unsigned(3 downto 0);
variable v_result : character;
begin
v_fourbit := resize(slv, 4);
case v_fourbit is
when "0000" => v_result := '0';
when "0001" => v_result := '1';
when "0010" => v_result := '2';
when "0011" => v_result := '3';
when "0100" => v_result := '4';
when "0101" => v_result := '5';
when "0110" => v_result := '6';
when "0111" => v_result := '7';
when "1000" => v_result := '8';
when "1001" => v_result := '9';
when "1010" => v_result := 'A';
when "1011" => v_result := 'B';
when "1100" => v_result := 'C';
when "1101" => v_result := 'D';
when "1110" => v_result := 'E';
when "1111" => v_result := 'F';
when "ZZZZ" => v_result := 'z';
when "UUUU" => v_result := 'u';
when "XXXX" => v_result := 'x';
when others => v_result := '?';
end case;
return v_result;
end function;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
constant c_hexlen : integer := (slv'length + 3)/4;
alias slv_norm : std_logic_vector(slv'length - 1 downto 0) is slv;
variable v_longslv : std_logic_vector(c_hexlen * 4 - 1 downto 0) := (others => '0');
variable v_result : string(1 to c_hexlen);
variable v_fourbit : std_logic_vector(3 downto 0);
begin
v_longslv(slv_norm'range) := slv_norm;
for i in 0 to c_hexlen - 1 loop
v_fourbit := v_longslv(((i * 4) + 3) downto (i * 4));
case v_fourbit is
when "0000" => v_result(c_hexlen - i) := '0';
when "0001" => v_result(c_hexlen - i) := '1';
when "0010" => v_result(c_hexlen - i) := '2';
when "0011" => v_result(c_hexlen - i) := '3';
when "0100" => v_result(c_hexlen - i) := '4';
when "0101" => v_result(c_hexlen - i) := '5';
when "0110" => v_result(c_hexlen - i) := '6';
when "0111" => v_result(c_hexlen - i) := '7';
when "1000" => v_result(c_hexlen - i) := '8';
when "1001" => v_result(c_hexlen - i) := '9';
when "1010" => v_result(c_hexlen - i) := 'A';
when "1011" => v_result(c_hexlen - i) := 'B';
when "1100" => v_result(c_hexlen - i) := 'C';
when "1101" => v_result(c_hexlen - i) := 'D';
when "1110" => v_result(c_hexlen - i) := 'E';
when "1111" => v_result(c_hexlen - i) := 'F';
when "ZZZZ" => v_result(c_hexlen - i) := 'z';
when "UUUU" => v_result(c_hexlen - i) := 'u';
when "XXXX" => v_result(c_hexlen - i) := 'x';
when others => v_result(c_hexlen - i) := '?';
end case;
end loop;
return v_result;
end hstr;
-- converts an unsigned into a hex string.
function hstr(uns : unsigned) return string is
begin
return hstr(std_logic_vector(uns));
end;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' => sl := 'U';
when 'X' => sl := 'X';
when '0' => sl := '0';
when '1' => sl := '1';
when 'Z' => sl := 'Z';
when 'W' => sl := 'W';
when 'L' => sl := 'L';
when 'H' => sl := 'H';
when '-' => sl := '-';
when others => sl := 'X';
end case;
return sl;
end to_std_logic;
function hchr_to_std_logic_vector(c: character) return std_logic_vector is
variable v_result : std_logic_vector(3 downto 0);
begin
case c is
when '0' => v_result := "0000";
when '1' => v_result := "0001";
when '2' => v_result := "0010";
when '3' => v_result := "0011";
when '4' => v_result := "0100";
when '5' => v_result := "0101";
when '6' => v_result := "0110";
when '7' => v_result := "0111";
when '8' => v_result := "1000";
when '9' => v_result := "1001";
when 'a' => v_result := "1010";
when 'b' => v_result := "1011";
when 'c' => v_result := "1100";
when 'd' => v_result := "1101";
when 'e' => v_result := "1110";
when 'f' => v_result := "1111";
when 'A' => v_result := "1010";
when 'B' => v_result := "1011";
when 'C' => v_result := "1100";
when 'D' => v_result := "1101";
when 'E' => v_result := "1110";
when 'F' => v_result := "1111";
when others => v_result := "XXXX";
assert FALSE
report "Illegal character "& c & "in hex string! "
severity warning;
end case;
return v_result;
end function;
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
function hstr_to_integer(str: string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in 1 to len loop
case to_lower(str(i)) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'a' => digit := 10;
when 'b' => digit := 11;
when 'c' => digit := 12;
when 'd' => digit := 13;
when 'e' => digit := 14;
when 'f' => digit := 15;
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hstr_to_std_logic_vector(str: string; len: integer) return std_logic_vector is
variable digit : std_logic_vector(3 downto 0);
variable result : std_logic_vector((str'length * 4) - 1 downto 0);
begin
-- we can not use hstr_to_integer and then convert to hex, because the integer range is
-- limited
for i in str'range loop
case to_lower(str(str'length - i + 1)) is
when '0' => digit := "0000";
when '1' => digit := "0001";
when '2' => digit := "0010";
when '3' => digit := "0011";
when '4' => digit := "0100";
when '5' => digit := "0101";
when '6' => digit := "0110";
when '7' => digit := "0111";
when '8' => digit := "1000";
when '9' => digit := "1001";
when 'a' => digit := "1010";
when 'b' => digit := "1011";
when 'c' => digit := "1100";
when 'd' => digit := "1101";
when 'e' => digit := "1110";
when 'f' => digit := "1111";
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity error;
end case;
result((i * 4) - 1 downto (i - 1) * 4) := digit;
end loop;
return result(len - 1 downto 0);
end;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
function is_hchr(c : character) return boolean is
variable v_result : boolean;
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|
'8'|'9'|'A'|'B'|'C'|'D'|'E'|'F'|
'a'|'b'|'c'|'d'|'e'|'f' => v_result := true;
when others => v_result := false;
end case;
return v_result;
end function;
function strcmp(a: string; b: string) return boolean is
variable r : boolean := true;
begin
for i in a'range loop
if i > b'right then
if a(i) /= NUL then -- b is shorter and a doesn't terminate here.
return false;
else
return true; -- b is shorter, but a does terminate here
end if;
end if;
if a(i) /= b(i) then -- characters are not the same
return false;
end if;
if a(i) = NUL and b(i) = NUL then -- a and b have a string terminator at the same place
-- and previous characters were all the same
return true;
end if;
end loop;
-- if b is longer, then check if b has a terminator
if (b'right > a'right) then
if b(a'right + 1) /= NUL then
return false;
end if;
end if;
return true;
end strcmp;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
procedure print(file out_file: TEXT; new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
procedure print(file out_file: TEXT; char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
procedure str_read(file in_file: TEXT; res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT; new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(character'pos(my_char), 8));
end;
function resize(s: string; size: natural; default: character := ' ') return string is
variable result: string(1 to size) := (others => default);
begin
if s'length > size then
result := s(result'range);
else
result(s'range) := s;
end if;
return result;
end function;
end tl_string_util_pkg;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v6.vhd
|
5
|
19323
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v6 is
generic (
g_simulation : boolean := false;
g_read_fifo : boolean := false;
q_tcko_data : time := 100 ps;
A_Width : integer := 13;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
-- clk_4x : in std_logic := '0';
-- dummy : out std_logic;
req : in t_mem_burst_16_req;
resp : out t_mem_burst_16_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_A : out std_logic_vector(A_Width-1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v6;
architecture Gideon of ext_mem_ctrl_v6 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002B", "000" ), -- mode register, burstlen=8, writelen=8, CAS lat = 2, interleaved
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ) );
type t_ints is array(natural range <>) of integer;
constant c_delays : t_ints(0 to 15) := (
2, 4, 2, 3, -- R2R (other row&other bank, other row, other bank, same row+bank)
4, 5, 4, 5, -- R2W
2, 5, 2, 3, -- W2R
2, 4, 2, 3 );-- W2W
type t_state is (boot, init, idle, sd_cas );
signal state : t_state;
signal sdram_d_o : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal sdram_d_t : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal wdata_tri : std_logic_vector(8 downto 0) := (others => '1');
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal mem_a_i : std_logic_vector(SDRAM_A'range) := (others => '0');
signal mem_ba_i : std_logic_vector(SDRAM_BA'range) := (others => '0');
signal cs_n_i : std_logic := '1';
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal do_refresh_d : std_logic := '0';
signal trigger_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi_d : std_logic_vector(7 downto 0) := (others => '0');
signal wdata : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_i : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_av : std_logic;
signal fifo_wdata_in : std_logic_vector(17 downto 0);
signal wdqm : std_logic_vector(1 downto 0);
signal dqm_override : std_logic := '1';
-- signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(5 downto 0) := "000000";
signal burst_start : std_logic_vector(5 downto 0) := "000000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal same_bank : std_logic;
signal last_row : std_logic_vector(12 downto 0) := "0101011010101";
signal addr_row : std_logic_vector(12 downto 0);
signal same_row : std_logic;
signal addr_column : std_logic_vector(9 downto 0);
signal next_activate : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal rwn_i : std_logic := '1';
signal tag_fifo : std_logic_vector(7 downto 0);
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic := '0'; -- forced low for when there is no fifo
signal push_cmd : std_logic;
signal push_read_cmd : std_logic;
signal crazy_index_slv : std_logic_vector(3 downto 0);
signal crazy_index : integer range 0 to 15;
signal sampled_dq : std_logic_vector(7 downto 0);
begin
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av and not do_refresh_d;
push_cmd <= req.request and not cmd_af;
push_read_cmd <= push_cmd and req.read_writen;
resp.ready <= not cmd_af;
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(address_fifo'length);
addr_bank <= address_fifo(14 downto 13);
addr_row <= address_fifo(24 downto 15) & address_fifo(12 downto 10);
addr_column <= address_fifo( 9 downto 0);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_tag_fifo: entity work.srl_fifo
generic map (
Width => 8,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => burst_start(1),
PutElement => push_read_cmd,
FlushFifo => '0',
DataIn => req.request_tag,
DataOut => tag_fifo,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => open );
r_read_fifo: if g_read_fifo generate
i_read_fifo: entity work.srl_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => dack(0),
FlushFifo => '0',
DataIn(15 downto 8) => rdata_lo,
DataIn(7 downto 0) => rdata_hi,
DataOut => resp.data,
SpaceInFifo => open,
AlmostFull => rdata_af,
DataInFifo => resp.rdata_av );
end generate;
r_read_direct: if not g_read_fifo generate
resp.data <= rdata_lo & rdata_hi;
resp.rdata_av <= dack(0);
end generate;
fifo_wdata_in <= req.byte_en & req.data;
wdqm <= (others => '1') when dqm_override='1' else
(others => '0') when dnext(0)='0' else not wdata(17 downto 16);
i_write_fifo: entity work.SRL_fifo
generic map (
Width => (c_data_width*9)/8,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => dnext(0),
PutElement => req.data_push,
FlushFifo => '0',
DataIn => fifo_wdata_in,
DataOut => wdata_i,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => wdata_av );
wdata <= wdata_i after 1 ns;
same_row <= '1' when addr_row = last_row else '0';
same_bank <= '1' when addr_bank = last_bank else '0';
crazy_index_slv <= not rwn_i & not rwn_fifo & same_row & same_bank;
crazy_index <= to_integer(unsigned(crazy_index_slv));
trigger_refresh <= do_refresh_d and not (inhibit_d or inhibit);
process(clock)
procedure send_refresh_cmd is
begin
if next_delay = 0 then
do_refresh <= '0';
do_refresh_d <= '0';
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
col_addr <= addr_column;
last_bank <= addr_bank;
last_row <= addr_row;
mem_a_i(addr_row'range) <= addr_row;
mem_ba_i <= addr_bank;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
end procedure;
procedure issue_read_or_write is
begin
mem_a_i(9 downto 0) <= col_addr;
do_refresh_d <= do_refresh;
if req_i='0' or do_refresh='1' then
if rwn_i='0' then
next_delay <= 5;
else
next_delay <= 4;
end if;
mem_a_i(10) <= '1'; -- auto precharge
next_activate <= '1';
else
next_delay <= c_delays(crazy_index);
mem_a_i(10) <= not (same_row and same_bank); -- do not AP when we'll continue in same row
next_activate <= not (same_row and same_bank); -- only activate next time if we also AP.
end if;
if delay=0 then
if rwn_i='0' then
if wdata_av='1' then
wdata_tri(7 downto 0) <= (others => '0') after 1 ns;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
dnext <= "1111" after 1 ns;
state <= idle;
end if;
else
if rdata_af='0' then
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
dack(dack'high downto dack'high-3) <= (others => '1');
burst_start(2) <= '1';
state <= idle;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
rdata_hi_d <= rdata_hi;
cs_n_i <= '1' after 1 ns;
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
if burst_start(1)='1' then
resp.data_tag <= tag_fifo;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
wdata_tri <= "11" & wdata_tri(wdata_tri'high downto 2) after 1 ns;
dack <= '0' & dack(dack'high downto 1);
burst_start <= '0' & burst_start(burst_start'high downto 1);
dnext <= '0' & dnext(dnext'high downto 1) after 1 ns;
case state is
when boot =>
enable_sdram <= '1';
if g_simulation then
state <= init;
elsif refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
mem_ba_i <= (others => '0'); -- for DDR and such, maybe the upper 2/3 bits
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if next_delay = 0 then
next_delay <= 7;
cs_n_i <= '0' after 1 ns;
if init_cnt = c_init_array'high then
state <= idle;
dqm_override <= '0';
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' then
if next_activate='1' and next_delay=0 then
accept_req;
elsif next_activate='0' and next_delay=1 then
rwn_i <= rwn_fifo;
col_addr <= addr_column;
state <= sd_cas;
end if;
else
do_refresh_d <= do_refresh;
end if;
end if;
when sd_cas =>
issue_read_or_write;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
resp.data_tag <= (others => '0');
dqm_override <= '1';
state <= boot;
wdata_tri <= (others => '0');
delay <= 0;
next_delay <= 0;
do_refresh <= '0';
do_refresh_d <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
next_activate <= '1';
rwn_i <= '1';
end if;
end if;
end process;
-- Generate rack; the signal that indicates that a request is going to be issued
-- and thus taken from the command fifo.
process(state, trigger_refresh, inhibit, req_i, next_delay, next_activate)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
null;
elsif inhibit='0' and req_i='1' then
if next_activate='1' and next_delay = 0 then
rack <= '1';
elsif next_activate='0' and next_delay = 1 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
SDRAM_A <= mem_a_i;
SDRAM_BA <= mem_ba_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_dout: entity work.my_ioddr
port map (
pin => SDRAM_DQ(i),
clock => clock,
D0 => wdata(8+i),
D1 => wdata(i),
T0 => wdata_tri(1),
T1 => wdata_tri(0),
Q0 => rdata_hi(i),
Q1 => rdata_lo(i) );
end generate;
select_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
i_dqm_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => wdqm(1),
D1 => wdqm(0),
R => '0',
S => '0' );
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/1541/vhdl_sim/harness_1541.vhd
|
5
|
5864
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std_logic_vector(17 downto 0);
signal sram_dq : std_logic_vector(31 downto 0);
signal sram_csn : std_logic;
signal sram_oen : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector(3 downto 0);
signal iec_atn : std_logic;
signal iec_data : std_logic;
signal iec_clock : std_logic;
---
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal mem_req : std_logic;
signal mem_readwriten : std_logic;
signal mem_address : std_logic_vector(19 downto 0) := (others => '0');
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
begin
-- 4 MHz clock
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
cpu: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
drive_select(0) => '0',
drive_select(1) => '0',
motor_on => motor_on,
mode => mode,
write_prot_n => '1',
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led );
iec_atn <= '0' when atn_o='0' else 'H'; -- open drain, with pull up
iec_clock <= '0' when clk_o='0' else 'H'; -- open drain, with pull up
iec_data <= '0' when data_o='0' else 'H'; -- open drain, with pull up
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
flop: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => '1', -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
-- signals from MOS 6522 VIA
motor_on => motor_on,
mode => mode,
write_prot_n => '1',
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
---
mem_clock => clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_readwriten,
mem_addr => mem_address,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
ram_ctrl: entity work.sram_8bit32
generic map (
SRAM_WR_ASU => 0,
SRAM_WR_Pulse => 1,
SRAM_WR_Hold => 2,
SRAM_RD_ASU => 0,
SRAM_RD_Pulse => 1,
SRAM_RD_Hold => 2 ) -- recovery time (bus turnaround)
port map (
clock => clock,
reset => reset,
req => mem_req,
readwriten => mem_readwriten,
address => mem_address,
rack => mem_rack,
dack => mem_dack,
wdata => mem_wdata,
rdata => mem_rdata,
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_DQ,
SRAM_BEn => SRAM_BEn );
sram: entity work.sram_model_32
generic map(18, 50 ns)
port map (SRAM_A, SRAM_DQ, SRAM_CSn, SRAM_BEn, SRAM_OEn, SRAM_WEn);
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
end structural;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/nano_cpu/vhdl_sim/ulpi_phy_bfm.vhd
|
10
|
10740
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end ulpi_phy_bfm;
architecture gideon of ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : integer := 0;
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_nxt_d : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
type t_data8 is array(natural range <>) of std_logic_vector(7 downto 0);
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
signal irq_status : std_logic_vector(7 downto 0) := X"00";
signal func_select : std_logic_vector(7 downto 0) := X"00";
signal intf_control : std_logic_vector(7 downto 0) := X"00";
signal otg_control : std_logic_vector(7 downto 0) := X"00";
signal scratch : std_logic_vector(7 downto 0) := X"00";
signal power : std_logic := '0';
signal power_level : std_logic_vector(1 downto 0) := "00";
signal pid : std_logic_vector(3 downto 0) := X"F";
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
function to_std(a : boolean) return std_logic is
begin
if (a) then
return '1';
else
return '0';
end if;
end function;
begin
crc_sync <= '1' when (state = idle) else '0';
irq_status(3) <= to_std(status_in(3 downto 2) = "01");
irq_status(2) <= status_in(3);
irq_status(1) <= to_std(status_in(3 downto 2) = "11");
status_in(3 downto 2) <= power_level;
process(power)
begin
if power'event then
if power = '1' then
power_level <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
elsif power = '0' then
power_level <= transport "11",
"10" after 3 us,
"01" after 6 us,
"00" after 10 us;
else
power_level <= "00";
end if;
end if;
end process;
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
variable a : integer;
begin
a := to_integer(unsigned(addr));
case a is
when 4 =>
func_select <= data;
if data(4 downto 0) = "10000" then -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
elsif data(4 downto 3) ="00" then -- normal operation
status_in(1 downto 0) <= data(1 downto 0); -- for the time being
end if;
when 7 =>
intf_control <= data;
when 8 =>
intf_control <= intf_control or data;
when 9 =>
intf_control <= intf_control and not data;
when 10 =>
otg_control <= data;
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
power <= '1';
else -- power off
report "Power Off";
power <= '0';
end if;
when 22 =>
scratch <= data;
when 23 =>
scratch <= scratch or data;
when 24 =>
scratch <= scratch and not data;
when others =>
null;
end case;
end procedure;
variable receive_buffer : t_data8(0 to 127);
variable transmit_buffer : t_data8(0 to 127);
variable receive_length : integer := 0;
variable transmit_length : integer := 0;
procedure determine_response is
begin
if receive_buffer(0) = X"43" then -- data0 packet
transmit_buffer(0) := X"D2";
transmit_length := 1;
do_send <= '1';
end if;
end procedure;
impure function read_ulpi_register(addr: std_logic_vector(5 downto 0)) return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
variable a : integer;
begin
a := to_integer(unsigned(addr));
ret := X"00";
case a is
when 19 | 20 =>
ret := irq_status;
when 0 =>
ret := X"24";
when 1|2 =>
ret := X"04";
when 4|5|6 =>
ret := func_select;
when 7|8|9 =>
ret := intf_control;
when 10|11|12 =>
ret := otg_control;
when 22|23|24 =>
ret := scratch;
when others =>
null;
end case;
return ret;
end function;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
counter <= 0;
byte_count := transmit_length;
elsif ulpi_dir_i = '0' then
pid <= ULPI_DATA(3 downto 0);
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
receive_length := 0;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
address := ULPI_DATA(5 downto 0);
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= transmit_buffer(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
report "Received packet with length = " & integer'image(receive_length);
determine_response;
else
if (ulpi_nxt_i = '1') and (pid /= X"0") then
receive_buffer(receive_length) := ULPI_DATA;
receive_length := receive_length + 1;
end if;
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= read_ulpi_register(address);
state <= idle;
when others =>
state <= idle;
end case;
ulpi_nxt_d <= ulpi_nxt_i;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => ulpi_nxt_d,
data_in => ULPI_DATA,
crc => data_crc );
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/sigma_delta_dac.vhd
|
4
|
2810
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sigma_delta_dac is
generic (
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end sigma_delta_dac;
architecture gideon of sigma_delta_dac is
-- signal converted : unsigned(g_width-1 downto 0);
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : unsigned(2 downto 0) := "000";
signal sine : signed(15 downto 0);
signal sine_enable : std_logic;
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
-- converted <= not sine(sine'high) & unsigned(sine(sine'high downto 0));
-- i_pilot: entity work.sine_osc
-- port map (
-- clock => clock,
-- enable => sine_enable,
-- reset => reset,
--
-- sine => sine,
-- cosine => open );
--
-- sine_enable <= '1' when divider="001" else '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
divider <= divider + 1;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
end if;
end if;
end process;
dac_out <= out_i;
end gideon;
|
gpl-3.0
|
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