repo_name
stringlengths 6
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stringlengths 5
236
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stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/assert_statement/rule_002_test_input.fixed.vhd
|
1
|
716
|
architecture ARCH of ENTITY1 is
begin
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
process begin
assert boolean report "Something" severity FAILURE;
end process;
assert boolean
report "Something" severity FAILURE;
end architecture ARCH;
|
gpl-3.0
|
Jorge9314/ElectronicaDigital
|
Impresora2D/antirebote.vhd
|
1
|
625
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity antirebote is
Port ( CLK : in STD_LOGIC;
a : in STD_LOGIC;
b : out STD_LOGIC);
end antirebote;
architecture Behavioral of antirebote is
signal cont : integer := 9999999;
begin
process begin
wait until rising_edge(CLK);
-- 10'000.000 -> reloj 50 Hz -> 200*(10**-3) / 20*(10**-9) = 10'000.000
b <= '0';
if (a = '0' and cont < 10000000) then
cont <= cont + 1;
end if;
if (a = '1' and cont < 10000000) then
cont <= cont + 1;
end if;
if (a = '1' and cont >= 10000000) then
b <= '1';
cont <= 0;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
J-Rios/VHDL_Modules
|
1.Combinational/Gate_NAND.vhd
|
1
|
435
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_NAND is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_NAND;
----------------------------------------------------------------------------------
architecture Behavioral of Gate_NAND is
begin
Z <= A nand B;
end Behavioral;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v7.vhd
|
5
|
21232
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v7 is
generic (
g_simulation : boolean := false;
g_read_fifo : boolean := false;
q_tcko_data : time := 100 ps;
A_Width : integer := 13;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
req : in t_mem_burst_32_req;
resp : out t_mem_burst_32_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_A : out std_logic_vector(A_Width-1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v7;
architecture Gideon of ext_mem_ctrl_v7 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002B", "000" ), -- mode register, burstlen=8, writelen=8, CAS lat = 2, interleaved
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ) );
type t_ints is array(natural range <>) of integer;
constant c_delays : t_ints(0 to 15) := (
2, 4, 2, 3, -- R2R (other row&other bank, other row, other bank, same row+bank)
4, 5, 4, 5, -- R2W
2, 5, 2, 3, -- W2R
2, 4, 2, 3 );-- W2W
type t_state is (boot, init, idle, sd_cas );
signal state : t_state;
signal sdram_d_o : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal sdram_d_t : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal wdata_tri : std_logic_vector(8 downto 0) := (others => '1');
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal mem_a_i : std_logic_vector(SDRAM_A'range) := (others => '0');
signal mem_ba_i : std_logic_vector(SDRAM_BA'range) := (others => '0');
signal cs_n_i : std_logic := '1';
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal do_refresh_d : std_logic := '0';
signal trigger_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_out : std_logic_vector(15 downto 0) := (others => '0');
signal wdata : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_i : std_logic_vector(35 downto 0) := (others => '0');
signal wdata_av : std_logic;
signal fifo_wdata_in : std_logic_vector(35 downto 0);
signal wdqm : std_logic_vector(1 downto 0);
signal dqm_override : std_logic := '1';
-- signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(5 downto 0) := "000000";
signal burst_start : std_logic_vector(5 downto 0) := "000000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal same_bank : std_logic;
signal last_row : std_logic_vector(12 downto 0) := "0101011010101";
signal addr_row : std_logic_vector(12 downto 0);
signal same_row : std_logic;
signal addr_column : std_logic_vector(9 downto 0);
signal next_activate : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal rwn_i : std_logic := '1';
signal tag_fifo : std_logic_vector(7 downto 0);
signal rdata_tag : std_logic_vector(7 downto 0);
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic := '0'; -- forced low for when there is no fifo
signal push_cmd : std_logic;
signal push_read_cmd : std_logic;
signal crazy_index_slv : std_logic_vector(3 downto 0);
signal crazy_index : integer range 0 to 15;
signal wtoggle : std_logic;
signal wdata_get : std_logic;
begin
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av and not do_refresh_d;
push_cmd <= req.request and not cmd_af;
push_read_cmd <= push_cmd and req.read_writen;
resp.ready <= not cmd_af;
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(address_fifo'length);
addr_bank <= address_fifo(14 downto 13);
addr_row <= address_fifo(24 downto 15) & address_fifo(12 downto 10);
addr_column <= address_fifo( 9 downto 0);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_tag_fifo: entity work.srl_fifo
generic map (
Width => 8,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => burst_start(1),
PutElement => push_read_cmd,
FlushFifo => '0',
DataIn => req.request_tag,
DataOut => tag_fifo,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => open );
rdata_out <= rdata_lo & rdata_hi;
b_read: block
signal rtoggle : std_logic;
signal rsp_data : std_logic_vector(31 downto 0);
signal rsp_data_tag : std_logic_vector(7 downto 0);
signal rsp_rdata_av : std_logic;
begin
-- data compacter 16->32
process(clock)
begin
if rising_edge(clock) then
-- handle reads
rsp_rdata_av <= '0';
if dack(0)='1' then
rtoggle <= not rtoggle;
if rtoggle='1' then
rsp_data(31 downto 16) <= rdata_out;
rsp_data_tag <= rdata_tag;
rsp_rdata_av <= '1';
else
rsp_data(15 downto 0) <= rdata_out;
end if;
end if;
-- reset
if reset='1' then
rtoggle <= '0';
rsp_data <= (others => '0');
rsp_data_tag <= (others => '0');
end if;
end if;
end process;
r_no_read_fifo: if not g_read_fifo generate
resp.rdata_av <= rsp_rdata_av;
resp.data <= rsp_data;
resp.data_tag <= rsp_data_tag;
end generate;
r_read_fifo: if g_read_fifo generate
i_read_fifo: entity work.srl_fifo
generic map (
Width => 40,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => rsp_rdata_av,
FlushFifo => '0',
DataIn(39 downto 32) => rsp_data_tag,
DataIn(31 downto 0) => rsp_data,
DataOut(39 downto 32) => resp.data_tag,
DataOut(31 downto 0) => resp.data,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => resp.rdata_av );
end generate;
end block;
fifo_wdata_in <= req.byte_en & req.data;
i_write_fifo: entity work.SRL_fifo
generic map (
Width => (c_data_width*9)/8,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => wdata_get,
PutElement => req.data_push,
FlushFifo => '0',
DataIn => fifo_wdata_in,
DataOut => wdata_i,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => wdata_av );
process(clock)
begin
if rising_edge(clock) then
if dnext(0)='1' then
wtoggle <= not wtoggle;
end if;
if reset='1' then
wtoggle <= '0';
end if;
end if;
end process;
wdata_get <= dnext(0) and wtoggle;
wdata(15 downto 0) <= wdata_i(15 downto 0) after 1 ns when wtoggle='0' else wdata_i(31 downto 16) after 1 ns;
wdata(17 downto 16) <= wdata_i(33 downto 32) after 1 ns when wtoggle='0' else wdata_i(35 downto 34) after 1 ns;
wdqm <= (others => '1') when dqm_override='1' else
(others => '0') when dnext(0)='0' else not wdata(17 downto 16);
same_row <= '1' when addr_row = last_row else '0';
same_bank <= '1' when addr_bank = last_bank else '0';
crazy_index_slv <= not rwn_i & not rwn_fifo & same_row & same_bank;
crazy_index <= to_integer(unsigned(crazy_index_slv));
trigger_refresh <= do_refresh_d and not (inhibit_d or inhibit);
process(clock)
procedure send_refresh_cmd is
begin
if next_delay = 0 then
do_refresh <= '0';
do_refresh_d <= '0';
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
col_addr <= addr_column;
last_bank <= addr_bank;
last_row <= addr_row;
mem_a_i(addr_row'range) <= addr_row;
mem_ba_i <= addr_bank;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
end procedure;
procedure issue_read_or_write is
begin
mem_a_i(9 downto 0) <= col_addr;
do_refresh_d <= do_refresh;
if req_i='0' or do_refresh='1' then
if rwn_i='0' then
next_delay <= 5;
else
next_delay <= 4;
end if;
mem_a_i(10) <= '1'; -- auto precharge
next_activate <= '1';
else
next_delay <= c_delays(crazy_index);
mem_a_i(10) <= not (same_row and same_bank); -- do not AP when we'll continue in same row
next_activate <= not (same_row and same_bank); -- only activate next time if we also AP.
end if;
if delay=0 then
if rwn_i='0' then
if wdata_av='1' then
wdata_tri(7 downto 0) <= (others => '0') after 1 ns;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
dnext <= "1111" after 1 ns;
state <= idle;
end if;
else
if rdata_af='0' then
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
dack(dack'high downto dack'high-3) <= (others => '1');
burst_start(2) <= '1';
state <= idle;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
cs_n_i <= '1' after 1 ns;
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
if burst_start(1)='1' then
rdata_tag <= tag_fifo;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
wdata_tri <= "11" & wdata_tri(wdata_tri'high downto 2) after 1 ns;
dack <= '0' & dack(dack'high downto 1);
burst_start <= '0' & burst_start(burst_start'high downto 1);
dnext <= '0' & dnext(dnext'high downto 1) after 1 ns;
case state is
when boot =>
enable_sdram <= '1';
if g_simulation then
state <= init;
elsif refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
mem_ba_i <= (others => '0'); -- for DDR and such, maybe the upper 2/3 bits
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if next_delay = 0 then
next_delay <= 7;
cs_n_i <= '0' after 1 ns;
if init_cnt = c_init_array'high then
state <= idle;
dqm_override <= '0';
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' then
if next_activate='1' and next_delay=0 then
accept_req;
elsif next_activate='0' and next_delay=1 then
rwn_i <= rwn_fifo;
col_addr <= addr_column;
state <= sd_cas;
end if;
else
do_refresh_d <= do_refresh;
end if;
end if;
when sd_cas =>
issue_read_or_write;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
rdata_tag <= (others => '0');
dqm_override <= '1';
state <= boot;
wdata_tri <= (others => '0');
delay <= 0;
next_delay <= 0;
do_refresh <= '0';
do_refresh_d <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
next_activate <= '1';
rwn_i <= '1';
end if;
end if;
end process;
-- Generate rack; the signal that indicates that a request is going to be issued
-- and thus taken from the command fifo.
process(state, trigger_refresh, inhibit, req_i, next_delay, next_activate)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
null;
elsif inhibit='0' and req_i='1' then
if next_activate='1' and next_delay = 0 then
rack <= '1';
elsif next_activate='0' and next_delay = 1 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
SDRAM_A <= mem_a_i;
SDRAM_BA <= mem_ba_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_dout: entity work.my_ioddr
port map (
pin => SDRAM_DQ(i),
clock => clock,
D0 => wdata(8+i),
D1 => wdata(i),
T0 => wdata_tri(1),
T1 => wdata_tri(0),
Q0 => rdata_hi(i),
Q1 => rdata_lo(i) );
end generate;
select_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
i_dqm_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => wdqm(1),
D1 => wdqm(0),
R => '0',
S => '0' );
end Gideon;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/1541/vhdl_sim/tb_floppy_stream.vhd
|
4
|
4531
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
entity tb_floppy_stream is
end tb_floppy_stream;
architecture tb of tb_floppy_stream is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal drv_rdata : std_logic_vector(7 downto 0) := X"01";
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
signal fifo_put : std_logic;
signal fifo_command : std_logic_vector(2 downto 0);
signal fifo_parameter : std_logic_vector(10 downto 0);
type t_buffer_array is array (natural range <>) of std_logic_vector(7 downto 0);
shared variable my_buffer : t_buffer_array(0 to 15) := (others => X"FF");
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy_stream
port map (
clock => clock,
clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
reset => reset,
drv_rdata => drv_rdata,
floppy_inserted => '1',
write_data => write_data,
fifo_put => fifo_put,
fifo_command => fifo_command,
fifo_parameter => fifo_parameter,
track => track,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
read_data => read_data );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
mode <= '0'; -- switch to write
wait;
end process;
fill: process
begin
wait until fifo_put='1';
wait for 10 ns;
if fifo_command = c_cmd_next then
drv_rdata <= drv_rdata + 1;
end if;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
end tb;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/ip/video/vhdl_source/char_generator.vhd
|
5
|
3411
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/cart_slot/vhdl_sim/reu_tc_1.vhd
|
5
|
6290
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/io/copper/vhdl_source/copper_engine.vhd
|
5
|
10510
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.copper_pkg.all;
entity copper_engine is
generic (
g_copper_size : natural := 12 );
port (
clock : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
phi2_tick : in std_logic;
ram_address : out unsigned(g_copper_size-1 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
ram_wdata : out std_logic_vector(7 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
control : in t_copper_control;
status : out t_copper_status );
end copper_engine;
architecture gideon of copper_engine is
signal irq_c : std_logic;
signal irq_d : std_logic;
signal opcode : std_logic_vector(7 downto 0);
signal sync : std_logic;
signal timer : unsigned(15 downto 0);
signal match : unsigned(15 downto 0);
signal addr_i : unsigned(ram_address'range);
type t_state is (idle, fetch, decode, fetch2, decode2, fetch3, decode3, wait_irq, wait_sync, wait_until, wait_dma,
record_start, recording, record_end);
signal state : t_state;
signal store_word : std_logic_vector(31 downto 0) := (others => '0');
signal store_trig : std_logic := '0';
signal fifo_dout : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_dav : std_logic;
signal fifo_pop : std_logic;
signal ram_we_i : std_logic;
begin
p_fsm: process(clock)
procedure process_fifo_data is
begin
if fifo_dav='1' then
addr_i <= addr_i + 1;
end if;
end procedure;
begin
if rising_edge(clock) then
irq_c <= not irq_n;
irq_d <= irq_c;
trigger_1 <= '0';
trigger_2 <= '0';
store_trig <= '0';
slot_resp <= c_slot_resp_init;
sync <= '0';
if timer = control.frame_length then
timer <= (others => '0');
sync <= '1';
elsif phi2_tick='1' then
timer <= timer + 1;
end if;
case state is
when idle =>
addr_i <= (others => '0');
case control.command is
when c_copper_cmd_play =>
state <= fetch;
status.running <= '1';
when c_copper_cmd_record =>
state <= record_start;
status.running <= '1';
when others =>
null;
end case;
when fetch =>
addr_i <= addr_i + 1;
state <= decode;
when decode =>
opcode <= ram_rdata;
if ram_rdata(7 downto 6) = c_copcode_write_reg(7 downto 6) then
state <= fetch2;
elsif ram_rdata(7 downto 6) = c_copcode_read_reg(7 downto 6) then
dma_req.request <= '1';
dma_req.read_writen <= '1';
dma_req.address <= X"D0" & "00" & unsigned(ram_rdata(5 downto 0));
state <= wait_dma;
else
case ram_rdata is
when c_copcode_wait_irq => -- waits until falling edge of IRQn
state <= wait_irq;
when c_copcode_wait_sync => -- waits until sync pulse from timer
state <= wait_sync;
when c_copcode_timer_clr => -- clears timer
timer <= (others => '0');
state <= fetch;
when c_copcode_capture => -- copies timer to measure register
status.measured_time <= timer;
state <= fetch;
when c_copcode_wait_for => -- takes a 1 byte argument
state <= fetch2;
when c_copcode_wait_until => -- takes 2 bytes argument (wait until timer match)
state <= fetch2;
when c_copcode_repeat => -- restart at program address 0.
addr_i <= (others => '0');
state <= fetch;
when c_copcode_end => -- ends operation and return to idle
state <= idle;
status.running <= '0';
when c_copcode_trigger_1 =>
trigger_1 <= '1';
state <= fetch;
when c_copcode_trigger_2 =>
trigger_2 <= '1';
state <= fetch;
when others =>
state <= fetch;
end case;
end if;
when wait_irq =>
if irq_c='1' and irq_d='0' then
state <= fetch;
end if;
when wait_sync =>
if sync='1' then
state <= fetch;
end if;
when fetch2 =>
addr_i <= addr_i + 1;
state <= decode2;
when decode2 =>
if opcode(7 downto 6) = c_copcode_write_reg(7 downto 6) then
dma_req.request <= '1';
dma_req.read_writen <= '0';
dma_req.address <= X"D0" & "00" & unsigned(opcode(5 downto 0));
dma_req.data <= ram_rdata;
state <= wait_dma;
else
case opcode is
when c_copcode_wait_for => -- takes a 1 byte argument
match <= timer + unsigned(ram_rdata);
state <= wait_until;
when c_copcode_wait_until => -- takes 2 bytes argument (wait until timer match)
match(7 downto 0) <= unsigned(ram_rdata);
state <= fetch3;
when others =>
state <= fetch; -- illegal opcode
end case;
end if;
when fetch3 =>
addr_i <= addr_i + 1;
state <= decode3;
when decode3 =>
-- the only opcode at this point requiring two bytes of opcode is the wait until..
match(15 downto 8) <= unsigned(ram_rdata);
state <= wait_until;
when wait_until =>
if timer = match then
state <= fetch;
end if;
when wait_dma =>
if dma_resp.rack='1' then
dma_req.request <= '0';
state <= fetch;
end if;
when record_start =>
if sync='1' then
state <= recording;
end if;
when recording =>
process_fifo_data;
if slot_req.bus_write='1' and slot_req.bus_address(15 downto 10)="110100" then
store_word(23 downto 16) <= std_logic_vector(slot_req.bus_address(7 downto 0));
store_word(31 downto 24) <= slot_req.data;
store_word(15 downto 0) <= std_logic_vector(timer);
store_trig <= '1';
end if;
if sync='1' then
store_word <= (others => '1');
store_trig <= '1';
state <= record_end;
end if;
when record_end =>
process_fifo_data;
if fifo_dav='0' and store_trig='0' then
state <= idle;
status.running <= '0';
end if;
when others =>
null;
end case;
if control.stop='1' then
state <= idle;
status.running <= '0';
dma_req.request <= '0';
end if;
if reset='1' then
state <= idle;
timer <= (others => '0');
match <= (others => '0');
status <= c_copper_status_init;
dma_req <= c_dma_req_init;
end if;
end if;
end process;
i_store_fifo: entity work.srl_fifo
generic map (
Width => 32,
Depth => 15,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => fifo_pop,
PutElement => store_trig,
FlushFifo => '0',
DataIn => store_word,
DataOut => fifo_dout,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => fifo_dav );
ram_we_i <= fifo_dav; -- whenever there is data, write!
fifo_pop <= '1' when addr_i(1 downto 0)="11" and ram_we_i='1' else '0'; -- pop data when we're writing the last byte of the word
with addr_i(1 downto 0) select
ram_wdata <=
fifo_dout(7 downto 0) when "00",
fifo_dout(15 downto 8) when "01",
fifo_dout(23 downto 16) when "10",
fifo_dout(31 downto 24) when others;
ram_address <= addr_i;
ram_we <= ram_we_i;
ram_en <= '1' when (state = fetch) or (state = fetch2) or (state = fetch3) or (ram_we_i='1') else '0';
end architecture;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate2_cached.vhd
|
4
|
9293
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/io/sigma_delta_dac/vhdl_source/hf_noise.vhd
|
3
|
3289
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hf_noise is
generic (
g_hp_filter : boolean := true );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
q : out signed(15 downto 0) );
end entity;
architecture structural of hf_noise is
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
constant c_type : string := "Fibonacci";
constant c_polynom : std_logic_vector := X"E10000";
constant c_seed : std_logic_vector := X"000001";
signal raw_lfsr : std_logic_vector(c_polynom'length-1 downto 0);
signal noise : signed(15 downto 0);
signal hp : signed(15 downto 0);
begin
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_seed => c_seed )
port map (
clock => clock,
enable => enable,
reset => reset,
q => raw_lfsr );
-- Reordering the bits somehow randomly,
-- gives a better spectral distribution
-- in case of Galois (flat!)! In face of Fibonacci,
-- this reordering gives ~20dB dips at odd
-- locations, depending on the reorder choice.
noise(15) <= raw_lfsr(1);
noise(14) <= raw_lfsr(4);
noise(13) <= raw_lfsr(7);
noise(12) <= raw_lfsr(10);
noise(11) <= raw_lfsr(13);
noise(10) <= raw_lfsr(16);
noise(09) <= raw_lfsr(19);
noise(08) <= raw_lfsr(22);
noise(07) <= raw_lfsr(20);
noise(06) <= raw_lfsr(17);
noise(05) <= raw_lfsr(14);
noise(04) <= raw_lfsr(11);
noise(03) <= raw_lfsr(8);
noise(02) <= raw_lfsr(5);
noise(01) <= raw_lfsr(2);
noise(00) <= raw_lfsr(18);
-- taking an up-range or down range gives a reasonably
-- flat frequency response, but lacks low frequencies (~20 dB)
-- In case of our high-freq noise that we need, this is not
-- a bad thing, as our filter doesn't need to be so sharp.
-- Fibonacci gives less low frequency noise than Galois!
-- differences seen with 1st order filter below were 5-10dB in
-- our band of interest.
-- noise <= signed(raw_lfsr(20 downto 5));
r_hp: if g_hp_filter generate
signal hp_a : signed(15 downto 0);
begin
i_hp: entity work.high_pass
generic map (
g_width => 15 )
port map (
clock => clock,
enable => enable,
reset => reset,
x => noise(14 downto 0),
-- q => hp_a );
-- i_hp_b: entity work.high_pass
-- generic map (
-- g_width => 16 )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- x => hp_a,
q => hp );
end generate;
q <= hp(15 downto 0) when g_hp_filter else noise;
end structural;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/sid6581/vhdl_sim/tb_oscillator.vhd
|
5
|
3080
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_oscillator is
end tb_oscillator;
architecture TB of tb_oscillator is
constant num_voices : integer := 8;
signal clk : std_logic := '0';
signal reset : std_logic;
signal freq : std_logic_vector(15 downto 0);
signal osc_val : std_logic_vector(23 downto 0);
signal voice_i : std_logic_vector(3 downto 0);
signal voice_o : std_logic_vector(3 downto 0);
signal voice_m : std_logic_vector(3 downto 0);
signal carry_20 : std_logic;
signal wave_out : std_logic_vector(7 downto 0);
signal wave_sel : std_logic_vector(3 downto 0);
type freq_array_t is array(natural range <>) of std_logic_vector(15 downto 0);
constant freq_array : freq_array_t(0 to 15) := ( X"A001", X"B003", X"B805", X"C000",
X"E00B", X"F00D", X"7011", X"FFFF",
X"0017", X"001D", X"0100", X"0200",
X"0400", X"0800", X"1000", X"2000" );
type sel_array_t is array(natural range <>) of std_logic_vector(3 downto 0);
constant sel_array : sel_array_t(0 to 15) := ( X"1", X"2", X"4", X"8", X"3", X"6", X"C", X"8",
X"9", X"7", X"E", X"D", X"B", X"5", X"A", X"F" );
type wave_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
signal wave_mem : wave_array_t (0 to num_voices-1) := (others => (others => '0'));
begin
clk <= not clk after 15 ns;
reset <= '1', '0' after 600 ns;
osc: entity work.oscillator
generic map (num_voices)
port map (
clk => clk,
reset => reset,
freq => freq,
voice_i => voice_i,
voice_o => voice_o,
osc_val => osc_val,
carry_20 => carry_20 );
process(clk)
begin
if rising_edge(clk) then
if reset='1' then
voice_i <= X"0";
elsif voice_i = num_voices-1 then
voice_i <= X"0";
else
voice_i <= voice_i + 1;
end if;
end if;
end process;
wmap: entity work.wave_map
generic map (
num_voices => 8, -- 8 or 16, clock should then be 8 or 16 MHz, too!
sample_bits=> 8 )
port map (
clk => clk,
reset => reset,
osc_val => osc_val,
carry_20 => carry_20,
voice_i => voice_o,
wave_sel => wave_sel,
sq_width => X"27D",
voice_o => voice_m,
wave_out => wave_out );
freq <= freq_array(conv_integer(voice_i));
wave_sel <= sel_array(conv_integer(voice_o));
process(clk)
begin
if rising_edge(clk) then
wave_mem(conv_integer(voice_m)) <= wave_out;
end if;
end process;
end TB;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/zpu/vhdl_source/blahram.vhd
|
5
|
2526
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_ram_size : natural := 13 );
port (
clock_a : in std_logic;
enable_a : in std_logic;
write_a : in std_logic;
address_a : in unsigned(g_ram_size-1 downto 2);
din_a : in unsigned(31 downto 0);
dout_a : out unsigned(31 downto 0);
clock_b : in std_logic;
enable_b : in std_logic;
write_b : in std_logic;
address_b : in unsigned(g_ram_size-1 downto 2);
din_b : in unsigned(31 downto 0);
dout_b : out unsigned(31 downto 0) );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram : entity is "yes";
end dpram;
architecture rtl of dpram is
constant c_num_words : integer := 2 ** (g_ram_size - 2);
type t_ram is array (0 to c_num_words-1) of unsigned(31 downto 0);
shared variable ram: t_ram := (others => X"00000000");
attribute ram_style : string;
attribute ram_style of ram : variable is "block";
begin
p_port_a: process (clock_a)
begin
if rising_edge(clock_a) then
if enable_a = '1' then
if write_a = '1' then
ram(to_integer(address_a)) := din_a;
-- synthesis translate_off
for i in din_a'range loop
assert din_a(i) = '0' or din_a(i) = '1'
report "Bit " & integer'image(i) & " is not 0 or 1."
severity failure;
end loop;
-- synthesis translate_on
end if;
dout_a <= ram(to_integer(address_a));
end if;
end if;
end process;
p_port_b: process (clock_b)
begin
if rising_edge(clock_b) then
if enable_b = '1' then
if write_b = '1' then
ram(to_integer(address_b)) := din_b;
-- synthesis translate_off
for i in din_b'range loop
assert din_b(i) = '0' or din_b(i) = '1'
report "Bit " & integer'image(i) & " is not 0 or 1, writing B."
severity failure;
end loop;
-- synthesis translate_on
end if;
dout_b <= ram(to_integer(address_b));
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/io/usb/vhdl_sim/ulpi_phy_bfm.vhd
|
3
|
6972
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end ulpi_phy_bfm;
architecture gideon of ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : unsigned(7 downto 0) := X"01";
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
begin
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
begin
if addr = "001010" then
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
if status_in(3)='0' then
status_in(3 downto 2) <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
end if;
else -- power off
report "Power Off";
status_in(3 downto 2) <= transport "11",
"10" after 1 us,
"01" after 2 us,
"00" after 3 us;
end if;
end if;
if addr = "000100" then
case data(2 downto 0) is
when "000" => -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
when "001"|"011" => -- powerup
status_in(1 downto 0) <= "11";
when "010" => -- unknown
status_in(1 downto 0) <= "00";
when "100" => -- peripheral chirp
status_in(1 downto 0) <= "10";
when "101"|"111" => -- peripheral FS
status_in(1 downto 0) <= "01";
when "110" => -- peripheral LS
status_in(1 downto 0) <= "10";
when others =>
null;
end case;
end if;
end procedure;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
byte_count := 20;
elsif ulpi_dir_i = '0' then
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= std_logic_vector(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
else
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= X"AA";
state <= idle;
when others =>
state <= idle;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
end gideon;
|
gpl-3.0
|
J-Rios/VHDL_Modules
|
2.Secuencial/RAM_dedicated.vhd
|
1
|
1343
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity BLOCKRAM is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
wr_en : in STD_LOGIC;
w_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
r_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
w_data : in STD_LOGIC_VECTOR(B-1 downto 0);
r_data : out STD_LOGIC_VECTOR(B-1 downto 0)
);
end BLOCKRAM;
-------------------------------------------------------------------------
architecture Behavioral of BLOCKRAM is
type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0);
signal array_reg : REG_FILE_TYPE;
begin
-- Read-First Mode
process(clk)
begin
if (rising_edge(clk)) then
if (wr_en = '1') then
array_reg(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data <= array_reg(to_integer(unsigned(r_addr)));
-- Write-First Mode
--process(clk)
--begin
--if (rising_edge(clk)) then
--if (wr_en = '1') then
--array_reg(to_integer(unsigned(w_addr))) <= w_data;
--r_data <= w_data;
--else
--r_data <= array_reg(to_integer(unsigned(r_addr)));
--end if;
--end if;
--end process;
end Behavioral;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/ip/busses/vhdl_bfm/mem_bus_master_bfm.vhd
|
5
|
2769
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
|
gpl-3.0
|
timofonic/1541UltimateII
|
fpga/io/usb/vhdl_source/ulpi_rx.vhd
|
3
|
5919
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo_with_checkers_top.vhd
|
3
|
5452
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_with_checkers_top is
port ( Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_in_out: out std_logic_vector(7 downto 0);
ReConf_FF_in_out: out std_logic;
-- Checker outputs
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_with_checkers_top;
architecture behavior of Rxy_Reconf_pseudo_with_checkers_top is
component Rxy_Reconf_pseudo is
port ( Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_in: out std_logic_vector(7 downto 0);
ReConf_FF_in: out std_logic
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
signal Rxy_in_sig: std_logic_vector (7 downto 0);
signal ReConf_FF_in_sig: std_logic;
begin
Rxy_in_out <= Rxy_in_sig;
ReConf_FF_in_out <= ReConf_FF_in_sig;
-- Rxy Reconfiguration (pseudo-combinational) module instantiation
Rxy_Reconf_pseudo0 : Rxy_Reconf_pseudo
port map (
Rxy_reconf => Rxy_reconf,
ReConf_FF_out => ReConf_FF_out,
Rxy => Rxy,
Reconfig => Reconfig,
flit_type => flit_type,
grants => grants,
empty => empty,
Rxy_in => Rxy_in_sig,
ReConf_FF_in => ReConf_FF_in_sig
);
CHECKERS : Rxy_Reconf_pseudo_checkers
port map (
ReConf_FF_out => ReConf_FF_out,
flit_type => flit_type,
empty => empty,
grants => grants,
Rxy_in => Rxy_in_sig,
Rxy_reconf => Rxy_reconf,
ReConf_FF_in => ReConf_FF_in_sig,
Rxy => Rxy,
Reconfig => Reconfig,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal
);
end;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/gamma.vhd
|
5
|
2501
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end gamma;
architecture Behavioral of gamma is
signal a_0_tmp_s : std_logic_vector(31 downto 0);
signal a_1_tmp_s : std_logic_vector(31 downto 0);
signal a_2_tmp_s : std_logic_vector(31 downto 0);
signal a_3_tmp_s : std_logic_vector(31 downto 0);
signal a_1_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_2_tmp_s : std_logic_vector(31 downto 0);
begin
--Gamma(a){
-- a[1] ^= ~a[3]&~a[2];
-- a[0] ^= a[2]& a[1];
-- tmp = a[3];
-- a[3] = a[0];
-- a[0] = tmp;
-- a[2] ^= a[0]^a[1]^a[3];
-- a[1] ^= ~a[3]&~a[2];
-- a[0] ^= a[2]& a[1];
--}
a_1_tmp_s <= a_1_in xor (not(a_3_in) and not(a_2_in)); -- a[1] ^= ~a[3]&~a[2];
a_0_tmp_s <= a_0_in xor (a_2_in and a_1_tmp_s); -- a[2]& a[1];
a_0_1_tmp_s <= a_3_in; -- a[0] = a[3];
a_3_tmp_s <= a_0_tmp_s; -- a[3] = a[0];
a_2_tmp_s <= a_0_1_tmp_s xor a_1_tmp_s xor a_2_in xor a_3_tmp_s; -- a[2] ^= a[0]^a[1]^a[3];
a_1_1_tmp_s <= a_1_tmp_s xor (not(a_3_tmp_s) and not(a_2_tmp_s)); -- a[1] ^= ~a[3]&~a[2];
a_0_2_tmp_s <= a_0_1_tmp_s xor (a_2_tmp_s and a_1_1_tmp_s); -- a[0] ^= a[2]& a[1];
a_3_out <= a_3_tmp_s;
a_2_out <= a_2_tmp_s;
a_1_out <= a_1_1_tmp_s;
a_0_out <= a_0_2_tmp_s;
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/Router_32_bit_credit_based_parity.vhd
|
3
|
16261
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
rogerioag/gcg
|
samples/unidade_a0/src/or2.vhd
|
1
|
238
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity or2 is
port(x, y: in std_logic; z: out std_logic);
end or2;
architecture logica of or2 is
begin
z <= x or y;
end logica;
|
gpl-3.0
|
rogerioag/gcg
|
samples/or2/templates/entity_tb.vhd
|
4
|
3064
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- print messages.
use std.textio.all;
use ieee.std_logic_textio.all;
entity <<ENTITY_NAME>>_tb is
end <<ENTITY_NAME>>_tb;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>>_tb is
-- Component declaration.
component <<ENTITY_NAME>>
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end component;
-- Specifies the entity which is linked with the component. (Especifica qual a entidade está vinculada com o componente).
for <<ENTITY_NAME>>_0: <<ENTITY_NAME>> use entity work.<<ENTITY_NAME>>;
signal <<s_t_sinais>>: <<type>>;
-- procedure print messages definition.
procedure print_message(<<params_in>>: <<type>>; <<params_out>>: <<type>>; <<params_exp>>: <<type>>) is
variable line_out: line;
begin
write(line_out, string'(" At time "));
write(line_out, now);
write(line_out, string'(", inputs ["));
<<print_in_var_values>>
write(line_out, string'("]"));
write(line_out, string'(", outputs ["));
<<print_out_var_values>>
write(line_out, string'("]"));
if <<compare_gen_exp>> then
write(line_out, string'(" [OK]"));
else
write(line_out, string'(" [Error]"));
end if;
writeline(output, line_out);
end procedure print_message;
begin
-- Component instantiation.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
<<ENTITY_NAME>>_0: <<ENTITY_NAME>> port map (<<port_map_entity_tb>>);
-- Process that works.
process
-- line to print.
variable line_out: line;
-- A record is created with the inputs and outputs of the entity.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- inputs.
<<record_in_vars>>: <<type>>;
-- outputs.
<<record_out_vars>>: <<type>>;
end record;
-- The input patterns are applied (injected) to the inputs of the entity under test.
type pattern_array is array (natural range <>) of pattern_type;
-- Test cases.
constant patterns : pattern_array :=
(
(test cases with <<case_test_model>> columns, '0'...),
(...)
);
begin
-- Message starting...
write(line_out, string'("Running testbench: <<ENTITY_NAME>>_tb."));
writeline(output, line_out);
write(line_out, string'(" Testing entity: <<ENTITY_NAME>>."));
writeline(output, line_out);
-- Injects the inputs and check thte outputs.
for i in patterns'range loop
-- Injects the inputs.
<<inputs_signals_injection>>
-- wait for results.
wait for 1 ns;
-- Checks the result with the expected output in the pattern.
print_message(<<params_in_print_call>>, <<params_out_print_call>>, <<params_exp_print_call>>);
<<asserts_vars>>
end loop;
write(line_out, string'("Execution of <<ENTITY_NAME>>_tb finished."));
writeline(output, line_out);
assert false report "End of test." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end <<ARCH_TYPE>>;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/rc_gen.vhd
|
5
|
1656
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- 0 (enc), 1 (dec)
rc_out : out std_logic_vector(7 downto 0));
end rc_gen;
architecture Behavioral of rc_gen is
signal rc_s : std_logic_vector(7 downto 0);
begin
pr_gen: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
rc_s <= X"80";
else
rc_s <= X"D4";
end if;
else
if enc = '0' then
if ((rc_s and X"80") = X"00") then
rc_s <= rc_s(6 downto 0) & '0';
else
rc_s <= (rc_s(6 downto 0) & '0') xor X"1B";
end if;
else
if ((rc_s and X"01") = X"00") then
rc_s <= '0' & rc_s(7 downto 1);
else
rc_s <= ('0' & rc_s(7 downto 1)) xor X"8D";
end if;
end if;
end if;
end if;
end process;
rc_out <= rc_s;
end Behavioral;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_2/pi_1.vhd
|
5
|
1312
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end pi_1;
architecture Behavioral of pi_1 is
begin
a_1_out <= a_1_in(30 downto 0) & a_1_in(31);
a_2_out <= a_2_in(26 downto 0) & a_2_in(31 downto 27);
a_3_out <= a_3_in(29 downto 0) & a_3_in(31 downto 30);
end Behavioral;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_1/noekeon_pipe/rc_shr.vhd
|
1
|
1390
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:46 02/24/2015
-- Design Name:
-- Module Name: rc_shr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(271 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end rc_shr;
architecture Behavioral of rc_shr is
signal sh_reg : std_logic_vector(271 downto 0);
begin
pr_shr: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
sh_reg <= rc_in;
else
sh_reg <= sh_reg(263 downto 0) & sh_reg(271 downto 264);
end if;
end if;
end process;
rc_out <= sh_reg(271 downto 264);
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/NI_Test/counter_threshold.vhd
|
9
|
3773
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/xbar.vhd
|
20
|
1004
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/xbar.vhd
|
20
|
1004
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers_with_checkers_top.vhd
|
3
|
52963
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_with_checkers_top is
port ( valid_in : in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
state_out: in std_logic_vector(4 downto 0);
faulty_packet_out: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
fault_info: out std_logic;
health_info: out std_logic;
read_en_out: out std_logic;
write_en_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
state_in: out std_logic_vector(4 downto 0);
faulty_packet_in: out std_logic;
fake_credit_out: out std_logic;
write_fake_flit_out: out std_logic;
fake_credit_counter_in: out std_logic_vector(1 downto 0);
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_with_checkers_top;
architecture behavior of FIFO_credit_based_control_part_with_checkers_top is
component FIFO_credit_based_pseudo is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
state_out: in std_logic_vector(4 downto 0);
faulty_packet_out: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
credit_out: out std_logic; -- credit_out removed due to creation of pseudo-combinational register, credit_out directly taken to the output interface.
empty_out: out std_logic;
full_out: out std_logic;
fault_info: out std_logic;
health_info: out std_logic;
read_en_out: out std_logic;
write_en_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
state_in: out std_logic_vector(4 downto 0);
faulty_packet_in: out std_logic;
fake_credit_out: out std_logic;
write_fake_flit_out: out std_logic;
fake_credit_counter_in: out std_logic_vector(1 downto 0)
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end component;
signal credit_out_sig: std_logic;
signal empty_out_sig, full_out_sig, fault_info_sig, health_info_sig, read_en_out_sig, write_en_out_sig: std_logic;
signal read_pointer_in_sig, write_pointer_in_sig: std_logic_vector(3 downto 0);
signal state_in_sig: std_logic_vector(4 downto 0);
signal faulty_packet_in_sig: std_logic;
signal fake_credit_out_sig: std_logic;
signal write_fake_flit_out_sig: std_logic;
signal fake_credit_counter_in_sig: std_logic_vector(1 downto 0);
begin
credit_out <= credit_out_sig;
empty_out <= empty_out_sig;
full_out <= full_out_sig;
fault_info <= fault_info_sig;
health_info <= health_info_sig;
read_en_out <= read_en_out_sig;
write_en_out <= write_en_out_sig;
read_pointer_in <= read_pointer_in_sig;
write_pointer_in <= write_pointer_in_sig;
state_in <= state_in_sig;
faulty_packet_in <= faulty_packet_in_sig;
fake_credit_out <= fake_credit_out_sig;
write_fake_flit_out <= write_fake_flit_out_sig;
fake_credit_counter_in <= fake_credit_counter_in_sig;
-- Credit-Based FIFO Control Part with Packet dropping instantiation
FIFO_CREDIT_BASED_CONTROL_PART_PSEUDO: FIFO_credit_based_pseudo port map ( valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
write_pointer => write_pointer,
state_out => state_out,
faulty_packet_out => faulty_packet_out,
fake_credit_counter => fake_credit_counter,
flit_type => flit_type,
fault_out => fault_out,
credit_out => credit_out_sig,
empty_out => empty_out_sig,
full_out => full_out_sig,
fault_info => fault_info_sig,
health_info => health_info_sig,
read_en_out => read_en_out_sig,
write_en_out => write_en_out_sig,
read_pointer_in => read_pointer_in_sig,
write_pointer_in => write_pointer_in_sig,
state_in => state_in_sig,
faulty_packet_in => faulty_packet_in_sig,
fake_credit_out => fake_credit_out_sig,
write_fake_flit_out => write_fake_flit_out_sig,
fake_credit_counter_in => fake_credit_counter_in_sig
);
-- Checkers instantiation
CHECKERS: FIFO_credit_based_control_part_checkers port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in_sig,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in_sig,
credit_out => credit_out_sig,
empty_out => empty_out_sig,
full_out => full_out_sig,
read_en_out => read_en_out_sig,
write_en_out => write_en_out_sig,
fake_credit => fake_credit_out_sig,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in_sig,
state_out => state_out,
state_in => state_in_sig,
fault_info => fault_info_sig,
health_info => health_info_sig,
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in_sig,
flit_type => flit_type,
fault_out => fault_out,
write_fake_flit => write_fake_flit_out_sig,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change => err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info => err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info => err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info => err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info => err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info => err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info => err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info => err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info => err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info => err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info => err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change,
--err_state_out_invalid_state_in_state_out_not_change => err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info => err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info => err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit => err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit => err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change => err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change
);
end behavior;
|
gpl-3.0
|
os-cillation/easyfpga-soc
|
easy_cores/wishbone_slave/wbs_dual_out.vhd
|
1
|
4931
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E S L A V E (wbs_dual_out.vhd)
-- with two output registers
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package wbs_defs is
type wbs_reg_type is record
reg1 : std_logic_vector(WB_DW-1 downto 0);
reg2 : std_logic_vector(WB_DW-1 downto 0);
end record;
component wbs_dual_out
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.wbs_defs.all;
-------------------------------------------------------------------------------
entity wbs_dual_out is
-------------------------------------------------------------------------------
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end wbs_dual_out;
-------------------------------------------------------------------------------
architecture behavioral of wbs_dual_out is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
constant REG1_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"00";
constant REG2_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"01";
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : wbs_reg_type;
signal reg1_adr_match_s, reg2_adr_match_s : std_logic;
signal reg1_ce_s, reg2_ce_s : std_logic;
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
reg1_adr_match_s <= '1' when wbs_in.adr = REG1_ADR else '0';
reg2_adr_match_s <= '1' when wbs_in.adr = REG2_ADR else '0';
-- register CE
reg1_ce_s <= wbs_in.stb AND wbs_in.we AND reg1_adr_match_s;
reg2_ce_s <= wbs_in.stb AND wbs_in.we AND reg2_adr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
reg_in_s.reg1 <= wbs_in.dat;
reg_in_s.reg2 <= wbs_in.dat;
-- register output -> wbs_out via demultiplexer
with wbs_in.adr select
wbs_out.dat <= reg_out_s.reg1 when REG1_ADR,
reg_out_s.reg2 when REG2_ADR,
(others => '-') when others;
-- register outputs -> non-wishbone outputs
reg1_out <= reg_out_s.reg1;
reg2_out <= reg_out_s.reg2;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- store reg1
if (reg1_ce_s = '1') then
reg_out_s.reg1 <= reg_in_s.reg1;
-- store reg2
elsif (reg2_ce_s = '1') then
reg_out_s.reg2 <= reg_in_s.reg2;
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/theta.vhd
|
5
|
3797
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end theta;
architecture Behavioral of theta is
signal a_1_0_s : std_logic_vector(31 downto 0);
signal a_3_0_s : std_logic_vector(31 downto 0);
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
signal m_1_tmp_0_s : std_logic_vector(31 downto 0);
signal m_1_tmp_1_s : std_logic_vector(31 downto 0);
signal m_1_tmp_2_s : std_logic_vector(31 downto 0);
signal m_1_tmp_3_s : std_logic_vector(31 downto 0);
signal m_2_tmp_0_s : std_logic_vector(31 downto 0);
signal m_2_tmp_1_s : std_logic_vector(31 downto 0);
signal m_2_tmp_2_s : std_logic_vector(31 downto 0);
signal m_2_tmp_3_s : std_logic_vector(31 downto 0);
begin
--Theta(k,a){
-- temp = a[0]^a[2];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[1] ^= temp;
-- a[3] ^= temp;
-- a[0] ^= k[0];
-- a[1] ^= k[1];
-- a[2] ^= k[2];
-- a[3] ^= k[3];
-- temp = a[1]^a[3];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[0] ^= temp;
-- a[2] ^= temp;
--}
m_1_tmp_0_s <= a_0_in xor a_2_in; -- temp = a[0]^a[2];
m_1_tmp_1_s <= m_1_tmp_0_s(23 downto 0) & m_1_tmp_0_s(31 downto 24); -- temp>>>8
m_1_tmp_2_s <= m_1_tmp_0_s(7 downto 0) & m_1_tmp_0_s(31 downto 8); -- temp<<<8;
m_1_tmp_3_s <= m_1_tmp_0_s xor m_1_tmp_1_s xor m_1_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_1_0_s <= a_1_in xor m_1_tmp_3_s; -- a[1] ^= temp;
a_3_0_s <= a_3_in xor m_1_tmp_3_s; -- a[3] ^= temp;
tmp_0_s <= a_0_in xor k_0_in; -- a[0] ^= k[0];
tmp_1_s <= a_1_0_s xor k_1_in; -- a[1] ^= k[1];
tmp_2_s <= a_2_in xor k_2_in; -- a[2] ^= k[2];
tmp_3_s <= a_3_0_s xor k_3_in; -- a[3] ^= k[3];
m_2_tmp_0_s <= tmp_1_s xor tmp_3_s; -- temp = a[1]^a[3];
m_2_tmp_1_s <= m_2_tmp_0_s(23 downto 0) & m_2_tmp_0_s(31 downto 24); -- temp>>>8
m_2_tmp_2_s <= m_2_tmp_0_s(7 downto 0) & m_2_tmp_0_s(31 downto 8); -- temp<<<8;
m_2_tmp_3_s <= m_2_tmp_0_s xor m_2_tmp_1_s xor m_2_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_0_out <= tmp_0_s xor m_2_tmp_3_s; -- a[0] ^= temp;
a_2_out <= tmp_2_s xor m_2_tmp_3_s; -- a[2] ^= temp;
a_1_out <= tmp_1_s;
a_3_out <= tmp_3_s;
end Behavioral;
|
gpl-3.0
|
os-cillation/easyfpga-soc
|
infrastructure/enable_controller.vhd
|
1
|
3065
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- E N A B L E C O N T R O L L E R
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enable_controller is
port (
-- mcu interface
fpga_active_i : in std_logic;
mcu_active_o : out std_logic;
-- soc interface
mcu_select_i : in std_logic;
fifo_enable_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end enable_controller;
architecture fsm of enable_controller is
type state_type is (mcu_active, fpga_active, switch_to_mcu);
signal current_state, next_state : state_type;
begin
-------------------------------------------------
-- Combinational next state and output logic
-------------------------------------------------
STATEMACHINE : process (current_state, fpga_active_i, mcu_select_i) is
begin
case current_state is
when mcu_active =>
fifo_enable_o <= '0';
mcu_active_o <= '1';
if rising_edge(fpga_active_i) then
next_state <= fpga_active;
else
next_state <= mcu_active;
end if;
when fpga_active =>
fifo_enable_o <= '1';
mcu_active_o <= '0';
if mcu_select_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= fpga_active;
end if;
when switch_to_mcu =>
fifo_enable_o <= '1';
mcu_active_o <= '1';
if fpga_active_i = '1' then
next_state <= switch_to_mcu;
else
next_state <= mcu_active;
end if;
end case;
end process STATEMACHINE;
-------------------------------------------------------------------
-- State register with sync reset. Resets to mcu_active state
-------------------------------------------------------------------
STATE_REGISTER : process (clk_i, rst_i) is
begin
if (rising_edge(clk_i)) then
if (rst_i = '1') then
current_state <= mcu_active;
else
current_state <= next_state;
end if;
end if;
end process STATE_REGISTER;
end fsm;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_2/noekeon_pipe/tb_reg_128_s.vhd
|
8
|
1067
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/eth_dma.vhd
|
12
|
6966
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/eth_dma.vhd
|
12
|
6966
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/LBDR_packet_drop_with_checkers_with_FI/Rxy_Reconf_pseudo_checkers.vhd
|
3
|
5092
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_tmp)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_tmp) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp <= '0';
end if;
end process;
-- Checked (changed)!
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in /= '0') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '1' and ReConf_FF_in /= '1') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in <= '0';
end if;
end process;
-- Checked (changed)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, Rxy_tmp_in, Rxy_reconf_PE)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '1' and Rxy_tmp_in /= Rxy_reconf_PE) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (Added)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, Rxy_tmp_in, Rxy_tmp)
begin
if ( (((ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '0') or
(ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1')) and Rxy_tmp_in /= Rxy_tmp) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal <= '0';
end if;
end process;
-- Checked (Added)!
process(ReConf_FF_out, flit_type, empty, grants, Reconfig_command, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig_command = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
-- Checked (updated)!
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_out_one_hot_pseudo_checkers.vhd
|
3
|
18996
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end Arbiter_out_one_hot_pseudo_checkers;
architecture behavior of Arbiter_out_one_hot_pseudo_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L;
-- Checkers
process (Requests, state_in)
begin
err_Requests_state_in_state_not_equal <= '0';
if (Requests = "00000" and state_in /= IDLE ) then
err_Requests_state_in_state_not_equal <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
-- Round 1
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_req_X_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_req_X_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_req_X_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_req_X_N <= '1';
end if;
end process;
process (state, credit, req_X_N, grant_Y_N)
begin
err_North_credit_not_zero_req_X_N_grant_N <= '0';
if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then
err_North_credit_not_zero_req_X_N_grant_N <= '1';
end if;
end process;
process (state, credit, req_X_N, grant_Y_N)
begin
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0';
if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_req_X_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_req_X_E <= '1';
end if;
end process;
process (state, credit, req_X_E, grant_Y_E)
begin
err_East_credit_not_zero_req_X_E_grant_E <= '0';
if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then
err_East_credit_not_zero_req_X_E_grant_E <= '1';
end if;
end process;
process (state, credit, req_X_E, grant_Y_E)
begin
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0';
if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_req_X_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_req_X_W <= '1';
end if;
end process;
process (state, credit, req_X_W, grant_Y_W)
begin
err_West_credit_not_zero_req_X_W_grant_W <= '0';
if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then
err_West_credit_not_zero_req_X_W_grant_W <= '1';
end if;
end process;
process (state, credit, req_X_W, grant_Y_W)
begin
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0';
if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_req_X_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_req_X_S <= '1';
end if;
end process;
process (state, credit, req_X_S, grant_Y_S)
begin
err_South_credit_not_zero_req_X_S_grant_S <= '0';
if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then
err_South_credit_not_zero_req_X_S_grant_S <= '1';
end if;
end process;
process (state, credit, req_X_S, grant_Y_S)
begin
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0';
if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_req_X_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_req_X_L <= '1';
end if;
end process;
process (state, credit, req_X_L, grant_Y_L)
begin
err_Local_credit_not_zero_req_X_L_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then
err_Local_credit_not_zero_req_X_L_grant_L <= '1';
end if;
end process;
process (state, credit, req_X_L, grant_Y_L)
begin
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
-- IDLE
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_req_X_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_req_X_E <= '1';
end if;
end process;
-- North
process (state, req_X_N, req_X_E, state_in)
begin
err_North_req_X_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_req_X_E <= '1';
end if;
end process;
-- East
process (state, req_X_E, req_X_W, state_in)
begin
err_East_req_X_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_req_X_W <= '1';
end if;
end process;
-- West
process (state, req_X_W, req_X_S, state_in)
begin
err_West_req_X_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_req_X_S <= '1';
end if;
end process;
-- South
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_req_X_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_req_X_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_req_X_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_req_X_N <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_req_X_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_req_X_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_req_X_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_req_X_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_req_X_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_req_X_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_req_X_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_req_X_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_req_X_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_req_X_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_req_X_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_req_X_E <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_req_X_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_req_X_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_req_X_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_req_X_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_req_X_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_req_X_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_req_X_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_req_X_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_req_X_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_req_X_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_req_X_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_req_X_W <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_req_X_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_req_X_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_req_X_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_req_X_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_req_X_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_req_X_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_req_X_E <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_req_X_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_req_X_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_req_X_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_req_X_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_req_X_S <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, state_in)
begin
err_request_IDLE_state <= '0';
if (Requests /= "00000" and state_in = IDLE) then
err_request_IDLE_state <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state, Grants)
begin
err_request_IDLE_not_Grants <= '0';
if (state = IDLE and Grants /= "00000") then
err_request_IDLE_not_Grants <= '1';
end if;
end process;
process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L)
begin
err_state_North_Invalid_Grant <= '0';
if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_North_Invalid_Grant <= '1';
end if;
end process;
process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L)
begin
err_state_East_Invalid_Grant <= '0';
if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_East_Invalid_Grant <= '1';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L)
begin
err_state_West_Invalid_Grant <= '0';
if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_West_Invalid_Grant <= '1';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L)
begin
err_state_South_Invalid_Grant <= '0';
if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then
err_state_South_Invalid_Grant <= '1';
end if;
end process;
-- Local or invalid state(s) (a bit different logic!)
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S)
begin
err_state_Local_Invalid_Grant <= '0';
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and
(grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then
err_state_Local_Invalid_Grant <= '1';
end if;
end process;
-- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them !
process (Grants)
begin
err_Grants_onehot_or_all_zero <= '0';
if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_Grants_onehot_or_all_zero <= '1';
end if;
end process;
end behavior;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/mlite_cpu.vhd
|
12
|
13651
|
---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a two or three stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #0:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #1:
-- 2. The memory returns the opcode.
-- Stage #2:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #3 (part of stage #2 if using two stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #3b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a two stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 0 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been Instantiated
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
-- * A specific memory address in external ram has been blocked to be used by the NI
-- * IRQ return address register have been changed! It used to be saved in R0, now it is R26
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mlite_cpu is
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
architecture logic of mlite_cpu is
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc_future : std_logic_vector(31 downto 2);
signal pc_current : std_logic_vector(31 downto 2);
signal pc_plus4 : std_logic_vector(31 downto 2);
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal exception_sig : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= ((mem_pause or pause_ctrl or pause_mult) and not pause_pipeline);
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
or intr_signal = '1' or exception_sig = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
intr_signal <= '0';
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
--don't try to interrupt a multi-cycle instruction
if pause_any = '0' then
if intr_in = '1' and intr_enable = '1' and pc_source = FROM_INC4 then -- pc_source = "00"
--the epc will contain pc+4
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end if;
end process;
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_future => pc_future,
pc_current => pc_current,
pc_plus4 => pc_plus4);
u2_mem_ctrl: mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
address_next => address_next,
byte_we_next => byte_we_next,
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r);
u3_control: control PORT MAP (
opcode => opcode, -- is it opcode or the whole instruction ??
intr_signal => intr_signal,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
mem_source_out=> mem_source,
exception_out=> exception_sig);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
interrupt_in => intr_in,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch);
u6_alu: alu
generic map (alu_type => alu_type)
port map (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
u7_shifter: shifter
generic map (shifter_type => shifter_type)
port map (
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
u8_mult: mult
generic map (mult_type => mult_type)
port map (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
pipeline2: if pipeline_stages <= 2 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
reg_destD <= reg_dest;
pause_pipeline <= '0';
end generate; --pipeline2
pipeline3: if pipeline_stages > 2 generate
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline3
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/LBDR_packet_drop_routing_part_pseudo_checkers.vhd
|
12
|
13914
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
--process (flit_type, empty, Requests_in)
--begin
-- if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and
-- Requests_in /= "00100" and Requests_in /= "01000" and Requests_in /= "10000") then
-- err_header_not_empty_Requests_in_onehot <= '1';
-- else
-- err_header_not_empty_Requests_in_onehot <= '0';
-- end if;
--end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, cur_addr, dst_addr, Req_L_in, Req_L_FF)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in /= Req_L_FF) then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if (flit_type = "001" and empty = '0' and ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='0' ) and dst_addr /= cur_addr and packet_drop_in <= '0' ) then
err_header_not_empty_packet_drop_in <= '1';
else
err_header_not_empty_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '0' and ( ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='1' ) or (dst_addr = cur_addr) ) and packet_drop_in /= packet_drop ) then
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '1';
else
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/LBDR_routing_part/RTL/LBDR_packet_drop_routing_part_pseudo_checkers.vhd
|
12
|
13914
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
--process (flit_type, empty, Requests_in)
--begin
-- if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and
-- Requests_in /= "00100" and Requests_in /= "01000" and Requests_in /= "10000") then
-- err_header_not_empty_Requests_in_onehot <= '1';
-- else
-- err_header_not_empty_Requests_in_onehot <= '0';
-- end if;
--end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, cur_addr, dst_addr, Req_L_in, Req_L_FF)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in /= Req_L_FF) then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if (flit_type = "001" and empty = '0' and ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='0' ) and dst_addr /= cur_addr and packet_drop_in <= '0' ) then
err_header_not_empty_packet_drop_in <= '1';
else
err_header_not_empty_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '0' and ( ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='1' ) or (dst_addr = cur_addr) ) and packet_drop_in /= packet_drop ) then
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '1';
else
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_logic_checkers/allocator_logic_pseudo.vhd
|
3
|
4094
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
grant_N_out, grant_E_out, grant_W_out, grant_S_out, grant_L_out : out std_logic
);
end allocator_logic_pseudo;
architecture behavior of allocator_logic_pseudo is
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
begin
-- The combionational part
-- We did this because of the checkers
grant_N_out <= grant_N;
grant_E_out <= grant_E;
grant_W_out <= grant_W;
grant_S_out <= grant_S;
grant_L_out <= grant_L;
---------------------------------------------
grant_N_N <= grant_N_N_sig and not empty_N;
grant_N_E <= grant_N_E_sig and not empty_E;
grant_N_W <= grant_N_W_sig and not empty_W;
grant_N_S <= grant_N_S_sig and not empty_S;
grant_N_L <= grant_N_L_sig and not empty_L;
grant_E_N <= grant_E_N_sig and not empty_N;
grant_E_E <= grant_E_E_sig and not empty_E;
grant_E_W <= grant_E_W_sig and not empty_W;
grant_E_S <= grant_E_S_sig and not empty_S;
grant_E_L <= grant_E_L_sig and not empty_L;
grant_W_N <= grant_W_N_sig and not empty_N;
grant_W_E <= grant_W_E_sig and not empty_E;
grant_W_W <= grant_W_W_sig and not empty_W;
grant_W_S <= grant_W_S_sig and not empty_S;
grant_W_L <= grant_W_L_sig and not empty_L;
grant_S_N <= grant_S_N_sig and not empty_N;
grant_S_E <= grant_S_E_sig and not empty_E;
grant_S_W <= grant_S_W_sig and not empty_W;
grant_S_S <= grant_S_S_sig and not empty_S;
grant_S_L <= grant_S_L_sig and not empty_L;
grant_L_N <= grant_L_N_sig and not empty_N;
grant_L_E <= grant_L_E_sig and not empty_E;
grant_L_W <= grant_L_W_sig and not empty_W;
grant_L_S <= grant_L_S_sig and not empty_S;
grant_L_L <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
valid_N <= grant_N;
valid_E <= grant_E;
valid_W <= grant_W;
valid_S <= grant_S;
valid_L <= grant_L;
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/LBDR_packet_drop_with_checkers_with_FI/Cx_Reconf_pseudo_checkers.vhd
|
3
|
7380
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
end if;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Processor_NI/mem_ctrl.vhd
|
13
|
6562
|
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/immortal_slack_monitor_instrument.vhd
|
3
|
6301
|
--Copyright (C) 2017 Konstantin Shibin
------------------------------------------------------------
-- File name: immortal_slack_monitor_instrument.vhd
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
entity immortal_slack_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end immortal_slack_monitor_instrument;
architecture rtl of immortal_slack_monitor_instrument is
component SReg is
Generic ( Size : positive := 32);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
signal update_strobe : std_logic;
signal shiftreg_update : std_logic_vector (31 downto 0);
signal threshold_H : std_logic_vector (4 downto 0);
signal threshold_L : std_logic_vector (4 downto 0);
signal monitor_controls : std_logic_vector (2 downto 0);
signal threshold_compare_dir : std_logic;
signal f_output_enable : std_logic;
signal threshold_H_active : std_logic;
signal threshold_L_active : std_logic;
signal threshold_H_GT : std_logic;
signal threshold_H_LE : std_logic;
signal threshold_L_GT : std_logic;
signal threshold_L_LE : std_logic;
signal data_sync, data_sync_first : std_logic_vector (31 downto 0);
signal xored_edges : std_logic_vector (30 downto 0);
signal edge_loc_binary : std_logic_vector (4 downto 0);
signal UE_prev : std_logic;
function one_hot_to_binary (onehot : std_logic_vector; size : natural) return std_logic_vector is
variable binary_vector : std_logic_vector (size-1 downto 0);
begin
binary_vector := (others => '0');
for i in onehot'range loop
if onehot(i) = '1' then
binary_vector := std_logic_vector(to_unsigned(i, size));
end if ;
end loop;
return binary_vector;
end function;
begin
-- Shift register for capturing data from monitor and updating control and compare threshold
shiftreg : SReg
Generic map ( Size => 32)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => SO,
SEL => SEL,
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => data_sync,
DO => shiftreg_update);
-- shiftreg_update description:
-- [4:0] threshold H
-- [9:5] threshold L
-- [10] threshold comparison direction: 0: slack >= threshold; 1: slack < threshold
-- [11] F flag output enabled
-- [12] threshold value update enable
-- [30:28] control signals
-- [31] control signals update enable
synchronizer_data : process(TCK,RST)
begin
if RST = '1' then
data_sync_first <= (others => '0');
data_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
data_sync_first <= data;
data_sync <= data_sync_first;
end if ;
end process ; -- synchronizer
update_strobes: process(TCK)
begin
if TCK'event and TCK = '0' then
UE_prev <= UE;
update_strobe <= not UE_prev and UE and SEL;
end if;
end process;
threshold_controls_set: process(TCK, RST)
begin
if RST = '1' then
threshold_H <= (others => '0');
threshold_L <= (others => '0');
threshold_compare_dir <= '0';
f_output_enable <= '0';
monitor_controls <= (others => '0');
elsif TCK'event and TCK = '0' then
if update_strobe = '1' then
if shiftreg_update(12) = '1' then -- update thresholds only when bit 12 allows it
threshold_H <= shiftreg_update(4 downto 0);
threshold_L <= shiftreg_update(9 downto 5);
threshold_compare_dir <= shiftreg_update(10);
f_output_enable <= shiftreg_update(11);
end if;
if shiftreg_update(31) = '1' then -- update controls only when bit 31 allows it
monitor_controls <= shiftreg_update(30 downto 28);
end if;
end if;
end if;
end process;
control <= monitor_controls;
xor_edge_detector: for i in 0 to 30 generate
xored_edges(i) <= data_sync(i) xnor data_sync(i+1);
end generate;
edge_loc_binary <= one_hot_to_binary(xored_edges, edge_loc_binary'length);
threshold_H_GT <= '1' when (to_integer(unsigned(threshold_H)) > to_integer(unsigned(edge_loc_binary))) else '0';
threshold_H_LE <= '1' when (to_integer(unsigned(threshold_H)) <= to_integer(unsigned(edge_loc_binary))) else '0';
threshold_L_GT <= '1' when (to_integer(unsigned(threshold_L)) > to_integer(unsigned(edge_loc_binary))) else '0';
threshold_L_LE <= '1' when (to_integer(unsigned(threshold_L)) <= to_integer(unsigned(edge_loc_binary))) else '0';
threshold_H_active <= (threshold_H_GT and threshold_compare_dir) or (threshold_H_LE and not threshold_compare_dir);
threshold_L_active <= (threshold_L_GT and threshold_compare_dir) or (threshold_L_LE and not threshold_compare_dir);
toF <= (threshold_H_active or threshold_L_active) and f_output_enable;
toC <= not (threshold_H_active and f_output_enable);
end;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/noekeon.vhd
|
1
|
7968
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(543 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(543 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
rc_in_s <= X"808080801b1b1b1b363636366c6c6c6cd8d8d8d8abababab4d4d4d4d9a9a9a9a2f2f2f2f5e5e5e5ebcbcbcbc63636363c6c6c6c697979797353535356a6a6a6ad4d4d4d4";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/alu.vhd
|
13
|
2633
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
do_add <= '1' when alu_function = ALU_ADD else '0';
sum <= bv_adder(a_in, b_in, do_add);
less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
else a_in(31);
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else
ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
a_in or b_in when alu_function=ALU_OR else
a_in and b_in when alu_function=ALU_AND else
a_in xor b_in when alu_function=ALU_XOR else
a_in nor b_in when alu_function=ALU_NOR else
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else (others => 'Z');
c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
(others => 'Z');
c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/reg_bank.vhd
|
6
|
17338
|
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "TRI_PORT_X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal tri_port_ram : ram_type := (others => ZERO);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "01110";--"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
-- Added by Behrad
--if interrupt_in = '1' then -- ??
-- intr_enable_reg <= '1';
--end if;
-- Added by Behrad
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) <= reg_dest_new;
end if;
end if;
end process;
end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type := (others => ZERO);
variable dual_port_ram2 : ram_type := (others => ZERO);
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
---- Option #3
---- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
---- distributed RAM for all Xilinx FPGAs
---- From library UNISIM; use UNISIM.vcomponents.all;
--xilinx_16x1d:
--if memory_type = "XILINX_16X" generate
-- signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
-- signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
-- signal weA, weB : std_logic;
-- signal no_connect : std_logic_vector(127 downto 0);
--begin
-- weA <= write_enable and not addr_write(4); --lower 16 registers
-- weB <= write_enable and addr_write(4); --upper 16 registers
-- reg_loop: for i in 0 to 31 generate
-- begin
-- --Read port 1 lower 16 registers
-- reg_bit1a : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weA, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPO => data_out1A(i), -- Port B 1-bit data output
-- SPO => no_connect(i) -- Port A 1-bit data output
-- );
-- --Read port 1 upper 16 registers
-- reg_bit1b : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weB, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPO => data_out1B(i), -- Port B 1-bit data output
-- SPO => no_connect(32+i) -- Port A 1-bit data output
-- );
-- --Read port 2 lower 16 registers
-- reg_bit2a : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weA, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPO => data_out2A(i), -- Port B 1-bit data output
-- SPO => no_connect(64+i) -- Port A 1-bit data output
-- );
-- --Read port 2 upper 16 registers
-- reg_bit2b : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weB, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPO => data_out2B(i), -- Port B 1-bit data output
-- SPO => no_connect(96+i) -- Port A 1-bit data output
-- );
-- end generate; --reg_loop
-- data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
-- data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
--end generate; --xilinx_16x1d
---- Option #4
---- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port
---- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5
---- From library UNISIM; use UNISIM.vcomponents.all;
--xilinx_32x1d:
--if memory_type = "XILINX_32X" generate
-- signal no_connect : std_logic_vector(63 downto 0);
--begin
-- reg_loop: for i in 0 to 31 generate
-- begin
-- --Read port 1
-- reg_bit1 : RAM32X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => write_enable, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- A4 => addr_write(4), -- Port A address[4] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPRA4 => addr_read1(4), -- Port B address[4] input bit
-- DPO => data_out1(i), -- Port B 1-bit data output
-- SPO => no_connect(i) -- Port A 1-bit data output
-- );
-- --Read port 2
-- reg_bit2 : RAM32X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => write_enable, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- A4 => addr_write(4), -- Port A address[4] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPRA4 => addr_read2(4), -- Port B address[4] input bit
-- DPO => data_out2(i), -- Port B 1-bit data output
-- SPO => no_connect(32+i) -- Port A 1-bit data output
-- );
-- end generate; --reg_loop
--end generate; --xilinx_32x1d
---- Option #5
---- Altera LPM_RAM_DP
--altera_mem:
--if memory_type = "ALTERA_LPM" generate
-- signal clk_delayed : std_logic;
-- signal addr_reg : std_logic_vector(4 downto 0);
-- signal data_reg : std_logic_vector(31 downto 0);
-- signal q1 : std_logic_vector(31 downto 0);
-- signal q2 : std_logic_vector(31 downto 0);
--begin
-- -- Altera dual port RAMs must have the addresses registered (sampled
-- -- at the rising edge). This is very unfortunate.
-- -- Therefore, the dual port RAM read clock must delayed so that
-- -- the read address signal can be sent from the mem_ctrl block.
-- -- This solution also delays the how fast the registers are read so the
-- -- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
-- clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
-- dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)
-- begin
-- if rising_edge(clk) and write_enable = '1' then
-- addr_reg <= addr_write;
-- data_reg <= reg_dest_new;
-- end if;
-- end process; --dpram_bypass
-- -- Bypass dpram if reading what was just written (Altera limitation)
-- data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
-- data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
-- lpm_ram_dp_component1 : lpm_ram_dp
-- generic map (
-- LPM_WIDTH => 32,
-- LPM_WIDTHAD => 5,
-- --LPM_NUMWORDS => 0,
-- LPM_INDATA => "REGISTERED",
-- LPM_OUTDATA => "UNREGISTERED",
-- LPM_RDADDRESS_CONTROL => "REGISTERED",
-- LPM_WRADDRESS_CONTROL => "REGISTERED",
-- LPM_FILE => "UNUSED",
-- LPM_TYPE => "LPM_RAM_DP",
-- USE_EAB => "ON",
-- INTENDED_DEVICE_FAMILY => "UNUSED",
-- RDEN_USED => "FALSE",
-- LPM_HINT => "UNUSED")
-- port map (
-- RDCLOCK => clk_delayed,
-- RDCLKEN => '1',
-- RDADDRESS => addr_read1,
-- RDEN => '1',
-- DATA => reg_dest_new,
-- WRADDRESS => addr_write,
-- WREN => write_enable,
-- WRCLOCK => clk,
-- WRCLKEN => '1',
-- Q => q1);
-- lpm_ram_dp_component2 : lpm_ram_dp
-- generic map (
-- LPM_WIDTH => 32,
-- LPM_WIDTHAD => 5,
-- --LPM_NUMWORDS => 0,
-- LPM_INDATA => "REGISTERED",
-- LPM_OUTDATA => "UNREGISTERED",
-- LPM_RDADDRESS_CONTROL => "REGISTERED",
-- LPM_WRADDRESS_CONTROL => "REGISTERED",
-- LPM_FILE => "UNUSED",
-- LPM_TYPE => "LPM_RAM_DP",
-- USE_EAB => "ON",
-- INTENDED_DEVICE_FAMILY => "UNUSED",
-- RDEN_USED => "FALSE",
-- LPM_HINT => "UNUSED")
-- port map (
-- RDCLOCK => clk_delayed,
-- RDCLKEN => '1',
-- RDADDRESS => addr_read2,
-- RDEN => '1',
-- DATA => reg_dest_new,
-- WRADDRESS => addr_write,
-- WREN => write_enable,
-- WRCLOCK => clk,
-- WRCLKEN => '1',
-- Q => q2);
--end generate; --altera_mem
end; --architecture ram_block
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/allocator_with_checkers_with_FI.vhd
|
3
|
95634
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E,
N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W,
N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S,
N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L,
N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N,
N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E,
E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W,
E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S,
E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L,
E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N,
E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E,
W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W,
W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S,
W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L,
W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N,
W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E,
S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W,
S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S,
S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L,
S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N,
S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E,
L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W,
L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S,
L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L,
L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N,
L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S,
L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic
);
end allocator;
architecture behavior of allocator is
-- Allocator logic checker outputs and allocator credit counter logic checker outputs go directly to the output interface of Allocator
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 9 bits
-- What about Arbiter_in and Arbiter_out ?!
signal FI_add_sta: std_logic_vector (8 downto 0); -- 7 bits for fault injection location address (ceil of log2(80) = 7)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (79 downto 0); -- 80 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(79 downto 0); -- 80 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
-- For making the chain of faulty data from L, N, E, W and S Arbiter_in and then to L, N, E, W and S Arbiter_out and then to the output of Allocator
signal fault_DO_serial_L_Arbiter_in_N_Arbiter_in, fault_DO_serial_N_Arbiter_in_E_Arbiter_in, fault_DO_serial_E_Arbiter_in_W_Arbiter_in: std_logic;
signal fault_DO_serial_W_Arbiter_in_S_Arbiter_in, fault_DO_serial_S_Arbiter_in_L_Arbiter_out, fault_DO_serial_L_Arbiter_out_N_Arbiter_out: std_logic;
signal fault_DO_serial_N_Arbiter_out_E_Arbiter_out, fault_DO_serial_E_Arbiter_out_W_Arbiter_out, fault_DO_serial_W_Arbiter_out_S_Arbiter_out: std_logic;
signal fault_DO_serial_S_Arbiter_out_Allocator_logic: std_logic;
----------------------------------------
----------------------------------------
-- So the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
-- These signals belong to Allocator
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
-- These signals are introduced when connecting output-related signals to the allocator checkers
signal valid_N_sig, valid_E_sig, valid_W_sig, valid_S_sig, valid_L_sig : std_logic;
signal grant_N_N_signal, grant_N_E_signal, grant_N_W_signal, grant_N_S_signal, grant_N_L_signal: std_logic;
signal grant_E_N_signal, grant_E_E_signal, grant_E_W_signal, grant_E_S_signal, grant_E_L_signal: std_logic;
signal grant_W_N_signal, grant_W_E_signal, grant_W_W_signal, grant_W_S_signal, grant_W_L_signal: std_logic;
signal grant_S_N_signal, grant_S_E_signal, grant_S_W_signal, grant_S_S_signal, grant_S_L_signal: std_logic;
signal grant_L_N_signal, grant_L_E_signal, grant_L_W_signal, grant_L_S_signal, grant_L_L_signal: std_logic;
-- Signal(s) used for creating the chain of injected fault locations
-- Total: ?? bits ??!!
-- Allocator internal-related signals
signal credit_counter_N_in_faulty, credit_counter_N_out_faulty: std_logic_vector(1 downto 0);
signal credit_counter_E_in_faulty, credit_counter_E_out_faulty: std_logic_vector(1 downto 0);
signal credit_counter_W_in_faulty, credit_counter_W_out_faulty: std_logic_vector(1 downto 0);
signal credit_counter_S_in_faulty, credit_counter_S_out_faulty: std_logic_vector(1 downto 0);
signal credit_counter_L_in_faulty, credit_counter_L_out_faulty: std_logic_vector(1 downto 0);
signal grant_N_faulty, grant_E_faulty, grant_W_faulty, grant_S_faulty, grant_L_faulty: std_logic;
signal grant_N_N_sig_faulty, grant_N_E_sig_faulty, grant_N_W_sig_faulty, grant_N_S_sig_faulty, grant_N_L_sig_faulty: std_logic;
signal grant_E_N_sig_faulty, grant_E_E_sig_faulty, grant_E_W_sig_faulty, grant_E_S_sig_faulty, grant_E_L_sig_faulty: std_logic;
signal grant_W_N_sig_faulty, grant_W_E_sig_faulty, grant_W_W_sig_faulty, grant_W_S_sig_faulty, grant_W_L_sig_faulty: std_logic;
signal grant_S_N_sig_faulty, grant_S_E_sig_faulty, grant_S_W_sig_faulty, grant_S_S_sig_faulty, grant_S_L_sig_faulty: std_logic;
signal grant_L_N_sig_faulty, grant_L_E_sig_faulty, grant_L_W_sig_faulty, grant_L_S_sig_faulty, grant_L_L_sig_faulty: std_logic;
-- Allocator output-related signals
signal valid_N_sig_faulty, valid_E_sig_faulty, valid_W_sig_faulty, valid_S_sig_faulty, valid_L_sig_faulty : std_logic;
signal grant_N_N_signal_faulty, grant_N_E_signal_faulty, grant_N_W_signal_faulty, grant_N_S_signal_faulty, grant_N_L_signal_faulty: std_logic;
signal grant_E_N_signal_faulty, grant_E_E_signal_faulty, grant_E_W_signal_faulty, grant_E_S_signal_faulty, grant_E_L_signal_faulty: std_logic;
signal grant_W_N_signal_faulty, grant_W_E_signal_faulty, grant_W_W_signal_faulty, grant_W_S_signal_faulty, grant_W_L_signal_faulty: std_logic;
signal grant_S_N_signal_faulty, grant_S_E_signal_faulty, grant_S_W_signal_faulty, grant_S_S_signal_faulty, grant_S_L_signal_faulty: std_logic;
signal grant_L_N_signal_faulty, grant_L_E_signal_faulty, grant_L_W_signal_faulty, grant_L_S_signal_faulty, grant_L_L_signal_faulty: std_logic;
begin
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 80 bits
-- for valid and grant output signals, not sure whether to include them or the signals with _sig and _signal suffix in their name ??!!
non_faulty_signals <= credit_counter_N_in & credit_counter_N_out & credit_counter_E_in & credit_counter_E_out &
credit_counter_W_in & credit_counter_W_out & credit_counter_S_in & credit_counter_S_out &
credit_counter_L_in & credit_counter_L_out & grant_N & grant_E & grant_W & grant_S &
grant_L & grant_N_N_sig & grant_N_E_sig & grant_N_W_sig & grant_N_S_sig & grant_N_L_sig &
grant_E_N_sig & grant_E_E_sig & grant_E_W_sig & grant_E_S_sig & grant_E_L_sig &
grant_W_N_sig & grant_W_E_sig & grant_W_W_sig & grant_W_S_sig & grant_W_L_sig &
grant_S_N_sig & grant_S_E_sig & grant_S_W_sig & grant_S_S_sig & grant_S_L_sig &
grant_L_N_sig & grant_L_E_sig & grant_L_W_sig & grant_L_S_sig & grant_L_L_sig &
valid_N_sig & valid_E_sig & valid_W_sig & valid_S_sig & valid_L_sig &
grant_N_N_signal & grant_N_E_signal & grant_N_W_signal & grant_N_S_signal & grant_N_L_signal &
grant_E_N_signal & grant_E_E_signal & grant_E_W_signal & grant_E_S_signal & grant_E_L_signal &
grant_W_N_signal & grant_W_E_signal & grant_W_W_signal & grant_W_S_signal & grant_W_L_signal &
grant_S_N_signal & grant_S_E_signal & grant_S_W_signal & grant_S_S_signal & grant_S_L_signal &
grant_L_N_signal & grant_L_E_signal & grant_L_W_signal & grant_L_S_signal & grant_L_L_signal;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 80, ADDRESS_WIDTH => 7)
port map (data_in=> non_faulty_signals , address => FI_add_sta(8 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 17 bits
credit_counter_N_in_faulty <= faulty_signals (79 downto 78);
credit_counter_N_out_faulty <= faulty_signals (77 downto 76);
credit_counter_E_in_faulty <= faulty_signals (75 downto 74);
credit_counter_E_out_faulty <= faulty_signals (73 downto 72);
credit_counter_W_in_faulty <= faulty_signals (71 downto 70);
credit_counter_W_out_faulty <= faulty_signals (69 downto 68);
credit_counter_S_in_faulty <= faulty_signals (67 downto 66);
credit_counter_S_out_faulty <= faulty_signals (65 downto 64);
credit_counter_L_in_faulty <= faulty_signals (63 downto 62);
credit_counter_L_out_faulty <= faulty_signals (61 downto 60);
grant_N_faulty <= faulty_signals (59);
grant_E_faulty <= faulty_signals (58);
grant_W_faulty <= faulty_signals (57);
grant_S_faulty <= faulty_signals (56);
grant_L_faulty <= faulty_signals (55);
grant_N_N_sig_faulty <= faulty_signals (54);
grant_N_E_sig_faulty <= faulty_signals (53);
grant_N_W_sig_faulty <= faulty_signals (52);
grant_N_S_sig_faulty <= faulty_signals (51);
grant_N_L_sig_faulty <= faulty_signals (50);
grant_E_N_sig_faulty <= faulty_signals (49);
grant_E_E_sig_faulty <= faulty_signals (48);
grant_E_W_sig_faulty <= faulty_signals (47);
grant_E_S_sig_faulty <= faulty_signals (46);
grant_E_L_sig_faulty <= faulty_signals (45);
grant_W_N_sig_faulty <= faulty_signals (44);
grant_W_E_sig_faulty <= faulty_signals (43);
grant_W_W_sig_faulty <= faulty_signals (42);
grant_W_S_sig_faulty <= faulty_signals (41);
grant_W_L_sig_faulty <= faulty_signals (40);
grant_S_N_sig_faulty <= faulty_signals (39);
grant_S_E_sig_faulty <= faulty_signals (38);
grant_S_W_sig_faulty <= faulty_signals (37);
grant_S_S_sig_faulty <= faulty_signals (36);
grant_S_L_sig_faulty <= faulty_signals (35);
grant_L_N_sig_faulty <= faulty_signals (34);
grant_L_E_sig_faulty <= faulty_signals (33);
grant_L_W_sig_faulty <= faulty_signals (32);
grant_L_S_sig_faulty <= faulty_signals (31);
grant_L_L_sig_faulty <= faulty_signals (30);
valid_N_sig_faulty <= faulty_signals (29);
valid_E_sig_faulty <= faulty_signals (28);
valid_W_sig_faulty <= faulty_signals (27);
valid_S_sig_faulty <= faulty_signals (26);
valid_L_sig_faulty <= faulty_signals (25);
grant_N_N_signal_faulty <= faulty_signals (24);
grant_N_E_signal_faulty <= faulty_signals (23);
grant_N_W_signal_faulty <= faulty_signals (22);
grant_N_S_signal_faulty <= faulty_signals (21);
grant_N_L_signal_faulty <= faulty_signals (20);
grant_E_N_signal_faulty <= faulty_signals (19);
grant_E_E_signal_faulty <= faulty_signals (18);
grant_E_W_signal_faulty <= faulty_signals (17);
grant_E_S_signal_faulty <= faulty_signals (16);
grant_E_L_signal_faulty <= faulty_signals (15);
grant_W_N_signal_faulty <= faulty_signals (14);
grant_W_E_signal_faulty <= faulty_signals (13);
grant_W_W_signal_faulty <= faulty_signals (12);
grant_W_S_signal_faulty <= faulty_signals (11);
grant_W_L_signal_faulty <= faulty_signals (10);
grant_S_N_signal_faulty <= faulty_signals (9);
grant_S_E_signal_faulty <= faulty_signals (8);
grant_S_W_signal_faulty <= faulty_signals (7);
grant_S_S_signal_faulty <= faulty_signals (6);
grant_S_L_signal_faulty <= faulty_signals (5);
grant_L_N_signal_faulty <= faulty_signals (4);
grant_L_E_signal_faulty <= faulty_signals (3);
grant_L_W_signal_faulty <= faulty_signals (2);
grant_L_S_signal_faulty <= faulty_signals (1);
grant_L_L_signal_faulty <= faulty_signals (0);
-- Total: 9 bits
SR: shift_register_serial_in generic map(REG_WIDTH => 9) -- What about Arbiter_in and Arbiter_out ?!
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE => UE, SI=> fault_DO_serial_S_Arbiter_out_Allocator_logic,
data_out_parallel=> FI_add_sta, SO=> SO
);
-------------------------------------
-------------------------------------
-- We did this because of the checkers
valid_N <= valid_N_sig; valid_E <= valid_E_sig; valid_W <= valid_W_sig; valid_S <= valid_S_sig; valid_L <= valid_L_sig;
grant_N_N <= grant_N_N_signal; grant_E_N <= grant_E_N_signal; grant_W_N <= grant_W_N_signal; grant_S_N <= grant_S_N_signal; grant_L_N <= grant_L_N_signal;
grant_N_E <= grant_N_E_signal; grant_E_E <= grant_E_E_signal; grant_W_E <= grant_W_E_signal; grant_S_E <= grant_S_E_signal; grant_L_E <= grant_L_E_signal;
grant_N_W <= grant_N_W_signal; grant_E_W <= grant_E_W_signal; grant_W_W <= grant_W_W_signal; grant_S_W <= grant_S_W_signal; grant_L_W <= grant_L_W_signal;
grant_N_S <= grant_N_S_signal; grant_E_S <= grant_E_S_signal; grant_W_S <= grant_W_S_signal; grant_S_S <= grant_S_S_signal; grant_L_S <= grant_L_S_signal;
grant_N_L <= grant_N_L_signal; grant_E_L <= grant_E_L_signal; grant_W_L <= grant_W_L_signal; grant_S_L <= grant_S_L_signal; grant_L_L <= grant_L_L_signal;
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
-- Taking Arbiter_in checker outputs to outputs of Allocator ??!! (Behrad has written this :( )
grant_N_N_signal <= grant_N_N_sig and not empty_N;
grant_N_E_signal <= grant_N_E_sig and not empty_E;
grant_N_W_signal <= grant_N_W_sig and not empty_W;
grant_N_S_signal <= grant_N_S_sig and not empty_S;
grant_N_L_signal <= grant_N_L_sig and not empty_L;
grant_E_N_signal <= grant_E_N_sig and not empty_N;
grant_E_E_signal <= grant_E_E_sig and not empty_E;
grant_E_W_signal <= grant_E_W_sig and not empty_W;
grant_E_S_signal <= grant_E_S_sig and not empty_S;
grant_E_L_signal <= grant_E_L_sig and not empty_L;
grant_W_N_signal <= grant_W_N_sig and not empty_N;
grant_W_E_signal <= grant_W_E_sig and not empty_E;
grant_W_W_signal <= grant_W_W_sig and not empty_W;
grant_W_S_signal <= grant_W_S_sig and not empty_S;
grant_W_L_signal <= grant_W_L_sig and not empty_L;
grant_S_N_signal <= grant_S_N_sig and not empty_N;
grant_S_E_signal <= grant_S_E_sig and not empty_E;
grant_S_W_signal <= grant_S_W_sig and not empty_W;
grant_S_S_signal <= grant_S_S_sig and not empty_S;
grant_S_L_signal <= grant_S_L_sig and not empty_L;
grant_L_N_signal <= grant_L_N_sig and not empty_N;
grant_L_E_signal <= grant_L_E_sig and not empty_E;
grant_L_W_signal <= grant_L_W_sig and not empty_W;
grant_L_S_signal <= grant_L_S_sig and not empty_S;
grant_L_L_signal <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handles the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Allocator logic checkers module instantiation
ALLOCATOR_LOGIC_CHECKERS:
allocator_logic_pseudo_checkers
PORT MAP (
empty_N => empty_N, empty_E => empty_E, empty_W => empty_W, empty_S => empty_S, empty_L => empty_L,
grant_N_N_sig => grant_N_N_sig_faulty, grant_N_E_sig => grant_N_E_sig_faulty, grant_N_W_sig => grant_N_W_sig_faulty, grant_N_S_sig => grant_N_S_sig_faulty, grant_N_L_sig => grant_N_L_sig_faulty,
grant_E_N_sig => grant_E_N_sig_faulty, grant_E_E_sig => grant_E_E_sig_faulty, grant_E_W_sig => grant_E_W_sig_faulty, grant_E_S_sig => grant_E_S_sig_faulty, grant_E_L_sig => grant_E_L_sig_faulty,
grant_W_N_sig => grant_W_N_sig_faulty, grant_W_E_sig => grant_W_E_sig_faulty, grant_W_W_sig => grant_W_W_sig_faulty, grant_W_S_sig => grant_W_S_sig_faulty, grant_W_L_sig => grant_W_L_sig_faulty,
grant_S_N_sig => grant_S_N_sig_faulty, grant_S_E_sig => grant_S_E_sig_faulty, grant_S_W_sig => grant_S_W_sig_faulty, grant_S_S_sig => grant_S_S_sig_faulty, grant_S_L_sig => grant_S_L_sig_faulty,
grant_L_N_sig => grant_L_N_sig_faulty, grant_L_E_sig => grant_L_E_sig_faulty, grant_L_W_sig => grant_L_W_sig_faulty, grant_L_S_sig => grant_L_S_sig_faulty, grant_L_L_sig => grant_L_L_sig_faulty,
valid_N => valid_N_sig_faulty, valid_E => valid_E_sig_faulty, valid_W => valid_W_sig_faulty, valid_S => valid_S_sig_faulty, valid_L => valid_L_sig_faulty,
grant_N_N => grant_N_N_signal_faulty, grant_N_E => grant_N_E_signal_faulty, grant_N_W => grant_N_W_signal_faulty,
grant_N_S => grant_N_S_signal_faulty, grant_N_L => grant_N_L_signal_faulty, grant_E_N => grant_E_N_signal_faulty,
grant_E_E => grant_E_E_signal_faulty, grant_E_W => grant_E_W_signal_faulty, grant_E_S => grant_E_S_signal_faulty,
grant_E_L => grant_E_L_signal_faulty, grant_W_N => grant_W_N_signal_faulty, grant_W_E => grant_W_E_signal_faulty,
grant_W_W => grant_W_W_signal_faulty, grant_W_S => grant_W_S_signal_faulty, grant_W_L => grant_W_L_signal_faulty,
grant_S_N => grant_S_N_signal_faulty, grant_S_E => grant_S_E_signal_faulty, grant_S_W => grant_S_W_signal_faulty,
grant_S_S => grant_S_S_signal_faulty, grant_S_L => grant_S_L_signal_faulty, grant_L_N => grant_L_N_signal_faulty,
grant_L_E => grant_L_E_signal_faulty, grant_L_W => grant_L_W_signal_faulty, grant_L_S => grant_L_S_signal_faulty,
grant_L_L => grant_L_L_signal_faulty,
grant_N => grant_N_faulty, grant_E => grant_E_faulty, grant_W => grant_W_faulty, grant_S => grant_S_faulty, grant_L => grant_L_faulty,
-- Checker Outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match
);
-- Allocator credit counter logic checkers module instantiation
ALLOCATOR_CREDIT_COUNTER_LOGIC_CHECKERS:
allocator_credit_counter_logic_pseudo_checkers
PORT MAP (
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
credit_counter_N_out => credit_counter_N_out_faulty, credit_counter_E_out => credit_counter_E_out_faulty,
credit_counter_W_out => credit_counter_W_out_faulty, credit_counter_S_out => credit_counter_S_out_faulty,
credit_counter_L_out => credit_counter_L_out_faulty,
valid_N => grant_N_faulty, -- Must be connected to grant signals!
valid_E => grant_E_faulty, -- Must be connected to grant signals!
valid_W => grant_W_faulty, -- Must be connected to grant signals!
valid_S => grant_S_faulty, -- Must be connected to grant signals!
valid_L => grant_L_faulty, -- Must be connected to grant signals!
credit_counter_N_in => credit_counter_N_in_faulty, credit_counter_E_in => credit_counter_E_in_faulty,
credit_counter_W_in => credit_counter_W_in_faulty, credit_counter_S_in => credit_counter_S_in_faulty,
credit_counter_L_in => credit_counter_L_in_faulty,
-- Checker Outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter In
-- North Arbiter_in with checkers integrated (module instantiation)
arb_N_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_Arbiter_in_N_Arbiter_in, SO=> fault_DO_serial_N_Arbiter_in_E_Arbiter_in,
-- North Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => N_err_IDLE_Req_N, err_IDLE_grant_N => N_err_IDLE_grant_N, err_North_Req_N => N_err_North_Req_N,
err_North_grant_N => N_err_North_grant_N, err_East_Req_E => N_err_East_Req_E, err_East_grant_E => N_err_East_grant_E,
err_West_Req_W => N_err_West_Req_W, err_West_grant_W => N_err_West_grant_W, err_South_Req_S => N_err_South_Req_S,
err_South_grant_S => N_err_South_grant_S, err_Local_Req_L => N_err_Local_Req_L, err_Local_grant_L => N_err_Local_grant_L,
err_IDLE_Req_E => N_err_IDLE_Req_E, err_IDLE_grant_E => N_err_IDLE_grant_E, err_North_Req_E => N_err_North_Req_E,
err_North_grant_E => N_err_North_grant_E, err_East_Req_W => N_err_East_Req_W, err_East_grant_W => N_err_East_grant_W,
err_West_Req_S => N_err_West_Req_S, err_West_grant_S => N_err_West_grant_S, err_South_Req_L => N_err_South_Req_L,
err_South_grant_L => N_err_South_grant_L, err_Local_Req_N => N_err_Local_Req_N, err_Local_grant_N => N_err_Local_grant_N,
err_IDLE_Req_W => N_err_IDLE_Req_W, err_IDLE_grant_W => N_err_IDLE_grant_W, err_North_Req_W => N_err_North_Req_W,
err_North_grant_W => N_err_North_grant_W, err_East_Req_S => N_err_East_Req_S, err_East_grant_S => N_err_East_grant_S,
err_West_Req_L => N_err_West_Req_L, err_West_grant_L => N_err_West_grant_L, err_South_Req_N => N_err_South_Req_N,
err_South_grant_N => N_err_South_grant_N, err_Local_Req_E => N_err_Local_Req_E, err_Local_grant_E => N_err_Local_grant_E,
err_IDLE_Req_S => N_err_IDLE_Req_S, err_IDLE_grant_S => N_err_IDLE_grant_S, err_North_Req_S => N_err_North_Req_S,
err_North_grant_S => N_err_North_grant_S, err_East_Req_L => N_err_East_Req_L, err_East_grant_L => N_err_East_grant_L,
err_West_Req_N => N_err_West_Req_N, err_West_grant_N => N_err_West_grant_N, err_South_Req_E => N_err_South_Req_E,
err_South_grant_E => N_err_South_grant_E, err_Local_Req_W => N_err_Local_Req_W, err_Local_grant_W => N_err_Local_grant_W,
err_IDLE_Req_L => N_err_IDLE_Req_L, err_IDLE_grant_L => N_err_IDLE_grant_L, err_North_Req_L => N_err_North_Req_L,
err_North_grant_L => N_err_North_grant_L, err_East_Req_N => N_err_East_Req_N, err_East_grant_N => N_err_East_grant_N,
err_West_Req_E => N_err_West_Req_E, err_West_grant_E => N_err_West_grant_E, err_South_Req_W => N_err_South_Req_W,
err_South_grant_W => N_err_South_grant_W, err_Local_Req_S => N_err_Local_Req_S, err_Local_grant_S => N_err_Local_grant_S,
err_state_in_onehot => N_err_state_in_onehot,
err_no_request_grants => N_err_no_request_grants,
err_request_no_grants => N_err_request_no_grants,
err_no_Req_N_grant_N => N_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => N_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => N_err_no_Req_L_grant_L
);
arb_E_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_Arbiter_in_E_Arbiter_in, SO=> fault_DO_serial_E_Arbiter_in_W_Arbiter_in,
-- East Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => E_err_IDLE_Req_N, err_IDLE_grant_N => E_err_IDLE_grant_N, err_North_Req_N => E_err_North_Req_N,
err_North_grant_N => E_err_North_grant_N, err_East_Req_E => E_err_East_Req_E, err_East_grant_E => E_err_East_grant_E,
err_West_Req_W => E_err_West_Req_W, err_West_grant_W => E_err_West_grant_W, err_South_Req_S => E_err_South_Req_S,
err_South_grant_S => E_err_South_grant_S, err_Local_Req_L => E_err_Local_Req_L, err_Local_grant_L => E_err_Local_grant_L,
err_IDLE_Req_E => E_err_IDLE_Req_E, err_IDLE_grant_E => E_err_IDLE_grant_E, err_North_Req_E => E_err_North_Req_E,
err_North_grant_E => E_err_North_grant_E, err_East_Req_W => E_err_East_Req_W, err_East_grant_W => E_err_East_grant_W,
err_West_Req_S => E_err_West_Req_S, err_West_grant_S => E_err_West_grant_S, err_South_Req_L => E_err_South_Req_L,
err_South_grant_L => E_err_South_grant_L, err_Local_Req_N => E_err_Local_Req_N, err_Local_grant_N => E_err_Local_grant_N,
err_IDLE_Req_W => E_err_IDLE_Req_W, err_IDLE_grant_W => E_err_IDLE_grant_W, err_North_Req_W => E_err_North_Req_W,
err_North_grant_W => E_err_North_grant_W, err_East_Req_S => E_err_East_Req_S, err_East_grant_S => E_err_East_grant_S,
err_West_Req_L => E_err_West_Req_L, err_West_grant_L => E_err_West_grant_L, err_South_Req_N => E_err_South_Req_N,
err_South_grant_N => E_err_South_grant_N, err_Local_Req_E => E_err_Local_Req_E, err_Local_grant_E => E_err_Local_grant_E,
err_IDLE_Req_S => E_err_IDLE_Req_S, err_IDLE_grant_S => E_err_IDLE_grant_S, err_North_Req_S => E_err_North_Req_S,
err_North_grant_S => E_err_North_grant_S, err_East_Req_L => E_err_East_Req_L, err_East_grant_L => E_err_East_grant_L,
err_West_Req_N => E_err_West_Req_N, err_West_grant_N => E_err_West_grant_N, err_South_Req_E => E_err_South_Req_E,
err_South_grant_E => E_err_South_grant_E, err_Local_Req_W => E_err_Local_Req_W, err_Local_grant_W => E_err_Local_grant_W,
err_IDLE_Req_L => E_err_IDLE_Req_L, err_IDLE_grant_L => E_err_IDLE_grant_L, err_North_Req_L => E_err_North_Req_L,
err_North_grant_L => E_err_North_grant_L, err_East_Req_N => E_err_East_Req_N, err_East_grant_N => E_err_East_grant_N,
err_West_Req_E => E_err_West_Req_E, err_West_grant_E => E_err_West_grant_E, err_South_Req_W => E_err_South_Req_W,
err_South_grant_W => E_err_South_grant_W, err_Local_Req_S => E_err_Local_Req_S, err_Local_grant_S => E_err_Local_grant_S,
err_state_in_onehot => E_err_state_in_onehot,
err_no_request_grants => E_err_no_request_grants,
err_request_no_grants => E_err_request_no_grants,
err_no_Req_N_grant_N => E_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => E_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => E_err_no_Req_L_grant_L
);
arb_W_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_Arbiter_in_W_Arbiter_in, SO=> fault_DO_serial_W_Arbiter_in_S_Arbiter_in,
-- West Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => W_err_IDLE_Req_N, err_IDLE_grant_N => W_err_IDLE_grant_N, err_North_Req_N => W_err_North_Req_N,
err_North_grant_N => W_err_North_grant_N, err_East_Req_E => W_err_East_Req_E, err_East_grant_E => W_err_East_grant_E,
err_West_Req_W => W_err_West_Req_W, err_West_grant_W => W_err_West_grant_W, err_South_Req_S => W_err_South_Req_S,
err_South_grant_S => W_err_South_grant_S, err_Local_Req_L => W_err_Local_Req_L, err_Local_grant_L => W_err_Local_grant_L,
err_IDLE_Req_E => W_err_IDLE_Req_E, err_IDLE_grant_E => W_err_IDLE_grant_E, err_North_Req_E => W_err_North_Req_E,
err_North_grant_E => W_err_North_grant_E, err_East_Req_W => W_err_East_Req_W, err_East_grant_W => W_err_East_grant_W,
err_West_Req_S => W_err_West_Req_S, err_West_grant_S => W_err_West_grant_S, err_South_Req_L => W_err_South_Req_L,
err_South_grant_L => W_err_South_grant_L, err_Local_Req_N => W_err_Local_Req_N, err_Local_grant_N => W_err_Local_grant_N,
err_IDLE_Req_W => W_err_IDLE_Req_W, err_IDLE_grant_W => W_err_IDLE_grant_W, err_North_Req_W => W_err_North_Req_W,
err_North_grant_W => W_err_North_grant_W, err_East_Req_S => W_err_East_Req_S, err_East_grant_S => W_err_East_grant_S,
err_West_Req_L => W_err_West_Req_L, err_West_grant_L => W_err_West_grant_L, err_South_Req_N => W_err_South_Req_N,
err_South_grant_N => W_err_South_grant_N, err_Local_Req_E => W_err_Local_Req_E, err_Local_grant_E => W_err_Local_grant_E,
err_IDLE_Req_S => W_err_IDLE_Req_S, err_IDLE_grant_S => W_err_IDLE_grant_S, err_North_Req_S => W_err_North_Req_S,
err_North_grant_S => W_err_North_grant_S, err_East_Req_L => W_err_East_Req_L, err_East_grant_L => W_err_East_grant_L,
err_West_Req_N => W_err_West_Req_N, err_West_grant_N => W_err_West_grant_N, err_South_Req_E => W_err_South_Req_E,
err_South_grant_E => W_err_South_grant_E, err_Local_Req_W => W_err_Local_Req_W, err_Local_grant_W => W_err_Local_grant_W,
err_IDLE_Req_L => W_err_IDLE_Req_L, err_IDLE_grant_L => W_err_IDLE_grant_L, err_North_Req_L => W_err_North_Req_L,
err_North_grant_L => W_err_North_grant_L, err_East_Req_N => W_err_East_Req_N, err_East_grant_N => W_err_East_grant_N,
err_West_Req_E => W_err_West_Req_E, err_West_grant_E => W_err_West_grant_E, err_South_Req_W => W_err_South_Req_W,
err_South_grant_W => W_err_South_grant_W, err_Local_Req_S => W_err_Local_Req_S, err_Local_grant_S => W_err_Local_grant_S,
err_state_in_onehot => W_err_state_in_onehot, err_no_request_grants => W_err_no_request_grants, err_request_no_grants => W_err_request_no_grants,
err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => W_err_no_Req_L_grant_L
);
arb_S_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_Arbiter_in_S_Arbiter_in, SO=> fault_DO_serial_S_Arbiter_in_L_Arbiter_out,
-- South Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => S_err_IDLE_Req_N, err_IDLE_grant_N => S_err_IDLE_grant_N, err_North_Req_N => S_err_North_Req_N,
err_North_grant_N => S_err_North_grant_N, err_East_Req_E => S_err_East_Req_E, err_East_grant_E => S_err_East_grant_E,
err_West_Req_W => S_err_West_Req_W, err_West_grant_W => S_err_West_grant_W, err_South_Req_S => S_err_South_Req_S,
err_South_grant_S => S_err_South_grant_S, err_Local_Req_L => S_err_Local_Req_L, err_Local_grant_L => S_err_Local_grant_L,
err_IDLE_Req_E => S_err_IDLE_Req_E, err_IDLE_grant_E => S_err_IDLE_grant_E, err_North_Req_E => S_err_North_Req_E,
err_North_grant_E => S_err_North_grant_E, err_East_Req_W => S_err_East_Req_W, err_East_grant_W => S_err_East_grant_W,
err_West_Req_S => S_err_West_Req_S, err_West_grant_S => S_err_West_grant_S, err_South_Req_L => S_err_South_Req_L,
err_South_grant_L => S_err_South_grant_L, err_Local_Req_N => S_err_Local_Req_N, err_Local_grant_N => S_err_Local_grant_N,
err_IDLE_Req_W => S_err_IDLE_Req_W, err_IDLE_grant_W => S_err_IDLE_grant_W, err_North_Req_W => S_err_North_Req_W,
err_North_grant_W => S_err_North_grant_W, err_East_Req_S => S_err_East_Req_S, err_East_grant_S => S_err_East_grant_S,
err_West_Req_L => S_err_West_Req_L, err_West_grant_L => S_err_West_grant_L, err_South_Req_N => S_err_South_Req_N,
err_South_grant_N => S_err_South_grant_N, err_Local_Req_E => S_err_Local_Req_E, err_Local_grant_E => S_err_Local_grant_E,
err_IDLE_Req_S => S_err_IDLE_Req_S, err_IDLE_grant_S => S_err_IDLE_grant_S, err_North_Req_S => S_err_North_Req_S,
err_North_grant_S => S_err_North_grant_S, err_East_Req_L => S_err_East_Req_L, err_East_grant_L => S_err_East_grant_L,
err_West_Req_N => S_err_West_Req_N, err_West_grant_N => S_err_West_grant_N, err_South_Req_E => S_err_South_Req_E,
err_South_grant_E => S_err_South_grant_E, err_Local_Req_W => S_err_Local_Req_W, err_Local_grant_W => S_err_Local_grant_W,
err_IDLE_Req_L => S_err_IDLE_Req_L, err_IDLE_grant_L => S_err_IDLE_grant_L, err_North_Req_L => S_err_North_Req_L,
err_North_grant_L => S_err_North_grant_L, err_East_Req_N => S_err_East_Req_N, err_East_grant_N => S_err_East_grant_N,
err_West_Req_E => S_err_West_Req_E, err_West_grant_E => S_err_West_grant_E, err_South_Req_W => S_err_South_Req_W,
err_South_grant_W => S_err_South_grant_W, err_Local_Req_S => S_err_Local_Req_S, err_Local_grant_S => S_err_Local_grant_S,
err_state_in_onehot => S_err_state_in_onehot, err_no_request_grants => S_err_no_request_grants, err_request_no_grants => S_err_request_no_grants,
err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => S_err_no_Req_L_grant_L
);
arb_L_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_Arbiter_in_N_Arbiter_in,
-- Local Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => L_err_IDLE_Req_N, err_IDLE_grant_N => L_err_IDLE_grant_N, err_North_Req_N => L_err_North_Req_N,
err_North_grant_N => L_err_North_grant_N, err_East_Req_E => L_err_East_Req_E, err_East_grant_E => L_err_East_grant_E,
err_West_Req_W => L_err_West_Req_W, err_West_grant_W => L_err_West_grant_W, err_South_Req_S => L_err_South_Req_S,
err_South_grant_S => L_err_South_grant_S, err_Local_Req_L => L_err_Local_Req_L, err_Local_grant_L => L_err_Local_grant_L,
err_IDLE_Req_E => L_err_IDLE_Req_E, err_IDLE_grant_E => L_err_IDLE_grant_E, err_North_Req_E => L_err_North_Req_E,
err_North_grant_E => L_err_North_grant_E, err_East_Req_W => L_err_East_Req_W, err_East_grant_W => L_err_East_grant_W,
err_West_Req_S => L_err_West_Req_S, err_West_grant_S => L_err_West_grant_S, err_South_Req_L => L_err_South_Req_L,
err_South_grant_L => L_err_South_grant_L, err_Local_Req_N => L_err_Local_Req_N, err_Local_grant_N => L_err_Local_grant_N,
err_IDLE_Req_W => L_err_IDLE_Req_W, err_IDLE_grant_W => L_err_IDLE_grant_W, err_North_Req_W => L_err_North_Req_W,
err_North_grant_W => L_err_North_grant_W, err_East_Req_S => L_err_East_Req_S, err_East_grant_S => L_err_East_grant_S,
err_West_Req_L => L_err_West_Req_L, err_West_grant_L => L_err_West_grant_L, err_South_Req_N => L_err_South_Req_N,
err_South_grant_N => L_err_South_grant_N, err_Local_Req_E => L_err_Local_Req_E, err_Local_grant_E => L_err_Local_grant_E,
err_IDLE_Req_S => L_err_IDLE_Req_S, err_IDLE_grant_S => L_err_IDLE_grant_S, err_North_Req_S => L_err_North_Req_S,
err_North_grant_S => L_err_North_grant_S, err_East_Req_L => L_err_East_Req_L, err_East_grant_L => L_err_East_grant_L,
err_West_Req_N => L_err_West_Req_N, err_West_grant_N => L_err_West_grant_N, err_South_Req_E => L_err_South_Req_E,
err_South_grant_E => L_err_South_grant_E, err_Local_Req_W => L_err_Local_Req_W, err_Local_grant_W => L_err_Local_grant_W,
err_IDLE_Req_L => L_err_IDLE_Req_L, err_IDLE_grant_L => L_err_IDLE_grant_L, err_North_Req_L => L_err_North_Req_L,
err_North_grant_L => L_err_North_grant_L, err_East_Req_N => L_err_East_Req_N, err_East_grant_N => L_err_East_grant_N,
err_West_Req_E => L_err_West_Req_E, err_West_grant_E => L_err_West_grant_E, err_South_Req_W => L_err_South_Req_W,
err_South_grant_W => L_err_South_grant_W, err_Local_Req_S => L_err_Local_Req_S, err_Local_grant_S => L_err_Local_grant_S,
err_state_in_onehot => L_err_state_in_onehot,
err_no_request_grants => L_err_no_request_grants,
err_request_no_grants => L_err_request_no_grants,
err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => L_err_no_Req_L_grant_L
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter Out mobuldes instantiation(s)
-- Y is N now
-- North Arbiter_out with checkers integrated
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig, grant_Y_E => grant_N_E_sig, grant_Y_W => grant_N_W_sig, grant_Y_S => grant_N_S_sig, grant_Y_L => grant_N_L_sig,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_Arbiter_out_N_Arbiter_out, SO=> fault_DO_serial_N_Arbiter_out_E_Arbiter_out,
-- Checker outputs
err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => N_err_IDLE_req_X_N,
err_North_req_X_N => N_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => N_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => N_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => N_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => N_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => N_err_IDLE_req_X_E, err_North_req_X_E => N_err_North_req_X_E, err_East_req_X_W => N_err_East_req_X_W,
err_West_req_X_S => N_err_West_req_X_S, err_South_req_X_L => N_err_South_req_X_L, err_Local_req_X_N => N_err_Local_req_X_N,
err_IDLE_req_X_W => N_err_IDLE_req_X_W, err_North_req_X_W => N_err_North_req_X_W, err_East_req_X_S => N_err_East_req_X_S,
err_West_req_X_L => N_err_West_req_X_L, err_South_req_X_N => N_err_South_req_X_N, err_Local_req_X_E => N_err_Local_req_X_E,
err_IDLE_req_X_S => N_err_IDLE_req_X_S, err_North_req_X_S => N_err_North_req_X_S, err_East_req_X_L => N_err_East_req_X_L,
err_West_req_X_N => N_err_West_req_X_N, err_South_req_X_E => N_err_South_req_X_E, err_Local_req_X_W => N_err_Local_req_X_W,
err_IDLE_req_X_L => N_err_IDLE_req_X_L, err_North_req_X_L => N_err_North_req_X_L, err_East_req_X_N => N_err_East_req_X_N,
err_West_req_X_E => N_err_West_req_X_E, err_South_req_X_W => N_err_South_req_X_W, err_Local_req_X_S => N_err_Local_req_X_S,
err_state_in_onehot => N_arbiter_out_err_state_in_onehot, err_no_request_grants => N_arbiter_out_err_no_request_grants,
err_request_IDLE_state => N_err_request_IDLE_state,
err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero
);
-- Y is E now
-- East Arbiter_out with checkers integrated
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig, grant_Y_E => grant_E_E_sig, grant_Y_W => grant_E_W_sig, grant_Y_S => grant_E_S_sig, grant_Y_L => grant_E_L_sig,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_Arbiter_out_E_Arbiter_out, SO=> fault_DO_serial_E_Arbiter_out_W_Arbiter_out,
-- Checker outputs
err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => E_err_IDLE_req_X_N, err_North_req_X_N => E_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => E_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => E_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => E_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => E_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => E_err_IDLE_req_X_E, err_North_req_X_E => E_err_North_req_X_E, err_East_req_X_W => E_err_East_req_X_W,
err_West_req_X_S => E_err_West_req_X_S, err_South_req_X_L => E_err_South_req_X_L, err_Local_req_X_N => E_err_Local_req_X_N,
err_IDLE_req_X_W => E_err_IDLE_req_X_W, err_North_req_X_W => E_err_North_req_X_W, err_East_req_X_S => E_err_East_req_X_S,
err_West_req_X_L => E_err_West_req_X_L, err_South_req_X_N => E_err_South_req_X_N, err_Local_req_X_E => E_err_Local_req_X_E,
err_IDLE_req_X_S => E_err_IDLE_req_X_S, err_North_req_X_S => E_err_North_req_X_S, err_East_req_X_L => E_err_East_req_X_L,
err_West_req_X_N => E_err_West_req_X_N, err_South_req_X_E => E_err_South_req_X_E, err_Local_req_X_W => E_err_Local_req_X_W,
err_IDLE_req_X_L => E_err_IDLE_req_X_L, err_North_req_X_L => E_err_North_req_X_L, err_East_req_X_N => E_err_East_req_X_N,
err_West_req_X_E => E_err_West_req_X_E, err_South_req_X_W => E_err_South_req_X_W, err_Local_req_X_S => E_err_Local_req_X_S,
err_state_in_onehot => E_arbiter_out_err_state_in_onehot, err_no_request_grants => E_arbiter_out_err_no_request_grants,
err_request_IDLE_state => E_err_request_IDLE_state,
err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero
);
-- Y is W now
-- West Arbiter_out with checkers integrated
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig, grant_Y_E => grant_W_E_sig, grant_Y_W => grant_W_W_sig, grant_Y_S => grant_W_S_sig, grant_Y_L => grant_W_L_sig,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_Arbiter_out_W_Arbiter_out, SO=> fault_DO_serial_W_Arbiter_out_S_Arbiter_out,
-- Checker outputs
err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => W_err_IDLE_req_X_N, err_North_req_X_N => W_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => W_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => W_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => W_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => W_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => W_err_IDLE_req_X_E, err_North_req_X_E => W_err_North_req_X_E, err_East_req_X_W => W_err_East_req_X_W,
err_West_req_X_S => W_err_West_req_X_S, err_South_req_X_L => W_err_South_req_X_L, err_Local_req_X_N => W_err_Local_req_X_N,
err_IDLE_req_X_W => W_err_IDLE_req_X_W, err_North_req_X_W => W_err_North_req_X_W, err_East_req_X_S => W_err_East_req_X_S,
err_West_req_X_L => W_err_West_req_X_L, err_South_req_X_N => W_err_South_req_X_N, err_Local_req_X_E => W_err_Local_req_X_E,
err_IDLE_req_X_S => W_err_IDLE_req_X_S, err_North_req_X_S => W_err_North_req_X_S, err_East_req_X_L => W_err_East_req_X_L,
err_West_req_X_N => W_err_West_req_X_N, err_South_req_X_E => W_err_South_req_X_E, err_Local_req_X_W => W_err_Local_req_X_W,
err_IDLE_req_X_L => W_err_IDLE_req_X_L, err_North_req_X_L => W_err_North_req_X_L, err_East_req_X_N => W_err_East_req_X_N,
err_West_req_X_E => W_err_West_req_X_E, err_South_req_X_W => W_err_South_req_X_W, err_Local_req_X_S => W_err_Local_req_X_S,
err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
err_no_request_grants => W_arbiter_out_err_no_request_grants,
err_request_IDLE_state => W_err_request_IDLE_state,
err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero
);
-- Y is S now
-- South Arbiter_out with checkers integrated
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig, grant_Y_E => grant_S_E_sig, grant_Y_W => grant_S_W_sig, grant_Y_S => grant_S_S_sig, grant_Y_L => grant_S_L_sig,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_Arbiter_out_S_Arbiter_out, SO=> fault_DO_serial_S_Arbiter_out_Allocator_logic,
-- Checker outputs
err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => S_err_IDLE_req_X_N, err_North_req_X_N => S_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => S_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => S_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => S_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => S_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => S_err_IDLE_req_X_E, err_North_req_X_E => S_err_North_req_X_E, err_East_req_X_W => S_err_East_req_X_W,
err_West_req_X_S => S_err_West_req_X_S, err_South_req_X_L => S_err_South_req_X_L, err_Local_req_X_N => S_err_Local_req_X_N,
err_IDLE_req_X_W => S_err_IDLE_req_X_W, err_North_req_X_W => S_err_North_req_X_W, err_East_req_X_S => S_err_East_req_X_S,
err_West_req_X_L => S_err_West_req_X_L, err_South_req_X_N => S_err_South_req_X_N, err_Local_req_X_E => S_err_Local_req_X_E,
err_IDLE_req_X_S => S_err_IDLE_req_X_S, err_North_req_X_S => S_err_North_req_X_S, err_East_req_X_L => S_err_East_req_X_L,
err_West_req_X_N => S_err_West_req_X_N, err_South_req_X_E => S_err_South_req_X_E, err_Local_req_X_W => S_err_Local_req_X_W,
err_IDLE_req_X_L => S_err_IDLE_req_X_L, err_North_req_X_L => S_err_North_req_X_L, err_East_req_X_N => S_err_East_req_X_N,
err_West_req_X_E => S_err_West_req_X_E, err_South_req_X_W => S_err_South_req_X_W, err_Local_req_X_S => S_err_Local_req_X_S,
err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
err_no_request_grants => S_arbiter_out_err_no_request_grants,
err_request_IDLE_state => S_err_request_IDLE_state,
err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero
);
-- Y is L now
-- Local Arbiter_out with checkers integrated
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig, grant_Y_E => grant_L_E_sig, grant_Y_W => grant_L_W_sig, grant_Y_S => grant_L_S_sig, grant_Y_L => grant_L_L_sig,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_Arbiter_in_L_Arbiter_out, SO=> fault_DO_serial_L_Arbiter_out_N_Arbiter_out,
-- Checker outputs
err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => L_err_IDLE_req_X_N, err_North_req_X_N => L_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => L_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => L_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => L_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => L_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => L_err_IDLE_req_X_E, err_North_req_X_E => L_err_North_req_X_E, err_East_req_X_W => L_err_East_req_X_W,
err_West_req_X_S => L_err_West_req_X_S, err_South_req_X_L => L_err_South_req_X_L, err_Local_req_X_N => L_err_Local_req_X_N,
err_IDLE_req_X_W => L_err_IDLE_req_X_W, err_North_req_X_W => L_err_North_req_X_W, err_East_req_X_S => L_err_East_req_X_S,
err_West_req_X_L => L_err_West_req_X_L, err_South_req_X_N => L_err_South_req_X_N, err_Local_req_X_E => L_err_Local_req_X_E,
err_IDLE_req_X_S => L_err_IDLE_req_X_S, err_North_req_X_S => L_err_North_req_X_S, err_East_req_X_L => L_err_East_req_X_L,
err_West_req_X_N => L_err_West_req_X_N, err_South_req_X_E => L_err_South_req_X_E, err_Local_req_X_W => L_err_Local_req_X_W,
err_IDLE_req_X_L => L_err_IDLE_req_X_L, err_North_req_X_L => L_err_North_req_X_L, err_East_req_X_N => L_err_East_req_X_N,
err_West_req_X_E => L_err_West_req_X_E, err_South_req_X_W => L_err_South_req_X_W, err_Local_req_X_S => L_err_Local_req_X_S,
err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
err_no_request_grants => L_arbiter_out_err_no_request_grants,
err_request_IDLE_state => L_err_request_IDLE_state,
err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
valid_N_sig <= grant_N;
valid_E_sig <= grant_E;
valid_W_sig <= grant_W;
valid_S_sig <= grant_S;
valid_L_sig <= grant_L;
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers.vhd
|
3
|
54694
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/network_2x2_NI_FI_packet_drop_SHMU_credit_based_with_checkers_tb.vhd
|
3
|
10824
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(7 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --component NoC_Node
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--fault injector signals
signal FI_Add_2_0, FI_Add_0_2: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: std_logic :='0';
signal FI_Add_3_1, FI_Add_1_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: std_logic :='0';
signal FI_Add_1_0, FI_Add_0_1: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: std_logic :='0';
signal FI_Add_3_2, FI_Add_2_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: std_logic :='0';
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
--fault injector signals
--FI vertical signals
FI_Add_2_0, FI_Add_0_2,
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0,
FI_Add_3_1, FI_Add_1_3,
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1,
--FI horizontal signals
FI_Add_1_0, FI_Add_0_1,
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0,
FI_Add_3_2, FI_Add_2_3,
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => "code_0.txt",
log_file => "output_0.txt")
port map( not_reset, clk,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => "code_1.txt",
log_file => "output_1.txt")
port map( not_reset, clk,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => "code_2.txt",
log_file => "output_2.txt")
port map( not_reset, clk,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => "code_3.txt",
log_file => "output_3.txt")
port map( not_reset, clk,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the fault generators
gen_fault(sta0_1_0, sta1_1_0, FI_Add_1_0, 63,442052708,1828205602);
gen_fault(sta0_0_1, sta1_0_1, FI_Add_0_1, 53,1295222520,931907344);
gen_fault(sta0_2_0, sta1_2_0, FI_Add_2_0, 70,384023008,1549010334);
gen_fault(sta0_0_2, sta1_0_2, FI_Add_0_2, 61,460224063,1900282825);
gen_fault(sta0_3_1, sta1_3_1, FI_Add_3_1, 51,1175811338,1371195782);
gen_fault(sta0_1_3, sta1_1_3, FI_Add_1_3, 48,2134559509,1884522909);
gen_fault(sta0_3_2, sta1_3_2, FI_Add_3_2, 52,69484405,203739638);
gen_fault(sta0_2_3, sta1_2_3, FI_Add_2_3, 48,1017472312,722198941);
end;
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_1/tb_round_f.vhd
|
3
|
4349
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rst : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period + clk_period/2;
rst <= '1';
wait for clk_period;
rst <= '0';
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
-- assert a_0_out = X"febb00d0"
-- report "ROUND ERROR (a_0)" severity FAILURE;
--
-- assert a_1_out = X"074ee42e"
-- report "ROUND ERROR (a_1)" severity FAILURE;
--
-- assert a_2_out = X"dde647ab"
-- report "ROUND ERROR (a_2)" severity FAILURE;
--
-- assert a_3_out = X"3207ef78"
-- report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
rogerioag/gcg
|
tutorial/ula/src/and2.vhd
|
1
|
345
|
-- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: and2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and2 is
port(a,b:in std_logic; y:out std_logic);
end and2;
architecture estrutural of and2 is
begin
y <= a and b;
end estrutural;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Processor_NI/reg_bank_tri_port.vhd
|
6
|
5215
|
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "TRI_PORT_X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal tri_port_ram : ram_type := (others => ZERO);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
--------------------------------------
-- Implements register bank control --
--------------------------------------
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new, intr_enable_reg,
data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";--"01110" --"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
-----------------------
-- Implements memory --
-----------------------
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
ram_proc: process(clk, addr_read1, addr_read2, addr_write,
reg_dest_new, write_enable)
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) <= reg_dest_new;
end if;
end if;
end process;
end; --architecture ram_block
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/reg_bank_tri_port.vhd
|
6
|
5215
|
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "TRI_PORT_X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal tri_port_ram : ram_type := (others => ZERO);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
--------------------------------------
-- Implements register bank control --
--------------------------------------
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new, intr_enable_reg,
data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";--"01110" --"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
-----------------------
-- Implements memory --
-----------------------
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
ram_proc: process(clk, addr_read1, addr_read2, addr_write,
reg_dest_new, write_enable)
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) <= reg_dest_new;
end if;
end if;
end process;
end; --architecture ram_block
|
gpl-3.0
|
rogerioag/gcg
|
samples/and2/templates/decl_components_instances.vhd
|
5
|
139
|
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/network_2x2_packet_drop_SHMU_credit_based_with_checkers.vhd
|
3
|
41163
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic;
--------------
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
COMPONENT router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
link_faults_async: out std_logic_vector(4 downto 0);
turn_faults_async: out std_logic_vector(19 downto 0)
);
end COMPONENT;
-- For IJAG
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- fault injector signals
signal TCK_0, TCK_1, TCK_2, TCK_3: std_logic;
signal SE_0, SE_1, SE_2, SE_3: std_logic;
signal UE_0, UE_1, UE_2, UE_3: std_logic;
signal SI_0, SI_1, SI_2, SI_3: std_logic;
signal SO_0, SO_1, SO_2, SO_3: std_logic;
--------------
-- IJTAG network signals
signal SIB_0_toSEL, SIB_1_toSEL, SIB_2_toSEL, SIB_3_toSEL : std_logic;
signal SIB_0_toCE, SIB_1_toCE, SIB_2_toCE, SIB_3_toCE : std_logic;
signal SIB_0_toRST, SIB_1_toRST, SIB_2_toRST, SIB_3_toRST : std_logic;
signal SIB_0_so, SIB_1_so, SIB_2_so, SIB_3_so : std_logic;
-- flags from checkers
signal F_R0, F_R1, F_R2, F_R3 : std_logic := '0';
signal C_R0, C_R1, C_R2, C_R3 : std_logic := '1';
-- flags top level
signal F_segtop_fromSIB_0, C_segtop_fromSIB_0 : std_logic;
signal F_segtop_fromSIB_1, C_segtop_fromSIB_1 : std_logic;
signal F_segtop_fromSIB_2, C_segtop_fromSIB_2 : std_logic;
signal F_segtop_fromSIB_3, C_segtop_fromSIB_3 : std_logic;
--------------
-- the checker output related ports (for unclassified fault information)
signal link_faults_async_0 : std_logic_vector(4 downto 0);
signal turn_faults_async_0: std_logic_vector(19 downto 0);
--------------
signal link_faults_async_1 : std_logic_vector(4 downto 0);
signal turn_faults_async_1: std_logic_vector(19 downto 0);
--------------
signal link_faults_async_2 : std_logic_vector(4 downto 0);
signal turn_faults_async_2: std_logic_vector(19 downto 0);
--------------
signal link_faults_async_3 : std_logic_vector(4 downto 0);
signal turn_faults_async_3: std_logic_vector(19 downto 0);
--------------
-- Fault injection related signals and constants
constant fault_clk_period : time := 1 ns;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
begin
---- Fault injection clock process (IJTAG-related)
--fault_clk_process :process
--begin
-- TCK_0 <= '0';
-- wait for fault_clk_period/2;
-- TCK_0 <= '1';
-- wait for fault_clk_period/2;
--end process;
---- Fault Injection Stimulus process (shifting in single SA0 fault at a location in L FIFO in Router 0)
--fault_injection_stim_proc: process
--begin
-- wait for 3000 ns;
-- UE_0 <= '0';
-- SE_0 <= '1';
-- -- Not Injecting fault to Allocator logic
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to S Arbiter_out
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to W Arbiter_out
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to E Arbiter_out
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to N Arbiter_out
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to L Arbiter_out
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to S Arbiter_in
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to W Arbiter_in
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to E Arbiter_in
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to N Arbiter_in
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to L Arbiter_in
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to S LBDR
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to W LBDR
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to E LBDR
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to N LBDR
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to L LBDR
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to S FIFO
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA0 fault injection at bit 40 (read_pointer(0))
-- -- Not Injecting fault to W FIFO
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA1 fault injection at bit 0 (LSB)
-- -- Injecting fault to E FIFO
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA1 fault injection at bit 0 (LSB)
-- -- Not Injecting fault to N FIFO
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA1 fault injection at bit 0 (LSB)
-- -- Injecting fault to L FIFO
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '0'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0';
-- SI_0 <= '1'; -- SA1 fault injection at bit 0 (LSB)
-- wait until TCK_0'event and TCK_0 ='0'; -- Actually affect the signal(s) with fault information
-- UE_0 <= '1';
-- SE_0 <= '0';
-- SI_0 <= '0';
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- --wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- wait until TCK_0'event and TCK_0 ='0'; -- No fault injection anymore and no shifting
-- UE_0 <= '0';
-- SE_0 <= '0';
-- SI_0 <= '0';
-- --wait until TCK_0'event and TCK_0 ='0';
-- wait; --??
--end process;
-- flags top level
toF <= F_segtop_fromSIB_0 or F_segtop_fromSIB_1 or F_segtop_fromSIB_2 or F_segtop_fromSIB_3;
toC <= C_segtop_fromSIB_0 and C_segtop_fromSIB_1 and C_segtop_fromSIB_2 and C_segtop_fromSIB_3;
SO <= SIB_3_so;
SIB_0 : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SIB_0_so,
toF => F_segtop_fromSIB_0,
toC => C_segtop_fromSIB_0,
-- Scan Interface host ----------------
fromSO => SO_0,
toCE => SIB_0_toCE,
toSE => SE_0,
toUE => UE_0,
toSEL => SIB_0_toSEL,
toRST => SIB_0_toRST,
toTCK => TCK_0,
toSI => SI_0,
fromF => F_R0,
fromC => C_R0
);
SIB_1 : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_0_so,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SIB_1_so,
toF => F_segtop_fromSIB_1,
toC => C_segtop_fromSIB_1,
-- Scan Interface host ----------------
fromSO => SO_1,
toCE => SIB_1_toCE,
toSE => SE_1,
toUE => UE_1,
toSEL => SIB_1_toSEL,
toRST => SIB_1_toRST,
toTCK => TCK_1,
toSI => SI_1,
fromF => F_R1,
fromC => C_R1
);
SIB_2 : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_1_so,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SIB_2_so,
toF => F_segtop_fromSIB_2,
toC => C_segtop_fromSIB_2,
-- Scan Interface host ----------------
fromSO => SO_2,
toCE => SIB_2_toCE,
toSE => SE_2,
toUE => UE_2,
toSEL => SIB_2_toSEL,
toRST => SIB_2_toRST,
toTCK => TCK_2,
toSI => SI_2,
fromF => F_R2,
fromC => C_R2
);
SIB_3 : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_2_so,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SIB_3_so,
toF => F_segtop_fromSIB_3,
toC => C_segtop_fromSIB_3,
-- Scan Interface host ----------------
fromSO => SO_3,
toCE => SIB_3_toCE,
toSE => SE_3,
toUE => UE_3,
toSEL => SIB_3_toSEL,
toRST => SIB_3_toRST,
toTCK => TCK_3,
toSI => SI_3,
fromF => F_R3,
fromC => C_R3
);
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
-- fault injector shift register with serial input signals
TCK_0, SE_0, UE_0, SI_0, SO_0,
-- the non-classified fault information
link_faults_async_0, turn_faults_async_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
-- fault injector shift register with serial input signals
TCK_1, SE_1, UE_1, SI_1, SO_1,
-- the non-classified fault information
link_faults_async_1, turn_faults_async_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
-- fault injector shift register with serial input signals
TCK_2, SE_2, UE_2, SI_2, SO_2,
-- the non-classified fault information
link_faults_async_2, turn_faults_async_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3,
-- fault injector shift register with serial input signals
TCK_3, SE_3, UE_3, SI_3, SO_3,
-- the non-classified fault information
link_faults_async_3, turn_faults_async_3
);
---------------------------------------------------------------
-- binding the routers together
-- vertical ins/outs
-- connecting router: 0 to router: 2 and vice versa
RX_N_2<= TX_S_0;
RX_S_0<= TX_N_2;
-------------------
-- connecting router: 1 to router: 3 and vice versa
RX_N_3<= TX_S_1;
RX_S_1<= TX_N_3;
-------------------
-- horizontal ins/outs
-- connecting router: 0 to router: 1 and vice versa
RX_E_0 <= TX_W_1;
RX_W_1 <= TX_E_0;
-------------------
-- connecting router: 2 to router: 3 and vice versa
RX_E_2 <= TX_W_3;
RX_W_3 <= TX_E_2;
-------------------
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Allocator_with_checkers/arbiter_out_one_hot_with_checkers.vhd
|
9
|
17021
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end;
architecture behavior of arbiter_out is
component Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE;
SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic;
begin
-- We did this because of the checker outputs!
grant_Y_N <= grant_Y_N_sig;
grant_Y_E <= grant_Y_E_sig;
grant_Y_W <= grant_Y_W_sig;
grant_Y_S <= grant_Y_S_sig;
grant_Y_L <= grant_Y_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1' then
state <= state_in;
end if;
end process;
-- Arbiter_out checkers module instantiation
ARBITER_OUT_ONE_HOT_CHECKERS: Arbiter_out_one_hot_pseudo_checkers
port map (
credit => credit,
req_X_N => X_N_Y,
req_X_E => X_E_Y,
req_X_W => X_W_Y,
req_X_S => X_S_Y,
req_X_L => X_L_Y,
state => state,
grant_Y_N => grant_Y_N_sig,
grant_Y_E => grant_Y_E_sig,
grant_Y_W => grant_Y_W_sig,
grant_Y_S => grant_Y_S_sig,
grant_Y_L => grant_Y_L_sig,
state_in => state_in,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => err_IDLE_req_X_N,
err_North_req_X_N => err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => err_IDLE_req_X_E,
err_North_req_X_E => err_North_req_X_E,
err_East_req_X_W => err_East_req_X_W,
err_West_req_X_S => err_West_req_X_S,
err_South_req_X_L => err_South_req_X_L,
err_Local_req_X_N => err_Local_req_X_N,
err_IDLE_req_X_W => err_IDLE_req_X_W,
err_North_req_X_W => err_North_req_X_W,
err_East_req_X_S => err_East_req_X_S,
err_West_req_X_L => err_West_req_X_L,
err_South_req_X_N => err_South_req_X_N,
err_Local_req_X_E => err_Local_req_X_E,
err_IDLE_req_X_S => err_IDLE_req_X_S,
err_North_req_X_S => err_North_req_X_S,
err_East_req_X_L => err_East_req_X_L,
err_West_req_X_N => err_West_req_X_N,
err_South_req_X_E => err_South_req_X_E,
err_Local_req_X_W => err_Local_req_X_W,
err_IDLE_req_X_L => err_IDLE_req_X_L,
err_North_req_X_L => err_North_req_X_L,
err_East_req_X_N => err_East_req_X_N,
err_West_req_X_E => err_West_req_X_E,
err_South_req_X_W => err_South_req_X_W,
err_Local_req_X_S => err_Local_req_X_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_IDLE_state => err_request_IDLE_state,
err_request_IDLE_not_Grants => err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero
);
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit)
begin
grant_Y_N_sig <= '0';
grant_Y_E_sig <= '0';
grant_Y_W_sig <= '0';
grant_Y_S_sig <= '0';
grant_Y_L_sig <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1' then
grant_Y_N_sig <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1' then
grant_Y_E_sig <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1' then
grant_Y_W_sig <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S_sig <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L_sig <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Allocator_with_checkers/Arbiter_in_one_hot_with_checkers.vhd
|
12
|
12952
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
begin
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state, -- _sig not needed, because it is an input port
state_in => state_in, -- _sig not needed, because it is an internal signal
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/Arbiter_in_one_hot_with_checkers.vhd
|
12
|
12952
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
begin
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state, -- _sig not needed, because it is an input port
state_in => state_in, -- _sig not needed, because it is an internal signal
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_with_checkers.vhd
|
3
|
23415
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal,
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
-- Signal(s) required for checker(s)
signal packet_drop_order_sig: std_logic;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Cx_in: in std_logic_vector(3 downto 0);
Temp_Cx: in std_logic_vector(3 downto 0);
reconfig_cx_in: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Faulty_C_N: in std_logic;
Faulty_C_E: in std_logic;
Faulty_C_W: in std_logic;
Faulty_C_S: in std_logic;
Temp_Cx_in: in std_logic_vector(3 downto 0);
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
begin
packet_drop_order <= packet_drop_order_sig;
-- LBDR packet drop routing part checkers instantiation
LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers
generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
dst_addr => dst_addr,
Cx => Cx,
Rxy => Rxy,
packet_drop => packet_drop,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
grants => grants,
packet_drop_order => packet_drop_order_sig,
packet_drop_in => packet_drop_in,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => err_grants_onehot,
err_grants_mismatch => err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => err_packet_drop_order
);
-- LBDR packet drop Cx Reconfiguration module checkers instantiation
Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers
port map ( reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in,
Cx => Cx,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal
);
-- LBDR packet drop Rxy Reconfiguration checkers instantiation
Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers
port map ( ReConf_FF_out => ReConf_FF_out,
flit_type => flit_type,
empty => empty,
grants => grants,
Rxy_in => Rxy_in,
Rxy_reconf => Rxy_reconf,
ReConf_FF_in => ReConf_FF_in,
Rxy => Rxy,
Reconfig => Reconfig,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal
);
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= Rxy_reconf;
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty)begin
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_reconf;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig = '1' then
ReConf_FF_in <= '1';
else
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order_sig <= packet_drop;
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/ram.vhd
|
6
|
3172
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 13;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
gpl-3.0
|
rogerioag/gcg
|
src/templates/decl_components.vhd
|
5
|
145
|
-- Declaration of Components.\n
component <<COMPONENT_NAME>>\n
port(<<ports_in>>: in <<type>>; <<ports_out>>: out <<type>>);\n
end component;\n
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/LBDR_packet_drop_with_checkers.vhd
|
6
|
27011
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
-- Signal(s) required for checker(s)
signal packet_drop_order_sig: std_logic;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
begin
packet_drop_order <= packet_drop_order_sig;
-- LBDR packet drop routing part checkers instantiation
LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers
generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
dst_addr => dst_addr,
Cx => Cx,
Rxy => Rxy,
packet_drop => packet_drop,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
grants => grants,
packet_drop_order => packet_drop_order_sig,
packet_drop_in => packet_drop_in,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => err_grants_onehot,
err_grants_mismatch => err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => err_packet_drop_order
);
-- LBDR packet drop Cx Reconfiguration module checkers instantiation
Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in,
Cx => Cx,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal
);
-- LBDR packet drop Rxy Reconfiguration checkers instantiation
Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers
port map (
ReConf_FF_out => ReConf_FF_out,
Rxy => Rxy,
Rxy_tmp => Rxy_tmp,
Reconfig_command => Reconfig_command,
flit_type => flit_type,
grants => grants,
empty => empty,
Rxy_reconf_PE => Rxy_reconf_PE,
Rxy_in => Rxy_in,
Rxy_tmp_in => Rxy_tmp_in,
ReConf_FF_in => ReConf_FF_in,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
Rxy_tmp <= (others => '0');
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Rxy_tmp <= Rxy_tmp_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin
Rxy_tmp_in <= Rxy_tmp;
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_tmp;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig_command = '1'then
Rxy_tmp_in <= Rxy_reconf_PE;
ReConf_FF_in <= '1';
else
Rxy_tmp_in <= Rxy_tmp;
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
elsif Reconfig_command = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= Cx_reconf_PE;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, dst_addr, cur_addr) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order_sig <= packet_drop;
END;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/shifter.vhd
|
16
|
3063
|
---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Processor_NI/uart.vhd
|
3
|
9274
|
---------------------------------------------------------------------
-- TITLE: Simulatable UART. Does not synthesize. Writes UART output to a file.
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
-- NOTICE: Please add the newline character ('\n') to the end of every
-- line you send over the UART, otherwise it won't save it.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
end; --architecture logic
|
gpl-3.0
|
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_1/noekeon.vhd
|
1
|
7924
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(271 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(271 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
rc_in_s <= X"80801b1b36366c6cd8d8abab4d4d9a9a2f2f5e5ebcbc6363c6c6979735356a6ad4d4";
-- 000000000000000000";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/RTL/Router_32_bit_credit_based.vhd
|
3
|
14588
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based;
architecture behavior of router_credit_based is
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
Project-Bonfire/KOIT
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Arbiter_in_one_hot_checkers/RTL_and_Synthesis/arbiter_in_one_hot_pseudo.vhd
|
3
|
4141
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end;
architecture behavior of arbiter_in_one_hot_pseudo is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N <= '0';
X_E <= '0';
X_W <= '0';
X_S <= '0';
X_L <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, am I correct ?
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
else
state_in <= state;
end if;
when others => -- Local state and invalid states
if req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z091-01_src/Source/tx_put_data.vhd
|
1
|
18302
|
--------------------------------------------------------------------------------
-- Title : tx_put_data
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_put_data.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- data handling module for tx path, controlled by tx_ctrl.vhd;
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- * tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_put_data is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end entity tx_put_data;
-- ****************************************************************************
architecture tx_put_data_arch of tx_put_data is
-- internal signals: ----------------------------------------------------------
signal aligned_int : std_logic;
signal data_in_q : std_logic_vector(63 downto 0);
signal data_q : std_logic_vector(63 downto 0);
signal data_qq : std_logic_vector(63 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal lower_addr_int : std_logic_vector(6 downto 0);
signal first_DW_int : std_logic_vector(3 downto 0);
signal last_DW_int : std_logic_vector(3 downto 0);
signal wr_rd_int : std_logic; -- =0: wr, =1: rd
signal mem_io_int : std_logic; -- =0: mem, =1: I/O
signal io_write_int : std_logic;
-------------------------------------------------------------------------------
begin
io_write <= io_write_int;
data_path : process(rst, clk)
begin
if(rst = '1') then
-- ports:
tx_st_data0 <= (others => '0');
data_length <= (others => '0');
aligned <= '0';
wr_rd <= '0';
posted <= '0';
byte_count <= (others => '0');
orig_addr <= (others => '0');
-- signals:
aligned_int <= '0';
data_in_q <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
req_id_int <= (others => '0');
tag_id_int <= (others => '0');
lower_addr_int <= (others => '0');
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
wr_rd_int <= '0';
mem_io_int <= '0';
io_write_int <= '0';
else
if(clk'event and clk = '1') then
-- capture data length from appropriate FIFO packet
if(get_header = '1' and c_wrrd = '0') then
data_length <= tx_c_head_out(9 downto 0);
elsif(get_header = '1' and c_wrrd = '1') then
data_length <= tx_wr_head_out(9 downto 0);
end if;
-- store alignment information for both completion and write/read transmissions
if(get_header = '1' and c_wrrd = '0') then
case tx_c_head_out(34) is
when '0' => -- check bit 2 of address for alignment
aligned_int <= '1' ;
aligned <= '1' ;
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
elsif(get_header = '1' and c_wrrd = '1') then
case tx_wr_head_out(34) is
when '0' =>
aligned_int <= '1';
aligned <= '1';
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
end if;
-- capture information if transmission is write or read
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(31) = '1') then
wr_rd <= '0';
wr_rd_int <= '0';
else
wr_rd <= '1';
wr_rd_int <= '1';
end if;
----------------------------------------------------------------------------------------
-- wr_rd is not reset if c_wrrd = 0 and if previous transfer is read it's stuck at '1'
-- which causes errors during transfer
-- thus added elsif
----------------------------------------------------------------------------------------
elsif get_header = '1' and c_wrrd = '0' then
wr_rd <= '0';
wr_rd_int <= '0';
end if;
-- define if transfer is posted or not
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(30) = '1') then -- posted
posted <= '1';
else -- non-posted
posted <= '0';
end if;
end if;
-- define wether transfer is of type memory or I/O
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(29) = '1') then
mem_io_int <= '0'; -- memory
else
mem_io_int <= '1'; -- I/O
end if;
end if;
-- store information on first/last byte enables
if(get_header = '1' and c_wrrd = '1') then
first_DW_int <= tx_wr_head_out(17 downto 14); -- first DW
last_DW_int <= tx_wr_head_out(13 downto 10); -- last DW
end if;
-- register header packet
if(get_header = '1' and c_wrrd = '0') then
data_in_q <= tx_c_head_out;
end if;
-- store requester ID
if(get_next_header = '1' and c_wrrd = '0') then
req_id_int <= tx_c_head_out(15 downto 0);
end if;
-- store tag ID
if(get_header = '1' and c_wrrd = '0') then
tag_id_int <= tx_c_head_out(25 downto 18);
end if;
-- store byte count
if(get_next_header = '1' and c_wrrd = '0') then
byte_count <= tx_c_head_out(27 downto 16);
end if;
-- store I/O write flag
if(get_next_header = '1' and c_wrrd = '0') then
io_write_int <= tx_c_head_out(28);
elsif c_wrrd = '1' then
io_write_int <= '0';
end if;
-- store original transfer address
if(get_header = '1' and c_wrrd = '0') then
orig_addr <= tx_c_head_out(63 downto 32);
elsif(get_header = '1' and c_wrrd = '1') then
orig_addr <= tx_wr_head_out(63 downto 32);
end if;
-- calculate lower address for completions
if(get_header = '1' and c_wrrd = '0') then
if(tx_c_head_out(17 downto 14) = "0000" or tx_c_head_out(14) = '1') then
lower_addr_int <= tx_c_head_out(38 downto 34) & "00"; -- calculate from first DW
elsif(tx_c_head_out(15 downto 14) = "10") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "01";
elsif(tx_c_head_out(16 downto 14) = "100") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "10";
elsif(tx_c_head_out(17 downto 14) = "1000") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "11";
-- coverage off
else
-- synthesis translate_off
report "wrong encoding of tx_c_head_out(17 downto 14)" severity error;
-- synthesis translate_on
-- coverage on
end if;
end if;
-- assebmle packets for transmission
-- c_wrrd controls whether completion or write/read transfer is needed
-- R := reserved according to PCIe base specification, thus set to '0' here
if(make_header = '1' and c_wrrd = '0') then
if(abort_compl = '1' or io_write_int = '1') then
data_qq(31 downto 24) <= "00001010"; -- fmt & type -> completion without data
else
data_qq(31 downto 24) <= "01001010"; -- fmt & type -> completion with data
end if;
data_qq(23) <= '0'; -- R
data_qq(22 downto 20) <= data_in_q(28 downto 26); -- TC
data_qq(19) <= '0'; -- R
data_qq(18) <= data_in_q(31); -- Attr(2)
data_qq(17 downto 14) <= '0' & '0' & '0' & '0'; -- R & TH & TD & EP
data_qq(13 downto 12) <= data_in_q(30 downto 29); -- Attr(1:0)
data_qq(11 downto 10) <= "00"; -- AT
data_qq(9 downto 0) <= data_in_q(9 downto 0); -- length
data_qq(63 downto 48) <= completer_id;
if(abort_compl = '1') then
data_qq(47 downto 45) <= "100"; -- completion status = completer abort
else
data_qq(47 downto 45) <= "000"; -- completion status = successful completion
end if;
data_qq(44) <= '0'; -- bcm
data_qq(43 downto 32) <= tx_c_head_out(27 downto 16); -- byte count
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 16) <= req_id_int; -- requester ID
data_q(15 downto 8) <= tag_id_int; -- tag ID
data_q(7 downto 0) <= '0' & lower_addr_int; -- R & lower address
elsif(make_header = '1' and c_wrrd = '1') then
if(mem_io_int = '0' and wr_rd_int = '0') then -- memory write
data_qq(31 downto 24) <= "01000000";
elsif(mem_io_int = '1' and wr_rd_int = '0') then -- I/O write
data_qq(31 downto 24) <= "01000010";
elsif(mem_io_int = '0' and wr_rd_int = '1') then -- memory read
data_qq(31 downto 24) <= "00000000";
else -- I/O read
data_qq(31 downto 24) <= "00000010";
end if;
-- R & TC(2:0) & R & Attr(2) & R & TH & TD & EP & Attr(1:0) & AT
data_qq(23 downto 10) <= '0' & "000" & '0' & '0' & '0' & '0' & '0' & '0' & "00" & "00";
data_qq(9 downto 0) <= send_len; -- length
data_qq(63 downto 48) <= req_id;
data_qq(47 downto 40) <= tag_nbr;
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 0) <= send_addr; -- address
-- do payload loop, that means: one request was transmitted from Wishbone but the length is too big
-- thus split up in order to obey PCIe max_payload_size or max_read_size, which means
-- to send several packets with the same header info except address and length
-- CAUTION:
-- if the last packet to be sent has length =1 then last_DW must be =0
-- and the original setting for last_DW must be inserted for first_DW
if(payload_loop = '0') then
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "01") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "10") then
if send_len = "0000000001" then
data_qq(39 downto 36) <= x"0";
data_qq(35 downto 32) <= last_DW_int;
else
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= x"F";
end if;
elsif(payload_loop = '1' and first_last_full = "11") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= x"F";
end if;
end if;
-- manage registration of data retrieved from FIFO's
if(data_enable = '1' and aligned_int = '0' and c_wrrd = '0') then
data_q(31 downto 0) <= tx_c_data_out(63 downto 32);
data_qq <= tx_c_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '0' and c_wrrd = '1') then
data_q(31 downto 0) <= tx_wr_data_out(63 downto 32);
data_qq <= tx_wr_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '0') then
data_q <= tx_c_data_out;
data_qq <= data_q;
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '1') then
data_q <= tx_wr_data_out;
data_qq <= data_q;
end if;
-- output registered data to Avalon ST data bus
if(data_enable = '1') then
tx_st_data0 <= data_qq;
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture tx_put_data_arch;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z126-01_src/Source/z126_01_ru_ctrl_cyc5.vhd
|
1
|
30439
|
---------------------------------------------------------------
-- Title : Remote Update Control
-- Project : General IP-core
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 14.0.2
---------------------------------------------------------------
-- Description : The module is used to control the
-- serial loading of the FPGA image using the
-- altera remote update block.
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_ru_ctrl_cyc5.vhd
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: z126_01_ru_ctrl_cyc5.vhd,v $
-- Revision 1.3 2015/02/18 16:58:36 AGeissler
-- R1: The remote update controller for CYCLONE V from altera
-- needs a startup time to initialize the internal registers
-- M1: Added state START_UP_WAIT to wait 128 clock cycles
-- R2: Missing data out for state WRITE_CURR_STATE
-- M2: Write 1 to configuration mode (AnF)
-- R3: Wrong bit ordering for reconfig_cond register because of change
-- internal register bits meaning for CYCLONE V
-- M3: Changed assignment to connect the register that the bit meaning
-- is equal to CYCLONE IV
-- R4: Wrong transition from CHECK_STATE to WRITE_CURR_STATE
-- M4: Changed transition to WRITE_BOOT_ADDR and adjust ru_ctrl_param
-- R5: The boot address is read wrong, it could be connected directly
-- M5: Changed boot address assignment
--
-- Revision 1.2 2014/12/02 10:32:27 AGeissler
-- R1: The watchdog value is not correctly set, so that the user image could not
-- be loaded
-- M1: Changed param value from enable to value
--
-- Revision 1.1 2014/11/24 16:44:18 AGeissler
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
USE work.z126_01_pkg.all;
ENTITY z126_01_ru_ctrl_cyc5 IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(23 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END z126_01_ru_ctrl_cyc5;
ARCHITECTURE z126_01_ru_ctrl_cyc5_arch OF z126_01_ru_ctrl_cyc5 IS
TYPE ru_ctrl_states IS (IDLE,
START_UP_WAIT,
READ_CURR_STATE,
READ_RECONFIG_COND,
CHECK_STATE,
WRITE_CURR_STATE,
WRITE_BOOT_ADDR,
WRITE_WATCHDOG_VALUE,
WRITE_WATCHDOG_ENABLE,
RECONFIGURE,
FPGA_IMAGE,
FALLBACK_IMAGE,
WRITE_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FGPA_IMAGE
);
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE3, CYCLONE4);
SIGNAL ru_ctrl_state : ru_ctrl_states := IDLE; -- remote update control block state signal
-- registers
SIGNAL reconfig_cond : std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
SIGNAL curr_state : std_logic; -- current state of fpga
-- '1' => A FPGA image is loaded
-- '0' => Fallback FPGA image is loaded
SIGNAL boot_addr : std_logic_vector(23 DOWNTO 0); -- fpga boot addr (only write able in Factory Mode)
SIGNAL board_status : std_logic_vector(1 DOWNTO 0); -- current state of fpga
-- delayed busy signal
SIGNAL ru_ctrl_busy_q : std_logic := '0'; -- used for edge detection
SIGNAL ru_ctrl_busy_qq : std_logic := '0'; -- used for delayed edge detection (for generate wb ack)
-- wishbone ack
SIGNAL wbs_reg_ack_int : std_logic := '0'; -- wishbone acknowledge internal
-- reset
SIGNAL reset_timer_int : std_logic := '0'; -- reset watchdog timer (triggers on falling edge)
SIGNAL reset_timer_cnt : std_logic_vector(15 DOWNTO 0); -- counter for reset watchdog timer (the watchdog reset must
-- be active for at least 250 ns!!)
-- startup counter
SIGNAL startup_cnt : unsigned(7 DOWNTO 0); -- startup count for FPGA initialization
BEGIN
-- wishbone data out
wbs_reg_dat_o <= x"00" & boot_addr;
wbs_reg_ack <= wbs_reg_ack_int;
-- data to remote update controller
ru_ctrl_dat_in_proc : PROCESS (ru_ctrl_state, boot_addr) IS
BEGIN
CASE ru_ctrl_state IS
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
ru_ctrl_data_in <= boot_addr(23 DOWNTO 0);
WHEN WRITE_BOOT_ADDR =>
ru_ctrl_data_in <= LOAD_FPGA_IMAGE_ADR(23 DOWNTO 0);
WHEN WRITE_WATCHDOG_ENABLE =>
-- enable watchdog
ru_ctrl_data_in <= x"000001";
WHEN WRITE_WATCHDOG_VALUE =>
-- the first 12 bit are the highest 12 bit (of 29 bit) in the watchdog timer value
ru_ctrl_data_in <= x"000" & x"100"; -- => 33554432 clock cycle (2^25) => ~1 sec
WHEN WRITE_CURR_STATE =>
ru_ctrl_data_in <= x"000001"; -- write '1' to Configuration Mode (AnF)
WHEN OTHERS =>
ru_ctrl_data_in <= x"000000";
END CASE;
END PROCESS;
-- reset remote update controller when reconfiguration from FPGA Image
ru_ctrl_reset <= rst; -- reset remote update controller
ru_ctrl_reconfig <= '1' WHEN ru_ctrl_state = RECONFIGURE ELSE '0'; -- start reconfiguration
ru_ctrl_reset_timer <= reset_timer_int; -- reset watchdog timer
-- register out
reg_reconfig_cond <= reconfig_cond; -- reconfiguration trigger condition of last reconfiguration
reg_board_status <= board_status; -- gives information whether the loading process was successful or not
-- wishbone acknowledge and watchdog counter
ru_ctrl_wb_ack_and_wdog_cnt_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
wbs_reg_ack_int <= '0';
reset_timer_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
-- wishbone acknowledge
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' AND wbs_reg_ack_int = '0' THEN
wbs_reg_ack_int <= '1';
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' AND ru_ctrl_busy_qq = '1' AND ru_ctrl_busy_q = '0' THEN
-- read acknowledge when busy falling edge delayed by 1 cycle (1 cycle needed to write the register)
wbs_reg_ack_int <= '1';
ELSE
wbs_reg_ack_int <= '0';
END IF;
-- watchdog counter
IF ru_ctrl_state = FPGA_IMAGE THEN
reset_timer_cnt <= std_logic_vector(unsigned(reset_timer_cnt) + 1);
ELSE
reset_timer_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
ru_ctrl_cyc5_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
ru_ctrl_state <= IDLE;
ru_ctrl_param <= (OTHERS=>'0');
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ru_ctrl_busy_q <= '0';
ru_ctrl_busy_qq <= '0';
reconfig_cond <= (OTHERS=>'0');
curr_state <= '0';
board_status <= (OTHERS=>'0');
boot_addr <= (OTHERS=>'0');
startup_cnt <= (OTHERS=>'0');
reset_timer_int <= '0';
ELSIF falling_edge(clk) THEN
ru_ctrl_busy_q <= ru_ctrl_busy;
ru_ctrl_busy_qq <= ru_ctrl_busy_q;
-- board status register
IF (ru_ctrl_state = CHECK_STATE
AND ( reconfig_cond(3) = '1' -- CRC-Error
OR reconfig_cond(2) = '1' -- nStatus triggered
OR reconfig_cond(1) = '1' -- watchdog timeout
) ) THEN
board_status <= "10"; -- error while loading image (FPGA Fallback Image is loaded!)
ELSIF curr_state = '1' THEN
board_status <= "01"; -- FPGA Image loaded
END IF;
-- last reconfiguration condition register
IF ru_ctrl_state = READ_RECONFIG_COND AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- The register reconfig_cond shall have the same bit meaning as for Cyclone IV devices
reconfig_cond(0) <= ru_ctrl_data_out(2); -- runconfig_source - Configuration reset triggered from logic array.
reconfig_cond(1) <= ru_ctrl_data_out(4); -- wdtimer_source - User Watchdog Timer timeout.
reconfig_cond(2) <= ru_ctrl_data_out(1); -- nstatus_source - nSTATUS asserted by an external device as the result of an error
reconfig_cond(3) <= ru_ctrl_data_out(0); -- crcerror_source - CRC error during application configuration
reconfig_cond(4) <= ru_ctrl_data_out(3); -- nconfig_source - External configuration reset (nCONFIG) assertion.
END IF;
-- current state register
IF ru_ctrl_state = READ_CURR_STATE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
curr_state <= ru_ctrl_data_out(0); -- get data from remote update block
END IF;
-- boot address register
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
IF wbs_reg_sel(0) = '1' THEN
boot_addr(7 DOWNTO 2) <= wbs_reg_dat_i(7 DOWNTO 2);
END IF;
IF wbs_reg_sel(1) = '1' THEN
boot_addr(15 DOWNTO 8) <= wbs_reg_dat_i(15 DOWNTO 8);
END IF;
IF wbs_reg_sel(2) = '1' THEN
boot_addr(23 DOWNTO 16) <= wbs_reg_dat_i(23 DOWNTO 16);
END IF;
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FALLBACK AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Fallback Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FGPA_IMAGE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
END IF;
CASE ru_ctrl_state IS
WHEN IDLE =>
-- read current state of remote update controller
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
WHEN START_UP_WAIT =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF startup_cnt(startup_cnt'HIGH) = '1' THEN
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= (OTHERS=>'0');
ELSE
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= startup_cnt + 1;
END IF;
WHEN READ_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' AND curr_state = '0' THEN
-- read reconfiguration trigger condition source when in Factory Mode
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- the FPGA Image is successfully loaded
-- the reconfiguration condition can only be read in Factory Mode!
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to store data in curr_state register
-- disable remote update controller access
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read current state of remote update controller
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- read current state
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_RECONFIG_COND =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- check in which state is the FPGA
ru_ctrl_state <= CHECK_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read reconfiguration trigger condition source
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN CHECK_STATE =>
IF LOAD_FPGA_IMAGE = TRUE AND reconfig_cond(3) = '0' AND reconfig_cond(2) = '0' AND reconfig_cond(1) = '0' THEN
-- we are still in the FPGA Fallback Image and no error
-- start loading the FPGA Image (enable watchdog, write boot address and write current state)
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- the FPGA Fallback Image is loaded
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_WATCHDOG_VALUE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write watchdog time out value
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_WATCHDOG_ENABLE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_BOOT_ADDR =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write watchdog time out value and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN RECONFIGURE =>
-- start reconfiguration
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- fpga should be reconfigurated so the fsm should stay in this state
-- until the reconfiguration is finished
ru_ctrl_state <= RECONFIGURE;
WHEN FPGA_IMAGE =>
-- reset the watchdog timer if the FPGA Image is successfully loaded
-- (the watchdog timer is reset on falling edge of reset_timer_int)
-- if the watchdog expires the FPGA Fallback Image will be loaded again
reset_timer_int <= reset_timer_cnt(reset_timer_cnt'high);
IF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- start reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN FALLBACK_IMAGE =>
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
-- indirecte interface register access write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- enable watchdog and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- set watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FGPA_IMAGE =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- disable remote update controller access
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
-- coverage off
WHEN OTHERS =>
ru_ctrl_state <= IDLE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- coverage on
END CASE;
END IF;
END PROCESS;
END z126_01_ru_ctrl_cyc5_arch;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z000-00_src/Source/fpga_pkg_2.vhd
|
1
|
7970
|
---------------------------------------------------------------
-- Title : Package for FPGA family type
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 24/10/06
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--! \desid
--! \archid
--! \desbody
---------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: fpga_pkg_2.vhd,v $
-- Revision 1.8 2014/11/19 10:10:34 FLenhardt
-- R: No support for device family "Cyclone V"
-- M: Added device family CYCLONE5 to family_type
--
-- Revision 1.7 2014/06/03 11:34:30 CSchwark
-- R: no support for device family SmartFusion2
-- M: added device family SF2 to family_type
--
-- Revision 1.6 2013/02/11 14:33:42 FLenhardt
-- * added CYCLONE4E
-- * added FUNCTION altera_device_family
--
-- Revision 1.5 2012/10/24 09:04:32 MMiehling
-- added ARRIA2_GX, ARRIA2_GZ
--
-- Revision 1.4 2010/12/22 14:22:27 TWickleder
-- added CYCLONE4
--
-- Revision 1.3 2010/05/05 10:27:55 TWickleder
-- added FUNCTION get_fsrev and conv_chr_to_int
--
-- Revision 1.2 2009/02/17 11:37:35 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:54 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:53 FWombacher
-- added comments
--
-- Revision 1.1 2008/10/22 14:19:15 FWombacher
-- Initial Revision
--
-- Revision 1.2 2007/12/12 14:04:48 mernst
-- Added Cyclone III device to FPGA_PKG
--
-- Revision 1.1 2006/11/27 14:15:26 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE fpga_pkg_2 IS
TYPE family_type IS (NONE, CYCLONE, CYCLONE2, CYCLONE3, CYCLONE4, CYCLONE4E, CYCLONE5, FLEX, ACEX, A3P, ARRIA_GX, ARRIA2_GX, ARRIA2_GZ, SF2);
TYPE supported_family_types IS array (natural range <>) OF family_type; -- for more than one supported devices
SUBTYPE supported_family_type IS family_type; -- for exactly one supported device
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string;
-- CONSTANT fpga_family : family_type := CYCLONE3;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer;
END fpga_pkg_2;
PACKAGE BODY fpga_pkg_2 IS
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string IS
BEGIN
IF FPGA_FAMILY = CYCLONE THEN
RETURN "Cyclone";
ELSIF FPGA_FAMILY = CYCLONE2 THEN
RETURN "Cyclone II";
ELSIF FPGA_FAMILY = CYCLONE3 THEN
RETURN "Cyclone III";
ELSIF FPGA_FAMILY = CYCLONE4E THEN
RETURN "Cyclone IV E";
ELSIF FPGA_FAMILY = CYCLONE4 THEN
RETURN "Cyclone IV GX";
ELSIF FPGA_FAMILY = CYCLONE5 THEN
RETURN "Cyclone V";
ELSIF FPGA_FAMILY = ARRIA_GX THEN
RETURN "Arria GX";
ELSIF FPGA_FAMILY = ARRIA2_GX THEN
RETURN "Arria II GX";
ELSIF FPGA_FAMILY = ARRIA2_GZ THEN
RETURN "Arria II GZ";
--ELSIF FPGA_FAMILY = THEN
-- RETURN "";
ELSE
ASSERT FALSE REPORT "UNSUPPORTED ALTERA DEVICE" SEVERITY FAILURE;
RETURN "";
END IF;
END altera_device_family;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
FOR i IN supported_devices'range LOOP
IF(device = supported_devices(i)) THEN
no_valid := FALSE;
ELSE
no_valid := no_valid;
END IF;
END LOOP;
RETURN no_valid;
END no_valid_device;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
IF(device = supported_device) THEN
no_valid := FALSE;
ELSE
no_valid := TRUE;
END IF;
RETURN no_valid;
END no_valid_device;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector IS
VARIABLE minor_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE major_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE scan_str : string(7 DOWNTO 1) := " ";
VARIABLE maj_str : string(3 DOWNTO 1) := " ";
VARIABLE min_str : string(3 DOWNTO 1) := " ";
VARIABLE fsrev_found : boolean := FALSE;
VARIABLE next_is_rev : boolean := FALSE;
VARIABLE major_found : boolean := FALSE;
VARIABLE minor_found : boolean := FALSE;
BEGIN
FOR i IN fsrev_str'range LOOP
scan_str := scan_str(6 DOWNTO 1) & fsrev_str(i); --shift string in
IF(scan_str = "%FSREV ") THEN fsrev_found := TRUE;
ELSIF(fsrev_found AND NOT next_is_rev) THEN
IF(scan_str(1) = ' ') THEN next_is_rev := TRUE; END IF;
ELSIF(next_is_rev AND NOT major_found) THEN
IF(scan_str(1) = '.') THEN major_found := TRUE; ELSE maj_str := maj_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(major_found AND NOT minor_found) THEN
IF(scan_str(1) = ' ') THEN minor_found := TRUE; ELSE min_str := min_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(minor_found) THEN exit;
END IF;
END LOOP;
minor_no := conv_std_logic_vector(100*conv_chr_to_int(min_str(3))+10*conv_chr_to_int(min_str(2))+conv_chr_to_int(min_str(1)),8);
major_no := conv_std_logic_vector(100*conv_chr_to_int(maj_str(3))+10*conv_chr_to_int(maj_str(2))+conv_chr_to_int(maj_str(1)),8);
RETURN (major_no&minor_no);
END get_fsrev;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer IS
VARIABLE num : integer := 0;
BEGIN
CASE char IS
WHEN '0' => num := 0;
WHEN '1' => num := 1;
WHEN '2' => num := 2;
WHEN '3' => num := 3;
WHEN '4' => num := 4;
WHEN '5' => num := 5;
WHEN '6' => num := 6;
WHEN '7' => num := 7;
WHEN '8' => num := 8;
WHEN '9' => num := 9;
WHEN OTHERS => num := 0;
END CASE;
RETURN num;
END conv_chr_to_int;
END;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z126-01_src/Source/z126_01_wb_if_arbiter.vhd
|
1
|
9810
|
---------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
---------------------------------------------------------------
-- File : z126_01_wb_if_arbiter.vhd
-- Author : ....
-- Email : ....
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created :
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : Quartus II
---------------------------------------------------------------
-- Description :
-- Master # 0 1
-- Slave : 0 1 1
-- Master 0 = 1 connection(s)
-- Master 1 = 1 connection(s)
-- Slave 0 = 2 connection(s)
--
-- This module is derived from the 16z100-
-- It contaions an additional arbitration of control
-- signals for the z126_01_wb2pasmi.vhd module in the 16z126-01
-- design.
---------------------------------------------------------------
-- Hierarchy:
--
-- z126_01_wb_pkg.vhd
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_if_arbiter.vhd,v $
-- Revision 1.1 2014/03/03 17:49:57 AGeissler
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.z126_01_pkg.ALL;
USE work.z126_01_wb_pkg.ALL;
ENTITY z126_01_wb_if_arbiter IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- master 0 interface
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic;
-- wb2pasmi master 0 control signals
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
-- master 1 interface
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic;
-- wb2pasmi master 1 control signals
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
-- slave 0 interface
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
-- wb2pasmi slave 0 control signals
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END z126_01_wb_if_arbiter;
ARCHITECTURE z126_01_wb_if_arbiter_arch OF z126_01_wb_if_arbiter IS
-- COMPONENT DECLARATIONS
COMPONENT z126_01_switch_fab_2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic;
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END COMPONENT;
-- synthesis translate_off
COMPONENT z126_01_wbmon IS
GENERIC (
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
bte : IN std_logic_vector(1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic
);
END COMPONENT;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL wbs_0_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_0_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmo_1_cyc_s : std_logic;
BEGIN
wbsi_0 <= wbsi_0_int;
wbsi_0_cyc <= wbsi_0_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
-- no data multiplexer for master #0 is needed, because of connection to one slave only
wbmi_0_int.dat <= wbso_0.dat;
wbmi_0_int.ack <= wbs_0_ack(0);
wbmi_0_int.err <= wbs_0_err(0);
-- no data multiplexer for master #1 is needed, because of connection to one slave only
wbmi_1_int.dat <= wbso_0.dat;
wbmi_1_int.ack <= wbs_0_ack(1);
wbmi_1_int.err <= wbs_0_err(1);
-- sf for slave #0:
sf_0: z126_01_switch_fab_2
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc,
ack_0 => wbs_0_ack(0),
err_0 => wbs_0_err(0),
wbo_1 => wbmo_1,
cyc_1 => wbmo_1_cyc,
ack_1 => wbs_0_ack(1),
err_1 => wbs_0_err(1),
-- slave bus:
wbo_slave => wbso_0,
wbi_slave => wbsi_0_int,
wbi_slave_cyc => wbsi_0_cyc_int,
-- wb2pasmi control signals
ctrlmo_0 => ctrlmo_0,
ctrlmi_0 => ctrlmi_0,
ctrlmo_1 => ctrlmo_1,
ctrlmi_1 => ctrlmi_1,
ctrlso_0 => ctrlso_0,
ctrlsi_0 => ctrlsi_0
);
-- synthesis translate_off
wbmo_0_cyc_s <= '1' WHEN wbmo_0_cyc = '0' ELSE '1';
wbm_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_0.adr,
sldat_i => wbmo_0.dat,
sldat_o => wbmi_0_int.dat,
cti => wbmo_0.cti,
bte => wbmo_0.bte,
sel => wbmo_0.sel,
cyc => wbmo_0_cyc_s,
stb => wbmo_0.stb,
ack => wbmi_0_int.ack,
err => wbmi_0_int.err,
we => wbmo_0.we
);
wbmo_1_cyc_s <= '1' WHEN wbmo_1_cyc = '0' ELSE '1';
wbm_1: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_1.adr,
sldat_i => wbmo_1.dat,
sldat_o => wbmi_1_int.dat,
cti => wbmo_1.cti,
bte => wbmo_1.bte,
sel => wbmo_1.sel,
cyc => wbmo_1_cyc_s,
stb => wbmo_1.stb,
ack => wbmi_1_int.ack,
err => wbmi_1_int.err,
we => wbmo_1.we
);
wbs_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbs_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_0_int.adr,
sldat_i => wbsi_0_int.dat,
sldat_o => wbso_0.dat,
cti => wbsi_0_int.cti,
bte => wbsi_0_int.bte,
sel => wbsi_0_int.sel,
cyc => wbsi_0_cyc_int,
stb => wbsi_0_int.stb,
ack => wbso_0.ack,
err => wbso_0.err,
we => wbsi_0_int.we
);
-- synthesis translate_on
END z126_01_wb_if_arbiter_arch;
|
gpl-3.0
|
iocoder/graduation
|
hardware/vga/vga.vhd
|
1
|
12584
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga is
Port ( CLK : in STD_LOGIC; -- 50MHz clock input
-- System Bus
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
RDY : out STD_LOGIC := '0';
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
-- VGA Port
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end vga;
architecture Structural of vga is
component clkgen is
Port (CLK : in STD_LOGIC;
CLK_56MHz : out STD_LOGIC;
CLK_50MHz : out STD_LOGIC;
CLK_28MHz : out STD_LOGIC;
CLK_25MHz : out STD_LOGIC;
CLK_12MHz : out STD_LOGIC);
end component;
component graphics is
Port ( CLK50 : in STD_LOGIC;
CLK12 : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
VBLANK : in STD_LOGIC;
VRAM0Read : out STD_LOGIC;
VRAM1Read : out STD_LOGIC;
VRAM2Read : out STD_LOGIC;
VRAM3Read : out STD_LOGIC;
VRAM4Read : out STD_LOGIC;
VRAM0Write : out STD_LOGIC;
VRAM1Write : out STD_LOGIC;
VRAM2Write : out STD_LOGIC;
VRAM3Write : out STD_LOGIC;
VRAM4Write : out STD_LOGIC;
VRAMAddr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAMDataOut : out STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : out STD_LOGIC;
SprWR : out STD_LOGIC;
SprAddr : out STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : out STD_LOGIC;
PalWR : out STD_LOGIC;
PalAddr : out STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
ROW_BASE : out STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : out STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : out STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
PPU_HSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_VSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
MODE : out STD_LOGIC);
end component;
component vgaram is
Port (CLK : in STD_LOGIC;
-- sequencer port:
SeqReadEnable : in STD_LOGIC;
SeqAddr : in STD_LOGIC_VECTOR (10 downto 0);
SeqDataOut : out STD_LOGIC_VECTOR ( 8 downto 0) := "000000000";
-- GU port:
GUReadEnable : in STD_LOGIC;
GUWriteEnable : in STD_LOGIC;
GUAddr : in STD_LOGIC_VECTOR (10 downto 0);
GUDataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
GUDataOut : out STD_LOGIC_VECTOR ( 8 downto 0));
end component;
component sequencer is
Port (CLK56 : in STD_LOGIC;
CLK28 : in STD_LOGIC;
SE : in STD_LOGIC;
MODE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC;
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC;
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC;
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC;
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0));
end component;
component dac is
Port (DE : in STD_LOGIC;
MODE : in STD_LOGIC;
COLOR : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component crt is
Port (CLK : in STD_LOGIC;
MODE : in STD_LOGIC;
VBLANK : out STD_LOGIC;
HS : out STD_LOGIC := '0';
VS : out STD_LOGIC := '0';
SE : out STD_LOGIC := '0';
DE : out STD_LOGIC := '0';
X : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
Y : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
B9 : out STD_LOGIC := '0');
end component;
signal CLK_56MHz : STD_LOGIC;
signal CLK_50MHz : STD_LOGIC;
signal CLK_28MHz : STD_LOGIC;
signal CLK_25MHz : STD_LOGIC;
signal CLK_12MHz : STD_LOGIC;
signal VRAM0Read : STD_LOGIC;
signal VRAM1Read : STD_LOGIC;
signal VRAM2Read : STD_LOGIC;
signal VRAM3Read : STD_LOGIC;
signal VRAM4Read : STD_LOGIC;
signal VRAM0Write : STD_LOGIC;
signal VRAM1Write : STD_LOGIC;
signal VRAM2Write : STD_LOGIC;
signal VRAM3Write : STD_LOGIC;
signal VRAM4Write : STD_LOGIC;
signal VRAMAddrFromGU : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM0DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM1DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM2DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM3DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM4DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAMDataFromGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal ROW_BASE : STD_LOGIC_VECTOR ( 7 downto 0);
signal CURSOR_ROW : STD_LOGIC_VECTOR ( 7 downto 0);
signal CURSOR_COL : STD_LOGIC_VECTOR ( 7 downto 0);
signal MODE : STD_LOGIC;
signal PPU_CTRL : STD_LOGIC_VECTOR (15 downto 0);
signal PPU_HSCR : STD_LOGIC_VECTOR ( 7 downto 0);
signal PPU_VSCR : STD_LOGIC_VECTOR ( 7 downto 0);
signal VBLANK : STD_LOGIC;
signal SE : STD_LOGIC;
signal DE : STD_LOGIC;
signal X : STD_LOGIC_VECTOR (15 downto 0);
signal Y : STD_LOGIC_VECTOR (15 downto 0);
signal B9 : STD_LOGIC;
signal COLOR : STD_LOGIC_VECTOR ( 5 downto 0);
signal VRAM0ReadEnable : STD_LOGIC;
signal VRAM0ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM0ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM1ReadEnable : STD_LOGIC;
signal VRAM1ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM1ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM2ReadEnable : STD_LOGIC;
signal VRAM2ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM2ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM3ReadEnable : STD_LOGIC;
signal VRAM3ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM3ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM4ReadEnable : STD_LOGIC;
signal VRAM4ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM4ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal SprRD : STD_LOGIC;
signal SprWR : STD_LOGIC;
signal SprAddr : STD_LOGIC_VECTOR ( 7 downto 0);
signal SprDataIn : STD_LOGIC_VECTOR ( 7 downto 0);
signal SprDataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal PalRD : STD_LOGIC;
signal PalWR : STD_LOGIC;
signal PalAddr : STD_LOGIC_VECTOR ( 4 downto 0);
signal PalDataIn : STD_LOGIC_VECTOR ( 7 downto 0);
signal PalDataOut : STD_LOGIC_VECTOR ( 7 downto 0);
begin
u0: clkgen port map (CLK, CLK_56MHz, CLK_50MHz, CLK_28MHz,
CLK_25MHz, CLK_12MHz);
u1: graphics port map (CLK, CLK_12MHz, CS, RW, A, Din, Dout,
INT, IAK, VBLANK,
VRAM0Read, VRAM1Read, VRAM2Read,
VRAM3Read, VRAM4Read,
VRAM0Write, VRAM1Write, VRAM2Write,
VRAM3Write, VRAM4Write,
VRAMAddrFromGU,
VRAM0DataToGU, VRAM1DataToGU, VRAM2DataToGU,
VRAM3DataToGU, VRAM4DataToGU, VRAMDataFromGU,
SprRD, SprWR, SprAddr, SprDataOut, SprDataIn,
PalRD, PalWR, PalAddr, PalDataOut, PalDataIn,
ROW_BASE, CURSOR_ROW, CURSOR_COL,
PPU_CTRL, PPU_HSCR, PPU_VSCR, MODE);
u2: vgaram port map (CLK_56MHz,
VRAM0ReadEnable, VRAM0ReadAddr, VRAM0ReadData,
VRAM0Read, VRAM0Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM0DataToGU);
u3: vgaram port map (CLK_56MHz,
VRAM1ReadEnable, VRAM1ReadAddr, VRAM1ReadData,
VRAM1Read, VRAM1Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM1DataToGU);
u4: vgaram port map (CLK_56MHz,
VRAM2ReadEnable, VRAM2ReadAddr, VRAM2ReadData,
VRAM2Read, VRAM2Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM2DataToGU);
u5: vgaram port map (CLK_56MHz,
VRAM3ReadEnable, VRAM3ReadAddr, VRAM3ReadData,
VRAM3Read, VRAM3Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM3DataToGU);
u6: vgaram port map (CLK_56MHz,
VRAM4ReadEnable, VRAM4ReadAddr, VRAM4ReadData,
VRAM4Read, VRAM4Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM4DataToGU);
u7: sequencer port map (CLK_56MHz, CLK_28MHz, SE,
MODE, ROW_BASE, CURSOR_ROW, CURSOR_COL,
PPU_CTRL, PPU_HSCR, PPU_VSCR,
X, Y, B9,
VRAM0ReadEnable, VRAM0ReadAddr, VRAM0ReadData,
VRAM1ReadEnable, VRAM1ReadAddr, VRAM1ReadData,
VRAM2ReadEnable, VRAM2ReadAddr, VRAM2ReadData,
VRAM3ReadEnable, VRAM3ReadAddr, VRAM3ReadData,
VRAM4ReadEnable, VRAM4ReadAddr, VRAM4ReadData,
SprRD, SprWR, SprAddr, SprDataIn, SprDataOut,
PalRD, PalWR, PalAddr, PalDataIn, PalDataOut,
COLOR);
u8: dac port map (DE, MODE, COLOR, R, G, B);
u9: crt port map (CLK_28MHz, MODE, VBLANK, HS, VS, SE, DE, X, Y, B9);
end Structural;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z002-01_src/Source/vme_dma.vhd
|
1
|
24988
|
--------------------------------------------------------------------------------
-- Title : DMA for VME Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : dma.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 24/06/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The vme core has a DMA controller for high performance data transfers between
-- the SRAM, PCI space and VMEbus. It is operated through a series of registers
-- that control the source/destination for the data, length of the transfer and
-- the transfer protocol (A24 or A32) to be used. These registers are not
-- directly accessible, but they will be loaded with the content of the Buffer
-- Descriptor(s) located in the local SRAM.
-- One buffer descriptor may be linked to the next buffer descriptor, such that
-- when the DMA has completed the operations described by one buffer descriptor,
-- it automatically moves on to the next buffer descriptor in the local SRAM
-- list. The last buffer descriptor is reached, when the DMA_NULL bit is set in
-- the corresponding buffer descriptor. The maximum number of linked buffer
-- descriptors is 112.
-- The DMA supports interrupt assertion when all specified buffer descriptors
-- are processed (signaled via dma_irq to PCIe, see DMA_IEN).
-- The DMA controller is able to transfer data from the SRAM, PCI space and
-- VMEbus to each other. For this reason source and/or destination address can
-- be incremented or not depending on the settings. The source and destination
-- address must be 8-byte aligned to each other.
-- The scatter-gather list is located in the local SRAM area, so a DMA can also
-- be initiated by an external VME master by accessing the SRAM via A24/A32
-- slave and the DMA Status Register via A16 slave.
-- If transfers to PCI space has to be done, the used memory space must be
-- allocated for this function in order to prevent data mismatch!
-- If DMA functionality is used, the entire local SRAM cannot be used by other
-- functions, because the buffer descriptors are located at the end of this!
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_mstr
-- vme_dma_slv
-- vme_dma_arbiter
-- vme_dma_du
-- vme_dma_au
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_dma.vhd,v $
-- Revision 1.2 2013/09/12 08:45:30 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.1 2012/03/29 10:14:48 MMiehling
-- Initial Revision
--
-- Revision 1.4 2006/05/18 14:02:16 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:20 mmiehling
-- Initial Revision
--
-- Revision 1.3 2004/08/13 15:41:08 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:15 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:46 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
irq_o : OUT std_logic;
-- vme_du
dma_sta : IN std_logic_vector(9 DOWNTO 0);
clr_dma_en : OUT std_logic;
set_dma_err : OUT std_logic;
dma_act_bd : OUT std_logic_vector(7 DOWNTO 4);
-- wb-slave
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
sel_i : IN std_logic_vector(3 DOWNTO 0);
adr_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
-- wb-master
stb_o : OUT std_logic;
ack_i : IN std_logic;
we_o : OUT std_logic;
cti : OUT std_logic_vector(2 DOWNTO 0);
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
err_i : IN std_logic;
cyc_o_sram : OUT std_logic;
cyc_o_vme : OUT std_logic;
cyc_o_pci : OUT std_logic;
sel_o : OUT std_logic_vector(3 DOWNTO 0);
adr_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0)
);
END vme_dma;
ARCHITECTURE vme_dma_arch OF vme_dma IS
COMPONENT vme_dma_arbiter
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- vme_dma_slv
slv_req : IN std_logic;
slv_ack : OUT std_logic;
-- vme_dma_mstr
mstr_req : IN std_logic;
mstr_ack : OUT std_logic;
-- result
arbit_slv : OUT std_logic -- if set, vme_dma_slv has access and vica verse
);
END COMPONENT;
COMPONENT vme_dma_slv
PORT (
rst : IN std_logic;
clk : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
slv_req : OUT std_logic;
slv_ack : IN std_logic
);
END COMPONENT;
COMPONENT vme_dma_au
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_signals
adr_o : OUT std_logic_vector(31 DOWNTO 0); -- adress for wb-bus
sel_o : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for wb_bus
we_o : OUT std_logic; -- write/read
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
cyc_o_sram : OUT std_logic; -- chip select for sram
cyc_o_pci : OUT std_logic; -- chip select for pci
cyc_o_vme : OUT std_logic; -- chip select for vme
stb_o : IN std_logic; -- request signal for cyc switching
-- fifo
fifo_empty : in std_logic;
fifo_full : in std_logic;
-- vme_dma_mstr
sour_dest : IN std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : IN std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : IN std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : OUT std_logic; -- if all data from one bd was read and stored in the fifo
load_cnt : IN std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : OUT std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : out std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : out std_logic; -- if all data from one bd was read and stored in the fifo
clr_dma_act_bd : IN std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
dma_act_bd : OUT std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
dma_dest_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : IN std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : IN std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : IN std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : IN std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0) -- size of data package
);
END COMPONENT;
COMPONENT vme_dma_du
PORT (
rst : IN std_logic;
clk : IN std_logic;
dma_sta : IN std_logic_vector(9 DOWNTO 0);
irq_o : OUT std_logic; -- irq for cpu; asserted when done or error (if enabled)
arbit_slv : IN std_logic; -- if set, dma_slv has access and vica verse
slv_ack : IN std_logic; -- if set, write from slave side will be done
mstr_ack : IN std_logic; -- if set, write from master side will be done
-- slave signals
adr_i : IN std_logic_vector(6 DOWNTO 2);
sel_i : IN std_logic_vector(3 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
we_i : IN std_logic;
ack_o : IN std_logic;
-- wb_master singals
adr_o : IN std_logic_vector(6 DOWNTO 2);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vme_dma_au
dma_act_bd : IN std_logic_vector(7 DOWNTO 4); -- active bd number
dma_dest_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : OUT std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : OUT std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : OUT std_logic; -- indicates if source adress should be incremented
inc_dest : OUT std_logic; -- indicates if destination adress should be incremented
dma_size : OUT std_logic_vector(15 DOWNTO 0); -- size of data package
clr_dma_act_bd : OUT std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- dma_mstr
set_dma_err : IN std_logic; -- sets dma error bit if vme error
clr_dma_en : IN std_logic; -- clears dma en bit if dma_mstr has done
dma_en : OUT std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : OUT std_logic; -- indicates the last bd
en_mstr_dat_i_reg : IN std_logic -- enable for data in
);
END COMPONENT;
COMPONENT vme_dma_mstr
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_master_bus
stb_o : OUT std_logic; -- request for wb_mstr_bus
ack_i : IN std_logic; -- acknoledge from wb_mstr_bus
err_i : IN std_logic; -- error answer from slave
cti : OUT std_logic_vector(2 DOWNTO 0);
-- fifo
fifo_empty : IN std_logic; -- indicates that no more data is available
fifo_full : in std_logic; -- indicates that no more data can be stored in fifo
fifo_almost_full : IN std_logic; -- indicates that only one data can be stored in the fifo
fifo_almost_empty : IN std_logic; -- indicates that only one data is stored in the fifo
fifo_wr : OUT std_logic; -- if asserted, fifo will be filled with another data
fifo_rd : OUT std_logic; -- if asserted, data will be read out from fifo
-- vme_dma_au
sour_dest : OUT std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : OUT std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : OUT std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
dma_act_bd : IN std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
load_cnt : OUT std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
we_o_int : IN std_logic;
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
set_dma_err : OUT std_logic; -- sets dma error bit if vme error
clr_dma_en : OUT std_logic; -- clears dma en bit if dma_mstr has done
dma_en : IN std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : IN std_logic; -- indicates the last bd
en_mstr_dat_i_reg : OUT std_logic; -- enable for data in
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0); -- size of data package
-- arbiter
mstr_req : OUT std_logic -- request for internal register access
);
END COMPONENT;
COMPONENT vme_dma_fifo
PORT (
rst : IN std_logic;
clk : IN std_logic;
fifo_clr : IN std_logic;
fifo_wr : IN std_logic;
fifo_rd : IN std_logic;
fifo_dat_i : IN std_logic_vector(31 DOWNTO 0);
fifo_dat_o : OUT std_logic_vector(31 DOWNTO 0);
fifo_almost_full : OUT std_logic;
fifo_almost_empty : OUT std_logic;
fifo_full : OUT std_logic;
fifo_empty : OUT std_logic
);
END COMPONENT;
-- fifo
SIGNAL fifo_almost_full : std_logic;
SIGNAL fifo_almost_empty : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
-- slv
SIGNAL slv_req : std_logic;
SIGNAL ack_o_int : std_logic;
-- arbiter
SIGNAL slv_ack : std_logic;
SIGNAL mstr_ack : std_logic;
SIGNAL arbit_slv : std_logic;
-- mstr
SIGNAL fifo_wr : std_logic;
SIGNAL fifo_rd : std_logic;
SIGNAL sour_dest : std_logic;
SIGNAL inc_adr : std_logic;
SIGNAL get_bd : std_logic;
SIGNAL load_cnt : std_logic;
SIGNAL set_dma_err_int : std_logic;
SIGNAL clr_dma_en_int : std_logic;
SIGNAL en_mstr_dat_i_reg : std_logic;
SIGNAL mstr_req : std_logic;
SIGNAL stb_o_int : std_logic;
-- du
SIGNAL dma_dest_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_dest_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_vme_am : std_logic_vector(4 DOWNTO 0);
SIGNAL blk_sgl : std_logic;
SIGNAL inc_sour : std_logic;
SIGNAL inc_dest : std_logic;
SIGNAL dma_size : std_logic_vector(15 DOWNTO 0);
SIGNAL start_dma : std_logic;
SIGNAL clr_fifo : std_logic;
SIGNAL dma_en : std_logic;
SIGNAL dma_null : std_logic;
SIGNAL clr_dma_act_bd : std_logic;
-- au
SIGNAL adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL reached_size : std_logic;
SIGNAL almost_reached_size : std_logic;
SIGNAL dma_act_bd_int : std_logic_vector(7 DOWNTO 2);
SIGNAL boundary : std_logic;
SIGNAL almost_boundary : std_logic;
SIGNAL we_o_int : std_logic;
BEGIN
adr_o <= adr_o_int;
ack_o <= ack_o_int;
stb_o <= stb_o_int;
we_o <= we_o_int;
clr_dma_en <= clr_dma_en_int;
set_dma_err <= set_dma_err_int;
dma_act_bd <= dma_act_bd_int(7 DOWNTO 4);
clr_fifo <= start_dma;
start_dma <= dma_sta(8);
dma_arb: vme_dma_arbiter
PORT MAP (
rst => rst ,
clk => clk ,
slv_req => slv_req ,
slv_ack => slv_ack ,
mstr_req => mstr_req ,
mstr_ack => mstr_ack ,
arbit_slv => arbit_slv
);
dma_slv: vme_dma_slv
PORT MAP (
rst => rst ,
clk => clk ,
stb_i => stb_i ,
ack_o => ack_o_int ,
we_i => we_i ,
cyc_i => cyc_i ,
slv_req => slv_req ,
slv_ack => slv_ack
);
dma_au: vme_dma_au
PORT MAP (
rst => rst ,
clk => clk ,
adr_o => adr_o_int ,
sel_o => sel_o ,
tga_o => tga_o,
we_o => we_o_int ,
boundary => boundary,
almost_boundary => almost_boundary,
cyc_o_sram => cyc_o_sram ,
cyc_o_pci => cyc_o_pci ,
cyc_o_vme => cyc_o_vme ,
stb_o => stb_o_int,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
clr_dma_act_bd => clr_dma_act_bd,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
load_cnt => load_cnt ,
start_dma => start_dma ,
dma_act_bd => dma_act_bd_int ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device,
dma_dest_device => dma_dest_device,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size
);
dma_du: vme_dma_du
PORT MAP (
rst => rst ,
clk => clk ,
dma_sta => dma_sta,
irq_o => irq_o ,
arbit_slv => arbit_slv ,
slv_ack => slv_ack ,
mstr_ack => mstr_ack ,
ack_o => ack_o_int ,
we_i => we_i,
adr_i => adr_i(6 DOWNTO 2) ,
sel_i => sel_i ,
slv_dat_i => slv_dat_i ,
slv_dat_o => slv_dat_o ,
clr_dma_act_bd => clr_dma_act_bd,
adr_o => adr_o_int(6 DOWNTO 2) ,
mstr_dat_i => mstr_dat_i ,
dma_act_bd => dma_act_bd_int(7 DOWNTO 4) ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device ,
dma_dest_device => dma_dest_device ,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size ,
-- start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg
);
dma_mstr: vme_dma_mstr
PORT MAP (
rst => rst ,
clk => clk ,
stb_o => stb_o_int ,
ack_i => ack_i ,
err_i => err_i ,
cti => cti,
fifo_empty => fifo_empty ,
fifo_full => fifo_full,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty ,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
boundary => boundary,
almost_boundary => almost_boundary,
we_o_int => we_o_int,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
dma_act_bd => dma_act_bd_int ,
load_cnt => load_cnt ,
start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
inc_sour => inc_sour,
inc_dest => inc_dest,
dma_size => dma_size,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg ,
mstr_req => mstr_req
);
dma_fifo: vme_dma_fifo
PORT MAP (
rst => rst ,
clk => clk ,
fifo_clr => clr_fifo,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
fifo_dat_i => mstr_dat_i ,
fifo_dat_o => mstr_dat_o ,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty,
fifo_full => fifo_full ,
fifo_empty => fifo_empty
);
END vme_dma_arch;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z002-01_src/Source/vme_dma_fifo.vhd
|
1
|
5964
|
--------------------------------------------------------------------------------
-- Title : FIFO for DMA
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_fifo.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 18/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of a fifo 256 x 32bit with logic.
-- A almost full and almost empty bit are generated.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_dma_fifo.vhd,v $
-- Revision 1.1 2012/03/29 10:14:43 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:02:24 MMiehling
-- changed fifo depth from 16 to 64
--
-- Revision 1.1 2005/10/28 17:52:25 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:19:41 mmiehling
-- changed sclr to aclr
--
-- Revision 1.3 2004/08/13 15:41:14 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:24 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:51 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY vme_dma_fifo IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
fifo_clr : IN std_logic;
fifo_wr : IN std_logic;
fifo_rd : IN std_logic;
fifo_dat_i : IN std_logic_vector(31 DOWNTO 0);
fifo_dat_o : OUT std_logic_vector(31 DOWNTO 0);
fifo_almost_full : OUT std_logic; -- two words can be written before fifo is full
fifo_almost_empty : OUT std_logic; -- one word is in fifo before empty
fifo_full : OUT std_logic; -- fifo is full
fifo_empty : OUT std_logic -- fifo is empty
);
END vme_dma_fifo;
ARCHITECTURE vme_dma_fifo_arch OF vme_dma_fifo IS
constant CONST_FIFO_SIZE : integer := 512;
SIGNAL fifo_usedw : std_logic_vector(8 DOWNTO 0);
SIGNAL low_level : std_logic:='0';
SIGNAL dat_o : std_logic_vector(31 DOWNTO 0);
BEGIN
PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
fifo_almost_full <= '0';
fifo_full <= '0';
fifo_empty <= '1';
fifo_almost_empty <= '0';
fifo_dat_o <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
-- indicate whether two words can be written to fifo before full
IF fifo_usedw = conv_std_logic_vector(CONST_FIFO_SIZE-3, 9) AND fifo_wr = '1' THEN
fifo_almost_full <= '1';
ELSIF fifo_rd = '1' THEN
fifo_almost_full <= '0';
END IF;
-- indicate whether fifo is full
IF fifo_usedw = conv_std_logic_vector(CONST_FIFO_SIZE-2, 9) AND fifo_wr = '1' THEN
fifo_full <= '1';
ELSIF fifo_rd = '1' THEN
fifo_full <= '0';
END IF;
-- indicate whether fifo is empty
IF fifo_usedw = conv_std_logic_vector(1, 9) AND fifo_rd = '1' THEN
fifo_empty <= '1';
ELSIF fifo_wr = '1' THEN
fifo_empty <= '0';
END IF;
-- indicate whether one word can be read before empty
IF fifo_usedw = conv_std_logic_vector(2, 9) AND fifo_rd = '1' THEN
fifo_almost_empty <= '1';
ELSIF fifo_usedw = conv_std_logic_vector(0, 9) AND fifo_wr = '1' THEN -- if fifo is empty an one word gets written
fifo_almost_empty <= '1';
ELSIF fifo_wr = '1' OR fifo_rd = '1' THEN
fifo_almost_empty <= '0';
END IF;
-- register for convertion of look-ahead fifo to normal fifo behaviour
IF fifo_clr = '1' THEN
fifo_dat_o <= (OTHERS => '0');
ELSIF fifo_rd = '1' THEN
fifo_dat_o <= dat_o;
END IF;
END IF;
END PROCESS;
fifo: scfifo --256x32bit
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Cyclone IV GX",
lpm_numwords => 512,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 32,
lpm_widthu => 9,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON")
PORT MAP (
aclr => fifo_clr,
clock => clk,
data => fifo_dat_i,
rdreq => fifo_rd,
wrreq => fifo_wr,
usedw => fifo_usedw,
q => dat_o);
END vme_dma_fifo_arch;
|
gpl-3.0
|
iocoder/graduation
|
hardware/vga/ppuseq.vhd
|
1
|
18456
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ppuseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0) := "000000");
end ppuseq;
architecture Dataflow of ppuseq is
signal phase : integer := 0;
signal counter : integer := 0;
signal PatAddr1 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr2 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatRead : STD_LOGIC := '0';
signal PatData : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
-- sprites
type sprites_t is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
signal sprites : sprites_t := (others => x"00");
signal sprindex : integer := 0;
signal sprdata : STD_LOGIC_VECTOR (7 downto 0) := x"00";
type sprcache_t is array (0 to 7) of STD_LOGIC_VECTOR (31 downto 0);
signal sprcache : sprcache_t := (others => x"00000000");
signal lastSprRD : STD_LOGIC := '0';
signal lastSprWR : STD_LOGIC := '0';
-- palette
type palette_t is array (0 to 15) of STD_LOGIC_VECTOR (5 downto 0);
signal PatPal : palette_t := (others => "000000"); -- pattern palette
signal SprPal : palette_t := (others => "000000"); -- sprite palette
signal lastPalRD : STD_LOGIC := '0';
signal lastPalWR : STD_LOGIC := '0';
attribute ram_style: string;
attribute ram_style of sprites : signal is "block";
-- attribute ram_style of sprcache : signal is "block";
begin
PatAddr <= PatAddr1 when phase = 2 else PatAddr2;
VRAM0Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM1Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM2Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM3Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM0Read <= (NOT PatAddr(12));
VRAM1Read <= (NOT PatAddr(12));
VRAM2Read <= ( PatAddr(12));
VRAM3Read <= ( PatAddr(12));
PatData( 7 downto 0) <= VRAM0Data or VRAM2Data;
PatData(15 downto 8) <= VRAM1Data or VRAM3Data;
process (CLK)
variable tcolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable scolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable ashift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable bshift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable n : integer := 0;
variable m : integer := 0;
variable sstate : integer := 0;
variable cur_y : integer := 0;
variable spr_y : integer := 0;
variable max_y : integer := 0;
variable row : integer := 0;
variable cur_x : integer := 0;
variable spr0x : integer := 0;
variable spr1x : integer := 0;
variable spr2x : integer := 0;
variable spr3x : integer := 0;
variable spr4x : integer := 0;
variable spr5x : integer := 0;
variable spr6x : integer := 0;
variable spr7x : integer := 0;
variable offset : integer := 0;
variable sprindx : integer := 0;
variable V : STD_LOGIC := '0'; -- vert. nametable
variable H : STD_LOGIC := '0'; -- hori. nametable
variable VT : STD_LOGIC_VECTOR ( 4 downto 0); -- vert. tile index
variable HT : STD_LOGIC_VECTOR ( 4 downto 0); -- hori. tile index
variable FV : STD_LOGIC_VECTOR ( 2 downto 0); -- vert. pixel index
variable FH : STD_LOGIC_VECTOR ( 2 downto 0); -- hori. pixel index
begin
if (CLK = '1' and CLK'event ) then
-- sprite processing
if (SE = '0' or phase = 0 or phase = 4) then
-- make use of hblank time by loading
if (n < 64 and m < 8) then
if (sstate = 0) then
-- current sprite in range?
spr_y := conv_integer(unsigned(sprdata))+1;
if (PPU_CTRL(5) = '0') then
max_y := spr_y + 8;
else
max_y := spr_y + 16;
end if;
if (cur_y >= spr_y and cur_y < max_y) then
-- in range
row := cur_y-spr_y;
sstate := 1;
sprindex <= sprindex + 2;
else
-- skip
n := n + 1;
sprindex <= sprindex + 4;
end if;
elsif (sstate = 1) then
-- store sprite attributes
sprcache(m)(15 downto 8) <= sprdata;
if (sprdata(7) = '1') then
if (PPU_CTRL(5) = '0') then
row := 7 - row;
else
row := 15 - row;
end if;
end if;
sprindex <= sprindex + 1;
sstate := 2;
elsif (sstate = 2) then
-- store sprite X
if (m = 0) then
spr0x:=conv_integer(unsigned(sprdata));
elsif (m = 1) then
spr1x:=conv_integer(unsigned(sprdata));
elsif (m = 2) then
spr2x:=conv_integer(unsigned(sprdata));
elsif (m = 3) then
spr3x:=conv_integer(unsigned(sprdata));
elsif (m = 4) then
spr4x:=conv_integer(unsigned(sprdata));
elsif (m = 5) then
spr5x:=conv_integer(unsigned(sprdata));
elsif (m = 6) then
spr6x:=conv_integer(unsigned(sprdata));
elsif (m = 7) then
spr7x:=conv_integer(unsigned(sprdata));
end if;
sprcache(m)(7 downto 0) <= sprdata;
sprindex <= sprindex - 2;
sstate := 3;
elsif (sstate = 3) then
--load color bit 0
if (PPU_CTRL(5) = '0') then
PatAddr2 <= PPU_CTRL(3) &
sprdata &
"0" &
conv_std_logic_vector(row,3);
elsif (row < 8) then
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "0" &
"0" &
conv_std_logic_vector(row,3);
else
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "1" &
"0" &
conv_std_logic_vector(row-8,3);
end if;
PatRead <= '1';
sprindex <= sprindex + 1;
sstate := 4;
elsif (sstate = 4) then
sstate := 5;
elsif (sstate = 5) then
-- read color bit 0
if (sprdata(6) = '0') then
sprcache(m)(16) <= PatData(7);
sprcache(m)(17) <= PatData(6);
sprcache(m)(18) <= PatData(5);
sprcache(m)(19) <= PatData(4);
sprcache(m)(20) <= PatData(3);
sprcache(m)(21) <= PatData(2);
sprcache(m)(22) <= PatData(1);
sprcache(m)(23) <= PatData(0);
sprcache(m)(24) <= PatData(15);
sprcache(m)(25) <= PatData(14);
sprcache(m)(26) <= PatData(13);
sprcache(m)(27) <= PatData(12);
sprcache(m)(28) <= PatData(11);
sprcache(m)(29) <= PatData(10);
sprcache(m)(30) <= PatData(9);
sprcache(m)(31) <= PatData(8);
else
sprcache(m)(31 downto 16) <= PatData;
end if;
-- next sprite
m := m + 1;
n := n + 1;
sprindex <= sprindex + 2;
sstate := 0;
end if;
end if;
end if;
-- rendering
if (SE = '0') then
-- reset state machine counters
phase <= 0;
counter <= 0;
-- reset color
if (phase /= 0) then
color <= "111111";
else
color <= "000000";
end if;
else
if (phase = 0) then
-- here we introduce little delay so that next line
-- is drawn in the middle of screen.
color <= "111111";
if (counter < 64) then
counter <= counter + 1;
else
counter <= 0;
phase <= 1;
-- beginning of a new row. Is this the first scanline?
if (Y = x"0000") then
-- first line on screen, reset vertical
V := PPU_CTRL(1);
VT := PPU_VSCR(7 downto 3);
FV := PPU_VSCR(2 downto 0);
elsif (Y(0) = '0') then
if (FV /= "111") then
-- next pixel inside the tile
FV := conv_std_logic_vector(
conv_integer(unsigned(FV))+1,3);
else
-- next tile
FV := "000";
if (VT /= "11101") then
-- next tile inside window
VT := conv_std_logic_vector(
conv_integer(unsigned(VT))+1,5);
else
-- next window
VT := "00000";
V := NOT V;
end if;
end if;
end if;
-- reset horizontal counters
H := PPU_CTRL(0);
HT := PPU_HSCR(7 downto 3);
FH := PPU_HSCR(2 downto 0);
-- pipelining, read patIndex of first pixel
VRAM4Read <= '1';
PatRead <= '1';
VRAM4Addr <= H & VT & HT;
end if;
elsif (phase = 1) then
-- load lowest 2 bits of color
PatAddr1 <= PPU_CTRL(4) & VRAM4Data(7 downto 0) & "0" & FV;
-- load associated attribute
VRAM4Addr <= H & "1111" & VT(4 downto 2) & HT(4 downto 2);
-- early calculation for shifts
bshift := FH;
ashift := VT(1)&HT(1)&"0";
-- prepare next column:
if (FH /= "111") then
-- next pixel inside the tile
FH := conv_std_logic_vector(
conv_integer(unsigned(FH))+1,3);
else
-- next tile
FH := "000";
if (HT /= "11111") then
-- next tile inside window
HT := conv_std_logic_vector(
conv_integer(unsigned(HT))+1,5);
else
-- next window
HT := "00000";
H := NOT H;
end if;
end if;
-- find matching sprite, if any
if (counter >= spr0x and counter < (spr0x+8)) then
sprindx := 0;
elsif (counter >= spr1x and counter < (spr1x+8)) then
sprindx := 1;
elsif (counter >= spr2x and counter < (spr2x+8)) then
sprindx := 2;
elsif (counter >= spr3x and counter < (spr3x+8)) then
sprindx := 3;
elsif (counter >= spr4x and counter < (spr4x+8)) then
sprindx := 4;
elsif (counter >= spr5x and counter < (spr5x+8)) then
sprindx := 5;
elsif (counter >= spr6x and counter < (spr6x+8)) then
sprindx := 6;
elsif (counter >= spr7x and counter < (spr7x+8)) then
sprindx := 7;
else
sprindx := 8;
end if;
-- go to next step
phase <= 2;
elsif (phase = 2) then
-- read tile color
tcolor(0) := PatData( 7-conv_integer(unsigned(bshift)));
tcolor(1) := PatData(15-conv_integer(unsigned(bshift)));
tcolor(2) := VRAM4Data(conv_integer(unsigned(ashift))+0);
tcolor(3) := VRAM4Data(conv_integer(unsigned(ashift))+1);
-- continue sprite evaluation
if (sprindx < 8) then
offset := counter -
conv_integer(unsigned(sprcache(sprindx)(7 downto 0)));
scolor(0) := sprcache(sprindx)(16+offset);
scolor(1) := sprcache(sprindx)(24+offset);
scolor(2) := sprcache(sprindx)(8);
scolor(3) := sprcache(sprindx)(9);
else
scolor := "0000";
end if;
-- output color
if (scolor(0) = '1' or scolor(1) = '1') then
-- sprite
color <= SprPal(conv_integer(unsigned(scolor)));
elsif (tcolor(1) = '0' and tcolor(0) = '0') then
-- background color
color <= PatPal(0);
else
color <= PatPal(conv_integer(unsigned(tcolor)));
end if;
-- load next pat index
VRAM4Addr <= H & VT & HT;
-- move to next state
if (counter < 255) then
counter <= counter + 1;
phase <= 1;
else
phase <= 3;
end if;
elsif (phase = 3) then
phase <= 4;
-- reset sprite cache
n := 0;
m := 0;
sstate := 0;
cur_y := conv_integer(unsigned(Y(9 downto 1)));
spr0x := 255;
spr1x := 255;
spr2x := 255;
spr3x := 255;
spr4x := 255;
spr5x := 255;
spr6x := 255;
spr7x := 255;
sprindex <= 0;
else
VRAM4Read <= '0';
PatRead <= '0';
color <= "111111";
end if;
end if;
end if;
end process;
-- sprite access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastSprRD /= SprRD and SprRD='1') then
-- read
SprDataOut <= sprites(conv_integer(unsigned(SprAddr)));
end if;
sprdata <= sprites(sprindex);
if (lastSprWR /= SprWR and SprWR='1') then
-- write
sprites(conv_integer(unsigned(SprAddr))) <= SprDataIn;
end if;
lastSprRD <= SprRD;
lastSprWR <= SprWR;
end if;
end process;
-- palette access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastPalRD /= PalRD and PalRD='1') then
-- read
if (PalAddr(4) = '0') then
PalDataOut(5 downto 0) <= PatPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
else
PalDataOut(5 downto 0) <= SprPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
end if;
end if;
if (lastPalWR /= PalWR and PalWR='1') then
-- write
if (PalAddr(4) = '0') then
PatPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
else
SprPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
end if;
end if;
lastPalRD <= PalRD;
lastPalWR <= PalWR;
end if;
end process;
end Dataflow;
|
gpl-3.0
|
michaelmiehling/A25_VME
|
16z002-01_src/Source/vme_ctrl.vhd
|
1
|
78573
|
--------------------------------------------------------------------------------
-- Title : VME IP Core Toplevel
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_ctrl.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 15/12/16
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_du
-- vme_au
-- vme_locmon
-- vme_mailbox
-- vme_master
-- vme_slave
-- vme_requester
-- vme_bustimer
-- vme_sys_arbiter
-- vme_arbiter
-- vme_wbm
-- vme_wbs
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.10 $
--
-- $Log: vme_ctrl.vhd,v $
-- Revision 1.10 2015/09/16 09:20:07 mwawrik
-- Added generics A16_REG_MAPPING and USE_LONGADD
--
-- Revision 1.9 2015/04/07 14:30:14 AGeissler
-- R1: New signals sl_acc_valid and asn_in_sl_reg
-- M1: Connected these signals to the corresponding component
--
-- Revision 1.8 2014/04/17 07:35:27 MMiehling
-- added generic LONGADD_SIZE
-- added signal prevent_sysrst
--
-- Revision 1.7 2013/09/12 08:45:32 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.6 2012/11/22 09:20:43 MMiehling
-- removed dummy signal
--
-- Revision 1.5 2012/11/15 09:43:55 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.4 2012/11/12 08:13:13 MMiehling
-- changed comments
--
-- Revision 1.3 2012/09/25 11:21:47 MMiehling
-- removed unused signals
--
-- Revision 1.2 2012/08/27 12:57:20 MMiehling
-- general rework
--
-- Revision 1.1 2012/03/29 10:14:49 MMiehling
-- Initial Revision
--
-- Revision 1.14 2010/03/12 13:38:20 mmiehling
-- changed commments
--
-- Revision 1.13 2006/06/02 15:48:57 MMiehling
-- changed comment
--
-- Revision 1.12 2006/05/18 14:29:05 MMiehling
-- added sl_acc for mailbox
--
-- Revision 1.11 2005/02/04 13:44:14 mmiehling
-- added generic simulation; added combinations of addr3+4
--
-- Revision 1.10 2004/11/02 11:29:55 mmiehling
-- moved dma_reg to vme_du
--
-- Revision 1.9 2004/07/27 17:15:39 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.8 2004/06/17 13:02:29 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.7 2003/12/17 15:51:45 MMiehling
-- byte swapping in "not swapped" mode was wrong
--
-- Revision 1.6 2003/12/01 10:03:53 MMiehling
-- changed all
--
-- Revision 1.5 2003/07/14 08:38:08 MMiehling
-- changed rst_counter; added lwordn
--
-- Revision 1.4 2003/06/24 13:47:08 MMiehling
-- removed burst; added loc_keep and rst_aonly
--
-- Revision 1.3 2003/06/13 10:06:35 MMiehling
-- improved
--
-- Revision 1.2 2003/04/22 11:03:00 MMiehling
-- added locmon and mailbox
--
-- Revision 1.1 2003/04/01 13:04:42 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.all;
ENTITY vme_ctrl IS
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write indication
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- mensb slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- mensb master
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : OUT std_logic;
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0);
vme_cyc_sram : OUT std_logic;
vme_cyc_pci : OUT std_logic;
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- the VME signals:
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END vme_ctrl;
ARCHITECTURE vme_ctrl_arch OF vme_ctrl IS
COMPONENT vme_du
GENERIC (
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- arbiter
sel_reg_data_in : IN std_logic; -- mux select signal for wbb/vme register access
sel_loc_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select signal for 0=reg, 1=vme data_out
en_wbm_dat_o : IN std_logic; -- enable for wbm_dat_o
-- requester
brl : OUT std_logic_vector(1 DOWNTO 0); -- bus request leve
-- vme_au
int_adr : IN std_logic_vector(18 DOWNTO 0); -- internal adress for reg
int_be : IN std_logic_vector(3 DOWNTO 0); -- internal byte enables
vme_adr_out : IN std_logic_vector(31 DOWNTO 0); -- vme adress lines
byte_routing : IN std_logic; -- mux select for byte routing
vme_adr_in : OUT std_logic_vector(31 DOWNTO 0); -- vme adress input lines
my_iack : IN std_logic;
d64 : IN std_logic; -- indicates d64 mblt
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
sl_writen_reg : IN std_logic; -- vme read/wrtie signal (registered with en_vme_adr_in)
iackn_in_reg : IN std_logic; -- iack signal (registered with en_vme_adr_in)
-- sys_arbiter
lwordn : IN std_logic; -- stored for vme slave access
-- ctrl_mux
write_flag : IN std_logic; -- write flag for register write access
-- master
oe_vd : IN std_logic; -- output enable for vme data
oe_va : IN std_logic; -- output enable for vme adress
second_word : IN std_logic; -- indicates data phase of d64
-- slave
sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select for vme data out
en_vme_data_out_reg : IN std_logic; -- register enable for vme data out
en_vme_data_out_reg_high: IN std_logic; -- register enable for vme data out high long
en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_data_in_reg_high : IN std_logic; -- register enable for vme data in high long
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
-- wbb_slave
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0); -- indicates dma(1) or normal(0) access
swap : IN std_logic; -- swapps bytes when enabled
-- wbb_master
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
sel_wbm_dat_o : IN std_logic; -- selects between low and high d32
-- register out
longadd : OUT std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
mstr_reg : OUT std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE) sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
slv16_reg : OUT std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : OUT std_logic_vector(3 DOWNTO 0); -- interrupt request register
pci_offset_q : OUT std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
-- register bits
set_berr : IN std_logic; -- if bit is set => berr bit will be set
rst_rmw : IN std_logic; -- if bit is set => rmw bit will be cleared
set_sysc : IN std_logic; -- if bit is set => sysc bit will be set
set_ato : IN std_logic; -- if bit is set => ato bit will be set
clr_sysr : IN std_logic; -- if bit is set => sysr bit will be cleared
mail_irq : IN std_logic_vector(7 DOWNTO 0); -- mailbox interrupt flags
loc_am_0 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : IN std_logic; -- loc-monitor #0 - irq
loc_irq_1 : IN std_logic; -- loc-monitor #1 - irq
loc_rw_0 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
loc_sel : IN std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
rst_aonly : IN std_logic; -- resets aonly bit
clr_locmon : OUT std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
-- irq pins
irq_i_n : IN std_logic_vector(7 DOWNTO 1);
irq_o_n : OUT std_logic_vector(7 DOWNTO 1);
acfailn : IN std_logic; -- ACFAIL# input from Power Supply
--vme
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
vd : INOUT std_logic_vector(31 DOWNTO 0);
va : INOUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT vme_sys_arbiter
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
io_ctrl : OUT io_ctrl_type;
ma_io_ctrl : IN io_ctrl_type;
sl_io_ctrl : IN io_ctrl_type;
mensb_req : IN std_logic; -- request signal for mensb slave access
slave_req : IN std_logic; -- request signal for slave access
mstr_busy : IN std_logic; -- master busy
mstr_vme_req : IN std_logic; -- master request VME interface
mensb_active : OUT std_logic; -- acknoledge/active signal for mensb slave access
slave_active : OUT std_logic; -- acknoledge/active signal for slave access
lwordn_slv : IN std_logic; -- stored for vme slave access
lwordn_mstr : IN std_logic; -- master access lwordn
lwordn : OUT std_logic; -- lwordn for vme_du multiplexer
write_flag : OUT std_logic; -- write flag for register access dependent on arbitration
ma_byte_routing : IN std_logic;
sl_byte_routing : IN std_logic;
byte_routing : OUT std_logic;
sl_sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select: 00=wbm_dat_i 01=wbs_dat_i 10=reg_data
sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0);
ma_oe_vd : IN std_logic; -- master output enable signal for VAD
sl_oe_vd : IN std_logic; -- slave output enable signal for VAD
oe_vd : OUT std_logic; -- output enable signal for VAD
ma_oe_va : IN std_logic; -- master output enable signal for VAD
sl_oe_va : IN std_logic; -- slave output enable signal for VAD
oe_va : OUT std_logic; -- output enable signal for VAD
ma_second_word : IN std_logic; -- differs between address and data phase in d64
sl_second_word : IN std_logic; -- differs between address and data phase in d64
second_word : OUT std_logic; -- differs between address and data phase in d64
ma_en_vme_data_out_reg : IN std_logic;
sl_en_vme_data_out_reg : IN std_logic;
reg_en_vme_data_out_reg : IN std_logic;
en_vme_data_out_reg : OUT std_logic;
ma_en_vme_data_out_reg_high : IN std_logic;
sl_en_vme_data_out_reg_high : IN std_logic;
en_vme_data_out_reg_high : OUT std_logic;
swap : OUT std_logic; -- swapping of data bytes on/off
ma_swap : IN std_logic;
sl_d64 : IN std_logic; -- indicates a d64 burst transmission
ma_d64 : IN std_logic;
d64 : OUT std_logic; -- indicates d64 master access
ma_en_vme_data_in_reg : IN std_logic; -- master enable of vme data in registers
sl_en_vme_data_in_reg : IN std_logic; -- slave enable of vme data in registers
en_vme_data_in_reg : OUT std_logic; -- enable of vme data in registers
ma_en_vme_data_in_reg_high : IN std_logic; -- master enable of vme data high in registers
sl_en_vme_data_in_reg_high : IN std_logic; -- slave enable of vme data high in registers
en_vme_data_in_reg_high : OUT std_logic; -- enable of vme data high in registers
vme_adr_locmon : OUT std_logic_vector(31 DOWNTO 2); -- adress for location monitor (either vme_adr_in or vme_adr_out)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress sampled with en_vme_adr_in
vme_adr_out : IN std_logic_vector(31 DOWNTO 2); -- vme adress for master access
loc_write_flag : IN std_logic; -- write flag for register access from mensb side
sl_write_flag : IN std_logic -- write flag for register access from vme side
);
END COMPONENT;
COMPONENT vme_wbs
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- wbs
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_sel_int : OUT std_logic_vector(3 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
loc_write_flag : OUT std_logic; -- write flag for register
ma_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
ma_en_vme_data_out_reg_high: OUT std_logic; -- for d64 high
set_berr : IN std_logic;
wb_dma_acc : OUT std_logic; -- indicates dma_access
mensb_req : OUT std_logic; -- request line for reg access
mensb_active : IN std_logic; -- acknoledge line
vme_acc_type : OUT std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME access
run_mstr : OUT std_logic; -- starts vme master
mstr_ack : IN std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : IN std_logic; -- if master is busy => 1
burst : OUT std_logic; -- indicates a burst transfer from dma to vme
sel_loc_data_out : OUT std_logic_vector(1 DOWNTO 0) -- mux select signal for 0=reg, 1=vme data_out
);
END COMPONENT;
COMPONENT vme_au
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
test : OUT std_logic;
-- mensb slave
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0); -- mensb slave adress lines
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0); -- mensb slave byte enable lines
wbs_we_i : IN std_logic; -- mensb slave read/write
vme_acc_type : IN std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME slave access
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- mensb master
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0); -- mensb master adress lines
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0); -- mensb master byte enable lines
wbm_we_o : OUT std_logic; -- mensb master read/write
sram_acc : OUT std_logic; -- sram access is requested by vmebus
pci_acc : OUT std_logic; -- pci access is requested by vmebus
reg_acc : OUT std_logic; -- reg access is requested by vmebus
sl_acc_wb : OUT std_logic_vector(4 DOWNTO 0); -- sampled with ld_loc_adr_cnt
-- vme
vme_adr_in : IN std_logic_vector(31 DOWNTO 0); -- vme address input lines
vme_adr_out : OUT std_logic_vector(31 DOWNTO 0); -- vme address output lines
---------------------------------------------------------------------------------------------------
-- pins to vmebus
asn_in : IN std_logic; -- vme adress strobe input
vam : INOUT std_logic_vector(5 DOWNTO 0); -- vme address modifier
dsan_out : OUT std_logic; -- data strobe byte(0) out
dsbn_out : OUT std_logic; -- data strobe byte(1) out
dsan_in : IN std_logic; -- data strobe byte(0) in
dsbn_in : IN std_logic; -- data strobe byte(1) in
writen : INOUT std_logic; -- write enable tco = tbd. tsu <= tbd. PIN tbd.
iackn : INOUT std_logic; -- handler's output ! PIN tbd.
iackin : IN std_logic; -- vme daisy chain interrupt acknoledge input
iackoutn : OUT std_logic; -- vme daisy chain interrupt acknoledge output
---------------------------------------------------------------------------------------------------
mensb_active : IN std_logic; -- acknoledge/active signal for mensb slave access
-- vme master
mstr_cycle : OUT std_logic; -- number of master cycles should be done (0=1x, 1=2x)
second_word : IN std_logic; -- indicates the second transmission if in D16 mode and 32bit should be transmitted
dsn_ena : IN std_logic; -- signal switches dsan_out and dsbn_out on and off
vam_oe : IN std_logic; -- vam output enable
ma_d64 : OUT std_logic; -- indicates a d64 burst transmission
sl_d64 : OUT std_logic; -- indicates a d64 burst transmission
-- vme slave
sl_acc : OUT std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
sl_acc_valid : OUT std_logic; -- sl_acc has been calculated and is valid
asn_in_sl_reg : IN std_logic; -- registered asn signal
ld_loc_adr_m_cnt : IN std_logic; -- load address counter
inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_writen_reg : OUT std_logic;
iackn_in_reg : OUT std_logic; -- iack signal (registered with en_vme_adr_in)
my_iack : OUT std_logic;
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
sl_en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
-- vme_sys_arbiter
sl_byte_routing : OUT std_logic; -- to mensb byte routing
ma_byte_routing : OUT std_logic; -- signal for byte swapping
sl_sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0); -- mux select: 00=loc_data_in_m 01=loc_data_in_s 10=reg_data
lwordn_slv : OUT std_logic; -- stored for vme slave access
lwordn_mstr : OUT std_logic; -- master access lwordn
-- locmon
vam_reg : OUT std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : OUT std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
-- vme_du
mstr_reg : IN std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE)
longadd : IN std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
slv16_reg : IN std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : IN std_logic_vector(3 DOWNTO 0); -- interrupt request register
sysc_reg : IN std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
pci_offset_q : IN std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
int_be : OUT std_logic_vector(3 DOWNTO 0); -- internal byte enables
int_adr : OUT std_logic_vector(18 DOWNTO 0) -- internal adress
);
END COMPONENT;
COMPONENT vme_master
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic;
test_c : OUT std_logic;
-- control signals from/to mensb_slave
run_mstr : IN std_logic; -- this pulse triggers start of Master
mstr_ack : OUT std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : OUT std_logic; -- master busy, set when running
vme_req : out std_logic; -- request VME interface access
burst : IN std_logic; -- indicates a vme burst request
ma_en_vme_data_in_reg : OUT std_logic; -- load register signal in data switch unit for rd vme
ma_en_vme_data_in_reg_high : OUT std_logic; -- load high register signal in data switch unit for rd vme
brel : OUT std_logic; -- release signal for Requester
wbs_we_i : IN std_logic; -- read /write
wb_dma_acc : IN std_logic; -- indicates dma_access
-- requester
dwb : OUT std_logic; -- device wants vme bus
dgb : IN std_logic; -- device gets vme bus
-------------------------------------------------------------------------------
-- PINs:
-- control signals from VMEbus:
berrn_in : IN std_logic; -- vme bus error signal
dtackn_in : IN std_logic; -- vme bus data acknoledge signal
-- control signals to VMEbus
asn_out : OUT std_logic;
-------------------------------------------------------------------------------
-- connected with vme_du:
rst_rmw : OUT std_logic; -- if bit is set => berr bit will be set
set_berr : OUT std_logic; -- if bit is set => rmw bit will be cleared
ma_oe_vd : OUT std_logic; -- output enable for vme data
ma_oe_va : OUT std_logic; -- output enable for vme adress
mstr_reg : IN std_logic_vector(5 DOWNTO 0); -- master configuration register(BERR-bit, REQ-bit, RMW-bit)
rst_aonly : OUT std_logic; -- resets aonly bit
-- connected with vme_au
dsn_ena : OUT std_logic; -- signal switches dsan and dsbn on and off
mstr_cycle : IN std_logic; -- signal indicates one or two cycles must be done
second_word : OUT std_logic; -- signal indicates the actual master cycle
vam_oe : OUT std_logic; -- vam output enable
d64 : IN std_logic; -- indicates a d64 burst transmission
-- connected with slave:
asn_in : IN std_logic; -- to detect a transaction
--data bus bus control signals for vmebus drivers
ma_io_ctrl : OUT io_ctrl_type
);
END COMPONENT;
COMPONENT vme_requester
PORT (
clk : IN std_logic;
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS:
-- Requesters Pins:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic;
bbsyn : OUT std_logic; -- bus busy signal
-------------------------------------------------------------------------------
-- connected with PowerPC Access
dwb : IN std_logic;
dgb : OUT std_logic;
FairReqEn : IN std_logic;
brl : IN std_logic_vector(1 DOWNTO 0); -- bus request level
-- from Arbiter:
bgintn : IN std_logic_vector(3 DOWNTO 0); -- from internal Arbiter if in Slot 1,
-- else outside from VMEbus
-- connected with master unit:
req_bit : IN std_logic; -- '0'= release on request; '1'= release when done
brel : IN std_logic -- indicates whether the bus arbitration can be released
);
END COMPONENT;
COMPONENT vme_arbiter
PORT (
clk : IN std_logic;
rst : IN std_logic;
bgintn : OUT std_logic_vector(3 DOWNTO 0); -- bus grant for all levels
-- vme_du
set_ato : OUT std_logic; -- if bit is set => ato bit will be set
sysc_bit : IN std_logic; -- '1' if board is in slot 1 => enables this vme arbiter
bgouten : IN std_logic; -- enables SGL and bg3out signal
-- PINs:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic
);
END COMPONENT;
COMPONENT vme_bustimer
PORT (
clk : IN std_logic; -- global clock
rst : IN std_logic; -- global reset
startup_rst : IN std_logic; -- powerup reset
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
set_sysc : OUT std_logic; -- if set sysc-bit will be set
sysc_bit : IN std_logic; -- 1=slot1 0=slotx
clr_sysr : OUT std_logic; -- if set sysr-bit will be cleared
sysr_bit : IN std_logic; -- 1=system reset
-- connected with Slave Unit
dsain : IN std_logic; -- data strobe a in
dsbin : IN std_logic; -- data strobe b in
bgouten : OUT std_logic; -- enables SGL and bg3out signal
-- bus grant daisy chain is driven through requester in Access VME:
-----------------------------------------------------------------------
-- PINs:
sysfailn : OUT std_logic; -- indicates when A15 is not ready or in reset
sysrstn_in : IN std_logic;
sysrstn_out : OUT std_logic;
v2p_rst : OUT std_logic; -- Reset between VMEbus and Host CPU
bg3n_in : IN std_logic; -- bus grant signal in (if not connected => slot01)
slot01n : OUT std_logic; -- enables V_SYSCLK (16 MHz)
berrn_out : OUT std_logic -- bus error
);
END COMPONENT;
COMPONENT vme_slave
PORT (
clk : IN std_logic; -- this Unit works at 66 MHz
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS (VMEbus, inputs asynchronous !):
asn_in : IN std_logic; -- vme adress strobe input
dsan_in : IN std_logic; -- vme data strobe A input
dsbn_in : IN std_logic; -- vme data strobe B input
dtackn_out : OUT std_logic; -- vme data acknowledge output
sl_writen_reg : IN std_logic; -- vme read/write
-------------------------------------------------------------------------------
-- vme-mstr
mstr_busy : IN std_logic; -- if set, vme-master is busy
-- vme_au
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- A16 hit, A24 hit, A32 hit, D32 blt, D64 blt
sl_acc_valid : IN std_logic; -- sl_acc has been calculated and is valid
my_iack : IN std_logic;
wbm_we_o : IN std_logic; -- mensb master read/write
reg_acc : IN std_logic; -- reg access is requested by vmebus
en_vme_adr_in : OUT std_logic; -- samples adress and am after asn goes low
asn_in_sl_reg : OUT std_logic; -- registered asn signal
-- sys_arbiter
slave_req : OUT std_logic; -- request signal for slave access
slave_active : IN std_logic; -- acknowledge/active signal for slave access
sl_write_flag : OUT std_logic; -- write flag for register access from vme side
sl_second_word : OUT std_logic; -- differs between address and data phase in d64 accesses
-- vme_du
sl_en_vme_data_in_reg : OUT std_logic; -- enable vme input reg
sl_en_vme_data_in_reg_high : OUT std_logic; -- slave enable of vme data high in registers
sl_oe_vd : OUT std_logic; -- output enable for vme data
sl_oe_va : OUT std_logic; -- output enable for vme adress
reg_en_vme_data_out_reg : OUT std_logic; -- enable vme output reg
sl_io_ctrl : OUT io_ctrl_type;
ld_loc_adr_m_cnt : OUT std_logic; -- load address counter
sl_inc_loc_adr_m_cnt : OUT std_logic; -- increment address counter
clr_intreq : OUT std_logic; -- clear interrupt request (intr(3) <= '0'
-- mensb_master
loc_keep : OUT std_logic; -- if '1', csn remains active (keeps bus)
mensb_mstr_req : OUT std_logic; -- mensb master request
mensb_mstr_ack : IN std_logic -- mensb master acknowledge
);
END COMPONENT;
COMPONENT vme_wbm
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- mensb master
loc_keep : IN std_logic; -- if '1', csn remains active (keeps bus)
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : IN std_logic;
vme_cyc_sram : OUT std_logic; -- keeps bus arbitration to sram as long as active
vme_cyc_pci : OUT std_logic; -- keeps bus arbitration to pci as long as active
-- vme_slave
mensb_mstr_req : IN std_logic; -- mensb master request
mensb_mstr_ack : OUT std_logic; -- mensb master acknoledge
-- vme_du
sel_wbm_dat_o : OUT std_logic;
en_wbm_dat_o : OUT std_logic;
sl_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
sl_en_vme_data_out_reg_high : OUT std_logic; -- for d64 high
-- vme_au
inc_loc_adr_m_cnt : OUT std_logic;
sl_acc_wb : IN std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
pci_acc : IN std_logic; -- pci access is requested by vmebus
sram_acc : IN std_logic -- sram access is requested by vmebus
);
END COMPONENT;
COMPONENT vme_mailbox
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- slave access address type (sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64)
wbm_adr_o : IN std_logic_vector(19 DOWNTO 2); -- mensb master adress lines
wbm_we_o : IN std_logic; -- mensb master read/write
mensb_mstr_req : IN std_logic; -- mensb master request
ram_acc : IN std_logic; -- external ram access
mail_irq : OUT std_logic_vector(7 DOWNTO 0) -- mailbox interrupt requests (flags)
);
END COMPONENT;
COMPONENT vme_locmon
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
sl_writen_reg : IN std_logic; -- vme write/read
vme_adr_locmon : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring (registered with en_vme_adr_in)
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- vme registered vam_in
clr_locmon : IN std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
loc_sel : OUT std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
loc_am_0 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : OUT std_logic; -- loc-monitor #0 - irq
loc_irq_1 : OUT std_logic; -- loc-monitor #1 - irq
loc_rw_0 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : IN std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : IN std_logic_vector(31 DOWNTO 0) -- location monitor #1 adress
);
END COMPONENT;
SIGNAL oe_vme_an : std_logic; -- data output enable A->B
SIGNAL oe_vme_dn : std_logic; -- data latch enable A->B
SIGNAL l_fpga_an : std_logic; -- address output enable B->A
SIGNAL oe_fpga_an : std_logic; -- address output enable A->B
SIGNAL dir_vam : std_logic;
-- vme_wbs
SIGNAL loc_write_flag : std_logic;
SIGNAL sel_loc_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL mensb_req : std_logic;
SIGNAL vme_acc_type : std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME access
SIGNAL ma_en_vme_data_out_reg : std_logic;
SIGNAL wb_dma_acc : std_logic; -- indicates dma_access
-- mensb_mstr
SIGNAL mensb_mstr_ack : std_logic;
SIGNAL wbs_sel_int : std_logic_vector(3 DOWNTO 0);
SIGNAL burst : std_logic;
SIGNAL sel_wbm_dat_o : std_logic;
-- vme_du
SIGNAL clr_locmon : std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
SIGNAL vme_adr_out : std_logic_vector(31 DOWNTO 0);
SIGNAL mstr_reg : std_logic_vector(13 DOWNTO 0);
SIGNAL sysc_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL longadd : std_logic_vector(7 DOWNTO 0);
SIGNAL slv16_reg : std_logic_vector(4 DOWNTO 0);
SIGNAL slv24_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_reg : std_logic_vector(23 DOWNTO 0);
SIGNAL slv24_pci_q : std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
SIGNAL slv32_pci_q : std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
SIGNAL intr_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL loc_am_0 : std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
SIGNAL loc_am_1 : std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
SIGNAL loc_irq_0 : std_logic; -- loc-monitor #0 - irq
SIGNAL loc_irq_1 : std_logic; -- loc-monitor #1 - irq
SIGNAL loc_rw_0 : std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
SIGNAL loc_rw_1 : std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
SIGNAL loc_adr_0 : std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
SIGNAL loc_adr_1 : std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
SIGNAL loc_sel : std_logic_vector(1 DOWNTO 0); -- these bits are loaded with address bits [4:3] if locmon hit address
SIGNAL pci_offset_q : std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
SIGNAL FairReqEn : std_logic;
SIGNAL brl : std_logic_vector(1 DOWNTO 0);
-- vme_au
SIGNAL sl_acc_wb : std_logic_vector(4 DOWNTO 0); -- sampled with ld_loc_adr_cnt
SIGNAL ma_d64 : std_logic;
SIGNAL sl_d64 : std_logic;
SIGNAL vam_reg : std_logic_vector(5 DOWNTO 0);
SIGNAL int_adr : std_logic_vector(18 DOWNTO 0);
SIGNAL vme_adr_in : std_logic_vector(31 DOWNTO 0);
SIGNAL wbm_adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL sl_sel_vme_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL int_be : std_logic_vector(3 DOWNTO 0);
SIGNAL ma_byte_routing : std_logic;
SIGNAL sl_byte_routing : std_logic;
SIGNAL sl_acc : std_logic_vector(4 DOWNTO 0);
SIGNAL sl_writen_reg : std_logic;
SIGNAL iackn_in_reg : std_logic; -- iack signal (registered with en_vme_adr_in)
SIGNAL reg_acc : std_logic;
SIGNAL sram_acc : std_logic;
SIGNAL pci_acc : std_logic;
SIGNAL clr_intreq : std_logic;
SIGNAL my_iack : std_logic;
SIGNAL wbm_we_o_int : std_logic;
SIGNAL lwordn_slv : std_logic; -- stored for vme slave access
SIGNAL lwordn_mstr : std_logic; -- master access lwordn
SIGNAL vme_adr_in_reg : std_logic_vector(31 DOWNTO 2);
-- vme_sys_arbiter
SIGNAL d64 : std_logic;
SIGNAL vme_adr_locmon : std_logic_vector(31 DOWNTO 2);
SIGNAL en_wbm_dat_o : std_logic; -- enable for wbm_dat_o
SIGNAL sel_vme_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL mensb_active : std_logic;
SIGNAL slave_active : std_logic;
SIGNAL write_flag : std_logic;
SIGNAL byte_routing : std_logic;
SIGNAL oe_va : std_logic;
SIGNAL oe_vd : std_logic;
SIGNAL en_vme_data_out_reg : std_logic;
SIGNAL ma_en_vme_data_out_reg_high : std_logic:='0';
SIGNAL sl_en_vme_data_out_reg_high : std_logic;
SIGNAL en_vme_data_out_reg_high : std_logic:='0';
SIGNAL en_vme_data_in_reg : std_logic;
SIGNAL lwordn : std_logic; -- lwordn for vme_du multiplexer
SIGNAL swap : std_logic;
SIGNAL en_vme_data_in_reg_high : std_logic:='0';
SIGNAL l_fpga_an_int : std_logic;
-- vme_master
SIGNAL ma_oe_va : std_logic;
SIGNAL ma_oe_vd : std_logic;
SIGNAL ma_en_vme_data_in_reg : std_logic;
SIGNAL ma_en_vme_data_in_reg_high : std_logic; -- load high register signal in data switch unit for rd vme
SIGNAL dwb : std_logic;
SIGNAL run_mstr : std_logic;
SIGNAL mstr_busy : std_logic;
SIGNAL mstr_vme_req : std_logic;
SIGNAL mstr_ack : std_logic;
SIGNAL brel : std_logic;
SIGNAL rst_rmw : std_logic;
SIGNAL set_berr : std_logic;
SIGNAL dsn_ena : std_logic;
SIGNAL mstr_cycle : std_logic;
SIGNAL sl_second_word : std_logic;
SIGNAL ma_second_word : std_logic;
SIGNAL second_word : std_logic;
SIGNAL vam_oe : std_logic;
SIGNAL oe_vme_an_m : std_logic;
SIGNAL oe_vme_dn_m : std_logic;
SIGNAL oe_fpga_an_m : std_logic;
SIGNAL l_fpga_an_m : std_logic;
SIGNAL rst_aonly : std_logic;
SIGNAL asn_out : std_logic;
SIGNAL ds_o_n_int : std_logic_vector(1 DOWNTO 0);
-- vme_slave
SIGNAL sl_acc_valid : std_logic;
SIGNAL asn_in_sl_reg : std_logic;
SIGNAL sl_en_vme_data_out_reg : std_logic;
SIGNAL reg_en_vme_data_out_reg : std_logic;
SIGNAL sl_write_flag : std_logic;
SIGNAL sl_oe_va : std_logic;
SIGNAL sl_oe_vd : std_logic;
SIGNAL sl_en_vme_data_in_reg : std_logic;
SIGNAL sl_en_vme_data_in_reg_high : std_logic;
SIGNAL slave_req : std_logic;
SIGNAL ld_loc_adr_m_cnt : std_logic;
SIGNAL inc_loc_adr_m_cnt : std_logic;
SIGNAL sl_inc_loc_adr_m_cnt : std_logic;
SIGNAL mensb_mstr_req : std_logic;
SIGNAL loc_keep : std_logic; -- if '1', csn remains active (keeps bus)
SIGNAL en_vme_adr_in : std_logic; -- samples adress and am after asn goes low
-- bustimer
SIGNAL set_sysc : std_logic:='0';
SIGNAL bgouten : std_logic;
SIGNAL clr_sysr : std_logic;
-- location
-- vmearbiter
SIGNAL bgintn : std_logic_vector(3 DOWNTO 0);
SIGNAL set_ato : std_logic;
-- interrupter
-- handler
-- requester
SIGNAL dgb : std_logic;
-- mailbox
SIGNAL mail_irq : std_logic_vector(7 DOWNTO 0);
SIGNAL io_ctrl : io_ctrl_type;
SIGNAL ma_io_ctrl : io_ctrl_type;
SIGNAL sl_io_ctrl : io_ctrl_type;
BEGIN
d_dir <= io_ctrl.d_dir ; -- NOT oe_fpga_dn_int;
d_oe_n <= io_ctrl.d_oe_n ; -- '0';
am_dir <= io_ctrl.am_dir ; -- dir_vam;
am_oe_n <= io_ctrl.am_oe_n; -- '0';
a_dir <= io_ctrl.a_dir ; -- ;
a_oe_n <= io_ctrl.a_oe_n ; -- '0';
test_vec.ato <= sysc_reg(2);
ds_oe_n <= '0' WHEN ds_o_n_int(0) = '0' OR ds_o_n_int(1) = '0' ELSE '1';
ds_o_n <= ds_o_n_int;
as_o_n <= asn_out;
as_oe_n <= asn_out;
vme_mstr_busy <= mstr_busy;
vme_berr <= mstr_reg(2);
postwr <= mstr_reg(4);
FairReqEn <= mstr_reg(6);
wbm_we_o <= wbm_we_o_int;
wbm_adr_o <= wbm_adr_o_int;
du : vme_du
GENERIC MAP (
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP (
clk => clk,
rst => rst,
dma_sta => dma_sta,
clr_dma_en => clr_dma_en,
set_dma_err => set_dma_err,
dma_act_bd => dma_act_bd,
wbm_err_i => wbm_err_i,
wbm_ack_i => wbm_ack_i,
startup_rst => startup_rst,
vme_irq => vme_irq,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
write_flag => write_flag,
d64 => d64,
vam_reg => vam_reg,
vme_adr_in_reg => vme_adr_in_reg,
sl_writen_reg => sl_writen_reg,
iackn_in_reg => iackn_in_reg,
sel_reg_data_in => mensb_active,
sel_loc_data_out => sel_loc_data_out,
en_wbm_dat_o => en_wbm_dat_o,
brl => brl,
second_word => second_word,
sel_wbm_dat_o => sel_wbm_dat_o,
wbs_tga_i => wbs_tga_i,
swap => swap,
lwordn => lwordn,
int_adr => int_adr,
int_be => int_be,
clr_intreq => clr_intreq,
vme_adr_out => vme_adr_out,
byte_routing => byte_routing,
vme_adr_in => vme_adr_in,
oe_va => oe_va,
oe_vd => oe_vd,
sel_vme_data_out => sel_vme_data_out,
en_vme_data_out_reg => en_vme_data_out_reg,
en_vme_data_out_reg_high => en_vme_data_out_reg_high,
en_vme_data_in_reg => en_vme_data_in_reg,
en_vme_data_in_reg_high => en_vme_data_in_reg_high,
clr_locmon => clr_locmon,
longadd => longadd,
mstr_reg => mstr_reg,
sysc_reg => sysc_reg,
set_berr => set_berr,
my_iack => my_iack,
rst_rmw => rst_rmw,
set_sysc => set_sysc,
set_ato => set_ato,
clr_sysr => clr_sysr,
wbs_dat_o => wbs_dat_o,
wbs_dat_i => wbs_dat_i,
wbm_dat_o => wbm_dat_o,
wbm_dat_i => wbm_dat_i,
slv16_reg => slv16_reg,
slv24_reg => slv24_reg,
slv32_reg => slv32_reg,
slv24_pci_q => slv24_pci_q,
slv32_pci_q => slv32_pci_q,
mail_irq => mail_irq,
loc_am_0 => loc_am_0,
loc_am_1 => loc_am_1,
loc_irq_0 => loc_irq_0,
loc_irq_1 => loc_irq_1,
loc_rw_0 => loc_rw_0,
loc_rw_1 => loc_rw_1,
loc_adr_0 => loc_adr_0,
loc_adr_1 => loc_adr_1,
loc_sel => loc_sel,
intr_reg => intr_reg,
pci_offset_q => pci_offset_q,
rst_aonly => rst_aonly,
irq_i_n => irq_i_n,
irq_o_n => irq_o_n,
acfailn => acfailn,
ga => ga,
gap => gap,
vd => vd,
va => va
);
sys_arbiter : vme_sys_arbiter
PORT MAP (
clk => clk,
rst => rst,
io_ctrl => io_ctrl,
ma_io_ctrl => ma_io_ctrl,
sl_io_ctrl => sl_io_ctrl,
mensb_req => mensb_req,
slave_req => slave_req,
mstr_busy => mstr_busy,
mstr_vme_req => mstr_vme_req,
mensb_active => mensb_active,
slave_active => slave_active,
lwordn_slv => lwordn_slv,
lwordn_mstr => lwordn_mstr,
lwordn => lwordn,
write_flag => write_flag,
ma_byte_routing => ma_byte_routing,
sl_byte_routing => sl_byte_routing,
byte_routing => byte_routing,
sl_sel_vme_data_out => sl_sel_vme_data_out,
sel_vme_data_out => sel_vme_data_out,
oe_vd => oe_vd,
ma_oe_vd => ma_oe_vd,
sl_oe_vd => sl_oe_vd,
oe_va => oe_va,
ma_oe_va => ma_oe_va,
sl_oe_va => sl_oe_va,
ma_second_word => ma_second_word,
sl_second_word => sl_second_word,
second_word => second_word,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
sl_en_vme_data_out_reg => sl_en_vme_data_out_reg,
reg_en_vme_data_out_reg => reg_en_vme_data_out_reg,
en_vme_data_out_reg => en_vme_data_out_reg,
ma_en_vme_data_out_reg_high => ma_en_vme_data_out_reg_high,
sl_en_vme_data_out_reg_high => sl_en_vme_data_out_reg_high,
en_vme_data_out_reg_high => en_vme_data_out_reg_high,
swap => swap,
ma_swap => vme_acc_type(5),
ma_d64 => ma_d64,
sl_d64 => sl_d64,
d64 => d64,
ma_en_vme_data_in_reg => ma_en_vme_data_in_reg,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
en_vme_data_in_reg => en_vme_data_in_reg,
ma_en_vme_data_in_reg_high => ma_en_vme_data_in_reg_high,
sl_en_vme_data_in_reg_high => sl_en_vme_data_in_reg_high,
en_vme_data_in_reg_high => en_vme_data_in_reg_high,
vme_adr_locmon => vme_adr_locmon,
vme_adr_in_reg => vme_adr_in_reg,
vme_adr_out => vme_adr_out(31 DOWNTO 2),
loc_write_flag => loc_write_flag,
sl_write_flag => sl_write_flag
);
wbs : vme_wbs
PORT MAP (
clk => clk,
rst => rst,
set_berr => set_berr,
wbs_stb_i => wbs_stb_i,
wbs_ack_o => wbs_ack_o,
wbs_err_o => wbs_err_o,
wbs_we_i => wbs_we_i,
wbs_cyc_i => wbs_cyc_i,
wbs_adr_i => wbs_adr_i,
wbs_sel_i => wbs_sel_i,
wbs_sel_int => wbs_sel_int,
wbs_tga_i => wbs_tga_i,
wb_dma_acc => wb_dma_acc,
loc_write_flag => loc_write_flag,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
ma_en_vme_data_out_reg_high => ma_en_vme_data_out_reg_high,
mensb_req => mensb_req,
mensb_active => mensb_active,
vme_acc_type => vme_acc_type,
run_mstr => run_mstr,
mstr_ack => mstr_ack,
mstr_busy => mstr_busy,
burst => burst,
sel_loc_data_out => sel_loc_data_out
);
au : vme_au
GENERIC MAP (
A16_REG_MAPPING => A16_REG_MAPPING,
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP (
clk => clk,
rst => rst,
test => open,
wbs_adr_i => wbs_adr_i,
wbs_sel_i => wbs_sel_int,
wbs_we_i => wbs_we_i,
wbs_tga_i => wbs_tga_i,
vme_adr_in => vme_adr_in,
vme_adr_out => vme_adr_out,
vme_adr_in_reg => vme_adr_in_reg,
sl_acc_wb => sl_acc_wb,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
asn_in => as_i_n,
mensb_active => mensb_active,
int_be => int_be,
int_adr => int_adr,
clr_intreq => clr_intreq,
iackn => iackn,
iackin => iackin,
iackoutn => iackoutn,
vam_oe => vam_oe,
vam => vam,
vme_acc_type => vme_acc_type,
second_word => second_word,
dsn_ena => dsn_ena,
mstr_reg => mstr_reg,
longadd => longadd,
mstr_cycle => mstr_cycle,
ma_byte_routing => ma_byte_routing,
sysc_reg => sysc_reg,
sl_sel_vme_data_out => sl_sel_vme_data_out,
sl_byte_routing => sl_byte_routing,
ld_loc_adr_m_cnt => ld_loc_adr_m_cnt,
inc_loc_adr_m_cnt => inc_loc_adr_m_cnt,
sl_inc_loc_adr_m_cnt => sl_inc_loc_adr_m_cnt,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
writen => writen,
sram_acc => sram_acc,
pci_acc => pci_acc,
ma_d64 => ma_d64,
sl_d64 => sl_d64,
reg_acc => reg_acc,
intr_reg => intr_reg,
lwordn_slv => lwordn_slv,
lwordn_mstr => lwordn_mstr,
en_vme_adr_in => en_vme_adr_in,
my_iack => my_iack,
wbm_adr_o => wbm_adr_o_int,
wbm_sel_o => wbm_sel_o,
wbm_we_o => wbm_we_o_int,
vam_reg => vam_reg,
dsan_out => ds_o_n_int(0),
dsbn_out => ds_o_n_int(1),
dsan_in => ds_i_n(0),
dsbn_in => ds_i_n(1),
sl_writen_reg => sl_writen_reg,
iackn_in_reg => iackn_in_reg,
sl_acc => sl_acc,
sl_acc_valid => sl_acc_valid,
pci_offset_q => pci_offset_q,
asn_in_sl_reg => asn_in_sl_reg,
slv24_pci_q => slv24_pci_q,
slv32_pci_q => slv32_pci_q,
slv16_reg => slv16_reg,
slv24_reg => slv24_reg,
slv32_reg => slv32_reg
);
master : vme_master
PORT MAP(
clk => clk,
rst => rst,
test_c => OPEN,
run_mstr => run_mstr,
mstr_ack => mstr_ack,
mstr_busy => mstr_busy,
vme_req => mstr_vme_req,
burst => burst,
ma_en_vme_data_in_reg => ma_en_vme_data_in_reg,
ma_en_vme_data_in_reg_high => ma_en_vme_data_in_reg_high,
wb_dma_acc => wb_dma_acc,
brel => brel,
wbs_we_i => wbs_we_i,
dwb => dwb,
dgb => dgb,
berrn_in => berrin,
dtackn_in => dtackin,
d64 => ma_d64,
asn_out => asn_out,
rst_aonly => rst_aonly,
rst_rmw => rst_rmw,
set_berr => set_berr,
vam_oe => vam_oe,
ma_oe_va => ma_oe_va,
ma_oe_vd => ma_oe_vd,
dsn_ena => dsn_ena,
mstr_cycle => mstr_cycle,
second_word => ma_second_word,
asn_in => as_i_n,
mstr_reg => mstr_reg(5 DOWNTO 0),
ma_io_ctrl => ma_io_ctrl
);
requester : vme_requester
PORT MAP (
clk => clk,
rst => rst,
br_i_n => br_i_n,
br_o_n => br_o_n,
bg_o_n => bg_o_n,
bbsyn_in => bbsyin,
bbsyn => bbsyn,
dwb => dwb,
dgb => dgb,
FairReqEn => FairReqEn,
brl => brl,
bgintn => bgintn,
req_bit => mstr_reg(1),
brel => brel
);
arbiter : vme_arbiter
PORT MAP (
clk => clk,
rst => rst,
bgintn => bgintn,
set_ato => set_ato,
sysc_bit => sysc_reg(0),
bgouten => bgouten,
br_i_n => br_i_n,
bbsyn_in => bbsyin,
bg_i_n => bg_i_n
);
bustimer : vme_bustimer
PORT MAP (
clk => clk,
rst => rst,
startup_rst => startup_rst,
prevent_sysrst => prevent_sysrst,
set_sysc => set_sysc,
sysc_bit => sysc_reg(0),
clr_sysr => clr_sysr,
sysr_bit => sysc_reg(1),
dsain => ds_i_n(0),
dsbin => ds_i_n(1),
bgouten => bgouten,
sysfailn => sysfail_o_n,
sysrstn_in => sysresin,
sysrstn_out => sysresn,
v2p_rst => v2p_rst,
bg3n_in => bg_i_n(3),
slot01n => slot01n,
berrn_out => berrn
);
slave : vme_slave
PORT MAP (
clk => clk,
rst => rst,
loc_keep => loc_keep,
mstr_busy => mstr_busy,
asn_in => as_i_n,
dsan_in => ds_i_n(0),
dsbn_in => ds_i_n(1),
reg_acc => reg_acc,
sl_writen_reg => sl_writen_reg,
en_vme_adr_in => en_vme_adr_in,
wbm_we_o => wbm_we_o_int,
dtackn_out => dtackn,
slave_req => slave_req,
slave_active => slave_active,
sl_write_flag => sl_write_flag,
sl_second_word => sl_second_word,
clr_intreq => clr_intreq,
sl_acc => sl_acc,
sl_acc_valid => sl_acc_valid,
asn_in_sl_reg => asn_in_sl_reg,
my_iack => my_iack,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
sl_en_vme_data_in_reg_high => sl_en_vme_data_in_reg_high,
sl_oe_va => sl_oe_va,
sl_oe_vd => sl_oe_vd,
reg_en_vme_data_out_reg => reg_en_vme_data_out_reg,
sl_io_ctrl => sl_io_ctrl,
ld_loc_adr_m_cnt => ld_loc_adr_m_cnt,
sl_inc_loc_adr_m_cnt => sl_inc_loc_adr_m_cnt,
mensb_mstr_req => mensb_mstr_req,
mensb_mstr_ack => mensb_mstr_ack
);
wbm : vme_wbm
PORT MAP (
clk => clk,
rst => rst,
loc_keep => loc_keep,
vme_cyc_sram => vme_cyc_sram,
vme_cyc_pci => vme_cyc_pci,
wbm_stb_o => wbm_stb_o,
wbm_err_i => wbm_err_i,
wbm_ack_i => wbm_ack_i,
wbm_we_o => wbm_we_o_int,
sl_en_vme_data_out_reg => sl_en_vme_data_out_reg,
sl_en_vme_data_out_reg_high => sl_en_vme_data_out_reg_high,
mensb_mstr_req => mensb_mstr_req,
mensb_mstr_ack => mensb_mstr_ack,
sel_wbm_dat_o => sel_wbm_dat_o,
en_wbm_dat_o => en_wbm_dat_o,
inc_loc_adr_m_cnt => inc_loc_adr_m_cnt,
sl_acc_wb => sl_acc_wb,
pci_acc => pci_acc,
sram_acc => sram_acc
);
mailbox : vme_mailbox
PORT MAP(
clk => clk,
rst => rst,
sl_acc => sl_acc,
wbm_adr_o => wbm_adr_o_int(19 DOWNTO 2),
wbm_we_o => wbm_we_o_int,
mensb_mstr_req => mensb_mstr_req,
ram_acc => sram_acc,
mail_irq => mail_irq
);
locmon : vme_locmon
PORT MAP(
clk => clk,
rst => rst,
en_vme_adr_in => en_vme_adr_in,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
sl_writen_reg => sl_writen_reg,
vme_adr_locmon => vme_adr_locmon,
vam_reg => vam_reg,
clr_locmon => clr_locmon,
loc_sel => loc_sel,
loc_am_0 => loc_am_0,
loc_am_1 => loc_am_1,
loc_irq_0 => loc_irq_0,
loc_irq_1 => loc_irq_1,
loc_rw_0 => loc_rw_0,
loc_rw_1 => loc_rw_1,
loc_adr_0 => loc_adr_0,
loc_adr_1 => loc_adr_1
);
END vme_ctrl_arch;
|
gpl-3.0
|
tghaefli/ADD
|
ISE/FMC_waj/fmc_chn.vhd
|
1
|
5606
|
-------------------------------------------------------------------------------
-- Entity: fmc_chn
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Floppy-Music Controller (1 channel)
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_chn is
generic(N : natural := 0 -- channel number
);
port(rst : in std_logic;
clk : in std_logic;
-- control inputs
tick_dur : in std_logic; -- nominal period = 1 ms
tick_nco : in std_logic; -- nominal period = 1 us
chn_enb : in std_logic;
-- outputs to pins
fmc_enb : out std_logic;
fmc_dir : out std_logic;
fmc_stp : out std_logic
);
end fmc_chn;
architecture rtl of fmc_chn is
-- output signals
signal stp_cnt : unsigned(6 downto 0);
constant MAX_STP : unsigned(6 downto 0) := to_unsigned(79-1,7);
signal stp_reg : std_logic;
signal dir_reg : std_logic;
-- ROM and addressing
signal rom_addr : std_logic_vector(FMC_ROM_AW-1 downto 0);
signal rom_data : std_logic_vector(FMC_ROM_DW-1 downto 0);
signal duration_cnt : unsigned(FMC_DUR_WW-1 downto 0);
signal tone_duration : unsigned(FMC_DUR_WW-1 downto 0);
signal tone_number : unsigned(FMC_TON_WW-1 downto 0);
signal tone_end_evt : std_logic;
-- LUT: tone number ==> NCO seed
type t_nco_lut is array (2**FMC_TON_WW-1 downto 0) of natural;
constant nco_lut : t_nco_lut := (
0,0,0,0,0,0,0,0,0,0,0,0,0,0,7382,6968,6577,6207,5859,5530,5220,4927,4650,4389,4143,3910,3691,
3484,3288,3104,2930,2765,2610,2463,2325,2195,2071,1955,1845,1742,1644,1552,1465,1383,1305,1232,
1163,1097,1036,978,923,871,822,776,732,691,652,616,581,549,518,489,461,0);
-- NCO signals
signal seed : unsigned(12 downto 0); -- 13 bit seed
signal nco_reg : unsigned(23 downto 0); -- 24 bit NCO
begin
-----------------------------------------------------------------------------
-- output assignments
-----------------------------------------------------------------------------
fmc_stp <= stp_reg;
fmc_dir <= dir_reg;
-----------------------------------------------------------------------------
-- generate and register FMC outputs
-----------------------------------------------------------------------------
P_out: process(rst, clk)
begin
if rst = '1' then
fmc_enb <= '1';
stp_reg <= '0';
dir_reg <= '0';
stp_cnt <= (others => '0');
elsif rising_edge(clk) then
-- set enable active during times when any tone is played
if tone_number > 0 then
-- enable is low-active
fmc_enb <= '0';
else
fmc_enb <= '1';
end if;
-- connect step output to NCO output (MSB) to generate desired frequency
stp_reg <= std_logic(nco_reg(nco_reg'left));
-- toggle direction output after every 80 steps (rising edges on fmc_stp)
if stp_reg = '0' and std_logic(nco_reg(nco_reg'left)) = '1' then
-- rising edge on step output
if stp_cnt = MAX_STP then
stp_cnt <= (others => '0');
dir_reg <= not dir_reg;
else
stp_cnt <= stp_cnt + 1;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- ROM addressing and tick counting
-----------------------------------------------------------------------------
P_read: process(rst, clk)
begin
if rst = '1' then
duration_cnt <= (others => '0');
tone_end_evt <= '0';
rom_addr <= (others => '0');
elsif rising_edge(clk) then
-- default assignment
tone_end_evt <= '0';
-- maintain tone duration counter
if tick_dur = '1' then
if duration_cnt = tone_duration-1 then
duration_cnt <= (others => '0');
tone_end_evt <= '1';
else
duration_cnt <= duration_cnt + 1;
end if;
end if;
-- maintain ROM address
if chn_enb = '0' or tone_duration = FMC_LAST_TONE then
-- restart playing from 1st tone
rom_addr <= (others => '0');
duration_cnt <= (others => '0');
elsif tone_end_evt = '1' then
rom_addr <= std_logic_vector(unsigned(rom_addr)+1);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- channel number dependent FMC ROM instance
-----------------------------------------------------------------------------
rom : entity work.fmc_rom
generic map(N => N)
port map (clk => clk,
addr => rom_addr,
data => rom_data
);
tone_duration <= unsigned(rom_data(FMC_DUR_WW+FMC_TON_WW-1 downto FMC_TON_WW));
tone_number <= unsigned(rom_data(FMC_TON_WW-1 downto 0));
-----------------------------------------------------------------------------
-- NCO (tone frequency generation)
-----------------------------------------------------------------------------
P_nco: process(rst, clk)
begin
if rst = '1' then
seed <= (others => '0');
nco_reg <= (others => '0');
elsif rising_edge(clk) then
seed <= to_unsigned(nco_lut(to_integer(tone_number)),13);
if tick_nco = '1' then
nco_reg <= nco_reg + seed;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
Alabamajack/Garfield
|
FPGA_Design/ip_intern/PWM_Generator/pwm_generator_avalon.vhd
|
1
|
3428
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_generator_avalon is
generic(
datawidth : natural := 32;
freq_core : natural := 100_000_000;
freq_pwm : natural := 10_000
);
port(
-- avalon clk interface, there is no need for a reset
clk : in std_logic;
reset : in std_logic;
-- avalon MM interface
address : in std_logic_vector(0 downto 0);
read, write, chipselect : in std_logic;
writedata : in std_logic_vector(datawidth - 1 downto 0);
readdata : out std_logic_vector(datawidth - 1 downto 0);
waitrequest : out std_logic;
-- avalon output interface
pwm_output_signal : out std_logic
);
end entity pwm_generator_avalon;
architecture RTL of pwm_generator_avalon is
----------------------------------------
-- constants
----------------------------------------
constant pwm_generator_bit_width : natural := 8;
----------------------------------------
-- signals
----------------------------------------
signal datavalid_write : boolean := false;
----------------------------------------
-- signals as registers
----------------------------------------
signal control_register : std_logic_vector(datawidth - 1 downto 0);
----------------------------------------
-- components
----------------------------------------
component pwm_generator
generic(
width : natural := 8;
freq_clock : integer := 50000000;
freq_pwm : integer := 1000
);
port(
clk : in std_logic;
pwmvalue : in std_logic_vector(width - 1 downto 0);
pwmout : out std_logic
);
end component pwm_generator;
begin
----------------------------------------
-- component instantiations
----------------------------------------
pwm_gen_inst : pwm_generator
generic map(
width => pwm_generator_bit_width,
freq_clock => freq_core,
freq_pwm => freq_pwm
)
port map(
clk => clk,
pwmvalue(pwm_generator_bit_width -1 downto 0) => control_register(pwm_generator_bit_width - 1 downto 0),
pwmout => pwm_output_signal
);
----------------------------------------
-- concurrent statements
----------------------------------------
waitrequest <= '1' when (write = '1' and chipselect = '1') and not datavalid_write else '0'; -- waitrequest must be asynchron and high until the data are taken
----------------------------------------
-- processes
----------------------------------------
--! @brief
write_proc : process(clk) is
begin
if rising_edge(clk) then
datavalid_write <= false;
if reset = '1' then
control_register <= (others => '0');
elsif chipselect = '1' then
if write = '1' then
case (address) is
when "0" =>
control_register(pwm_generator_bit_width - 1 downto 0) <= writedata(pwm_generator_bit_width - 1 downto 0);
when others =>
null;
end case;
datavalid_write <= true;
end if;
end if;
end if;
end process write_proc;
--! @brief
read_proc : process(chipselect, read, address, control_register) is
begin
if chipselect = '1' and read = '1' then
case address is
when "0" =>
readdata <= control_register;
when others =>
null;
end case;
end if;
end process read_proc;
end architecture RTL;
|
gpl-3.0
|
tghaefli/ADD
|
ISE/FMC/fmc_top.vhd
|
1
|
5482
|
-------------------------------------------------------------------------------
-- Entity: fmc_top
-- Author: Sandro Arnold
-------------------------------------------------------------------------------
-- Description: Testatbung FMC Controller
-- FMC_TOP Top Level Entity of Floppy Music Controller
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_top is
port(rst : in std_logic;
clk : in std_logic;
-- FMC_TOP bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- FMC_TOP pin signals
fmc_top_out_enb : out std_logic_vector(N_FMC-1 downto 0);
fmc_top_out_step : out std_logic_vector(N_FMC-1 downto 0);
fmc_top_out_dir : out std_logic_vector(N_FMC-1 downto 0)
);
end fmc_top;
architecture rtl of fmc_top is
-- address select signal
signal addr_sel : t_fmc_addr_sel;
-- prescaler signals
signal tick_dur : std_logic;
signal tick_nco : std_logic;
signal dur_cnt : integer range 0 to DUR_SCALE/2 := 0; -- toggling frequency = 2*f_tick_dur
signal nco_cnt : integer range 0 to NCO_SCALE/2 := 0; -- toggling frequency = 2*f_tick_nco
-- peripheral registers
signal chn_enb_reg : std_logic_vector(DW-1 downto 0);
signal spd_fac_reg : std_logic_vector(DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- FMC_CH ---------------------------------------------------------------------
gen_i_fmc_ch: for k in 0 to N_FMC-1 generate
i_fmc_ch: entity work.fmc_ch
generic map(N => k)
port map(
rst => rst,
clk => clk,
enb => chn_enb_reg(k),
tick_dur => tick_dur,
tick_nco => tick_nco,
fmc_ch_out_enb => fmc_top_out_enb(k),
fmc_chn_out_step => fmc_top_out_step(k),
fmc_chn_out_dir => fmc_top_out_dir(k)
);
end generate gen_i_fmc_ch;
-----------------------------------------------------------------------------
-- Address Decoding (combinationally)
-----------------------------------------------------------------------------
process(bus_in.addr)
begin
case bus_in.addr is
-- Port 1 addresses -----------------------------------------------------
when c_addr_fmc_chn_enb => addr_sel <= fmc_chn_enb;
when c_addr_fmc_tmp_ctrl => addr_sel <= fmc_tmp_ctrl;
-- unused addresses -----------------------------------------------------
when others => addr_sel <= none;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Access (R and R/W registers)
-----------------------------------------------------------------------------
P_read: process(clk)
begin
if rising_edge(clk) then
-- default assignment
bus_out.data <= (others => '0');
-- use address select signal
case addr_sel is
when fmc_chn_enb => bus_out.data <= chn_enb_reg;
when fmc_tmp_ctrl => bus_out.data <= spd_fac_reg;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Access (R/W regsiters only)
-----------------------------------------------------------------------------
P_write: process(clk, rst)
begin
if rst = '1' then
chn_enb_reg <= (others => '0');
spd_fac_reg <= (others => '0'); -- output disabled per default
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
-- use address select signal
case addr_sel is
when fmc_chn_enb => chn_enb_reg <= bus_in.data;
when fmc_tmp_ctrl => spd_fac_reg <= bus_in.data;
when others => null;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- tick_dur
-----------------------------------------------------------------------------
tick_duration: process (rst, clk) begin
if (rst = '1') then
tick_dur <= '0';
dur_cnt <= 0;
elsif rising_edge(clk) then
if (tick_dur = '1') then
tick_dur <= '0';
end if;
if (dur_cnt = DUR_SCALE-1) then
tick_dur <= not tick_dur;
dur_cnt <= 0;
else
dur_cnt <= dur_cnt + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- tick_nco
-----------------------------------------------------------------------------
tick_ncoscillator: process (rst, clk) begin
if (rst = '1') then
tick_nco <= '0';
nco_cnt <= 0;
elsif rising_edge(clk) then
if (tick_nco = '1') then
tick_nco <= '0';
end if;
if (nco_cnt = NCO_SCALE-1) then
tick_nco <= '1';
nco_cnt <= 0;
else
nco_cnt <= nco_cnt + 1;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
tghaefli/ADD
|
EDK/IVK_Repos/IVK_IPLib/pcores/sg_xsvi_fanout_plbw_v1_01_a/hdl/vhdl/sg_xsvi_fanout_plbw.vhd
|
1
|
10007
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_xsvi_fanout_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_xsvi_fanout_plbw;
architecture structural of sg_xsvi_fanout_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_xsvi_fanout_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
gpl-3.0
|
tghaefli/ADD
|
ISE/FMC_waj/cpu_reg.vhd
|
3
|
2773
|
-------------------------------------------------------------------------------
-- Entity: cpu_reg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Register block for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 x 16
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_reg is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
reg_in : in t_ctr2reg;
reg_out : out t_reg2ctr;
alu_res : in std_logic_vector(DW-1 downto 0);
alu_op1 : out std_logic_vector(DW-1 downto 0);
alu_op2 : out std_logic_vector(DW-1 downto 0)
);
end cpu_reg;
architecture rtl of cpu_reg is
signal reg_blk : t_regblk;
begin
-----------------------------------------------------------------------------
-- Mux and register data/address to Control Unit depending on source info.
-----------------------------------------------------------------------------
P_mux: process(clk)
begin
if rising_edge(clk) then
reg_out.data <= reg_blk(to_integer(unsigned(reg_in.dest)));
reg_out.addr <= reg_blk(to_integer(unsigned(reg_in.src1)))(AW-1 downto 0);
end if;
end process;
-----------------------------------------------------------------------------
-- Mux input data to ALU combinationally depending on source info from
-- control unit.
-----------------------------------------------------------------------------
alu_op1 <= reg_blk(to_integer(unsigned(reg_in.src1)));
alu_op2 <= reg_blk(to_integer(unsigned(reg_in.src2)));
-----------------------------------------------------------------------------
-- CPU register block
-- Store ALU result or data from control unit depending on different enable
-- signals and destination info given from the control unit.
-- Note: Some CPU registers have non-zero reset values to allow simulation
-- of register-to-register instructions without load-instructions.
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
reg_blk <= (others => (others => '0'));
elsif rising_edge(clk) then
if reg_in.enb_res = '1' then
-- store result from ALU
reg_blk(to_integer(unsigned(reg_in.dest))) <= alu_res;
elsif reg_in.enb_data = '1' then
-- store data from Ctrl (ld instruction)
reg_blk(to_integer(unsigned(reg_in.dest))) <= reg_in.data;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
Alabamajack/Garfield
|
FPGA_Design/ip_intern/Rotary_Encoder/rotary_encoder_avalon.vhd
|
1
|
4850
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rotary_encoder_avalon is
generic(
datawidth : natural := 32
);
port(
-- ! avalon clk interface
clk : in std_logic;
-- ! avalon reset interface
rst : in std_logic;
-- ! avalon MM interface
address : in std_logic_vector(0 downto 0);
read, write, chipselect : in std_logic;
writedata : in std_logic_vector(datawidth - 1 downto 0);
readdata : out std_logic_vector(datawidth - 1 downto 0);
waitrequest : out std_logic;
-- ! avalon input interface
rotary_signal : in std_logic
);
end entity rotary_encoder_avalon;
architecture RTL of rotary_encoder_avalon is
-- --------------------------------------
-- constants
-- --------------------------------------
constant bit_enable_pos : natural := 0;
constant bit_clearcounter_pos : natural := 1;
constant bit_resetcore_pos : natural := 2;
constant bit_countererror_pos : natural := 16;
-- --------------------------------------
-- signals
-- --------------------------------------
signal datavalid_write : boolean := false;
signal reset_int : std_logic;
signal clear_counter : std_logic;
signal enable : std_logic;
signal counter : std_logic_vector(datawidth - 1 downto 0);
signal counter_error : boolean;
-- --------------------------------------
-- signals as registers
-- --------------------------------------
signal control_register_path : std_logic_vector(datawidth/2 - 1 downto 0) := (others => '0');
signal status_register_path : std_logic_vector(datawidth/2 - 1 downto 0) := (others => '0');
signal control_status_register : std_logic_vector(datawidth - 1 downto 0);
-- --------------------------------------
-- components
-- --------------------------------------
component rotary_encoder
generic(
core_frequency : natural := 100_000_000;
counter_width : natural := 32
);
port(
clk : in std_logic;
rst : in std_logic;
clear_counter : in std_logic;
enable : in std_logic;
counter : out std_logic_vector(counter_width - 1 downto 0);
counter_error : out boolean;
rotary_signal : in std_logic
);
end component rotary_encoder;
begin
-- --------------------------------------
-- components instantiations
-- --------------------------------------
rotary_enc_inst : rotary_encoder
generic map(
core_frequency => 100_000_000,
counter_width => datawidth
)
port map(
clk => clk,
rst => rst,
clear_counter => clear_counter,
enable => enable,
counter => counter,
counter_error => counter_error,
rotary_signal => rotary_signal
);
-- --------------------------------------
-- concurrent statements
-- --------------------------------------
control_status_register <= status_register_path & control_register_path;
reset_int <= rst or control_register_path(bit_resetcore_pos);
waitrequest <= '1' when (write = '1' and chipselect = '1') and not datavalid_write else '0';
status_register_path(bit_countererror_pos - datawidth/2) <= '1' when counter_error else '0';
enable <= control_register_path(bit_enable_pos);
clear_counter <= control_register_path(bit_clearcounter_pos);
-- --------------------------------------
-- processes
-- --------------------------------------
write_proc : process(clk) is
begin
if rising_edge(clk) then
control_register_path(bit_clearcounter_pos) <= '0';
datavalid_write <= false;
if reset_int = '1' then
control_register_path <= (others => '0');
elsif chipselect = '1' and write = '1' then
case address is
when "0" => -- the control register; base address 0x00
control_register_path(bit_enable_pos) <= writedata(bit_enable_pos);
control_register_path(bit_clearcounter_pos) <= writedata(bit_clearcounter_pos);
control_register_path(bit_resetcore_pos) <= writedata(bit_resetcore_pos);
when "1" => -- the result register, there is no write allowed; base address 0x04
null;
when others =>
null;
end case;
datavalid_write <= true;
else
null;
end if;
end if;
end process write_proc;
read_proc : process(address, chipselect, control_status_register, counter, read) is
begin
readdata <= (others => '0');
if chipselect = '1' and read = '1' then
case address is
when "0" => -- control/status register
readdata <= control_status_register;
when "1" => -- result register
readdata <= counter;
when others => null;
end case;
end if;
end process read_proc;
end architecture RTL;
|
gpl-3.0
|
tghaefli/ADD
|
ISE/FMC_waj/ram.vhd
|
3
|
1847
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (
-- prelimenary RAM initialization
0 => std_logic_vector(to_unsigned(16#00_FF#, DW)),
1 => std_logic_vector(to_unsigned(16#FF_01#, DW)),
2 => std_logic_vector(to_unsigned(16#7F_FF#, DW)),
3 => std_logic_vector(to_unsigned(16#7F_FE#, DW)),
others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.wr_enb = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
gpl-3.0
|
tghaefli/ADD
|
EDK/IVK_Repos/IVK_IPLib/pcores/sg_cfa_gamma_plbw_v1_00_a/hdl/vhdl/sg_cfa_gamma.vhd
|
1
|
210700
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_a629aff4db5bb1c8.vhd when simulating
-- the core, addsb_11_0_a629aff4db5bb1c8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_a629aff4db5bb1c8 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END addsb_11_0_a629aff4db5bb1c8;
ARCHITECTURE addsb_11_0_a629aff4db5bb1c8_a OF addsb_11_0_a629aff4db5bb1c8 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_a629aff4db5bb1c8
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_a629aff4db5bb1c8 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 1,
c_a_width => 12,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 1,
c_b_value => "000000000000",
c_b_width => 12,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 12,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_a629aff4db5bb1c8
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_a629aff4db5bb1c8_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_c25f95ce6b0868c9.vhd when simulating
-- the core, addsb_11_0_c25f95ce6b0868c9. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_c25f95ce6b0868c9 IS
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END addsb_11_0_c25f95ce6b0868c9;
ARCHITECTURE addsb_11_0_c25f95ce6b0868c9_a OF addsb_11_0_c25f95ce6b0868c9 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_c25f95ce6b0868c9
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_c25f95ce6b0868c9 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 1,
c_a_width => 11,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 1,
c_b_value => "00000000000",
c_b_width => 11,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 11,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_c25f95ce6b0868c9
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_c25f95ce6b0868c9_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_2be284cffc9a51ef.vhd when simulating
-- the core, bmg_62_2be284cffc9a51ef. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_2be284cffc9a51ef IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END bmg_62_2be284cffc9a51ef;
ARCHITECTURE bmg_62_2be284cffc9a51ef_a OF bmg_62_2be284cffc9a51ef IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_2be284cffc9a51ef
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_2be284cffc9a51ef USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_2be284cffc9a51ef.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_2be284cffc9a51ef
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END bmg_62_2be284cffc9a51ef_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bmg_62_efdcd0e54d01b373.vhd when simulating
-- the core, bmg_62_efdcd0e54d01b373. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bmg_62_efdcd0e54d01b373 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END bmg_62_efdcd0e54d01b373;
ARCHITECTURE bmg_62_efdcd0e54d01b373_a OF bmg_62_efdcd0e54d01b373 IS
-- synthesis translate_off
COMPONENT wrapped_bmg_62_efdcd0e54d01b373
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bmg_62_efdcd0e54d01b373 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "bmg_62_efdcd0e54d01b373.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 255,
c_read_depth_b => 255,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 255,
c_write_depth_b => 255,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bmg_62_efdcd0e54d01b373
PORT MAP (
clka => clka,
ena => ena,
addra => addra,
douta => douta
);
-- synthesis translate_on
END bmg_62_efdcd0e54d01b373_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_3eb0c8dcd9c22b4d.vhd when simulating
-- the core, cntr_11_0_3eb0c8dcd9c22b4d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_3eb0c8dcd9c22b4d IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END cntr_11_0_3eb0c8dcd9c22b4d;
ARCHITECTURE cntr_11_0_3eb0c8dcd9c22b4d_a OF cntr_11_0_3eb0c8dcd9c22b4d IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_3eb0c8dcd9c22b4d
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_3eb0c8dcd9c22b4d USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 12,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_3eb0c8dcd9c22b4d
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_3eb0c8dcd9c22b4d_a;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_f4d0462e0e is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_f4d0462e0e;
architecture behavior of mcode_block_f4d0462e0e is
signal plbrst_1_110: unsigned((1 - 1) downto 0);
signal plbabus_1_118: unsigned((32 - 1) downto 0);
signal plbpavalid_1_127: unsigned((1 - 1) downto 0);
signal plbrnw_1_139: unsigned((1 - 1) downto 0);
signal plbwrdbus_1_147: unsigned((32 - 1) downto 0);
signal rddata_1_158: unsigned((32 - 1) downto 0);
signal addrpref_1_166: unsigned((20 - 1) downto 0);
signal plbrstreg_12_24_next: boolean;
signal plbrstreg_12_24: boolean := false;
signal plbabusreg_13_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_13_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_14_28_next: boolean;
signal plbpavalidreg_14_28: boolean := false;
signal plbrnwreg_15_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_15_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_16_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_16_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_28_23_next: boolean;
signal avalidreg_28_23: boolean := false;
signal ps1reg_39_20_next: boolean;
signal ps1reg_39_20: boolean := false;
signal psreg_47_19_next: boolean;
signal psreg_47_19: boolean := false;
type array_type_rdcompdelay_58_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25: array_type_rdcompdelay_58_25 := (
"0",
"0",
"0");
signal rdcompdelay_58_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_58_25_push_front_pop_back_en: std_logic;
signal rdcompreg_62_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_62_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_66_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_66_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_70_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_70_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_84_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_84_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_20_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_21_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_32_1_slice: unsigned((20 - 1) downto 0);
signal rel_33_4: boolean;
signal ps1_join_33_1: boolean;
signal ps_42_1_bit: boolean;
signal bitnot_49_49: boolean;
signal bitnot_49_73: boolean;
signal bit_49_49: boolean;
signal addrack_49_1_convert: unsigned((1 - 1) downto 0);
signal bit_55_43: unsigned((1 - 1) downto 0);
signal bitnot_72_35: unsigned((1 - 1) downto 0);
signal wrdackreg_72_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_76_1_bit: unsigned((1 - 1) downto 0);
signal rel_78_4: boolean;
signal rddbus1_join_78_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_97_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_12_24_next_x_000000: boolean;
signal plbpavalidreg_14_28_next_x_000000: boolean;
begin
plbrst_1_110 <= std_logic_vector_to_unsigned(plbrst);
plbabus_1_118 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_1_127 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_1_139 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_1_147 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_1_158 <= std_logic_vector_to_unsigned(rddata);
addrpref_1_166 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_12_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_12_24 <= plbrstreg_12_24_next;
end if;
end if;
end process proc_plbrstreg_12_24;
proc_plbabusreg_13_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_13_25 <= plbabusreg_13_25_next;
end if;
end if;
end process proc_plbabusreg_13_25;
proc_plbpavalidreg_14_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_14_28 <= plbpavalidreg_14_28_next;
end if;
end if;
end process proc_plbpavalidreg_14_28;
proc_plbrnwreg_15_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_15_24 <= plbrnwreg_15_24_next;
end if;
end if;
end process proc_plbrnwreg_15_24;
proc_plbwrdbusreg_16_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_16_27 <= plbwrdbusreg_16_27_next;
end if;
end if;
end process proc_plbwrdbusreg_16_27;
proc_avalidreg_28_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_28_23 <= avalidreg_28_23_next;
end if;
end if;
end process proc_avalidreg_28_23;
proc_ps1reg_39_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_39_20 <= ps1reg_39_20_next;
end if;
end if;
end process proc_ps1reg_39_20;
proc_psreg_47_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_47_19 <= psreg_47_19_next;
end if;
end if;
end process proc_psreg_47_19;
rdcompdelay_58_25_back <= rdcompdelay_58_25(2);
proc_rdcompdelay_58_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_58_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_58_25(i) <= rdcompdelay_58_25(i-1);
end loop;
rdcompdelay_58_25(0) <= rdcompdelay_58_25_front_din;
end if;
end if;
end process proc_rdcompdelay_58_25;
proc_rdcompreg_62_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_62_23 <= rdcompreg_62_23_next;
end if;
end if;
end process proc_rdcompreg_62_23;
proc_rddackreg_66_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_66_23 <= rddackreg_66_23_next;
end if;
end if;
end process proc_rddackreg_66_23;
proc_wrdackreg_70_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_70_23 <= wrdackreg_70_23_next;
end if;
end if;
end process proc_wrdackreg_70_23;
proc_rddbusreg_84_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_84_23 <= rddbusreg_84_23_next;
end if;
end if;
end process proc_rddbusreg_84_23;
bankaddr_20_1_slice <= u2u_slice(plbabusreg_13_25, 11, 10);
linearaddr_21_1_slice <= u2u_slice(plbabusreg_13_25, 9, 2);
addrpref_in_32_1_slice <= u2u_slice(plbabusreg_13_25, 31, 12);
rel_33_4 <= addrpref_in_32_1_slice = addrpref_1_166;
proc_if_33_1: process (rel_33_4)
is
begin
if rel_33_4 then
ps1_join_33_1 <= true;
else
ps1_join_33_1 <= false;
end if;
end process proc_if_33_1;
ps_42_1_bit <= ((boolean_to_vector(ps1_join_33_1) and boolean_to_vector(plbpavalidreg_14_28)) = "1");
bitnot_49_49 <= ((not boolean_to_vector(plbrstreg_12_24)) = "1");
bitnot_49_73 <= ((not boolean_to_vector(psreg_47_19)) = "1");
bit_49_49 <= ((boolean_to_vector(bitnot_49_49) and boolean_to_vector(ps_42_1_bit) and boolean_to_vector(bitnot_49_73)) = "1");
addrack_49_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_49_49)), 0, 1, 0);
bit_55_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_15_24));
bitnot_72_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_15_24));
wrdackreg_72_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_49_1_convert) and unsigned_to_std_logic_vector(bitnot_72_35));
rdsel_76_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_58_25_back) or unsigned_to_std_logic_vector(rdcompreg_62_23));
rel_78_4 <= rdsel_76_1_bit = std_logic_vector_to_unsigned("1");
proc_if_78_1: process (rddata_1_158, rel_78_4)
is
begin
if rel_78_4 then
rddbus1_join_78_1 <= rddata_1_158;
else
rddbus1_join_78_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_78_1;
plbwrdbusreg_97_1_slice <= u2u_slice(plbwrdbus_1_147, 31, 0);
plbrstreg_12_24_next_x_000000 <= (plbrst_1_110 /= "0");
plbrstreg_12_24_next <= plbrstreg_12_24_next_x_000000;
plbabusreg_13_25_next <= plbabus_1_118;
plbpavalidreg_14_28_next_x_000000 <= (plbpavalid_1_127 /= "0");
plbpavalidreg_14_28_next <= plbpavalidreg_14_28_next_x_000000;
plbrnwreg_15_24_next <= plbrnw_1_139;
plbwrdbusreg_16_27_next <= plbwrdbusreg_97_1_slice;
avalidreg_28_23_next <= plbpavalidreg_14_28;
ps1reg_39_20_next <= ps1_join_33_1;
psreg_47_19_next <= ps_42_1_bit;
rdcompdelay_58_25_front_din <= bit_55_43;
rdcompdelay_58_25_push_front_pop_back_en <= '1';
rdcompreg_62_23_next <= rdcompdelay_58_25_back;
rddackreg_66_23_next <= rdcompreg_62_23;
wrdackreg_70_23_next <= wrdackreg_72_1_bit;
rddbusreg_84_23_next <= rddbus1_join_78_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_16_27);
addrack <= unsigned_to_std_logic_vector(addrack_49_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_62_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_70_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_20_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_15_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_66_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_84_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_21_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_2c4e41848b is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_bayer_ctrl : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_bayer_ctrl_din : out std_logic_vector((32 - 1) downto 0);
sm_bayer_ctrl_en : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_2c4e41848b;
architecture behavior of mcode_block_2c4e41848b is
signal wrdbus_1_76: unsigned((32 - 1) downto 0);
signal bankaddr_1_84: unsigned((2 - 1) downto 0);
signal linearaddr_1_94: unsigned((8 - 1) downto 0);
signal rnwreg_1_106: unsigned((1 - 1) downto 0);
signal addrack_1_114: unsigned((1 - 1) downto 0);
signal sm_bayer_ctrl_1_123: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_19_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_19_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal read_bank_out_reg_72_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_72_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_75_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_75_26: unsigned((2 - 1) downto 0) := "00";
signal opcode_31_1_concat: unsigned((12 - 1) downto 0);
signal rel_52_4: boolean;
signal sm_bayer_ctrl_en_join_52_1: boolean;
signal slice_67_38: unsigned((32 - 1) downto 0);
signal rel_77_4: boolean;
signal rel_80_8: boolean;
signal rel_83_8: boolean;
signal rel_86_8: boolean;
signal read_bank_out_reg_join_77_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_76 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_84 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_94 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_106 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_114 <= std_logic_vector_to_unsigned(addrack);
sm_bayer_ctrl_1_123 <= std_logic_vector_to_unsigned(sm_bayer_ctrl);
proc_reg_bank_out_reg_19_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_19_30 <= reg_bank_out_reg_19_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_19_30;
proc_read_bank_out_reg_72_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_72_31 <= read_bank_out_reg_72_31_next;
end if;
end if;
end process proc_read_bank_out_reg_72_31;
proc_bankaddr_reg_75_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_75_26 <= bankaddr_reg_75_26_next;
end if;
end if;
end process proc_bankaddr_reg_75_26;
opcode_31_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_114) & unsigned_to_std_logic_vector(rnwreg_1_106) & unsigned_to_std_logic_vector(bankaddr_1_84) & unsigned_to_std_logic_vector(linearaddr_1_94));
rel_52_4 <= opcode_31_1_concat = std_logic_vector_to_unsigned("101000000000");
proc_if_52_1: process (rel_52_4)
is
begin
if rel_52_4 then
sm_bayer_ctrl_en_join_52_1 <= true;
else
sm_bayer_ctrl_en_join_52_1 <= false;
end if;
end process proc_if_52_1;
slice_67_38 <= u2u_slice(wrdbus_1_76, 31, 0);
rel_77_4 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("00");
rel_80_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("01");
rel_83_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("10");
rel_86_8 <= bankaddr_reg_75_26 = std_logic_vector_to_unsigned("11");
proc_if_77_1: process (read_bank_out_reg_72_31, reg_bank_out_reg_19_30, rel_77_4, rel_80_8, rel_83_8, rel_86_8)
is
begin
if rel_77_4 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_80_8 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_83_8 then
read_bank_out_reg_join_77_1 <= reg_bank_out_reg_19_30;
elsif rel_86_8 then
read_bank_out_reg_join_77_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_77_1 <= read_bank_out_reg_72_31;
end if;
end process proc_if_77_1;
reg_bank_out_reg_19_30_next <= sm_bayer_ctrl_1_123;
read_bank_out_reg_72_31_next <= read_bank_out_reg_join_77_1;
bankaddr_reg_75_26_next <= bankaddr_1_84;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_72_31);
sm_bayer_ctrl_din <= unsigned_to_std_logic_vector(slice_67_38);
sm_bayer_ctrl_en <= boolean_to_vector(sm_bayer_ctrl_en_join_52_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_1a0db76efe is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((2 - 1) downto 0);
d1 : in std_logic_vector((2 - 1) downto 0);
d2 : in std_logic_vector((2 - 1) downto 0);
d3 : in std_logic_vector((2 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_1a0db76efe;
architecture behavior of mux_1a0db76efe is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((2 - 1) downto 0);
signal d1_1_27: std_logic_vector((2 - 1) downto 0);
signal d2_1_30: std_logic_vector((2 - 1) downto 0);
signal d3_1_33: std_logic_vector((2 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((2 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_5753e4c658 is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_5753e4c658;
architecture behavior of delay_5753e4c658 is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_a3ccf865c7 is
port (
d : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_a3ccf865c7;
architecture behavior of delay_a3ccf865c7 is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((1 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_332f1d2335 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_332f1d2335;
architecture behavior of expr_332f1d2335 is
signal d0_1_24: unsigned((1 - 1) downto 0);
signal d1_1_28: unsigned((1 - 1) downto 0);
signal bitnot_5_36: unsigned((1 - 1) downto 0);
signal fulldout_5_2_bit: unsigned((1 - 1) downto 0);
begin
d0_1_24 <= std_logic_vector_to_unsigned(d0);
d1_1_28 <= std_logic_vector_to_unsigned(d1);
bitnot_5_36 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(d0_1_24));
fulldout_5_2_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(d1_1_28) and unsigned_to_std_logic_vector(bitnot_5_36));
dout <= unsigned_to_std_logic_vector(fulldout_5_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_3c2515cf08 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_3c2515cf08;
architecture behavior of expr_3c2515cf08 is
signal a_1_24: boolean;
signal b_1_27: boolean;
signal fulldout_5_2_bit: boolean;
begin
a_1_24 <= ((a) = "1");
b_1_27 <= ((b) = "1");
fulldout_5_2_bit <= ((boolean_to_vector(b_1_27) and boolean_to_vector(a_1_24)) = "1");
dout <= boolean_to_vector(fulldout_5_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component cntr_11_0_3eb0c8dcd9c22b4d
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of cntr_11_0_3eb0c8dcd9c22b4d:
component is true;
attribute fpga_dont_touch of cntr_11_0_3eb0c8dcd9c22b4d:
component is "true";
attribute box_type of cntr_11_0_3eb0c8dcd9c22b4d:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "cntr_11_0_3eb0c8dcd9c22b4d")) generate
core_instance0: cntr_11_0_3eb0c8dcd9c22b4d
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
en : in std_logic_vector (en_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0) generate
reg : synth_reg
generic map (
width => dout_width,
latency => latency
)
port map (
i => result,
ce => internal_ce,
clr => clr,
clk => clk,
o => dout
);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_c_in : integer := 0;
c_has_c_out : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if (delta > 0) then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component addsb_11_0_c25f95ce6b0868c9
port (
a: in std_logic_vector(11 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(11 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_c25f95ce6b0868c9:
component is true;
attribute fpga_dont_touch of addsb_11_0_c25f95ce6b0868c9:
component is "true";
attribute box_type of addsb_11_0_c25f95ce6b0868c9:
component is "black_box";
component addsb_11_0_a629aff4db5bb1c8
port (
a: in std_logic_vector(12 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(12 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_a629aff4db5bb1c8:
component is true;
attribute fpga_dont_touch of addsb_11_0_a629aff4db5bb1c8:
component is "true";
attribute box_type of addsb_11_0_a629aff4db5bb1c8:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process (a, b, core_s)
begin
full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "addsb_11_0_c25f95ce6b0868c9")) generate
core_instance0: addsb_11_0_c25f95ce6b0868c9
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "addsb_11_0_a629aff4db5bb1c8")) generate
core_instance1: addsb_11_0_a629aff4db5bb1c8
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency
)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if ((c_latency = 0) or (c_latency = 1)) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test: if (c_has_c_out = 1) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if (((latency = 0) or (extra_registers = 0)) and
(c_has_c_out = 1)) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if (c_has_c_out = 0) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_e6f5ee726b is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_e6f5ee726b;
architecture behavior of concat_e6f5ee726b is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((2 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d0d1b9533e is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_d0d1b9533e;
architecture behavior of concat_d0d1b9533e is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_33cb3f7e58 is
port (
d : in std_logic_vector((10 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_33cb3f7e58;
architecture behavior of delay_33cb3f7e58 is
signal d_1_22: std_logic_vector((10 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "0000000000");
signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_0025330cf4 is
port (
d : in std_logic_vector((2 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_0025330cf4;
architecture behavior of delay_0025330cf4 is
signal d_1_22: std_logic_vector((2 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "00");
signal op_mem_20_24_front_din: std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((2 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((2 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_ec78404abf is
port (
d : in std_logic_vector((12 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_ec78404abf;
architecture behavior of delay_ec78404abf is
signal d_1_22: std_logic_vector((12 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "000000000000");
signal op_mem_20_24_front_din: std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((12 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((12 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_0fbdd36101 is
port (
d : in std_logic_vector((10 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_0fbdd36101;
architecture behavior of delay_0fbdd36101 is
signal d_1_22: std_logic_vector((10 - 1) downto 0);
signal en_1_25: std_logic;
type array_type_op_mem_20_24 is array (0 to (2 - 1)) of std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"0000000000",
"0000000000");
signal op_mem_20_24_front_din: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((10 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
signal op_mem_shift_join_27_9: std_logic_vector((10 - 1) downto 0);
signal op_mem_shift_join_27_9_en: std_logic;
begin
d_1_22 <= d;
en_1_25 <= en(0);
op_mem_20_24_back <= op_mem_20_24(1);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 1 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
proc_if_27_9: process (d_1_22, en_1_25)
is
begin
if en_1_25 = '1' then
op_mem_shift_join_27_9_en <= '1';
else
op_mem_shift_join_27_9_en <= '0';
end if;
op_mem_shift_join_27_9 <= d_1_22;
end process proc_if_27_9;
op_mem_20_24_front_din <= op_mem_shift_join_27_9;
op_mem_20_24_push_front_pop_back_en <= op_mem_shift_join_27_9_en;
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_4fe5face7f is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((10 - 1) downto 0);
d1 : in std_logic_vector((10 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_4fe5face7f;
architecture behavior of mux_4fe5face7f is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((10 - 1) downto 0);
signal d1_1_27: std_logic_vector((10 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_61418c8488 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((10 - 1) downto 0);
d1 : in std_logic_vector((10 - 1) downto 0);
d2 : in std_logic_vector((10 - 1) downto 0);
d3 : in std_logic_vector((10 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_61418c8488;
architecture behavior of mux_61418c8488 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((10 - 1) downto 0);
signal d1_1_27: std_logic_vector((10 - 1) downto 0);
signal d2_1_30: std_logic_vector((10 - 1) downto 0);
signal d3_1_33: std_logic_vector((10 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((10 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity shift_d9577b2c80 is
port (
ip : in std_logic_vector((11 - 1) downto 0);
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end shift_d9577b2c80;
architecture behavior of shift_d9577b2c80 is
signal ip_1_23: unsigned((11 - 1) downto 0);
type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0);
signal op_mem_46_20: array_type_op_mem_46_20 := (
0 => "000000000000");
signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0);
signal op_mem_46_20_back: unsigned((12 - 1) downto 0);
signal op_mem_46_20_push_front_pop_back_en: std_logic;
signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0);
begin
ip_1_23 <= std_logic_vector_to_unsigned(ip);
op_mem_46_20_back <= op_mem_46_20(0);
proc_op_mem_46_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then
op_mem_46_20(0) <= op_mem_46_20_front_din;
end if;
end if;
end process proc_op_mem_46_20;
cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 1);
op_mem_46_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity shift_0a73a8a346 is
port (
ip : in std_logic_vector((10 - 1) downto 0);
op : out std_logic_vector((12 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end shift_0a73a8a346;
architecture behavior of shift_0a73a8a346 is
signal ip_1_23: unsigned((10 - 1) downto 0);
type array_type_op_mem_46_20 is array (0 to (1 - 1)) of unsigned((12 - 1) downto 0);
signal op_mem_46_20: array_type_op_mem_46_20 := (
0 => "000000000000");
signal op_mem_46_20_front_din: unsigned((12 - 1) downto 0);
signal op_mem_46_20_back: unsigned((12 - 1) downto 0);
signal op_mem_46_20_push_front_pop_back_en: std_logic;
signal cast_internal_ip_25_3_lsh: unsigned((12 - 1) downto 0);
begin
ip_1_23 <= std_logic_vector_to_unsigned(ip);
op_mem_46_20_back <= op_mem_46_20(0);
proc_op_mem_46_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_46_20_push_front_pop_back_en = '1')) then
op_mem_46_20(0) <= op_mem_46_20_front_din;
end if;
end if;
end process proc_op_mem_46_20;
cast_internal_ip_25_3_lsh <= u2u_cast(ip_1_23, 0, 12, 2);
op_mem_46_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(cast_internal_ip_25_3_lsh);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlspram is
generic (
core_name0: string := "";
c_width: integer := 12;
c_address_width: integer := 4;
latency: integer := 1
);
port (
data_in: in std_logic_vector(c_width - 1 downto 0);
addr: in std_logic_vector(c_address_width - 1 downto 0);
we: in std_logic_vector(0 downto 0);
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0);
ce: in std_logic;
clk: in std_logic;
data_out: out std_logic_vector(c_width - 1 downto 0)
);
end xlspram ;
architecture behavior of xlspram is
component synth_reg
generic (
width: integer;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal core_data_out, dly_data_out: std_logic_vector(c_width - 1 downto 0);
signal core_we, core_ce, sinit: std_logic;
component bmg_62_2be284cffc9a51ef
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
dina: in std_logic_vector(c_width - 1 downto 0);
wea: in std_logic_vector(0 downto 0);
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_2be284cffc9a51ef:
component is true;
attribute fpga_dont_touch of bmg_62_2be284cffc9a51ef:
component is "true";
attribute box_type of bmg_62_2be284cffc9a51ef:
component is "black_box";
begin
data_out <= dly_data_out;
core_we <= we(0);
core_ce <= ce and en(0);
sinit <= rst(0) and ce;
comp0: if ((core_name0 = "bmg_62_2be284cffc9a51ef")) generate
core_instance0: bmg_62_2be284cffc9a51ef
port map (
addra => addr,
clka => clk,
dina => data_in,
wea(0) => core_we,
ena => core_ce,
douta => core_data_out
);
end generate;
latency_test: if (latency > 1) generate
reg: synth_reg
generic map (
width => c_width,
latency => latency - 1
)
port map (
i => core_data_out,
ce => core_ce,
clr => '0',
clk => clk,
o => dly_data_out
);
end generate;
latency_1: if (latency <= 1) generate
dly_data_out <= core_data_out;
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_1b0d89c05a is
port (
d : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_1b0d89c05a;
architecture behavior of delay_1b0d89c05a is
signal d_1_22: std_logic_vector((1 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (7 - 1)) of std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
"0",
"0",
"0",
"0",
"0",
"0",
"0");
signal op_mem_20_24_front_din: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((1 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(6);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
for i in 6 downto 1 loop
op_mem_20_24(i) <= op_mem_20_24(i-1);
end loop;
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_e1f6cb3ad9 is
port (
d : in std_logic_vector((24 - 1) downto 0);
q : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_e1f6cb3ad9;
architecture behavior of delay_e1f6cb3ad9 is
signal d_1_22: std_logic_vector((24 - 1) downto 0);
type array_type_op_mem_20_24 is array (0 to (1 - 1)) of std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24: array_type_op_mem_20_24 := (
0 => "000000000000000000000000");
signal op_mem_20_24_front_din: std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24_back: std_logic_vector((24 - 1) downto 0);
signal op_mem_20_24_push_front_pop_back_en: std_logic;
begin
d_1_22 <= d;
op_mem_20_24_back <= op_mem_20_24(0);
proc_op_mem_20_24: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_20_24_push_front_pop_back_en = '1')) then
op_mem_20_24(0) <= op_mem_20_24_front_din;
end if;
end if;
end process proc_op_mem_20_24;
op_mem_20_24_front_din <= d_1_22;
op_mem_20_24_push_front_pop_back_en <= '1';
q <= op_mem_20_24_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlsprom is
generic (
core_name0: string := "";
c_width: integer := 12;
c_address_width: integer := 4;
latency: integer := 1
);
port (
addr: in std_logic_vector(c_address_width - 1 downto 0);
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0);
ce: in std_logic;
clk: in std_logic;
data: out std_logic_vector(c_width - 1 downto 0)
);
end xlsprom ;
architecture behavior of xlsprom is
component synth_reg
generic (
width: integer;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal core_addr: std_logic_vector(c_address_width - 1 downto 0);
signal core_data_out: std_logic_vector(c_width - 1 downto 0);
signal core_ce, sinit: std_logic;
component bmg_62_efdcd0e54d01b373
port (
addra: in std_logic_vector(c_address_width - 1 downto 0);
clka: in std_logic;
ena: in std_logic;
douta: out std_logic_vector(c_width - 1 downto 0)
);
end component;
attribute syn_black_box of bmg_62_efdcd0e54d01b373:
component is true;
attribute fpga_dont_touch of bmg_62_efdcd0e54d01b373:
component is "true";
attribute box_type of bmg_62_efdcd0e54d01b373:
component is "black_box";
begin
core_addr <= addr;
core_ce <= ce and en(0);
sinit <= rst(0) and ce;
comp0: if ((core_name0 = "bmg_62_efdcd0e54d01b373")) generate
core_instance0: bmg_62_efdcd0e54d01b373
port map (
addra => core_addr,
clka => clk,
ena => core_ce,
douta => core_data_out
);
end generate;
latency_test: if (latency > 1) generate
reg: synth_reg
generic map (
width => c_width,
latency => latency - 1
)
port map (
i => core_data_out,
ce => core_ce,
clr => '0',
clk => clk,
o => data
);
end generate;
latency_1: if (latency <= 1) generate
data <= core_data_out;
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_8712d31083 is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((2 - 1) downto 0);
y : out std_logic_vector((10 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_8712d31083;
architecture behavior of concat_8712d31083 is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((2 - 1) downto 0);
signal y_2_1_concat: unsigned((10 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_cda50df78a is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_cda50df78a;
architecture behavior of constant_cda50df78a is
begin
op <= "00";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/EDK Processor"
entity edk_processor_entity_33f025737d is
port (
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(31 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(31 downto 0);
plb_memmap_x1: out std_logic
);
end edk_processor_entity_33f025737d;
architecture structural of edk_processor_entity_33f025737d is
signal bankaddr: std_logic_vector(1 downto 0);
signal bayer_ctrl_din_x0: std_logic_vector(31 downto 0);
signal bayer_ctrl_dout_x0: std_logic_vector(31 downto 0);
signal bayer_ctrl_en_x0: std_logic;
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x0: std_logic;
signal plb_clk_1_sg_x0: std_logic;
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
plb_abus_net_x0 <= plb_abus;
plb_ce_1_sg_x0 <= plb_ce_1;
plb_clk_1_sg_x0 <= plb_clk_1;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
bayer_ctrl_dout_x0 <= to_register;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= bayer_ctrl_din_x0;
plb_memmap_x1 <= bayer_ctrl_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_f4d0462e0e
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_2c4e41848b
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => plb_ce_1_sg_x0,
clk => plb_clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_bayer_ctrl => bayer_ctrl_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_bayer_ctrl_din => bayer_ctrl_din_x0,
sm_bayer_ctrl_en(0) => bayer_ctrl_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer/Subsystem"
entity subsystem_entity_387011edf3 is
port (
from_register: in std_logic_vector(31 downto 0);
pos: in std_logic_vector(1 downto 0);
bsel: out std_logic_vector(1 downto 0);
gsel: out std_logic;
rsel: out std_logic_vector(1 downto 0)
);
end subsystem_entity_387011edf3;
architecture structural of subsystem_entity_387011edf3 is
signal delay15_q_net_x0: std_logic_vector(1 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(31 downto 0);
signal mux7_y_net_x0: std_logic_vector(1 downto 0);
signal mux8_y_net: std_logic_vector(1 downto 0);
signal mux9_y_net_x0: std_logic_vector(1 downto 0);
signal slice10_y_net: std_logic_vector(1 downto 0);
signal slice11_y_net: std_logic_vector(1 downto 0);
signal slice12_y_net: std_logic_vector(1 downto 0);
signal slice13_y_net: std_logic_vector(1 downto 0);
signal slice14_y_net: std_logic_vector(1 downto 0);
signal slice17_y_net_x0: std_logic;
signal slice3_y_net: std_logic_vector(1 downto 0);
signal slice4_y_net: std_logic_vector(1 downto 0);
signal slice5_y_net: std_logic_vector(1 downto 0);
signal slice6_y_net: std_logic_vector(1 downto 0);
signal slice7_y_net: std_logic_vector(1 downto 0);
signal slice8_y_net: std_logic_vector(1 downto 0);
signal slice9_y_net: std_logic_vector(1 downto 0);
begin
from_register_data_out_net_x0 <= from_register;
delay15_q_net_x0 <= pos;
bsel <= mux9_y_net_x0;
gsel <= slice17_y_net_x0;
rsel <= mux7_y_net_x0;
mux7: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice5_y_net,
d1 => slice4_y_net,
d2 => slice3_y_net,
d3 => slice6_y_net,
sel => delay15_q_net_x0,
y => mux7_y_net_x0
);
mux8: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice9_y_net,
d1 => slice8_y_net,
d2 => slice7_y_net,
d3 => slice10_y_net,
sel => delay15_q_net_x0,
y => mux8_y_net
);
mux9: entity work.mux_1a0db76efe
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice14_y_net,
d1 => slice13_y_net,
d2 => slice12_y_net,
d3 => slice11_y_net,
sel => delay15_q_net_x0,
y => mux9_y_net_x0
);
slice10: entity work.xlslice
generic map (
new_lsb => 14,
new_msb => 15,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice10_y_net
);
slice11: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 7,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice11_y_net
);
slice12: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 5,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice12_y_net
);
slice13: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 3,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice13_y_net
);
slice14: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice14_y_net
);
slice17: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 2,
y_width => 1
)
port map (
x => mux8_y_net,
y(0) => slice17_y_net_x0
);
slice3: entity work.xlslice
generic map (
new_lsb => 20,
new_msb => 21,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 18,
new_msb => 19,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 17,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 22,
new_msb => 23,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 12,
new_msb => 13,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 11,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 9,
x_width => 32,
y_width => 2
)
port map (
x => from_register_data_out_net_x0,
y => slice9_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer/xy_ctrs"
entity xy_ctrs_entity_9e9b1c9cc9 is
port (
av: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
en: in std_logic;
vb: in std_logic;
x: out std_logic_vector(11 downto 0);
y: out std_logic_vector(11 downto 0)
);
end xy_ctrs_entity_9e9b1c9cc9;
architecture structural of xy_ctrs_entity_9e9b1c9cc9 is
signal active_video_i_net_x0: std_logic;
signal bool1_dout_net: std_logic;
signal bool2_dout_net: std_logic;
signal bool3_dout_net: std_logic;
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal delay20_q_net: std_logic;
signal delay21_q_net: std_logic;
signal enable_op_net_x0: std_logic;
signal expression1_dout_net: std_logic;
signal expression3_dout_net: std_logic;
signal expression_dout_net: std_logic;
signal inverter_op_net: std_logic;
signal vblank_i_net_x0: std_logic;
signal xcounter_op_net_x0: std_logic_vector(11 downto 0);
signal ycounter_op_net_x0: std_logic_vector(11 downto 0);
begin
active_video_i_net_x0 <= av;
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
enable_op_net_x0 <= en;
vblank_i_net_x0 <= vb;
x <= xcounter_op_net_x0;
y <= ycounter_op_net_x0;
bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => expression3_dout_net,
en => "1",
dout(0) => bool1_dout_net
);
bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => active_video_i_net_x0,
en => "1",
dout(0) => bool2_dout_net
);
bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
din(0) => expression_dout_net,
en => "1",
dout(0) => bool3_dout_net
);
delay20: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
d(0) => vblank_i_net_x0,
q(0) => delay20_q_net
);
delay21: entity work.delay_a3ccf865c7
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
d(0) => active_video_i_net_x0,
en(0) => enable_op_net_x0,
q(0) => delay21_q_net
);
expression: entity work.expr_332f1d2335
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => vblank_i_net_x0,
d1(0) => delay20_q_net,
dout(0) => expression_dout_net
);
expression1: entity work.expr_3c2515cf08
port map (
a(0) => bool1_dout_net,
b(0) => enable_op_net_x0,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
expression3: entity work.expr_332f1d2335
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => active_video_i_net_x0,
d1(0) => delay21_q_net,
dout(0) => expression3_dout_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip(0) => bool2_dout_net,
op(0) => inverter_op_net
);
xcounter: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d",
op_arith => xlUnsigned,
op_width => 12
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => enable_op_net_x0,
rst(0) => inverter_op_net,
op => xcounter_op_net_x0
);
ycounter: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3eb0c8dcd9c22b4d",
op_arith => xlUnsigned,
op_width => 12
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => expression1_dout_net,
rst(0) => bool3_dout_net,
op => ycounter_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/bayer"
entity bayer_entity_7e9fc9cbc8 is
port (
avi: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(31 downto 0);
hbi: in std_logic;
hsi: in std_logic;
vbi: in std_logic;
vdi: in std_logic_vector(9 downto 0);
vsi: in std_logic;
avo: out std_logic;
hbo: out std_logic;
hso: out std_logic;
vbo: out std_logic;
vdo: out std_logic_vector(23 downto 0);
vso: out std_logic
);
end bayer_entity_7e9fc9cbc8;
architecture structural of bayer_entity_7e9fc9cbc8 is
signal active_video_delay_q_net_x0: std_logic;
signal active_video_i_net_x1: std_logic;
signal addsub1_s_net: std_logic_vector(10 downto 0);
signal addsub5_s_net: std_logic_vector(10 downto 0);
signal bayer_conv: std_logic_vector(9 downto 0);
signal blue: std_logic_vector(9 downto 0);
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal concat1_y_net: std_logic_vector(23 downto 0);
signal concat2_y_net_x0: std_logic_vector(9 downto 0);
signal concat_y_net: std_logic_vector(1 downto 0);
signal convert_dout_net: std_logic;
signal d0: std_logic_vector(9 downto 0);
signal d1: std_logic_vector(9 downto 0);
signal d3: std_logic_vector(9 downto 0);
signal data_delay_q_net_x0: std_logic_vector(23 downto 0);
signal davg: std_logic_vector(11 downto 0);
signal davg_x0: std_logic_vector(11 downto 0);
signal davg_x1: std_logic_vector(9 downto 0);
signal delay10_q_net: std_logic_vector(9 downto 0);
signal delay11_q_net: std_logic_vector(9 downto 0);
signal delay12_q_net: std_logic_vector(9 downto 0);
signal delay13_q_net: std_logic_vector(9 downto 0);
signal delay14_q_net: std_logic_vector(9 downto 0);
signal delay15_q_net_x0: std_logic_vector(1 downto 0);
signal delay17_q_net: std_logic_vector(11 downto 0);
signal delay19_q_net: std_logic_vector(11 downto 0);
signal delay1_q_net: std_logic_vector(9 downto 0);
signal delay20_q_net: std_logic_vector(11 downto 0);
signal delay5_q_net: std_logic_vector(11 downto 0);
signal delay6_q_net: std_logic_vector(11 downto 0);
signal delay9_q_net: std_logic_vector(9 downto 0);
signal dir: std_logic_vector(11 downto 0);
signal dir_x0: std_logic_vector(9 downto 0);
signal enable_op_net_x0: std_logic;
signal from_register_data_out_net_x1: std_logic_vector(31 downto 0);
signal green: std_logic_vector(9 downto 0);
signal havg: std_logic_vector(10 downto 0);
signal havg_x0: std_logic_vector(11 downto 0);
signal havg_x1: std_logic_vector(9 downto 0);
signal hblank_delay_q_net_x0: std_logic;
signal hblank_i_net_x0: std_logic;
signal hsync_delay_q_net_x0: std_logic;
signal hsync_i_net_x0: std_logic;
signal mux7_y_net_x0: std_logic_vector(1 downto 0);
signal mux9_y_net_x0: std_logic_vector(1 downto 0);
signal red: std_logic_vector(9 downto 0);
signal single_port_ram_data_out_net: std_logic_vector(9 downto 0);
signal slice15_y_net: std_logic_vector(10 downto 0);
signal slice16_y_net: std_logic_vector(10 downto 0);
signal slice17_y_net_x0: std_logic;
signal slice6_y_net: std_logic;
signal slice7_y_net: std_logic_vector(7 downto 0);
signal slice8_y_net: std_logic_vector(7 downto 0);
signal slice9_y_net: std_logic_vector(7 downto 0);
signal slice_y_net: std_logic;
signal vavg: std_logic_vector(10 downto 0);
signal vavg_x0: std_logic_vector(11 downto 0);
signal vavg_x1: std_logic_vector(9 downto 0);
signal vblank_delay_q_net_x0: std_logic;
signal vblank_i_net_x1: std_logic;
signal vsync_delay_q_net_x0: std_logic;
signal vsync_i_net_x0: std_logic;
signal xavg: std_logic_vector(9 downto 0);
signal xcounter_op_net_x0: std_logic_vector(11 downto 0);
signal ycounter_op_net_x0: std_logic_vector(11 downto 0);
begin
active_video_i_net_x1 <= avi;
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
from_register_data_out_net_x1 <= from_register;
hblank_i_net_x0 <= hbi;
hsync_i_net_x0 <= hsi;
vblank_i_net_x1 <= vbi;
concat2_y_net_x0 <= vdi;
vsync_i_net_x0 <= vsi;
avo <= active_video_delay_q_net_x0;
hbo <= hblank_delay_q_net_x0;
hso <= hsync_delay_q_net_x0;
vbo <= vblank_delay_q_net_x0;
vdo <= data_delay_q_net_x0;
vso <= vsync_delay_q_net_x0;
active_video_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => active_video_i_net_x1,
q(0) => active_video_delay_q_net_x0
);
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d0,
b => delay12_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => addsub1_s_net
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => delay1_q_net,
b => delay11_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => vavg
);
addsub3: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 11,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 11,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 12,
core_name0 => "addsb_11_0_a629aff4db5bb1c8",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 12,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 12
)
port map (
a => havg,
b => vavg,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => davg
);
addsub5: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d3,
b => delay14_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => addsub5_s_net
);
addsub6: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 10,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 10,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 11,
core_name0 => "addsb_11_0_c25f95ce6b0868c9",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 11,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 11
)
port map (
a => d1,
b => delay13_q_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => havg
);
addsub7: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 11,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 11,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 12,
core_name0 => "addsb_11_0_a629aff4db5bb1c8",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 12,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 12
)
port map (
a => addsub1_s_net,
b => addsub5_s_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
en => "1",
s => davg_x0
);
concat: entity work.concat_e6f5ee726b
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => slice_y_net,
in1(0) => slice6_y_net,
y => concat_y_net
);
concat1: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => slice7_y_net,
in1 => slice8_y_net,
in2 => slice9_y_net,
y => concat1_y_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
din(0) => active_video_i_net_x1,
en => "1",
dout(0) => convert_dout_net
);
data_delay: entity work.delay_e1f6cb3ad9
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => concat1_y_net,
q => data_delay_q_net_x0
);
delay1: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d0,
en(0) => enable_op_net_x0,
q => delay1_q_net
);
delay10: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d1,
en(0) => enable_op_net_x0,
q => delay10_q_net
);
delay11: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => d3,
en(0) => enable_op_net_x0,
q => delay11_q_net
);
delay12: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay1_q_net,
en(0) => enable_op_net_x0,
q => delay12_q_net
);
delay13: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay10_q_net,
en(0) => enable_op_net_x0,
q => delay13_q_net
);
delay14: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay11_q_net,
en(0) => enable_op_net_x0,
q => delay14_q_net
);
delay15: entity work.delay_0025330cf4
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => concat_y_net,
en(0) => enable_op_net_x0,
q => delay15_q_net_x0
);
delay17: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => davg_x0,
en(0) => enable_op_net_x0,
q => delay17_q_net
);
delay19: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => dir,
en(0) => enable_op_net_x0,
q => delay19_q_net
);
delay20: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => davg,
en(0) => enable_op_net_x0,
q => delay20_q_net
);
delay5: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => havg_x0,
en(0) => enable_op_net_x0,
q => delay5_q_net
);
delay6: entity work.delay_ec78404abf
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => vavg_x0,
en(0) => enable_op_net_x0,
q => delay6_q_net
);
delay7: entity work.delay_0fbdd36101
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => delay9_q_net,
en(0) => enable_op_net_x0,
q => d0
);
delay8: entity work.delay_33cb3f7e58
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => single_port_ram_data_out_net,
en(0) => enable_op_net_x0,
q => d1
);
delay9: entity work.delay_0fbdd36101
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d => bayer_conv,
en(0) => enable_op_net_x0,
q => delay9_q_net
);
enable: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => enable_op_net_x0
);
hblank_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => hblank_i_net_x0,
q(0) => hblank_delay_q_net_x0
);
hsync_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => hsync_i_net_x0,
q(0) => hsync_delay_q_net_x0
);
mux2: entity work.mux_4fe5face7f
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => xavg,
sel(0) => slice17_y_net_x0,
y => green
);
mux3: entity work.mux_61418c8488
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => havg_x1,
d2 => vavg_x1,
d3 => davg_x1,
sel => mux9_y_net_x0,
y => blue
);
mux4: entity work.mux_61418c8488
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => dir_x0,
d1 => havg_x1,
d2 => vavg_x1,
d3 => davg_x1,
sel => mux7_y_net_x0,
y => red
);
shift: entity work.shift_d9577b2c80
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => havg,
op => havg_x0
);
shift1: entity work.shift_d9577b2c80
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => vavg,
op => vavg_x0
);
shift2: entity work.shift_0a73a8a346
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip => delay10_q_net,
op => dir
);
single_port_ram: entity work.xlspram
generic map (
c_address_width => 11,
c_width => 10,
core_name0 => "bmg_62_2be284cffc9a51ef",
latency => 1
)
port map (
addr => slice15_y_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
data_in => delay9_q_net,
en(0) => enable_op_net_x0,
rst => "0",
we(0) => convert_dout_net,
data_out => single_port_ram_data_out_net
);
single_port_ram1: entity work.xlspram
generic map (
c_address_width => 11,
c_width => 10,
core_name0 => "bmg_62_2be284cffc9a51ef",
latency => 1
)
port map (
addr => slice16_y_net,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
data_in => single_port_ram_data_out_net,
en(0) => enable_op_net_x0,
rst => "0",
we(0) => convert_dout_net,
data_out => d3
);
slice: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 12,
y_width => 1
)
port map (
x => ycounter_op_net_x0,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay17_q_net,
y => davg_x1
);
slice10: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 9,
x_width => 10,
y_width => 10
)
port map (
x => concat2_y_net_x0,
y => bayer_conv
);
slice15: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 10,
x_width => 12,
y_width => 11
)
port map (
x => xcounter_op_net_x0,
y => slice15_y_net
);
slice16: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 10,
x_width => 12,
y_width => 11
)
port map (
x => xcounter_op_net_x0,
y => slice16_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay5_q_net,
y => havg_x1
);
slice3: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay19_q_net,
y => dir_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay6_q_net,
y => vavg_x1
);
slice5: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 11,
x_width => 12,
y_width => 10
)
port map (
x => delay20_q_net,
y => xavg
);
slice6: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 12,
y_width => 1
)
port map (
x => xcounter_op_net_x0,
y(0) => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => red,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => green,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 9,
x_width => 10,
y_width => 8
)
port map (
x => blue,
y => slice9_y_net
);
subsystem_387011edf3: entity work.subsystem_entity_387011edf3
port map (
from_register => from_register_data_out_net_x1,
pos => delay15_q_net_x0,
bsel => mux9_y_net_x0,
gsel => slice17_y_net_x0,
rsel => mux7_y_net_x0
);
vblank_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => vblank_i_net_x1,
q(0) => vblank_delay_q_net_x0
);
vsync_delay: entity work.delay_1b0d89c05a
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
d(0) => vsync_i_net_x0,
q(0) => vsync_delay_q_net_x0
);
xy_ctrs_9e9b1c9cc9: entity work.xy_ctrs_entity_9e9b1c9cc9
port map (
av => active_video_i_net_x1,
ce_1 => ce_1_sg_x1,
clk_1 => clk_1_sg_x1,
en => enable_op_net_x0,
vb => vblank_i_net_x1,
x => xcounter_op_net_x0,
y => ycounter_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma/gamma"
entity gamma_entity_43073d24ce is
port (
ce_1: in std_logic;
clk_1: in std_logic;
in1: in std_logic_vector(23 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end gamma_entity_43073d24ce;
architecture structural of gamma_entity_43073d24ce is
signal blue: std_logic_vector(7 downto 0);
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(23 downto 0);
signal data_delay_q_net_x1: std_logic_vector(23 downto 0);
signal green: std_logic_vector(7 downto 0);
signal red: std_logic_vector(7 downto 0);
signal rom_blue_data_net: std_logic_vector(7 downto 0);
signal rom_green_data_net: std_logic_vector(7 downto 0);
signal rom_red_data_net: std_logic_vector(7 downto 0);
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
data_delay_q_net_x1 <= in1;
out1 <= concat_y_net_x0;
concat: entity work.concat_d0d1b9533e
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => rom_red_data_net,
in1 => rom_green_data_net,
in2 => rom_blue_data_net,
y => concat_y_net_x0
);
rom_blue: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => blue,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_blue_data_net
);
rom_green: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => green,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_green_data_net
);
rom_red: entity work.xlsprom
generic map (
c_address_width => 8,
c_width => 8,
core_name0 => "bmg_62_efdcd0e54d01b373",
latency => 1
)
port map (
addr => red,
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
en => "1",
rst => "0",
data => rom_red_data_net
);
slice15downto8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => green
);
slice23downto16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => red
);
slice7downto0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 24,
y_width => 8
)
port map (
x => data_delay_q_net_x1,
y => blue
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "sg_cfa_gamma"
entity sg_cfa_gamma is
port (
active_video_i: in std_logic;
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(31 downto 0);
dout: in std_logic_vector(31 downto 0);
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_ce_1: in std_logic;
plb_clk_1: in std_logic;
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(7 downto 0);
vsync_i: in std_logic;
active_video_o: out std_logic;
data_in: out std_logic_vector(31 downto 0);
en: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_cfa_gamma;
architecture structural of sg_cfa_gamma is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "sg_cfa_gamma,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,sample_periods=1.00000000000 1.00000000000,testbench=0,total_blocks=223,xilinx_adder_subtracter_block=6,xilinx_binary_shift_operator_block=3,xilinx_bit_slice_extractor_block=29,xilinx_bitwise_expression_evaluator_block=3,xilinx_bus_concatenator_block=4,xilinx_bus_multiplexer_block=6,xilinx_constant_block_block=3,xilinx_counter_block=2,xilinx_delay_block=28,xilinx_edk_processor_block=1,xilinx_gateway_in_block=12,xilinx_gateway_out_block=22,xilinx_inverter_block=1,xilinx_mcode_block_block=2,xilinx_shared_memory_based_from_register_block=1,xilinx_shared_memory_based_to_register_block=1,xilinx_single_port_random_access_memory_block=2,xilinx_single_port_read_only_memory_block=3,xilinx_system_generator_block=1,xilinx_type_converter_block=4,}";
signal active_video_delay_q_net_x0: std_logic;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal ce_1_sg_x3: std_logic;
signal clk_1_sg_x3: std_logic;
signal concat2_y_net_x0: std_logic_vector(9 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal data_delay_q_net_x1: std_logic_vector(23 downto 0);
signal data_in_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal dout_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal hblank_delay_q_net_x0: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_delay_q_net_x0: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal vblank_delay_q_net_x0: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(7 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_delay_q_net_x0: std_logic;
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
ce_1_sg_x3 <= ce_1;
clk_1_sg_x3 <= clk_1;
data_out_net <= data_out;
dout_net <= dout;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_ce_1_sg_x1 <= plb_ce_1;
plb_clk_1_sg_x1 <= plb_clk_1;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
active_video_o <= active_video_o_net;
data_in <= data_in_net;
en <= en_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
bayer_7e9fc9cbc8: entity work.bayer_entity_7e9fc9cbc8
port map (
avi => active_video_i_net,
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
from_register => data_out_net,
hbi => hblank_i_net,
hsi => hsync_i_net,
vbi => vblank_i_net,
vdi => concat2_y_net_x0,
vsi => vsync_i_net,
avo => active_video_delay_q_net_x0,
hbo => hblank_delay_q_net_x0,
hso => hsync_delay_q_net_x0,
vbo => vblank_delay_q_net_x0,
vdo => data_delay_q_net_x1,
vso => vsync_delay_q_net_x0
);
concat2: entity work.concat_8712d31083
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => video_data_i_net,
in1 => constant_op_net,
y => concat2_y_net_x0
);
constant_x0: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
delay1: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => hsync_delay_q_net_x0,
q(0) => hsync_o_net
);
delay2: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => vblank_delay_q_net_x0,
q(0) => vblank_o_net
);
delay3: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => hblank_delay_q_net_x0,
q(0) => hblank_o_net
);
delay4: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => vsync_delay_q_net_x0,
q(0) => vsync_o_net
);
delay5: entity work.delay_5753e4c658
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
d(0) => active_video_delay_q_net_x0,
q(0) => active_video_o_net
);
edk_processor_33f025737d: entity work.edk_processor_entity_33f025737d
port map (
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
to_register => dout_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_net,
plb_memmap_x1 => en_net
);
gamma_43073d24ce: entity work.gamma_entity_43073d24ce
port map (
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
in1 => data_delay_q_net_x1,
out1 => video_data_o_net
);
end structural;
|
gpl-3.0
|
Alabamajack/Garfield
|
FPGA_Design/ip_intern/Rotary_Encoder/rotary_encoder.vhdl
|
1
|
2353
|
--! @file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rotary_encoder is
generic(
--! the nominal frequency of the clock
core_frequency : natural := 100_000_000;
--! the width of the outputed counter register
counter_width : natural := 32
);
port(
--! the clk from the core
clk : in std_logic;
--! general reset from the core
rst : in std_logic;
--! for clearing the internal counter, this signal must be HIGH
--! it only counts rising edges on the signal line!
clear_counter : in std_logic;
--! enable signal, if low, the counter will not count anymore
enable : in std_logic;
--! the counter register which contains counts since the last clear_counter or rst
counter : out std_logic_vector(counter_width - 1 downto 0);
--! shows if there was an error with the counting; if there was an error, the counter starts from zero
counter_error : out boolean;
--! the signal from outside the fpga system which comes from a led or rotary sensor
rotary_signal : in std_logic
);
end entity rotary_encoder;
architecture RTL of rotary_encoder is
signal old_signal : bit := '0';
signal internal_counter : unsigned(counter_width - 1 downto 0) := (others => '0');
signal reset_counter : boolean := false;
begin
reset_counter <= true when rst = '1' or clear_counter = '1' else false;
counter <= std_logic_vector(internal_counter);
signal_counting : process(clk) is
begin
if rising_edge(clk) then
if reset_counter = true then
internal_counter <= (others => '0');
else
if enable = '1' then
old_signal <= '0';
if rotary_signal = '0' and old_signal = '0' then
-- nothing changed
old_signal <= '0';
elsif rotary_signal = '0' and old_signal = '1' then
-- falling edge
old_signal <= '0';
elsif rotary_signal = '1' and old_signal = '0' then
-- now there was a rising edge on the rotary_signal
old_signal <= '1';
internal_counter <= internal_counter + 1;
elsif rotary_signal = '1' and old_signal = '1' then
-- there was and is high level
old_signal <= '1';
else
counter_error <= true;
internal_counter <= (others => '0');
end if;
end if;
end if;
end if;
end process signal_counting;
end architecture RTL;
|
gpl-3.0
|
tghaefli/ADD
|
ISE/FMC_waj/fmc_rom.vhd
|
2
|
5939
|
-------------------------------------------------------------------------------
-- Entity: fmc_rom
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ROM for Floppy-Music Controller (channel-dependent content)
-- NOTE:
-- Since XST does not support the 'val attribute, the following cannot be used
-- to form the channel-number dependent MIF file name:
-- "fmc_rom_" & character'val(N+48) & ".mif"
-- As a workaround, a wrapper unit with conditional generate statements is
-- used.
-------------------------------------------------------------------------------
-- Total # of FFs: FMC_ROM_DW
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- FMC ROM core unit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.mcu_pkg.all;
entity fmc_rom_core is
generic(MIF : string := "rom.mif" -- ROM init file
);
port(clk : in std_logic;
addr : in std_logic_vector(FMC_ROM_AW-1 downto 0);
data : out std_logic_vector(FMC_ROM_DW-1 downto 0)
);
end fmc_rom_core;
architecture rtl of fmc_rom_core is
type t_rom is array (0 to 2**FMC_ROM_AW-1) of std_logic_vector(FMC_ROM_DW-1 downto 0);
impure function f_assign_mif(file_name : in string) return t_rom is
FILE f : text open read_mode is file_name;
variable l : line;
variable s : string(FMC_ROM_DW downto 1);
variable r : t_rom;
begin
for i in t_rom'range loop
if not endfile(f) then
-- Note: The last row in .mif should have no CR
readline(f,l);
read(l,s);
for k in s'range loop
if s(k) = '1' then
r(i)(k-1) := '1';
else
r(i)(k-1) := '0';
end if;
end loop;
end if;
end loop;
return r;
end function;
signal rom_table : t_rom := f_assign_mif(MIF);
signal data_reg : std_logic_vector(FMC_ROM_DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Behavioral description of ROM with latency of 2 cc
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
data_reg <= rom_table(to_integer(unsigned(addr)));
data <= data_reg;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Wrapper Unit (workaround)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_rom is
generic(N : natural := 0 -- channel number
);
port(clk : in std_logic;
addr : in std_logic_vector(FMC_ROM_AW-1 downto 0);
data : out std_logic_vector(FMC_ROM_DW-1 downto 0)
);
end fmc_rom;
architecture rtl of fmc_rom is
begin
-- ROM 0 ------------------------------------
rom_0: if N = 0 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_0.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 1 ------------------------------------
rom_1: if N = 1 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_1.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 2 ------------------------------------
rom_2: if N = 2 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_2.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 3 ------------------------------------
rom_3: if N = 3 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_3.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 4 ------------------------------------
rom_4: if N = 4 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_4.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 5 ------------------------------------
rom_5: if N = 5 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_5.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 6 ------------------------------------
rom_6: if N = 6 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_6.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
-- ROM 7 ------------------------------------
rom_7: if N = 7 generate
rom_core : entity work.fmc_rom_core
generic map(MIF => "fmc_rom_7.mif")
port map (clk => clk,
addr => addr,
data => data
);
end generate;
end rtl;
|
gpl-3.0
|
tghaefli/ADD
|
EDK/IVK_Repos/IVK_IPLib/pcores/sg_2d_fir_plbw_v1_01_a/hdl/vhdl/sg_2d_fir_plbw.vhd
|
3
|
10089
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_2d_fir_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
reset: in std_logic;
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_2d_fir_plbw;
architecture structural of sg_2d_fir_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal reset_x0: std_logic;
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
reset_x0 <= reset;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_2d_fir_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
reset => reset_x0,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
src/comps/delta_delay.vhd
|
1
|
490
|
library ieee;
use ieee.std_logic_1164.all;
entity delta_delay is
generic(
N : natural := 1
);
port(
A : in std_logic;
Z : out std_logic
);
end entity delta_delay;
architecture delta_delay_arch of delta_delay is
signal Z_aux : std_logic_vector(N-2 downto 0);
begin
Z_aux(0) <= A; -- 1 delta
ciclo: for i in 1 to (N-2) generate
Z_aux(i) <= Z_aux(i-1);
end generate;
Z <= Z_aux(N-2); -- 1 delta
end delta_delay_arch;
|
gpl-3.0
|
kuba-moo/VHDL-lib
|
globals.vhd
|
1
|
1338
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- globals for projects using my modules
package globals is
constant FPGA_CLK_FREQ : integer := 100000000; -- 100 MHz
subtype byte_t is std_logic_vector(7 downto 0);
-- register interface
--constant REG_ADDR_W : integer := 5;
subtype reg_addr_t is std_logic_vector(REG_ADDR_W - 1 downto 0);
constant reg_addr_invl : std_logic_vector(REG_ADDR_W - 1 downto 0) := ( others => '1' );
type reg_bus_t is record
wr : std_logic;
data : byte_t;
addr : reg_addr_t;
end record reg_bus_t;
end globals;
package body globals is
end globals;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
old/fix_floating_point_files/numeric_std_unsigned_c.vhdl
|
1
|
80681
|
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED" from "numeric_std".
--
-- This is the updated (proposed) new package to be
-- balloted in January.
--
-- New subprograms are at the end of the package header
-- and the package body. These are to be revised, ID's
-- assigned, and voted into the ballot version.
--
-- Other changes will be noted here.
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- begin LCS-2006-130
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use work.numeric_std_additions.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
end package body NUMERIC_STD_UNSIGNED;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
src/video_ram/dual_port_ram.vhd
|
1
|
1703
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dual_port_ram is
generic (
DATA_WIDTH : natural := 1;
ADDRESS_WIDTH : natural := 18
);
port (
clock: in std_logic;
write_enable : in std_logic;
address_A : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
address_B : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_A : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_B : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity dual_port_ram;
architecture dual_port_ram_arq of dual_port_ram is
attribute ram_style : string;
constant memo_size : natural := 2**ADDRESS_WIDTH;
subtype memo_i is integer range 0 to memo_size-1;
subtype t_word is std_logic_vector(DATA_WIDTH-1 downto 0);
type memo is array(0 to (memo_size-1)) of t_word;
signal RAM : memo := (others => (others => '0'));
attribute ram_style of ram: signal is "block";
-- DEBUG
---type memo_aux is array(0 to (memo_size-1)) of std_logic;
---signal RAM_aux : memo_aux := (others => '0');
signal address_A_int : memo_i := 0;---integer := 0;
signal address_B_int : memo_i := 0;---integer := 0;
begin
--DEBUG
---ram_test: for i in 0 to memo_size-1 generate
--- RAM_aux(i) <= RAM(i)(0);
---end generate;
address_A_int <= to_integer(unsigned(address_A));
address_B_int <= to_integer(unsigned(address_B));
process(clock)
begin
if rising_edge(clock) then
if write_enable = '1' then
RAM(address_A_int) <= data_A;
end if;
data_B <= RAM(address_B_int);
end if;
end process;
end;
|
gpl-3.0
|
kuba-moo/VHDL-lib
|
counter_en.vhd
|
1
|
1599
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter with enable
entity counter_en is
port (Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
Cnt : out std_logic_vector (1 downto 0));
end counter_en;
-- Operation:
-- Count number of cycles @Enable is up.
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again.
architecture Behavioral of counter_en is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
if Enable = '1' then
count <= count + 1;
end if;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
src/video_ram/video_ram.vhd
|
1
|
1344
|
-- Recibe para escribir (A) y devuelve lectura (B)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_ram is
generic(
N_bits_row : integer := 10;
N_bits_col : integer := 10;
N_rows : integer := 480;
N_cols : integer := 640
);
port(
clock: in std_logic;
write_enable : in std_logic;
A_row : in std_logic_vector(N_bits_row-1 downto 0);
B_row : in std_logic_vector(N_bits_row-1 downto 0);
A_col : in std_logic_vector(N_bits_col-1 downto 0);
B_col : in std_logic_vector(N_bits_col-1 downto 0);
data_A : in std_logic;
data_B : out std_logic
);
end;
architecture video_ram_arq of video_ram is
signal A_address : std_logic_vector(N_bits_row + N_bits_col - 1 downto 0) := (others => '0');
signal B_address : std_logic_vector(N_bits_row + N_bits_col - 1 downto 0) := (others => '0');
begin
A_address <= A_row & A_col;
B_address <= B_row & B_col;
mem: entity work.dual_port_ram
generic map(
DATA_WIDTH => 1,
ADDRESS_WIDTH => N_bits_row + N_bits_col
)
port map(
clock => clock,
write_enable => write_enable,
address_A => A_address,
address_B => B_address,
data_A(0) => data_A,
data_B(0) => data_B
);
end;
|
gpl-3.0
|
kuba-moo/VHDL-lib
|
uart_rx.vhd
|
2
|
4036
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.globals.all;
-- UART receive
entity uart_rx is
generic (FREQUENCY : integer);
port (Clk : in std_logic;
Rst : in std_logic;
RsRx : in std_logic;
Byte : out byte_t;
Valid : out std_logic);
end uart_rx;
-- Operation:
-- When @RsRx goes down start counting bit time, sample on half of bit time.
-- To rule out spurious starts wait for @RsRx to go low for a few cycles.
architecture Behavioral of uart_rx is
constant CLK_MAX : integer := FPGA_CLK_FREQ/FREQUENCY;
constant CLK_SAMPLE : integer := CLK_MAX/2;
type a2_byte is array(1 downto 0) of byte_t;
type state_t is (IDLE, START, RX, STOP);
signal bit_no, NEXT_bit_no : integer range 0 to 8;
signal value, NEXT_value : byte_t;
signal cnt, NEXT_cnt : integer range 0 to CLK_MAX;
signal state, NEXT_state : state_t;
signal rx_d : std_logic_vector(1 downto 0);
begin
Byte <= value;
rx_d(0) <= RsRx when rising_edge(Clk);
rx_d(1) <= rx_d(0) when rising_edge(Clk);
NEXT_fsm : process (state, cnt, value, bit_no, rx_d(1))
begin
NEXT_state <= state;
NEXT_cnt <= cnt + 1;
NEXT_value <= value;
NEXT_bit_no <= bit_no;
Valid <= '0';
case state is
when IDLE =>
if rx_d(1) = '0' then -- waiting for a stable low input will
-- offset the sampling time by 8, but it
-- should be ok for UART rates
NEXT_bit_no <= bit_no + 1;
if CONV_std_logic_vector(bit_no, 4)(3) = '1' then
NEXT_state <= START;
NEXT_cnt <= 0;
end if;
else
NEXT_bit_no <= 0;
end if;
when START =>
if cnt = CLK_MAX then
NEXT_state <= RX;
NEXT_cnt <= 0;
NEXT_bit_no <= 0;
end if;
when RX =>
if CONV_std_logic_vector(bit_no, 4)(3) = '1' then
NEXT_state <= STOP;
Valid <= '1';
end if;
if cnt = CLK_SAMPLE then
NEXT_value(bit_no) <= rx_d(1);
end if;
if cnt = CLK_MAX then
NEXT_state <= RX;
NEXT_cnt <= 0;
NEXT_bit_no <= bit_no + 1;
end if;
when STOP =>
if cnt = CLK_SAMPLE then -- go to IDLE early, if we wait full
-- bit time, delays from IDLE might
-- accumulate
NEXT_state <= IDLE;
end if;
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
cnt <= NEXT_cnt;
value <= NEXT_value;
bit_no <= NEXT_bit_no;
if Rst = '1' then
state <= IDLE;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Feuerwerk/fpgaNES
|
master_reconfig.vhd
|
1
|
6755
|
-- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0%
-- GENERATION: XML
-- master_reconfig.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity master_reconfig is
generic (
ENABLE_BYTEENABLE : boolean := false;
BYTEENABLE_WIDTH : integer := 4;
RECONFIG_ADDR_WIDTH : integer := 6;
RECONFIG_DATA_WIDTH : integer := 32;
reconf_width : integer := 64;
WAIT_FOR_LOCK : boolean := true
);
port (
mgmt_clk : in std_logic := '0'; -- mgmt_clk.clk
mgmt_reset : in std_logic := '0'; -- mgmt_reset.reset
mgmt_waitrequest : out std_logic; -- mgmt_avalon_slave.waitrequest
mgmt_read : in std_logic := '0'; -- .read
mgmt_write : in std_logic := '0'; -- .write
mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
mgmt_address : in std_logic_vector(5 downto 0) := (others => '0'); -- .address
mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll.reconfig_to_pll
reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => '0') -- reconfig_from_pll.reconfig_from_pll
);
end entity master_reconfig;
architecture rtl of master_reconfig is
component altera_pll_reconfig_top is
generic (
device_family : string := "";
ENABLE_MIF : boolean := false;
MIF_FILE_NAME : string := "";
ENABLE_BYTEENABLE : boolean := false;
BYTEENABLE_WIDTH : integer := 4;
RECONFIG_ADDR_WIDTH : integer := 6;
RECONFIG_DATA_WIDTH : integer := 32;
reconf_width : integer := 64;
WAIT_FOR_LOCK : boolean := true
);
port (
mgmt_clk : in std_logic := 'X'; -- clk
mgmt_reset : in std_logic := 'X'; -- reset
mgmt_waitrequest : out std_logic; -- waitrequest
mgmt_read : in std_logic := 'X'; -- read
mgmt_write : in std_logic := 'X'; -- write
mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata
mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll
reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_from_pll
mgmt_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component altera_pll_reconfig_top;
begin
master_reconfig_inst : component altera_pll_reconfig_top
generic map (
device_family => "Cyclone V",
ENABLE_MIF => false,
MIF_FILE_NAME => "",
ENABLE_BYTEENABLE => ENABLE_BYTEENABLE,
BYTEENABLE_WIDTH => BYTEENABLE_WIDTH,
RECONFIG_ADDR_WIDTH => RECONFIG_ADDR_WIDTH,
RECONFIG_DATA_WIDTH => RECONFIG_DATA_WIDTH,
reconf_width => reconf_width,
WAIT_FOR_LOCK => WAIT_FOR_LOCK
)
port map (
mgmt_clk => mgmt_clk, -- mgmt_clk.clk
mgmt_reset => mgmt_reset, -- mgmt_reset.reset
mgmt_waitrequest => mgmt_waitrequest, -- mgmt_avalon_slave.waitrequest
mgmt_read => mgmt_read, -- .read
mgmt_write => mgmt_write, -- .write
mgmt_readdata => mgmt_readdata, -- .readdata
mgmt_address => mgmt_address, -- .address
mgmt_writedata => mgmt_writedata, -- .writedata
reconfig_to_pll => reconfig_to_pll, -- reconfig_to_pll.reconfig_to_pll
reconfig_from_pll => reconfig_from_pll, -- reconfig_from_pll.reconfig_from_pll
mgmt_byteenable => "0000" -- (terminated)
);
end architecture rtl; -- of master_reconfig
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll_reconfig" version="18.0" >
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="ENABLE_MIF" value="false" />
-- Retrieval info: <generic name="MIF_FILE_NAME" value="" />
-- Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
-- Retrieval info: </instance>
-- IPFS_FILES : master_reconfig.vho
-- RELATED_FILES: master_reconfig.vhd, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
gpl-3.0
|
erevejach14/Arquitectura
|
suma/suma.vhd
|
1
|
820
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity suma is
port( cin : in std_logic;
x : in std_logic_vector( 3 downto 0);
y : in std_logic_vector( 3 downto 0);
s : out std_logic_vector( 3 downto 0);
cout : out std_logic);
end;
architecture hola of suma is
signal c : std_logic_vector( 0 to 4);
begin
c(0) <= cin;
--i = 0
s(0) <= c(0) xor x(0) xor y(0);
c(1) <= (x(0) and y(0)) or (c(0) and (x(0) xor y(0)));
--i = 1
s(1) <= c(1) xor x(1) xor y(1);
c(2) <= (x(1) and y(1)) or (c(1) and (x(1) xor y(1)));
--i = 2
s(2) <= c(2) xor x(2) xor y(2);
c(3) <= (x(2) and y(2)) or (c(2) and (x(2) xor y(2)));
--i = 3
s(3) <= c(3) xor x(3) xor y(3);
c(4) <= (x(3) and y(3)) or (c(3) and (x(3) xor y(3)));
cout <= c(4);
end hola;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
old/testers/tester_ram_interna.vhd
|
1
|
3454
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity tester_ram_interna is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
port(
clk_i: in std_logic; -- Clock general
rst_i: in std_logic := '0'; -- Botón de reset
pos_leida: out t_pos;
ena_o: out std_logic := '0';
ram_int_refresh: out std_logic := '0'
);
attribute loc: string;
attribute loc of clk_i: signal is "B8";
end;
architecture tester_ram_interna_arq of tester_ram_interna is
signal RxRdy: std_logic := '0'; -- Dato listo para leerse
signal Dout_uart: std_logic_vector(15 downto 0) := (others => '0');
signal Dout_memint: t_pos_mem := (others => (others => '0'));
signal pos_leida_aux: t_pos := (others => CERO);
type memo_t is array(0 to 39) of std_logic_vector(15 downto 0);
constant testmemo : memo_t := (
"0000000000000000",
"0000000000000100",
"0000000000001100",
"0000000001100000",
"0000000000000010",
"0000000000000001",
"1000001100000000",
"1000000000010000",
"0100000000010000",
"1111111111111111",
"1111111111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000010",
"0000000000000001",
"1000001100000000",
"1000000000010000",
"0100000000010000",
"1111111111111111",
"1111111111111110",
"1111111111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000010",
"0100000000010000",
"1111111111111111",
"1111111111111110",
"1111101111101111",
"0000000000000010",
"1000000000000011",
"0000000000000011",
"0000000001100000",
"0000000000000001",
"0000000000000010"
);
begin
process(clk_i)
variable i : natural := 0;
variable j : natural := 0;
variable n : natural := 0;
begin
if rising_edge(clk_i) then
i := i + 1;
if i > 32 then
i := 0;
Dout_uart <= testmemo(j);
RxRdy <= '1';
j := j + 1;
if j >= testmemo'length then
j := 0;
end if;
end if;
--- else RxRdy <= '0';
if n < 150 then
report "pos_leida 1 " & integer'image(to_integer(signed(pos_leida_aux(1))))-- & " ena_o " & ena_o
severity note;
report "pos_leida 2 " & integer'image(to_integer(signed(pos_leida_aux(2))))-- & " ena_o " & ena_o
severity note;
report "pos_leida 3 " & integer'image(to_integer(signed(pos_leida_aux(3))))-- & " ena_o " & ena_o
severity note;
n := n + 1;
end if;
end if;
end process;
--- Se guarda un dato de lectura listo en memoria [interna]. Continuamente se leen y guardan en vector pos_leida
ram_int: entity work.ram_interna
generic map(
N_BITS => N_BITS_COORD---,
---CANT_P => 50---0
) port map(
clk => clk_i,
rst => rst_i,
Rx => RxRdy,
Din => Dout_uart,
Dout => Dout_memint,
Rdy => ena_o,
barrido => ram_int_refresh
);
---pos_leida_aux(i) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_leida_aux(i)),N_BITS_COORD));
pos_leida_aux(1) <= to_float(Dout_memint(1));
pos_leida_aux(2) <= to_float(Dout_memint(2));
pos_leida_aux(3) <= to_float(Dout_memint(3));
pos_leida <= pos_leida_aux;
end;
|
gpl-3.0
|
MartinCura/SistDig-TP4
|
old/UART/data_adq/data_loader.vhd
|
1
|
2130
|
--lee de la uart y combina LSB y MSB en un dato de 16bits con los datos de la UART.
--(Toma LSB y MSB de la uart)
--Version con maquinola de estados
-------------------------------------------------------------------------------
--UNIDAD ASINCRONICA
--Algo que podria generar problemas es inicializar la senial RxRdy_out en cero
--justo debajo del begin. Habria que revisar eso como prioridad en caso de que falle
--la recepcion de datos.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
entity data_loader is
generic (
in_data_bits : natural := 8; --cantidad de bits del dato que entra
out_data_bits: natural:=16; -- cant de bits del dato que sale
data_midpoint: natural:=8 -- bits/2 del dato que sale
);
port(
--clock: in std_logic;
reset: in std_logic;
data_in: in std_logic_vector(in_data_bits-1 downto 0);
data_out: out std_logic_vector(out_data_bits-1 downto 0);
RxRdy_in: in std_logic;
RxRdy_out: out std_logic
);
end entity data_loader;
architecture data_loader_arch of data_loader is
type state_t is (LSB, MSB);
signal state : state_t := LSB;
begin
FSM: process(RxRdy_in, reset, state, data_in)
begin
RxRdy_out <= '0';
-- RESET
if reset = '1' then
data_out <= (others => '0');
state <= LSB;
RxRdy_out <= '0';
else
case state is
-- LSByte
when LSB =>
if RxRdy_in = '1' then
data_out(data_midpoint-1 downto 0) <= data_in;
RxRdy_out <= '0';
state <= MSB;
end if;
-- MSByte
when MSB =>
if RxRdy_in = '1' then
data_out(out_data_bits-1 downto data_midpoint) <= data_in;
RxRdy_out <= '1';
state <= LSB;
end if;
end case;
end if;
end process;
end data_loader_arch;
-------------------------------------------------------------------------------
|
gpl-3.0
|
kuba-moo/VHDL-lib
|
bus_tail_strip.vhd
|
1
|
2041
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Remove last @N_BYTES from data flying through Bus
entity bus_tail_strip is
generic (N_BYTES : integer);
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector(7 downto 0));
end bus_tail_strip;
-- Operation:
-- Delay all signals and "and" incoming @PktIn with @PktOut to cut it early.
-- NOTE: input is registered which may not be necessary. Remove clocking of
-- delay*(0) to stop registering input.
architecture Behavioral of bus_tail_strip is
type byte_vec is array (0 to N_BYTES) of std_logic_vector(7 downto 0);
signal delayByte : byte_vec;
signal delayPkt : std_logic_vector(0 to N_BYTES);
begin
delayByte(0) <= DataIn when rising_edge(Clk);
delayPkt(0) <= PktIn when rising_edge(Clk);
delay_path : for i in 0 to N_BYTES - 1
generate
delayByte(i + 1) <= delayByte(i) when rising_edge(Clk);
delayPkt(i + 1) <= delayPkt(i) when rising_edge(Clk);
end generate delay_path;
DataOut <= delayByte(N_BYTES);
PktOut <= delayPkt(0) and delayPkt(N_BYTES);
end Behavioral;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd
|
4
|
39337
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
gpl-3.0
|
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