repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
metaspace/ghdl_extra
|
int_bool/int_bitvector.vhdl
|
1
|
903
|
-- int_bitvector.vhdl
-- créé sam. janv. 29 12:11:00 CET 2011 par [email protected]
library IEEE;
use IEEE.numeric_bit.all;
package int_bitvector is
subtype int_1 is unsigned( 0 downto 0);
subtype int_2 is unsigned( 1 downto 0);
subtype int_3 is unsigned( 2 downto 0);
subtype int_4 is unsigned( 3 downto 0);
subtype int_5 is unsigned( 4 downto 0);
subtype int_8 is unsigned( 7 downto 0);
subtype int_16 is unsigned(15 downto 0);
subtype int_32 is unsigned(31 downto 0);
function from_int(i, j : integer) return unsigned;
function to_int(i : unsigned) return integer;
end package int_bitvector;
package body int_bitvector is
function from_int(i, j : integer) return unsigned is
begin
return unsigned(to_signed(i,j));
end from_int;
function to_int(i : unsigned) return integer is
begin
return to_integer(i);
end to_int;
end package body int_bitvector;
|
gpl-3.0
|
kuba-moo/VHDL-precise-packet-generator
|
stat_writer.vhd
|
1
|
2604
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity stat_writer is
port (Clk : in std_logic;
Rst : in std_logic;
MemWe : out std_logic_vector(0 downto 0);
MemAddr : out std_logic_vector(8 downto 0);
MemDin : out std_logic_vector(35 downto 0);
MemDout : in std_logic_vector(35 downto 0);
Value : in std_logic_vector(8 downto 0);
Kick : in std_logic);
end stat_writer;
architecture Behavioral of stat_writer is
type state_t is (ZERO_OUT, IDLE, READ_OLD, WRITE_NEW);
signal state, NEXT_state : state_t;
signal addr, NEXT_addr : std_logic_vector(8 downto 0);
begin
MemAddr <= addr;
NEXT_fsm : process (state, addr, MemDout, Value, Kick)
begin
NEXT_state <= state;
NEXT_addr <= addr;
MemDin <= MemDout + 1;
MemWe <= "0";
case state is
when ZERO_OUT =>
NEXT_addr <= addr + 1;
MemWe <= "1";
MemDin <= (others => '0');
if addr = b"1" & X"FF" then
NEXT_state <= IDLE;
end if;
when IDLE =>
if Kick = '1' then
NEXT_state <= READ_OLD;
NEXT_addr <= Value;
end if;
when READ_OLD =>
NEXT_state <= WRITE_NEW;
when WRITE_NEW =>
NEXT_state <= IDLE;
MemWe <= "1";
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
addr <= NEXT_addr;
if Rst = '1' then
state <= ZERO_OUT;
addr <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
kuba-moo/VHDL-precise-packet-generator
|
reg_ro.vhd
|
2
|
2277
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- read only register
entity reg_ro is
generic (REG_BYTES : integer;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : in std_logic_vector(REG_BYTES*8 - 1 downto 0));
end reg_ro;
-- Operation:
-- Report @Value to the bus when address matches.
-- WARNING: this version of ro-register is NOT atomic.
architecture Behavioral of reg_ro is
constant OFFSET_LEN : integer := integer(ceil(log2(real(REG_BYTES))));
constant REG_BITS : integer := REG_BYTES*8;
subtype OffsetRange is natural range OFFSET_LEN - 1 downto 0;
subtype AddrRange is natural range REG_ADDR_W - 1 downto OFFSET_LEN;
signal offset : integer;
signal bus_addr, reg_addr : std_logic_vector(AddrRange);
begin
offset <= CONV_integer(RegBusI.addr(OffsetRange));
bus_addr <= RegBusI.addr(AddrRange);
reg_addr <= REG_ADDR_BASE(AddrRange);
read_out : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if bus_addr = reg_addr and RegBusI.wr = '0' then
RegBusO.data <= Value(7 + offset*8 downto offset*8);
end if;
if Rst = '1' then
RegBusO.addr <= reg_addr_invl;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
manosaloscables/vhdl
|
circuitos_secuenciales/sram_doble_puerto/sram_dp.vhd
|
1
|
1862
|
-- ******************************************************************
-- * RAM síncrona de doble puerto simplificada para FPGAs de Altera *
-- ******************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_dp is
generic(
DIR_ANCHO : integer:=2;
DATOS_ANCHO: integer:=8
);
port(
clk: in std_logic;
we : in std_logic; -- Activador de escritura
-- Direcciones de escritura y lectura
w_dir: in std_logic_vector(DIR_ANCHO-1 downto 0); -- Escritura
r_dir: in std_logic_vector(DIR_ANCHO-1 downto 0); -- Lectura
-- Registros que reflejan cómo los módulos de memoria embebida están
-- empaquetados con una interfaz síncrona en los chips Cyclone.
d: in std_logic_vector(DATOS_ANCHO-1 downto 0);
q: out std_logic_vector(DATOS_ANCHO-1 downto 0)
);
end sram_dp;
-- ****************************************************************************
-- Si w_addr y r_addr son iguales, q adquiere los datos actuales (nuevos datos)
-- ****************************************************************************
architecture arq_dir_reg of sram_dp is
--------------------------------------------------------------------
-- Crear un tipo de datos de dos dimensiones definido por el usuario
type mem_tipo_2d is array (0 to 2**DIR_ANCHO-1)
of std_logic_vector (DATOS_ANCHO-1 downto 0);
signal sram: mem_tipo_2d;
--------------------------------------------------------------------
signal dir_reg: std_logic_vector(DIR_ANCHO-1 downto 0);
begin
process (clk) begin
if(rising_edge(clk)) then
if (we='1') then
sram(to_integer(unsigned(w_dir))) <= d;
end if;
dir_reg <= r_dir;
end if;
end process;
-- Salida
q <= sram(to_integer(unsigned(dir_reg)));
end arq_dir_reg;
|
gpl-3.0
|
rodrigofegui/UnB
|
2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificacao-Principal/seven_seg_decoder.vhd
|
2
|
1153
|
--Módulo para converter um dado para mostrar no display 7 segmentos da placa DE2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab02/lab02/ipcore_dir/ROM_D/example_design/ROM_D_prod_exdes.vhd
|
8
|
5117
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab03/lab03/ipcore_dir/ROM_D/example_design/ROM_D_prod_exdes.vhd
|
8
|
5117
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_D_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(10-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end ROM_D_exdes;
architecture xilinx of ROM_D_exdes is
component ROM_D is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_D
port map (
SPO => SPO,
A => A
);
end xilinx;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab08/lab08/ipcore_dir/ROM_D/simulation/ROM_D_tb_agen.vhd
|
8
|
4316
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_D_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF ROM_D_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab03/lab03/ipcore_dir/ROM_D/simulation/ROM_D_tb_agen.vhd
|
8
|
4316
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_D_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_D_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF ROM_D_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
rodrigofegui/UnB
|
2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificacao-Principal/PC.vhd
|
2
|
742
|
--Módulo para contador de programa PC
--Declaracao de bibliotecas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PC is
generic (DATA_WIDTH : natural := 32); --ULA faz operacoes com dados de 32 bits
port (
clk, rst : in std_logic;
add_in: in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
add_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity PC;
architecture Behavioral of PC is
begin
process(clk, rst)
begin
if (rst = '0') then
add_out <= (others => '0'); --endereco inicial
else
if rising_edge(clk) then
add_out <= add_in; --o valor da entrada ira passar para saida
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
rodrigofegui/UnB
|
2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Codificacao-Principal/Uniciclo.vhd
|
2
|
11412
|
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------------------------
--Módulo principal do processador uniciclo, fazendo a união dos módulos componentes
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uniciclo is
generic(DATA_WIDTH : natural := 32;
ADDRESS_WIDTH: natural := 5);
port (clk, rst : in std_logic := '1';
SW : in std_logic_vector(13 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0));
end entity uniciclo;
architecture Behavioral of uniciclo is
signal aux_switch : std_logic_vector(1 downto 0);
signal HEX0_pc, HEX1_pc, HEX2_pc, HEX3_pc, HEX4_pc, HEX5_pc, HEX6_pc, HEX7_pc: std_logic_vector(6 downto 0);
signal HEX0_mi, HEX1_mi, HEX2_mi, HEX3_mi, HEX4_mi, HEX5_mi, HEX6_mi, HEX7_mi: std_logic_vector(6 downto 0);
signal HEX0_reg, HEX1_reg, HEX2_reg, HEX3_reg, HEX4_reg, HEX5_reg, HEX6_reg, HEX7_reg: std_logic_vector(6 downto 0);
signal HEX0_md, HEX1_md, HEX2_md, HEX3_md, HEX4_md, HEX5_md, HEX6_md, HEX7_md: std_logic_vector(6 downto 0);
signal display, result_soma1, result_soma2, md_out : std_logic_vector(31 downto 0);
signal result_mux_branch, result_mux_jump : std_logic_vector(31 downto 0);
signal pc_in, pc_out, mi_out, rdata1, rdata2, rdata3, imediato_shift, imediato_shift_desloc, shamt_shift, mux_jump_in : std_logic_vector(31 downto 0);
signal opcode : std_logic_vector(5 downto 0);
signal wdata : std_logic_vector(31 downto 0);
signal wadd: std_logic_vector(4 downto 0);
signal beq_and_z, bne_and_notz, beq_or_bne : std_logic;
signal jump_jr : std_logic;
signal ulain : std_logic_vector(31 downto 0);
signal saida_mux_mem : std_logic_vector(31 downto 0);
signal ulaout : std_logic_vector(31 downto 0);
signal zero : std_logic := '0';
signal ctrl_alu : std_logic_vector(3 downto 0);
signal saida_mux_ula : std_logic_vector(31 downto 0);
signal nro_4 : std_logic_vector(31 downto 0):=x"00000004";
signal ra : std_logic_vector(4 downto 0):="11111";
--sinais de controle
signal RegDst : std_logic_vector(1 downto 0);
signal ALUOp : std_logic_vector (2 downto 0);
signal Jump, Jal, Branch, Bne, MemtoReg, MemWrite, ALUSrc, RegWrite : std_logic;
begin
contador_programa: entity work.PC port map(clk => clk, rst => rst, add_in => pc_in, add_out => pc_out);
soma1: entity work.somador port map(dataIn1 => pc_out, dataIn2 => nro_4, dataOut => result_soma1);
mi: entity work.mi port map(clk => clk, address => pc_out(8 downto 2), instruction => mi_out);
controle: entity work.controle port map(opcode => mi_out(31 downto 26) , RegDst => RegDst , Jump => Jump, Jal => Jal,
Branch => Branch, Bne => Bne, MemtoReg => MemtoReg , ALUOp => ALUOp,
MemWrite => MemWrite, ALUSrc => ALUSrc, RegWrite => RegWrite);
mux1: entity work.mux_5bits port map(sel => RegDst, dataIn1 => mi_out(20 downto 16), dataIn2 => mi_out(15 downto 11),
dataIn3 => ra, dataOut => wadd);
breg: entity work.reg_bank port map(clk => clk, wren => RegWrite, radd1 => mi_out(25 downto 21), radd2 => mi_out(20 downto 16),
radd3 => SW(6 downto 2) ,wadd => wadd,
wdata => wdata,
rdata1 => rdata1, rdata2 => rdata2, rdata3 => rdata3);
mux_ula: entity work.mux2 port map(sel => ALUSrc, dataIn1 => rdata2, dataIn2 => imediato_shift,
dataOut => saida_mux_ula);
ula_controle: entity work.controleAlu port map(funct => mi_out(5 downto 0),
ALUOp => ALUOp,
CTRLOut => ctrl_alu,
Jr => jump_jr);
ula: entity work.alu port map(input1 => rdata1, input2 => saida_mux_ula, input3 => shamt_shift, operation => ctrl_alu,
output => ulaout, zero => zero);
mem_data: entity work.md port map(clk => clk,
we => MemWrite,
adr => ulaout(8 downto 2),
din => rdata2,
dout => md_out);
mux_mem: entity work.mux2 port map(sel => MemtoReg, dataIn1 => ulaout, dataIn2 => md_out,
dataOut => saida_mux_mem);
soma2: entity work.somador port map(dataIn1 => result_soma1, dataIn2 => imediato_shift_desloc, dataOut => result_soma2);
mux_branch: entity work.mux2 port map(sel => beq_or_bne, dataIn1 => result_soma1, dataIn2 => result_soma2,
dataOut => result_mux_branch);
mux_jump: entity work.mux2 port map(sel => Jump, dataIn1 => result_mux_branch, dataIn2 => mux_jump_in,
dataOut => result_mux_jump);
mux_jr: entity work.mux2 port map(sel => jump_jr, dataIn1 => result_mux_jump, dataIn2 => rdata1,
dataOut => pc_in);
mux_jal: entity work.mux2 port map(sel => Jal, dataIn1 => saida_mux_mem, dataIn2 => result_soma1,
dataOut => wdata);
dec1 : entity work.dec_pc port map(clk => clk, rst => rst, SW => pc_out,
HEX0 =>HEX0_pc,
HEX1 =>HEX1_pc,
HEX2 =>HEX2_pc,
HEX3 =>HEX3_pc,
HEX4 =>HEX4_pc,
HEX5 =>HEX5_pc,
HEX6 =>HEX6_pc,
HEX7 =>HEX7_pc);
dec2 : entity work.dec_mi port map(clk => clk, SW => pc_out(8 downto 2),
HEX0 =>HEX0_mi,
HEX1 =>HEX1_mi,
HEX2 =>HEX2_mi,
HEX3 =>HEX3_mi,
HEX4 =>HEX4_mi,
HEX5 =>HEX5_mi,
HEX6 =>HEX6_mi,
HEX7 =>HEX7_mi);
dec3 : entity work.dec_reg port map(clk => clk, SW => SW(6 downto 2),
HEX0 =>HEX0_reg,
HEX1 =>HEX1_reg,
HEX2 =>HEX2_reg,
HEX3 =>HEX3_reg,
HEX4 =>HEX4_reg,
HEX5 =>HEX5_reg,
HEX6 =>HEX6_reg,
HEX7 =>HEX7_reg);
dec4 : entity work.dec_mem port map(clk => clk, SW => SW(13 downto 7),
HEX0 =>HEX0_md,
HEX1 =>HEX1_md,
HEX2 =>HEX2_md,
HEX3 =>HEX3_md,
HEX4 =>HEX4_md,
HEX5 =>HEX5_md,
HEX6 =>HEX6_md,
HEX7 =>HEX7_md);
--definicao de alguns sinais intermediarios
mux_jump_in <= result_soma1(31 downto 28)&mi_out(25 downto 0)&"00";
beq_and_z <= Branch and zero;
bne_and_notz <= Branch and not(zero);
beq_or_bne <= beq_and_z or bne_and_notz;
imediato_shift <= x"0000"&(mi_out(15 downto 0)) when mi_out(15)='0' else x"ffff"&(mi_out(15 downto 0)) when mi_out(15)='1';
imediato_shift_desloc <= imediato_shift(29 downto 0)&"00";
shamt_shift <= "000000000000000000000000000" & (mi_out(10 downto 6)) when mi_out(10)='0' else
"111111111111111111111111111" & (mi_out(10 downto 6)) when mi_out(10)='1';
aux_switch <= SW(1 downto 0);
HEX0 <= HEX0_pc when aux_switch <= "00" else
HEX0_mi when aux_switch <= "01" else
HEX0_reg when aux_switch <= "10" else
HEX0_md when aux_switch <= "11";
HEX1 <=HEX1_pc when aux_switch <= "00" else
HEX1_mi when aux_switch <= "01" else
HEX1_reg when aux_switch <= "10" else
HEX1_md when aux_switch <= "11";
HEX2 <=HEX2_pc when aux_switch <= "00" else
HEX2_mi when aux_switch <= "01" else
HEX2_reg when aux_switch <= "10" else
HEX2_md when aux_switch <= "11";
HEX3 <=HEX3_pc when aux_switch <= "00" else
HEX3_mi when aux_switch <= "01" else
HEX3_reg when aux_switch <= "10" else
HEX3_md when aux_switch <= "11";
HEX4 <=HEX4_pc when aux_switch <= "00" else
HEX4_mi when aux_switch <= "01" else
HEX4_reg when aux_switch <= "10" else
HEX4_md when aux_switch <= "11";
HEX5 <=HEX5_pc when aux_switch <= "00" else
HEX5_mi when aux_switch <= "01" else
HEX5_reg when aux_switch <= "10" else
HEX5_md when aux_switch <= "11";
HEX6 <=HEX6_pc when aux_switch <= "00" else
HEX6_mi when aux_switch <= "01" else
HEX6_reg when aux_switch <= "10" else
HEX6_md when aux_switch <= "11";
HEX7 <=HEX7_pc when aux_switch <= "00" else
HEX7_mi when aux_switch <= "01" else
HEX7_reg when aux_switch <= "10" else
HEX7_md when aux_switch <= "11";
end Behavioral;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab10/lab10/ipcore_dir/RAM_B/simulation/random.vhd
|
101
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab06/lab06/ipcore_dir/RAM_B/simulation/random.vhd
|
101
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab01/lab01/ipcore_dir/ROM_D/simulation/ROM_D_tb_synth.vhd
|
8
|
6921
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_D_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_D_TB_PKG.ALL;
ENTITY ROM_D_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_D_tb_synth;
ARCHITECTURE ROM_D_synth_ARCH OF ROM_D_tb_synth IS
COMPONENT ROM_D_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(10-1-(4*0*boolean'pos(10>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_D_TB_STIM_GEN_INST:ENTITY work.ROM_D_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_D_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab02/lab02/ipcore_dir/RAM_B/example_design/RAM_B_exdes.vhd
|
12
|
4595
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END RAM_B_exdes;
ARCHITECTURE xilinx OF RAM_B_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT RAM_B IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : RAM_B
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab04/lab04/ipcore_dir/RAM_B/simulation/RAM_B_synth.vhd
|
12
|
7867
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_B_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_B_synth_ARCH OF RAM_B_synth IS
COMPONENT RAM_B_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_B_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab07/lab07/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd
|
10
|
10063
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : RAM_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab04/lab04/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd
|
10
|
10063
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : RAM_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
manosaloscables/vhdl
|
circuitos_secuenciales/sram_un_puerto/sram_up.vhd
|
1
|
1556
|
-- ************************************
-- * RAM síncrona de un puerto Altera *
-- ************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_up is
generic(
DIR_ANCHO: integer:=2;
DATOS_ANCHO: integer:=8
);
port(
clk: in std_logic;
we: in std_logic; -- Activador de escritura
-- Dirección de memoria
dir: in std_logic_vector(DIR_ANCHO-1 downto 0);
-- Registros que reflejan cómo los módulos de memoria embebida están
-- empaquetados con una interfaz síncrona en los chips Cyclone.
d: in std_logic_vector(DATOS_ANCHO-1 downto 0);
q: out std_logic_vector(DATOS_ANCHO-1 downto 0)
);
end sram_up;
-- Arquitectura que registra la dirección de lectura
architecture arq_dir_reg of sram_up is
--------------------------------------------------------------------
-- Crear un tipo de datos de dos dimensiones definido por el usuario
type mem_tipo_2d is array (0 to 2**DIR_ANCHO-1)
of std_logic_vector (DATOS_ANCHO-1 downto 0);
signal sram: mem_tipo_2d;
--------------------------------------------------------------------
signal dir_reg: std_logic_vector(DIR_ANCHO-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we='1') then
sram(to_integer(unsigned(dir))) <= d;
end if;
dir_reg <= dir;
end if;
end process;
-- Salida
q <= sram(to_integer(unsigned(dir_reg)));
end arq_dir_reg;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab03/lab03/ipcore_dir/RAM_B/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
rodrigofegui/UnB
|
2017.1/Organização e Arquitetura de Computadores/Trabalhos/Projeto Final/Referências/dec_mem/memory.vhd
|
1
|
1123
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity memory is
generic(N: integer := 7; M: integer := 32);
port(
clk: in STD_LOGIC := '0';
we: in STD_LOGIC := '0';
adr: in STD_LOGIC_VECTOR(N-1 downto 0) := (others => '0');
din: in STD_LOGIC_VECTOR(M-1 downto 0) := (others => '0');
dout: out STD_LOGIC_VECTOR(M-1 downto 0)
);
end;
architecture memory_arch of memory is
type mem_array is array(0 to (2**N-1)) of STD_LOGIC_VECTOR(M-1 downto 0);
signal mem: mem_array := (
x"abababab",
x"efefefef",
x"02146545",
x"85781546",
x"69782314",
x"25459789",
x"245a65c5",
x"ac5b4b5b",
x"ebebebeb",
x"cacacaca",
x"ecececec",
x"facfcafc",
x"ecaecaaa",
x"dadadeac",
others => (others => '1')
);
begin
process(clk) begin
if clk'event and clk='1' then
if we='1' then
mem(to_integer(unsigned(adr))) <= din;
end if;
end if;
end process;
dout <= mem(to_integer(unsigned(adr)));
end;
|
gpl-3.0
|
rodrigofegui/UnB
|
2017.1/Organização e Arquitetura de Computadores/Trabalhos/Trabalho 3/Codificação/Banco Registradores/RB_tb.vhd
|
1
|
5192
|
----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: TestBank do Banco de Registradores
-- Descrição: TestBank para o Conjunto de registradores com largura de
-- palavra parametrizável e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade
----------------------------------
entity RG_tb is
Generic (DATA_WIDTH_GB : natural := 32;
ADDRESS_WIDTH_GB : natural := 5;
AMOUNT_REG_GB : natural := 32);
end RG_tb;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RG_tb_Op of RG_tb is
-- Componente descrito no proprio arquivo *.vhd
component RegBank is
Generic (DATA_WIDTH : natural := DATA_WIDTH_GB;
ADDRESS_WIDTH : natural := ADDRESS_WIDTH_GB;
AMOUNT_REG : natural := AMOUNT_REG_GB);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
type vector_array is array (natural range <>) of std_logic_vector(ADDRESS_WIDTH_GB - 1 downto 0);
type vector_array2 is array (natural range <>) of std_logic_vector(DATA_WIDTH_GB - 1 downto 0);
-- Clock e periodo de mudanca
signal CLK : std_logic := '0';
constant PERIOD : time := 25 us;
constant PAUSA : time := 24 us;
-- Manipuladores do banco de registradores
signal WREN : std_logic;
signal RADD1, RADD2 : std_logic_vector(ADDRESS_WIDTH_GB - 1 downto 0);
signal WADD : std_logic_vector(ADDRESS_WIDTH_GB - 1 downto 0);
signal WDATA : std_logic_vector(DATA_WIDTH_GB - 1 downto 0);
signal RDATA1, RDATA2 : std_logic_vector(DATA_WIDTH_GB - 1 downto 0);
begin
-- Gerar clock
CLK <= not(CLK) after PERIOD;
-- Manipulador do Banco de Registradores
RB_TB: RegBank port map(CLK, WREN,
RADD1, RADD2,
WADD,
WDATA,
RDATA1, RDATA2);
-- Teste em si
teste: process
variable init0 : std_logic := '0';
variable init1 : std_logic_vector(ADDRESS_WIDTH_GB - 1 downto 0) := (others => '0');
variable init2 : std_logic_vector(DATA_WIDTH_GB - 1 downto 0) := (others => '0');
variable ender : vector_array(0 to 7);
variable valor : vector_array2(0 to 15);
begin
-- Inicializaçao para o teste
WREN <= init0;
RADD1 <= init1;
RADD2 <= init1;
WADD <= init1;
WDATA <= init2;
RDATA1 <= init2;
RDATA2 <= init2;
-- Valores aleatorios para escrita
valor(00) := x"00025900";
valor(01) := x"00026797";
valor(02) := x"00092430";
valor(03) := x"00059664";
valor(04) := x"00008572";
valor(05) := x"00004416";
valor(06) := x"00000016";
valor(07) := x"00030581";
valor(08) := x"00006963";
valor(09) := x"00009871";
valor(10) := x"00091257";
valor(11) := x"00082022";
valor(12) := x"00089633";
valor(13) := x"00058236";
valor(14) := x"00052965";
valor(15) := x"00000001";
-- Teste com WREN em '1' e em '0'
for enable in std_logic range '1' downto '0' loop
WREN <= enable;
-- Escrevendo valores nos registradores
for valorAtri in valor'range loop
WDATA <= valor(valorAtri);
-- Acesso ao endereco para escrita, para todos os registradores
-- incluindo o $zero (o mesmo nao deve ser alterado)
for endereco in 0 to AMOUNT_REG_GB loop
WADD <= std_logic_vector(to_signed(endereco, WADD'length));
report "Com WREN = " & std_logic'image(WREN) severity NOTE;
report "Escreveu-se -> " & integer'image(to_integer(unsigned(WADD)))
& " no end. -> " & integer'image(to_integer(unsigned(WDATA))) severity NOTE;
wait for 2 * PERIOD;
-- Testando leitura, com e sem a habilitacao do WREN
-- com RADD1 e RADD2 para todas as possibilidades;
-- Considera-se leitura e escrita para o mesmo registrador
for leitura1 in 0 to AMOUNT_REG_GB loop
RADD1 <= std_logic_vector(to_signed(leitura1, RADD1'length));
for leitura2 in 0 to AMOUNT_REG_GB loop
RADD2 <= std_logic_vector(to_signed(leitura2, RADD2'length));
report "Com WREN = " & std_logic'image(WREN) severity NOTE;
report "Leu-se -> " & integer'image(to_integer(unsigned(RDATA1))) & " do end. -> " & integer'image(to_integer(unsigned(RADD1))) severity NOTE;
report "Leu-se -> " & integer'image(to_integer(unsigned(RDATA2))) & " do end. -> " & integer'image(to_integer(unsigned(RADD2))) severity NOTE;
wait for 2 * PERIOD;
end loop;
end loop;
end loop;
end loop;
end loop;
end process teste;
end architecture RG_tb_Op;
|
gpl-3.0
|
jobisoft/jTDC
|
modules/VFB6/mez_lvds_in.vhdl
|
1
|
3917
|
-------------------------------------------------------------------------
---- ----
---- Engineer: Ph. Hoffmeister ----
---- Company : ELB-Elektroniklaboratorien Bonn UG ----
---- (haftungsbeschränkt) ----
---- ----
---- Target Devices: ELB_LVDS_INPUT_MEZ v1.0 ----
---- Description : Component for LVDS input adapter ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 ELB ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mez_lvds_in is
Port ( data : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
MEZ : inout STD_LOGIC_VECTOR (73 downto 0));
end mez_lvds_in;
architecture Behavioral of mez_lvds_in is
signal MEZ_buffer : std_logic_vector (73 downto 0);
begin
buffers: for i in 0 to 73 generate
IBUF_MEZ : IBUF generic map ( IOSTANDARD => "LVCMOS33") port map ( I => MEZ(i), O => MEZ_buffer(i) );
end generate buffers;
data (16) <= not MEZ_buffer (1);
data (0) <= not MEZ_buffer (0);
data (17) <= not MEZ_buffer (3);
data (1) <= not MEZ_buffer (2);
data (18) <= not MEZ_buffer (5);
data (2) <= not MEZ_buffer (4);
data (19) <= not MEZ_buffer (7);
data (3) <= not MEZ_buffer (6);
data (20) <= not MEZ_buffer (9);
data (4) <= not MEZ_buffer (8);
data (21) <= not MEZ_buffer (11);
data (5) <= not MEZ_buffer (10);
data (22) <= not MEZ_buffer (13);
data (6) <= not MEZ_buffer (12);
data (23) <= not MEZ_buffer (15);
data (7) <= not MEZ_buffer (14);
data (24) <= not MEZ_buffer (41);
data (8) <= not MEZ_buffer (40);
data (25) <= not MEZ_buffer (43);
data (9) <= not MEZ_buffer (42);
data (26) <= not MEZ_buffer (45);
data (10) <= not MEZ_buffer (44);
data (27) <= not MEZ_buffer (47);
data (11) <= not MEZ_buffer (46);
data (28) <= not MEZ_buffer (49);
data (12) <= not MEZ_buffer (48);
data (29) <= not MEZ_buffer (51);
data (13) <= not MEZ_buffer (50);
data (30) <= not MEZ_buffer (53);
data (14) <= not MEZ_buffer (52);
data (31) <= not MEZ_buffer (55);
data (15) <= not MEZ_buffer (54);
--defined as inputs, simply leave them open
--MEZ(39 downto 16) <= (others=>'0');
--MEZ(73 downto 56) <= (others=>'0');
end Behavioral;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab01/lab01/ipcore_dir/RAM_B/simulation/checker.vhd
|
69
|
5607
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-3.0
|
SWORDfpga/ComputerOrganizationDesign
|
labs/lab10/lab10/ipcore_dir/RAM_B/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
hacklabmikkeli/rough-boy
|
synthesizer_test.vhdl
|
2
|
1014
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity synthesizer_test is
end entity;
architecture synthesizer_test_impl of synthesizer_test is
begin
end architecture;
|
gpl-3.0
|
hacklabmikkeli/rough-boy
|
waveshaper_test.vhdl
|
2
|
1011
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity waveshaper_test is
end entity;
architecture waveshaper_test_impl of waveshaper_test is
begin
end architecture;
|
gpl-3.0
|
rafa-jfet/OFM
|
ARCHIVOS VHDL/gray2angleinc.vhd
|
1
|
3389
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:15:11 05/08/2015
-- Design Name:
-- Module Name: gray2angleinc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gray2angleinc is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR (0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
anginc_out : out STD_LOGIC_VECTOR (2 downto 0);
ok_anginc_out : out STD_LOGIC);
end gray2angleinc;
architecture Behavioral of gray2angleinc is
type estado is ( bit_0,
bit_1,
bit_2,
salida_valida );
signal estado_actual : estado;
signal estado_nuevo : estado;
signal anginc_int, p_anginc_int : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
anginc_out <= anginc_int;
comb : process ( estado_actual, bit_in, ok_bit_in, anginc_int, modulation)
begin
p_anginc_int <= anginc_int;
ok_anginc_out <= '0';
estado_nuevo <= estado_actual;
case estado_actual is
when bit_0 =>
if ok_bit_in = '1' then
p_anginc_int(2) <= bit_in(0);
if modulation = "100" then
-- gray a decimal multiplicado por 4 (desplazamiento bits izq *2)
-- p_anginc_int(2) <= bit_in; --(gray a decimal) *2
p_anginc_int ( 1 downto 0 ) <= "00";
estado_nuevo <= salida_valida;
else
-- p_anginc_int(0) <= bit_in;
estado_nuevo <= bit_1;
end if;
end if;
when bit_1 =>
if ok_bit_in = '1' then
p_anginc_int(1) <= anginc_int(2) xor bit_in(0);
if modulation = "010" then
-- gray a decimal multiplicado por 2 (desplazamiento bits izq)
---- p_anginc_int(2) <= anginc_int(0);
-- p_anginc_int(1) <= anginc_int(0) xor bit_in;
p_anginc_int(0) <= '0';
estado_nuevo <= salida_valida;
else
-- p_anginc_int(1) <= bit_in;
estado_nuevo <= bit_2;
end if;
end if;
when bit_2 =>
p_anginc_int(0) <= anginc_int(1) xor bit_in(0);
if ok_bit_in = '1' then
-- gray a decimal
-- p_anginc_int(2) <= bit_in; --bin2 = gray2
-- p_anginc_int(1) <= anginc_int(1) xor bit_in; --bin1 = gray1 xor bin2(=gray2)
-- p_anginc_int(0) <= anginc_int(0) xor anginc_int(1) xor bit_in; --bin0 = gray0 xor bin1(=gray1 xor bin2)
estado_nuevo <= salida_valida;
end if;
when salida_valida =>
ok_anginc_out <= '1';
estado_nuevo <= bit_0;
end case;
end process;
sinc : process ( reset, clk )
begin
if ( reset = '1' ) then
anginc_int <= "000";
estado_actual <= bit_0;
elsif ( rising_edge(clk) ) then
anginc_int <= p_anginc_int;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
rafa-jfet/OFM
|
ARCHIVOS VHDL/FSM.vhd
|
1
|
5508
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:21:00 03/23/2015
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FSM is
Generic (ancho_bus_dir:integer:=9;
VAL_SAT_CONT:integer:=5208;
ANCHO_CONTADOR:integer:=13;
ULT_DIR_TX : integer := 420);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
button : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
direcc : out STD_LOGIC_VECTOR (ancho_bus_dir -1 downto 0);
TX : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type estado is (reposo,
inicio,
test_data,
b_start,
b_0,
b_1,
b_2,
b_3,
b_4,
b_5,
b_6,
b_7,
b_paridad,
b_stop,
espera,
fin);
signal estado_actual: estado;
signal estado_nuevo: estado;
signal dir, p_dir: std_logic_vector (ancho_bus_dir -1 downto 0);
signal cont, p_cont: std_logic_vector (ANCHO_CONTADOR -1 downto 0);
signal byte_tx, p_byte_tx : std_logic_vector (1 downto 0);
signal data, p_data : std_logic_vector (7 downto 0);
begin
direcc <= dir;
maq_estados:process(estado_actual, button, data, cont, dir, byte_tx, data_in)
begin
p_dir <= dir;
p_cont <= cont;
p_byte_tx <= byte_tx;
p_data <= data;
TX <= '1';
case estado_actual is
when reposo =>
TX <= '1';
p_dir <= (others => '0');
p_cont <= (others => '0');
p_byte_tx <= "00";
if button = '1' then
estado_nuevo <= inicio;
else
estado_nuevo <= reposo;
end if;
when inicio =>
TX <= '1';
estado_nuevo <= test_data;
case byte_tx is
when "00" =>
p_data <= data_in (31 downto 24);
when "01" =>
p_data <= data_in (23 downto 16);
when "10" =>
p_data <= data_in (15 downto 8);
when OTHERS =>
p_data <= data_in (7 downto 0);
end case;
when test_data =>
TX <= '1';
if dir = ULT_DIR_TX then
estado_nuevo <= fin;
else
estado_nuevo <= b_start;
end if;
when b_start =>
TX <= '0';
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_0;
else
estado_nuevo <= b_start;
end if;
when b_0 =>
TX <= data(0);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_1;
else
estado_nuevo <= b_0;
end if;
when b_1 =>
TX <= data(1);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_2;
else
estado_nuevo <= b_1;
end if;
when b_2 =>
TX <= data(2);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_3;
else
estado_nuevo <= b_2;
end if;
when b_3 =>
TX <= data(3);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_4;
else
estado_nuevo <= b_3;
end if;
when b_4 =>
TX <= data(4);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_5;
else
estado_nuevo <= b_4;
end if;
when b_5 =>
TX <= data(5);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_6;
else
estado_nuevo <= b_5;
end if;
when b_6 =>
TX <= data(6);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_7;
else
estado_nuevo <= b_6;
end if;
when b_7 =>
TX <= data(7);
p_cont <= cont +1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_paridad;
else
estado_nuevo <= b_7;
end if;
when b_paridad =>
TX <= data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);
p_cont <= cont + 1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= b_stop;
else
estado_nuevo <= b_paridad;
end if;
when b_stop =>
TX <= '1';
p_cont <= cont + 1;
if cont = VAL_SAT_CONT then
p_cont <= (others => '0');
estado_nuevo <= espera;
else
estado_nuevo <= b_stop;
end if;
when espera =>
p_byte_tx <= byte_tx +1;
if (byte_tx = "11") then
p_dir <= dir +1;
end if;
estado_nuevo <= inicio;
when fin =>
end case;
end process;
sinc:process(reset, clk)
begin
if reset = '1' then
cont <= (others => '0');
estado_actual <= reposo;
dir <= (others => '0');
byte_tx <= (others => '0');
data <= (others => '0');
elsif rising_edge(clk) then
cont <= p_cont;
estado_actual <= estado_nuevo;
dir <= p_dir;
byte_tx <= p_byte_tx;
data <= p_data;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
rafa-jfet/OFM
|
ARCHIVOS VHDL/guardaifft.vhd
|
1
|
2526
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:49:53 06/29/2015
-- Design Name:
-- Module Name: guardaifft - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity guardaifft is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
dv : in STD_LOGIC;
cpv : in STD_LOGIC;
edone : in STD_LOGIC;
xk_index : in STD_LOGIC_VECTOR(6 downto 0);
we : out STD_LOGIC;
xk_re : in STD_LOGIC_VECTOR (15 downto 0);
xk_im : in STD_LOGIC_VECTOR (15 downto 0);
EnableTxserie : out STD_LOGIC;
dato_out : out STD_LOGIC_VECTOR (31 downto 0);
addresout : out STD_LOGIC_VECTOR (8 downto 0));
end guardaifft;
architecture Behavioral of guardaifft is
type estado is ( reposo,
inicio,
fin);
signal estado_actual, estado_nuevo : estado;
signal dir_actual, dir_nueva: STD_LOGIC_VECTOR(8 downto 0);
begin
sinc : process(reset, clk)
begin
if(reset='1') then
estado_actual <= reposo;
dir_actual <= (others => '0');
elsif (clk='1' and clk'event) then
dir_actual <= dir_nueva;
estado_actual <= estado_nuevo;
end if;
end process;
addresout <= dir_actual;
dato_out <= xk_re & xk_im;
comb : process (estado_actual, dir_actual, dv, cpv, xk_index, edone)
begin
we <= dv;
dir_nueva <= dir_actual;
EnableTxserie <= '0';
case estado_actual is
when reposo =>
if ( dv='1') then
estado_nuevo <= inicio;
dir_nueva <=dir_actual+1;
else
estado_nuevo <= reposo;
end if;
when inicio =>
if (dv='1') then
dir_nueva <= dir_actual+1;
estado_nuevo <=inicio;
else
estado_nuevo<= fin;
end if;
when fin =>
EnableTXserie<='1';
estado_nuevo <=reposo;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/vhdlFile/constant_declaration/classification_test_input.vhd
|
1
|
407
|
architecture RTL of FIFO is
constant StartDay : WeekDay := Sat;
constant LogicalGND : Bit := '0';
constant BusWidth, QueueLength : Integer := 16;
constant CLKPeriod : Time := 15 ns;
constant MaxSimTime : Time := 200 * CLKPeriod;
constant EntryCode : NumericCodeType := (2,6,4,8,0,0,1,3);
constant DataBusReset: Std_Logic_Vector(7 downto 0) := "00000000";
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/package/rule_003_test_input.fixed.vhd
|
1
|
133
|
package fifo_pkg is
end package;
library ieee;
package fifo_pkg is
end package;
-- Comment
package fifo_pkg is
end package;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/variable/rule_012_test_input.vhd
|
1
|
349
|
architecture RTL of FIFO is
shared variable v_shar_var1 : integer;
begin
process
variable v_var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/subprogram_body/rule_201_test_input.fixed.vhd
|
1
|
736
|
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 is
constant width : integer := 32;
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
constant width : integer := 32;
begin
end procedure proc1;
-- Fixes follow
procedure proc1 is
constant width : integer := 32;
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
constant width : integer := 32;
begin
end procedure proc1;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/file_statement/rule_001_test_input.fixed.vhd
|
1
|
521
|
architecture RTL of FIFO is
file defaultImage : load_file_type open read_mode is load_file_name;
file defaultImage : load_file_type
open read_mode is load_file_name;
file defaultImage : load_file_type
open read_mode
is load_file_name;
-- Violations below
file defaultImage : load_file_type open read_mode is load_file_name;
file defaultImage : load_file_type
open read_mode is load_file_name;
file defaultImage : load_file_type
open read_mode
is load_file_name;
begin
end;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/afifo.vhd
|
20
|
9200
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generic/rule_010_test_input.fixed_move_left.vhd
|
1
|
441
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32) -- Comment
;
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32); -- Comment should stay
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/kintex7/rx-core/wb_rx_bridge.vhd
|
1
|
13975
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Bridge between Rx core and Mem
-- ####################################
-- # Address Map:
-- # 0x0000: Start Adr (RO)
-- # 0x0001: Data Cnt (RO)
-- # 0x0002[0]: Loopback (RW)
-- # 0x0003: Data Rate (RO)
-- # 0x0004: Loop Fifo (WO)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(63 downto 0);
dma_dat_i : in std_logic_vector(63 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(63 downto 0);
rx_valid_i : in std_logic;
-- Status In
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end wb_rx_bridge;
architecture Behavioral of wb_rx_bridge is
-- Cmoponents
COMPONENT rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT rx_bridge_ctrl_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Constants
constant c_ALMOST_FULL_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(240, 8);
constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((1680*30), 32); -- ~200kByte, magic number (!!) divisible my any channel number of to 8
constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms
constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec
constant c_EMPTY_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(16, 8);
constant c_EMPTY_TIMEOUT : unsigned(9 downto 0) := TO_UNSIGNED(2000, 10);
-- Signals
signal data_fifo_din : std_logic_vector(63 downto 0);
signal data_fifo_dout : std_logic_vector(63 downto 0);
signal data_fifo_wren : std_logic;
signal data_fifo_rden : std_logic;
signal data_fifo_full : std_logic;
signal data_fifo_empty : std_logic;
signal data_fifo_almost_full : std_logic;
signal data_fifo_prog_empty : std_logic;
signal data_fifo_empty_cnt : unsigned(10 downto 0);
signal data_fifo_empty_true : std_logic;
signal data_fifo_empty_pressure : std_logic;
signal ctrl_fifo_din : std_logic_vector(63 downto 0);
signal ctrl_fifo_dout : std_logic_vector(63 downto 0);
signal ctrl_fifo_wren : std_logic;
signal ctrl_fifo_rden : std_logic;
signal ctrl_fifo_full : std_logic;
signal ctrl_fifo_empty : std_logic;
signal dma_stb_t : std_logic;
signal dma_stb_valid : std_logic;
signal dma_adr_cnt : unsigned(31 downto 0);
signal dma_start_adr : unsigned(31 downto 0);
signal dma_data_cnt : unsigned(31 downto 0);
signal dma_data_cnt_d : unsigned(31 downto 0);
signal dma_timeout_cnt : unsigned(31 downto 0);
signal dma_ack_cnt : unsigned(7 downto 0);
signal rx_data_local : std_logic_vector(31 downto 0);
signal rx_valid_local : std_logic;
signal rx_data_local_d : std_logic_vector(31 downto 0);
signal rx_valid_local_d : std_logic;
signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0);
signal time_cnt : unsigned(31 downto 0);
signal time_pulse : std_logic;
signal data_rate_cnt : unsigned(31 downto 0);
signal trig_cnt : unsigned(31 downto 0);
signal trig_pulse_d0 : std_logic;
signal trig_pulse_d1 : std_logic;
signal trig_pulse_pos : std_logic;
-- Registers
signal loopback : std_logic;
signal data_rate : std_logic_vector(31 downto 0);
begin
--Tie offs
irq_o <= '0';
busy_o <= data_fifo_full;
-- Wishbone Slave
wb_slave_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_stall_o <= '0';
ctrl_fifo_rden <= '0';
rx_valid_local <= '0';
ctrl_fifo_dout_tmp <= (others => '0');
-- Regs
loopback <= '0';
elsif rising_edge(sys_clk_i) then
-- Default
wb_ack_o <= '0';
ctrl_fifo_rden <= '0';
wb_stall_o <= '0';
rx_valid_local <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '0') then
-- READ
if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr
if (ctrl_fifo_empty = '0') then
wb_dat_o <= ctrl_fifo_dout(31 downto 0);
ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32);
wb_ack_o <= '1';
ctrl_fifo_rden <= '1';
else
wb_dat_o <= x"FFFFFFFF";
ctrl_fifo_dout_tmp <= (others => '0');
wb_ack_o <= '1';
ctrl_fifo_rden <= '0';
end if;
elsif (wb_adr_i(3 downto 0) = x"1") then -- Count
wb_dat_o <= ctrl_fifo_dout_tmp;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= loopback;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate
wb_dat_o <= data_rate;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= data_fifo_empty_true;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count
wb_dat_o <= std_logic_vector(dma_data_cnt_d);
wb_ack_o <= '1';
else
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end if;
else
-- WRITE
wb_ack_o <= '1';
if (wb_adr_i(3 downto 0) = x"2") then
loopback <= wb_dat_i(0);
elsif (wb_adr_i(3 downto 0) = x"4") then
rx_valid_local <= '1';
end if;
end if;
end if;
end if;
end process wb_slave_proc;
-- Data from Rx
data_rec : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i <= '0') then
data_fifo_wren <= '0';
data_fifo_din <= (others => '0');
elsif rising_edge(sys_clk_i) then
if (loopback = '1') then
data_fifo_wren <= rx_valid_local_d;
data_fifo_din <= X"03000000" & rx_data_local_d;
else
data_fifo_wren <= rx_valid_i;
data_fifo_din <= rx_data_i;
end if;
end if;
end process data_rec;
-- Empty logic to produce some backpressure
data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure;
empty_proc : process(dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fifo_empty_pressure <= '0';
data_fifo_empty_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Timeout Counter
if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then
data_fifo_empty_cnt <= data_fifo_empty_cnt + 1;
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_cnt <= (others => '0');
end if;
if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_prog_empty = '0') then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_pressure <= '1';
end if;
end if;
end process empty_proc;
-- DMA Master and data control
dma_stb_valid <= dma_stb_t and not data_fifo_empty;
to_ddr_proc: process(dma_clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
dma_stb_t <= '0';
data_fifo_rden <= '0';
dma_adr_o <= (others => '0');
dma_dat_o <= (others => '0');
dma_cyc_o <= '0';
dma_stb_o <= '0';
dma_we_o <= '1'; -- Write only
elsif rising_edge(dma_clk_i) then
if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then
dma_stb_t <= '1';
data_fifo_rden <= '1';
else
dma_stb_t <= '0';
data_fifo_rden <= '0';
end if;
if (data_fifo_empty = '0' or dma_ack_cnt > 0) then
dma_cyc_o <= '1';
else
dma_cyc_o <= '0';
end if;
dma_adr_o <= std_logic_vector(dma_adr_cnt);
dma_dat_o <= data_fifo_dout;
dma_stb_o <= dma_stb_t and not data_fifo_empty;
dma_we_o <= '1'; -- Write only
end if;
end process to_ddr_proc;
adr_proc : process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ctrl_fifo_wren <= '0';
dma_adr_cnt <= (others => '0');
dma_start_adr <= (others => '0');
dma_data_cnt <= (others => '0');
dma_data_cnt_d <= (others => '0');
dma_timeout_cnt <= (others => '0');
ctrl_fifo_din(63 downto 0) <= (others => '0');
dma_ack_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Address Counter
if (dma_stb_valid = '1') then
dma_adr_cnt <= dma_adr_cnt + 1;
end if;
if (dma_stb_valid = '1' and dma_ack_i = '0') then
dma_ack_cnt <= dma_ack_cnt + 1;
elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then
dma_ack_cnt <= dma_ack_cnt - 1;
end if;
-- Package size counter
-- Check if Fifo is full
if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(2, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + dma_data_cnt;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '1') then
dma_data_cnt <= dma_data_cnt + 2;
ctrl_fifo_wren <= '0';
else
ctrl_fifo_wren <= '0';
end if;
dma_data_cnt_d <= dma_data_cnt;
-- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt);
-- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1);
-- end if;
-- Timeout counter
if (dma_data_cnt > 0 and data_fifo_empty = '1') then
dma_timeout_cnt <= dma_timeout_cnt + 1;
elsif (data_fifo_empty = '0') then
dma_timeout_cnt <= TO_UNSIGNED(0, 32);
end if;
end if;
end process adr_proc;
-- Data Rate maeasurement
data_rate_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_rate_cnt <= (others => '0');
data_rate <= (others => '0');
time_cnt <= (others => '0');
time_pulse <= '0';
elsif rising_edge(sys_clk_i) then
-- 1Hz pulser
if (time_cnt = c_TIME_FRAME) then
time_cnt <= (others => '0');
time_pulse <= '1';
else
time_cnt <= time_cnt + 1;
time_pulse <= '0';
end if;
if (time_pulse = '1') then
data_rate <= std_logic_vector(data_rate_cnt);
data_rate_cnt <= (others => '0');
elsif (data_fifo_wren = '1') then
data_rate_cnt <= data_rate_cnt + 1;
end if;
end if;
end process data_rate_proc;
-- Loopback delay
delayproc : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_data_local <= (others => '0');
rx_data_local_d <= (others => '0');
rx_valid_local_d <= '0';
elsif rising_edge(sys_clk_i) then
rx_data_local_d <= wb_dat_i;
rx_valid_local_d <= rx_valid_local;
end if;
end process;
-- Trigger sync and count
trig_sync : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_pulse_d0 <= '0';
trig_pulse_d1 <= '0';
trig_pulse_pos <= '0';
trig_cnt <= (others => '0');
elsif rising_edge(sys_clk_i) then
trig_pulse_d0 <= trig_pulse_i;
trig_pulse_d1 <= trig_pulse_d0;
if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then
trig_pulse_pos <= '1';
else
trig_pulse_pos <= '0';
end if;
if (trig_pulse_pos = '1') then
trig_cnt <= trig_cnt + 1;
end if;
end if;
end process trig_sync;
cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => sys_clk_i,
rd_clk => dma_clk_i,
din => data_fifo_din,
wr_en => data_fifo_wren,
rd_en => data_fifo_rden,
prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD),
prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD),
dout => data_fifo_dout,
full => data_fifo_full,
empty => data_fifo_empty_true,
prog_full => data_fifo_almost_full,
prog_empty => data_fifo_prog_empty
);
cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => dma_clk_i,
rd_clk => sys_clk_i,
din => ctrl_fifo_din,
wr_en => ctrl_fifo_wren,
rd_en => ctrl_fifo_rden,
dout => ctrl_fifo_dout,
full => ctrl_fifo_full,
empty => ctrl_fifo_empty
);
end Behavioral;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity_specification/rule_100_test_input.fixed.vhd
|
1
|
265
|
architecture RTL of FIFO is
attribute coordinate of comp_1: component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1: component is (0.0, 17.5);
attribute coordinate of comp_1: component is (0.0, 17.5);
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/package_body/rule_402_test_input.fixed.vhd
|
1
|
448
|
package body RTL is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
procedure rst_procedure is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
begin
end procedure;
end package body RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/sequential/rule_007_test_input.vhd
|
1
|
282
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <= sig2; sig2 <= sig3; -- Comment 1
siga <= sigb; sigb <= sigc; sigc <= sigd;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generic/rule_010_test_input.fixed.vhd
|
1
|
442
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32 -- Comment should stay
);
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/function/rule_006_test_input.fixed.vhd
|
1
|
425
|
architecture RTL of FIFO is
function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
-- Violations follow
function func1 return integer;
function func1 return integer;
pure function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
impure function func1 return integer;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_029_test_input.vhd
|
1
|
151
|
entity FIFO is
port (
I_INPUT : in std_logic
);
begin
end entity;
entity FIFO is
port (
I_INPUT : in std_logic
);begin
end entity;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/constant/rule_001_test_input.vhd
|
1
|
314
|
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin
process
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/case/rule_007_test_input.vhd
|
1
|
459
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
-- Comments are fine
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
sig1 <= sig2;
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/context/rule_014_test_input.fixed_lower.vhd
|
4
|
145
|
--This should pass
context con1 is
end context con1;
--These should fail
context con1 is
end context con1;
context co1 is
end context con1;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/comment/comment_process_test_input.vhd
|
1
|
811
|
architecture ARCH of ENTITY is
begin
-- comment
-- comment
-- comment
PROC_1 : process (a) is
-- comment
-- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
PROC_1 : process (a) is
-- comment
-- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
PROC_1 : process (a) is
variable a : integer 0 to 10; -- comment
variable b : natural 0 to 256; -- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generate/rule_006_test_input.fixed.vhd
|
1
|
695
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
end;
|
gpl-3.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/sim_models/T80a.vhd
|
2
|
7682
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
D_I : in std_logic_vector(7 downto 0);
D_O : out std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D_I, -- D -> D_I
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D_I); -- D -> D_I
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/if_statement/rule_006_test_input.vhd
|
1
|
1085
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Check overrides
if a = '1' then
case x is
end case;
end if;
if a = '1' then
case x is
end case;
end if;
-- Check loop statements
if a = '1' then
LOOP_LABEL : loop
end loop;
end if;
if a = '1' then
loop
end loop;
end if;
if a = '1' then
while a = 0
loop
end loop;
end if;
if a = '1' then
for i in 0 to 13
loop
end loop;
end if;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/styles/jcl/comments.fixed.vhd
|
1
|
526
|
--! Comment 1
library ieee;
--! Comment 1.5
use ieee.std_logic_1164.all;
--! Comment 2
library ieee;
--! Comment 2.5
use ieee.std_logic_1164.all;
--! Comment 3
--! Comment 3.5
use ieee.std_logic_1164.all;
--! Comment 4
--! Comment 5
architecture RTL of FIFO is
begin
SOME_LABEL : case D_DEPTH generate
-- When comment
-- When comment
when 0 =>
-- Comment 10
b <= 0;
-- When Comment 2
-- When Comment 2
when 1 =>
end generate SOME_LABEL;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_waveforms/rule_103_test_input.fixed.vhd
|
1
|
410
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else'1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else'1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/library/rule_002_test_input.vhd
|
1
|
36
|
library ieee;
library ieee;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/if_statement/rule_030_test_input.vhd
|
1
|
423
|
architecture RTL of FIFO is
begin
process
begin
if a then
if b then
if c then
c <= d;
end if;
a <= b;
end if;
b <= c;
end if;
z <= a;
-- Violations below
if a then
if b then
if c then
c <= d;
end if;
a <= b;
end if;
b <= c;
end if;
z <= a;
end process;
end architecture RTL;
|
gpl-3.0
|
Jorge9314/ElectronicaDigital
|
Impresora2D/rs232_tb.vhd
|
1
|
4331
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rs232_tb IS
END rs232_tb;
ARCHITECTURE behavior OF rs232_tb IS
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
Activador_Envio_Mensaje : IN std_logic;
Salida_1bit : OUT std_logic;
Entrada_1bit : IN std_logic;
Mensaje_8bits : OUT std_logic_vector(7 downto 0);
Activador_Entrega_Mensaje : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Entrada_8bits : std_logic_vector(7 downto 0) := (others => '0');
signal Activador_Envio_Mensaje : std_logic := '0';
signal Entrada_1bit : std_logic := '0';
--Outputs
signal Salida_1bit : std_logic;
signal Mensaje_8bits : std_logic_vector(7 downto 0);
signal Activador_Entrega_Mensaje : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232 PORT MAP (
clk => clk,
Entrada_8bits => Entrada_8bits,
Activador_Envio_Mensaje => Activador_Envio_Mensaje,
Salida_1bit => Salida_1bit,
Entrada_1bit => Entrada_1bit,
Mensaje_8bits => Mensaje_8bits,
Activador_Entrega_Mensaje => Activador_Entrega_Mensaje
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-------------------------------------------------------------
-- Recibo un 11111111 con paridad 0
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 01111110 con paridad 1 MALO!!!!!!
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 10110110 con paridad 1
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
wait;
end process;
END;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/procedure/rule_200_test_input.fixed.vhd
|
1
|
242
|
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
-- Violations follow
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_expressions/rule_102_test_input.fixed.vhd
|
1
|
411
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1')else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/loop_statement/rule_003_test_input.vhd
|
1
|
151
|
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop end
loop;
end process;
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/function/rule_008_test_input.vhd
|
1
|
401
|
architecture RTL of FIFO is
function func1 (
a : integer;
constant b : integer;
signal c : std_logic;
variable v : std_logic;
file f : std_logic
) return integer;
-- Violations
function func1 (
a : integer;
constant b : integer;
signal c : std_logic;
variable v : std_logic;
file f : std_logic
) return integer;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_020_test_input.fixed_combined_generic.vhd
|
1
|
700
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/whitespace/rule_002_test_input.vhd
|
1
|
247
|
library ieee;
library ieee;
library ieee;
library ieee;
library ieee;
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_no_align_paren_no_align_when_yes_wrap_at_when_yes_align_else_yes.vhd
|
1
|
2219
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/signal/rule_600_test_input.vhd
|
1
|
197
|
architecture RTL of FIFO is
signal sig1_s : std_logic;
signal sig2_s : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/concurrent/rule_401_test_input.vhd
|
1
|
434
|
architecture rtl of fifo is
begin
wr_data <=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
d <=
(d2 xor to_stdulogic(gen2)) &
(d1 xor to_stdulogic(gen1));
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/use_clause/rule_502_test_input.fixed_upper_with_exceptions.vhd
|
3
|
181
|
use My_Math_Stuff.MY_STRING_STUFF.my_string_stuff;
use My_Math_Stuff.My_Math_Stuff.My_Math_Stuff;
use My_Logic_Stuff.my_logic_stuff.MY_LOGIC_STUFF;
use ieee.std_logic_1164.all;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/port_map/rule_002_test_input.vhd
|
2
|
585
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/context/rule_022_test_input.fixed_remove.vhd
|
1
|
215
|
--This should pass
context con1 is
end context;
context con2 is
end context;
--This should fail
context con3 is
end;
context con4 is
end
;
-- Split declaration across lines
context
con5
is
end
context
;
|
gpl-3.0
|
Yarr/Yarr-fw
|
syn/spec/top_yarr_spec_fe65p2.vhd
|
1
|
62889
|
--------------------------------------------
-- Project: YARR
-- Author: Timon Heim ([email protected])
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.board_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity yarr is
port
(
-- On board 20MHz oscillator
clk20_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n : out std_logic; -- 25MHz VCXO
pll20dac_sync_n : out std_logic; -- 20MHz VCXO
plldac_din : out std_logic;
plldac_sclk : out std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
clk_125m_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- DDR3
DDR3_CAS_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_RZQ : inout std_logic;
DDR3_ZIO : inout std_logic;
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
DAC_LD : out std_logic;
INJ_SW : out std_logic;
DAC_DIN : out std_logic;
DAC_CLK : out std_logic;
DAC_CS : out std_logic;
TRIGGER_P : out std_logic;
TRIGGER_N : out std_logic;
CLK_DATA_P : out std_logic;
CLK_DATA_N : out std_logic;
RST_0_P : out std_logic;
RST_0_N : out std_logic;
CLK_CNFG_P : out std_logic;
CLK_CNFG_N : out std_logic;
PIX_D_CNFG_P : out std_logic;
PIX_D_CNFG_N : out std_logic;
LD_CNFG_P : out std_logic;
LD_CNFG_N : out std_logic;
CLK_BX_P : out std_logic;
CLK_BX_N : out std_logic;
RST_1_P : out std_logic;
RST_1_N : out std_logic;
EN_PIX_SR_CNFG_P : out std_logic;
EN_PIX_SR_CNFG_N : out std_logic;
SI_CNFG_P : out std_logic;
SI_CNFG_N : out std_logic;
SO_CNFG_P : in std_logic;
SO_CNFG_N : in std_logic;
HIT_OR_P : in std_logic;
HIT_OR_N : in std_logic;
OUT_DATA_P : in std_logic;
OUT_DATA_N : in std_logic;
EXT_4_P : out std_logic;
EXT_4_N : out std_logic;
EXT_3_P : in std_logic;
EXT_3_N : in std_logic;
EXT_2_P : out std_logic;
EXT_2_N : out std_logic;
EXT_1_P : in std_logic;
EXT_1_N : in std_logic;
IO_0 : out std_logic;
IO_1 : in std_logic
);
end yarr;
architecture rtl of yarr is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
COMPONENT fe65p2_addon
PORT(
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
clk_bx_o : OUT std_logic;
trig_o : OUT std_logic;
clk_cnfg_o : OUT std_logic;
en_pix_sr_cnfg_o : OUT std_logic;
ld_cnfg_o : OUT std_logic;
si_cnfg_o : OUT std_logic;
pix_d_cnfg_o : OUT std_logic;
clk_data_o : OUT std_logic;
rst_0_o : OUT std_logic;
rst_1_o : OUT std_logic;
dac_sclk_o : OUT std_logic;
dac_sdi_o : OUT std_logic;
dac_ld_o : OUT std_logic;
dac_cs_o : OUT std_logic;
inj_sw_o : OUT std_logic
);
END COMPONENT;
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- Async
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
component clk_gen
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLK_40_90 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component ila_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk : std_logic;
-- IO clocks
signal CLK_40 : std_logic;
signal CLK_80 : std_logic;
signal CLK_125 : std_logic;
signal CLK_160 : std_logic;
signal CLK_640 : std_logic;
signal CLK_40_buf : std_logic;
signal CLK_40_90_buf : std_logic;
signal CLK_80_buf : std_logic;
signal CLK_160_buf : std_logic;
signal CLK_640_buf : std_logic;
signal ioclk_fb : std_logic;
-- System clock generation
signal sys_clk_in : std_logic;
signal sys_clk_40_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_40 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal locked : std_logic;
signal locked_v : std_logic_vector(1 downto 0);
signal rst_n : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0');
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal ram_we : std_logic;
-- DMAbus RX bridge
signal rx_dma_adr : std_logic_vector(31 downto 0);
signal rx_dma_dat_o : std_logic_vector(31 downto 0);
signal rx_dma_dat_i : std_logic_vector(31 downto 0);
signal rx_dma_cyc : std_logic;
signal rx_dma_stb : std_logic;
signal rx_dma_we : std_logic;
signal rx_dma_ack : std_logic;
signal rx_dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_out : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- I2C
signal scl_t : std_logic;
signal sda_t : std_logic;
-- Trigger logic
signal int_busy_t : std_logic;
signal trig_tag_t : std_logic_vector(31 downto 0);
signal int_trig_t : std_logic;
signal eudet_trig_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_rst_t : std_logic;
signal eudet_busy_t : std_logic;
-- FOR TESTS
signal debug : std_logic_vector(31 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
-- ILA
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal debug_dma : std_logic_vector(31 downto 0);
signal ddr_status : std_logic_vector(31 downto 0);
signal gn4124_core_Status : std_logic_vector(31 downto 0);
signal tx_data_o : std_logic_vector(0 downto 0);
signal trig_pulse : std_logic;
signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0);
signal rx_data : std_logic_vector(31 downto 0);
signal rx_valid : std_logic;
signal rx_busy : std_logic;
-- FMC
signal dac_ld_t : std_logic;
signal inj_sw_t : std_logic;
signal dac_din_t : std_logic;
signal dac_clk_t : std_logic;
signal dac_cs_t : std_logic;
signal trigger_t : std_logic;
signal clk_data_t : std_logic;
signal rst_0_t : std_logic;
signal clk_cnfg_t : std_logic;
signal pix_d_cnfg_t : std_logic;
signal ld_cnfg_t : std_logic;
signal clk_bx_t : std_logic;
signal rst_1_t : std_logic;
signal en_pix_sr_cnfg_t : std_logic;
signal si_cnfg_t : std_logic;
signal so_cnfg_t : std_logic;
signal hit_or_t : std_logic;
signal out_data_t : std_logic;
begin
-- Buffers
dac_ld <= dac_ld_t;
inj_sw <= inj_sw_t;
dac_din <= dac_din_t;
dac_clk <= dac_clk_t;
dac_cs <= dac_cs_t;
trigger_buf : OBUFDS port map (O => trigger_n, OB => trigger_p, I => not trigger_t); -- inv
clk_datar_buf : OBUFDS port map (O => clk_data_p, OB => clk_data_n, I => clk_data_t);
rst_0_buf : OBUFDS port map (O => rst_0_n, OB => rst_0_p, I => not rst_0_t); -- inv
clk_cnfg_buf : OBUFDS port map (O => clk_cnfg_n, OB => clk_cnfg_p, I => clk_cnfg_t); --inv
pix_d_cnfg_buf : OBUFDS port map (O => pix_d_cnfg_p, OB => pix_d_cnfg_n, I => pix_d_cnfg_t);
ld_cnfg_buf : OBUFDS port map (O => ld_cnfg_p, OB => ld_cnfg_n, I => ld_cnfg_t);
clk_bx_buf : OBUFDS port map (O => clk_bx_p, OB => clk_bx_n, I => clk_bx_t);
en_pix_sr_cnfg_buf : OBUFDS port map (O => en_pix_sr_cnfg_n, OB => en_pix_sr_cnfg_p, I => not en_pix_sr_cnfg_t); -- inv
rst_1_buf : OBUFDS port map (O => rst_1_n, OB => rst_1_p, I => not rst_1_t); --inv
si_cnfg_buf : OBUFDS port map (O => si_cnfg_p, OB => si_cnfg_n, I => si_cnfg_t);
eudet_clk_buf : OBUFDS port map (O => EXT_4_P, OB => EXT_4_N, I => not eudet_clk_t);
eudet_busy_buf : OBUFDS port map (O => EXT_2_P, OB => EXT_2_N, I => eudet_busy_t);
so_cnfg_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => so_cnfg_t, I => so_cnfg_p, IB => so_cnfg_n);
hit_or_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => hit_or_t, I => hit_or_p, IB => hit_or_n);
out_data_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => out_data_t, I => out_data_p, IB => out_data_n);
eudet_rst_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_rst_t, I => EXT_3_P, IB => EXT_3_N);
eudet_trig_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_trig_t, I => EXT_1_P, IB => EXT_1_N);
fe_data_i(0) <= not out_data_t;
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
IBUFGDS_gn_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL18_I"
)
port map (
O => l_clk, -- Clock buffer output
I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS_pll_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25"
)
port map (
O => CLK_125, -- Clock buffer output
I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
cmp_fe65p2_addon: fe65p2_addon PORT MAP(
clk_i => CLK_40,
rst_n => rst_n,
serial_in => fe_cmd_o(0),
clk_rx_i => CLK_40,
clk_bx_o => clk_bx_t,
trig_o => trigger_t,
clk_cnfg_o => clk_cnfg_t,
en_pix_sr_cnfg_o => en_pix_sr_cnfg_t,
ld_cnfg_o => ld_cnfg_t,
si_cnfg_o => si_cnfg_t,
pix_d_cnfg_o => pix_d_cnfg_t,
clk_data_o => clk_data_t,
rst_0_o => rst_0_t,
rst_1_o => rst_1_t,
dac_sclk_o => dac_clk_t,
dac_sdi_o => dac_din_t,
dac_ld_o => dac_ld_t,
dac_cs_o => dac_cs_t,
inj_sw_o => inj_sw_t
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => rst_n,
status_o => gn4124_core_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_out,
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0'
);
GPIO(0) <= irq_out;
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk,
rst_n_i => rst_n,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
-- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-- port map(
-- rst_n_i => rst_n,
-- wb_clk_i => sys_clk,
-- wb_addr_i => wb_adr(1 downto 0),
-- wb_data_i => wb_dat_o,
-- wb_data_o => wb_dat_i(63 downto 32),
-- wb_cyc_i => wb_cyc(1),
-- wb_sel_i => wb_sel,
-- wb_stb_i => wb_stb,
-- wb_we_i => wb_we,
-- wb_ack_o => wb_ack(1),
-- dummy_stat_reg_1_i => dummy_stat_reg_1,
-- dummy_stat_reg_2_i => dummy_stat_reg_2,
-- dummy_stat_reg_3_i => dummy_stat_reg_3,
-- dummy_stat_reg_switch_i => dummy_stat_reg_switch
-- );
cmp_wb_tx_core : wb_tx_core port map
(
-- Sys connect
wb_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
wb_stall_o => wb_stall(1),
-- TX
tx_clk_i => CLK_40,
tx_data_o => fe_cmd_o,
trig_pulse_o => trig_pulse,
ext_trig_i => int_trig_t
);
cmp_wb_rx_core: wb_rx_core PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(95 downto 64),
wb_cyc_i => wb_cyc(2),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(2),
wb_stall_o => wb_stall(2),
rx_clk_i => CLK_40,
rx_serdes_clk_i => CLK_160,
rx_data_i => fe_data_i,
rx_valid_o => rx_valid,
rx_data_o => rx_data,
trig_tag_i => trig_tag_t,
busy_o => open,
debug_o => debug
);
cmp_wb_rx_bridge : wb_rx_bridge port map (
-- Sys Connect
sys_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(127 downto 96),
wb_cyc_i => wb_cyc(3),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(3),
wb_stall_o => wb_stall(3),
-- Wishbone DMA Master Interface
dma_clk_i => sys_clk,
dma_adr_o => rx_dma_adr,
dma_dat_o => rx_dma_dat_o,
dma_dat_i => rx_dma_dat_i,
dma_cyc_o => rx_dma_cyc,
dma_stb_o => rx_dma_stb,
dma_we_o => rx_dma_we,
dma_ack_i => rx_dma_ack,
dma_stall_i => rx_dma_stall,
-- Rx Interface (sync to sys_clk)
rx_data_i => rx_data,
rx_valid_i => rx_valid,
-- Status in
trig_pulse_i => trig_pulse,
-- Status out
irq_o => open,
busy_o => rx_busy
);
wb_dat_i(159 downto 136) <= (others => '0');
cmp_i2c_master : i2c_master_wb_top
port map (
wb_clk_i => sys_clk,
wb_rst_i => not rst_n,
arst_i => rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
wb_dat_o => wb_dat_i(135 downto 128),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(4),
wb_ack_o => wb_ack(4),
wb_inta_o => open,
scl => open,
sda => open
);
cmp_wb_trigger_logic: wb_trigger_logic PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr(31 downto 0),
wb_dat_i => wb_dat_o(31 downto 0),
wb_dat_o => wb_dat_i(191 downto 160),
wb_cyc_i => wb_cyc(5),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(5),
ext_trig_i => "00" & IO_1 & not hit_or_t,
ext_trig_o => open,
ext_busy_i => '0',
ext_busy_o => IO_0,
eudet_clk_o => eudet_clk_t,
eudet_busy_o => eudet_busy_t,
eudet_trig_i => eudet_trig_t,
eudet_rst_i => eudet_rst_t,
clk_i => CLK_40,
trig_tag => trig_tag_t
);
--wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
-- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));
-- dummy_stat_reg_1 <= X"DEADBABE";
-- dummy_stat_reg_2 <= X"BEEFFACE";
-- dummy_stat_reg_3 <= X"12345678";
-- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
led_red_o <= dummy_ctrl_reg_led(0);
led_green_o <= dummy_ctrl_reg_led(1);
-- TRIG0(31 downto 0) <= (others => '0');
TRIG1(31 downto 0) <= (others => '0');
TRIG2(31 downto 0) <= (others => '0');
-- TRIG0(12 downto 0) <= (others => '0');
--TRIG1(31 downto 0) <= rx_dma_dat_o;
--TRIG1(31 downto 0) <= dma_dat_i;
-- TRIG1(31 downto 0) <= gn4124_core_status;
-- TRIG2(31 downto 0) <= ddr_status;
-- TRIG0(13) <= rx_dma_cyc;
-- TRIG0(14) <= rx_dma_stb;
-- TRIG0(15) <= rx_dma_we;
-- TRIG0(16) <= rx_dma_ack;
-- TRIG0(17) <= rx_dma_stall;
-- TRIG0(18) <= dma_cyc;
-- TRIG0(19) <= dma_stb;
-- TRIG0(20) <= dma_we;
-- TRIG0(21) <= dma_ack;
-- TRIG0(22) <= dma_stall;
-- TRIG0(23) <= irq_out;
-- TRIG0(24) <= rx_busy;
-- TRIG0(31 downto 25) <= (others => '0');
-- TRIG0(0) <= rx_valid;
-- TRIG0(1) <= fe_cmd_o(0);
-- TRIG0(2) <= trig_pulse;
-- TRIG0(3) <= fe_cmd_o(0);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= rx_data;
-- TRIG2 <= debug;
-- TRIG0(0) <= scl;
-- TRIG0(1) <= sda;
-- TRIG0(2) <= wb_stb;
-- TRIG0(3) <= wb_ack(4);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= wb_adr;
-- TRIG2 <= wb_dat_o;
TRIG0(14 downto 0) <= trig_tag_t(14 downto 0);
TRIG0(15) <= int_trig_t;
TRIG0(16) <= eudet_trig_t;
TRIG0(17) <= eudet_clk_t;
TRIG0(18) <= eudet_busy_t;
TRIG0(19) <= trigger_t;
TRIG0(20) <= hit_or_t;
ila_i : ila
port map (
CONTROL => CONTROL,
CLK => CLK_40,
-- CLK => sys_clk,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
ila_icon_i : ila_icon
port map (
CONTROL0 => CONTROL);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- FOR TEST
------------------------------------------------------------------------------
p_led_cnt : process (L_RST_N, sys_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (sys_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(sys_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
rst_n <= (L_RST_N and sys_clk_pll_locked and locked);
cmp_clk_gen : clk_gen
port map (
-- Clock in ports
CLK_40_IN => sys_clk_40,
CLKFB_IN => ioclk_fb,
-- Clock out ports
CLK_640 => CLK_640_buf,
CLK_160 => CLK_160_buf,
CLK_80 => CLK_80_buf,
CLK_40 => CLK_40_buf,
CLK_40_90 => CLK_40_90_buf,
CLKFB_OUT => ioclk_fb,
-- Status and control signals
RESET => not L_RST_N,
LOCKED => locked
);
BUFPLL_640 : BUFPLL
generic map (
DIVIDE => 4, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => CLK_640, -- 1-bit output: Output I/O clock
LOCK => open, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => CLK_160, -- 1-bit input: BUFG clock input
LOCKED => locked, -- 1-bit input: LOCKED input from PLL
PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL
);
cmp_ioclk_160_buf : BUFG
port map (
O => CLK_160,
I => CLK_160_buf);
cmp_ioclk_80_buf : BUFG
port map (
O => CLK_80,
I => CLK_80_buf);
cmp_ioclk_40_buf : BUFG
port map (
O => CLK_40,
I => CLK_40_buf);
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 40.000 MHz IO driver clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
sys_clk <= l_clk;
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n <= '1';
pll20dac_sync_n <= '1';
plldac_din <= '0';
plldac_sclk <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_40_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_40,
I => sys_clk_40_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_ddr3_ctrl: ddr3_ctrl PORT MAP(
clk_i => ddr_clk,
rst_n_i => rst_n,
status_o => ddr_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk,
wb0_sel_i => dma_sel,
wb0_cyc_i => dma_cyc,
wb0_stb_i => dma_stb,
wb0_we_i => dma_we,
wb0_addr_i => dma_adr,
wb0_data_i => dma_dat_o,
wb0_data_o => dma_dat_i,
wb0_ack_o => dma_ack,
wb0_stall_o => dma_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => open,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk,
wb1_sel_i => "1111",
wb1_cyc_i => rx_dma_cyc,
wb1_stb_i => rx_dma_stb,
wb1_we_i => rx_dma_we,
wb1_addr_i => rx_dma_adr,
wb1_data_i => rx_dma_dat_o,
wb1_data_o => rx_dma_dat_i,
wb1_ack_o => rx_dma_ack,
wb1_stall_o => rx_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
end rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/conditional_waveforms/rule_501_test_input.fixed_lower.vhd
|
1
|
400
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_201_test_input.fixed.vhd
|
1
|
418
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/sp6_data_gen.vhd
|
20
|
37259
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_022_test_input.fixed.vhd
|
1
|
91
|
entity FIFO is
end entity;
entity FIFO --Comment
--Comment
--Comment
is
end entity;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/if_statement/rule_025_test_input.fixed_upper.vhd
|
1
|
566
|
architecture RTL of FIFO is
begin
process
begin
IF a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
IF x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
IF a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
IF x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/case_generate_alternative/rule_500_test_input.fixed_upper.vhd
|
1
|
207
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
WHEN choice =>
end generate;
GEN_LABEL : case expression generate
WHEN choice =>
end generate;
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/procedure_call/rule_003_test_input.vhd
|
1
|
837
|
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
connect_ports
(
port_1 => data
,
port_2 => enable,
port_3 => overflow
,
port_4 => underflow
);
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/styles/indent_only/c16/Board_cpu.vhd
|
1
|
3945
|
--
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity board_cpu is
PORT ( CLK40 : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
CLK_OUT : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
ENABLE_N : out STD_LOGIC;
DEACTIVATE_N : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
XM_CE_N : out STD_LOGIC;
XM_OE_N : out STD_LOGIC;
XM_WE_N : inout STD_LOGIC;
XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
);
end board_cpu;
architecture behavioral of board_cpu is
COMPONENT cpu
PORT( CLK_I : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
END COMPONENT;
signal XM_WDAT : std_logic_vector( 7 downto 0);
signal XM_RDAT : std_logic_vector( 7 downto 0);
signal MEM_T : std_logic;
signal XM_WE : std_logic;
signal WE_N : std_logic;
signal DEL_WE_N : std_logic;
signal XM_CE : std_logic;
signal LCLK : std_logic;
begin
cp: cpu
PORT MAP( CLK_I => CLK40,
SWITCH => SWITCH,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
XM_ADR(14 downto 0) => XM_ADR,
XM_ADR(15) => open,
XM_RDAT => XM_RDAT,
XM_WDAT => XM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SEG1 => SEG1,
SEG2 => SEG2,
LED => LED
);
ENABLE_N <= '0';
DEACTIVATE_N <= '1';
CLK_OUT <= LCLK;
MEM_T <= DEL_WE_N; -- active low
WE_N <= not XM_WE;
XM_OE_N <= XM_WE;
XM_CE_N <= not XM_CE;
p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
process(CLK40)
begin
if (rising_edge(CLK40)) then
LCLK <= not LCLK;
end if;
end process;
end behavioral;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/generate/rule_007_test_input.vhd
|
1
|
722
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/vhdlFile/file_declaration/classification_test_input.vhd
|
1
|
310
|
architecture RTL of FIFO is
file F1 : IntegerFile;
file F2 : IntegerFile is "test.dat";
file F3 : IntegerFile open WRITE_MODEW is "test.dat";
file F1, F2, F3 : IntegerFile open WRITE_MODEW is "test.dat";
file F1 : IntegerFile open WRITE_MODEM is (something(else));
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/tool_integration/quality_report/example.vhd
|
1
|
62
|
entity fifo is
end;
architecture rtl of fifo is
begin
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/architecture/rule_013_test_input.fixed_lower.vhd
|
1
|
221
|
architecture rtl of ENT is
begin
end RTL;
architecture rtl of ENT is
begin
end rtl;
architecture rtl of ENT is
begin
end Rtl;
architecture rtl of ENT is
begin
end;
architecture rtl of ENT is
begin
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/signal/rule_002_test_input.fixed_upper.vhd
|
1
|
193
|
architecture RTL of FIFO is
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
-- Violations below
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/concurrent/rule_010_test_input.vhd
|
1
|
447
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/constant/rule_017_test_input.fixed_array_constraint__all_in_one_line.vhd
|
1
|
550
|
architecture rtl of fifo is
constant sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0)
,
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0));
constant sig9 : t_data_struct(data(7 downto 0));
constant sig9 : t_data_struct(
data(7 downto 0)
);
begin
end architecture rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/context/rule_025_test_input.vhd
|
2
|
123
|
--This should pass
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
-- Comment
end context c1;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/entity/rule_200_test_input.fixed.vhd
|
1
|
353
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
package my_pkg is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end package my_pkg;
-- Violation below
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/mcb_soft_calibration_top.vhd
|
19
|
21926
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/kintex7/rx-core/cdr_serdes.vhd
|
1
|
8668
|
-- CDR with SERDES
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity cdr_serdes is
port
(
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
slip : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end cdr_serdes;
architecture rtl of cdr_serdes is
signal AZ : std_logic_vector(4 downto 0) := (others => '0');
signal BZ : std_logic_vector(4 downto 0) := (others => '0');
signal CZ : std_logic_vector(4 downto 0) := (others => '0');
signal DZ : std_logic_vector(4 downto 0) := (others => '0');
signal AAP, AAN : std_logic := '0';
signal BBP, BBN : std_logic := '0';
signal CCP, CCN : std_logic := '0';
signal DDP, DDN : std_logic := '0';
signal use_A : std_logic := '0';
signal use_B : std_logic := '0';
signal use_C : std_logic := '0';
signal use_D : std_logic := '0';
signal use_A1, use_A2 : std_logic := '0';
signal use_B1, use_B2 : std_logic := '0';
signal use_C1, use_C2 : std_logic := '0';
signal use_D1, use_D2 : std_logic := '0';
signal use_A_reg : std_logic := '0';
signal use_B_reg : std_logic := '0';
signal use_C_reg : std_logic := '0';
signal use_D_reg : std_logic := '0';
signal use_A_reg2 : std_logic := '0';
signal use_B_reg2 : std_logic := '0';
signal use_C_reg2 : std_logic := '0';
signal use_D_reg2 : std_logic := '0';
signal sdata_A : std_logic_vector(1 downto 0) := "00";
signal sdata_B : std_logic_vector(1 downto 0) := "00";
signal sdata_C : std_logic_vector(1 downto 0) := "00";
signal sdata_D : std_logic_vector(1 downto 0) := "00";
signal pipe_ce0 : std_logic := '0';
signal pipe_ce1 : std_logic := '0';
signal valid_int : std_logic_vector(1 downto 0) := "00";
signal lockcnt : integer range 0 to 128 := 0;
begin
serdes : ISERDESE2
generic map (
DATA_RATE => "SDR", -- DDR, SDR
DATA_WIDTH => 4, -- Parallel data width (2-8,10,14)
DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
-- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD
NUM_CE => 2, -- Number of clock enables (1,2)
OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
-- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
O => open, -- 1-bit output: Combinatorial output
-- Q1 - Q8: 1-bit (each) output: Registered data outputs
Q1 => AZ(0),
Q2 => BZ(0),
Q3 => CZ(0),
Q4 => DZ(0),
Q5 => open,
Q6 => open,
Q7 => open,
Q8 => open,
-- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => slip, -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
-- CLKDIV when asserted (active High). Subsequently, the data seen on the
-- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one
-- position every time Bitslip is invoked (DDR operation is different from
-- SDR).
-- CE1, CE2: 1-bit (each) input: Data register clock enable inputs
CE1 => '1',
CE2 => '0',
CLKDIVP => '0', -- 1-bit input: TBD
-- Clocks: 1-bit (each) input: ISERDESE2 clock input ports
CLK => clk640, -- 1-bit input: High-speed clock
CLKB => '0', -- 1-bit input: High-speed secondary clock
CLKDIV => clk160, -- 1-bit input: Divided clock
OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion
DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion
-- Input Data: 1-bit (each) input: ISERDESE2 data input ports
D => din, -- 1-bit input: Data input
DDLY => '0', -- 1-bit input: Serial data from IDELAYE2
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
OCLKB => '0', -- 1-bit input: High speed negative edge output clock
RST => reset, -- 1-bit input: Active high asynchronous reset
-- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
process begin
wait until rising_edge(clk160);
if reset = '1' then
AZ(4 downto 1) <= (others => '0');
BZ(4 downto 1) <= (others => '0');
CZ(4 downto 1) <= (others => '0');
DZ(4 downto 1) <= (others => '0');
AAP <= '0'; AAN <= '0';
BBP <= '0'; BBN <= '0';
CCP <= '0'; CCN <= '0';
DDP <= '0'; DDN <= '0';
use_A1 <= '0'; use_A2 <= '0'; use_A <= '0';
use_B1 <= '0'; use_B2 <= '0'; use_B <= '0';
use_C1 <= '0'; use_C2 <= '0'; use_C <= '0';
use_D1 <= '0'; use_D2 <= '0'; use_D <= '0';
use_A_reg <= '0'; use_A_reg2 <= '0';
use_B_reg <= '0'; use_B_reg2 <= '0';
use_C_reg <= '0'; use_C_reg2 <= '0';
use_D_reg <= '0'; use_D_reg2 <= '0';
sdata_A <= "00";
sdata_B <= "00";
sdata_C <= "00";
sdata_D <= "00";
valid_int <= "00";
data_value <= "00";
data_valid <= "00";
data_lock <= '0';
lockcnt <= 0;
pipe_ce0 <= '0';
pipe_ce1 <= '0';
else
-- clock in the data
AZ(4 downto 1) <= AZ(3 downto 0);
BZ(4 downto 1) <= BZ(3 downto 0);
CZ(4 downto 1) <= CZ(3 downto 0);
DZ(4 downto 1) <= DZ(3 downto 0);
-- find positive edges
AAP <= (AZ(2) xor AZ(3)) and not AZ(2);
BBP <= (BZ(2) xor BZ(3)) and not BZ(2);
CCP <= (CZ(2) xor CZ(3)) and not CZ(2);
DDP <= (DZ(2) xor DZ(3)) and not DZ(2);
-- find negative edges
AAN <= (AZ(2) xor AZ(3)) and AZ(2);
BBN <= (BZ(2) xor BZ(3)) and BZ(2);
CCN <= (CZ(2) xor CZ(3)) and CZ(2);
DDN <= (DZ(2) xor DZ(3)) and DZ(2);
-- decision of sampling point
use_A1 <= (BBP and not CCP and not DDP and AAP);
use_A2 <= (BBN and not CCN and not DDN and AAN);
use_B1 <= (CCP and not DDP and AAP and BBP);
use_B2 <= (CCN and not DDN and AAN and BBN);
use_C1 <= (DDP and AAP and BBP and CCP);
use_C2 <= (DDN and AAN and BBN and CCN);
use_D1 <= (AAP and not BBP and not CCP and not DDP);
use_D2 <= (AAN and not BBN and not CCN and not DDN);
use_A <= use_A1 or use_A2;
use_B <= use_B1 or use_B2;
use_C <= use_C1 or use_C2;
use_D <= use_D1 or use_D2;
-- if we found an edge
if (use_A or use_B or use_C or use_D) = '1' then
lockcnt <= 127;
pipe_ce0 <= '1'; -- sync marker
pipe_ce1 <= '1';
else
if lockcnt = 0 then
pipe_ce0 <= '0';
else
lockcnt <= lockcnt - 1;
end if;
pipe_ce1 <= '0';
end if;
-- register
use_A_reg <= use_A;
use_B_reg <= use_B;
use_C_reg <= use_C;
use_D_reg <= use_D;
if pipe_ce1 = '1' then
use_A_reg2 <= use_A_reg;
use_B_reg2 <= use_B_reg;
use_C_reg2 <= use_C_reg;
use_D_reg2 <= use_D_reg;
end if;
-- collect output data
sdata_A(0) <= AZ(4) and use_A_reg2; sdata_A(1) <= AZ(4) and use_D_reg2;
sdata_B(0) <= BZ(4) and use_B_reg2; sdata_B(1) <= '0';
sdata_C(0) <= CZ(4) and use_C_reg2; sdata_C(1) <= '0';
sdata_D(0) <= DZ(4) and use_D_reg2; sdata_D(1) <= DZ(4) and use_A_reg2;
-- ouput data if we have seen an edge
if pipe_ce0 = '1' then
data_value <= sdata_A or sdata_B or sdata_C or sdata_D;
end if;
-- data valid output
if use_D_reg2 = '1' and use_A_reg = '1' then
valid_int <= "00"; -- move from A to D: no valid data
elsif use_A_reg2 = '1' and use_D_reg = '1' then
valid_int <= "11"; -- move from D to A: 2 bits valid
else
valid_int <= "01"; -- only one bit is valid
end if;
if pipe_ce0 = '1' then
data_valid <= valid_int;
else
data_valid <= "00";
end if;
data_lock <= pipe_ce0;
end if;
end process;
end architecture;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/constant/rule_006_test_input.fixed.vhd
|
1
|
172
|
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/vhdlFile/return_statement/classification_test_input.vhd
|
1
|
200
|
architecture RTL of ENTITY_NAME is
begin
process
begin
return std_logic_vector(3 downto 0);
RETURN_LABEL : return std_logic_vector(3 downto 0);
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/package_body/rule_202_test_input.fixed.vhd
|
1
|
242
|
library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
-- Comments could be allowed
end package body;
library ieee;
package body fifo_pkg is
constant a : std_logic;
end package body;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/process/rule_022_test_input.vhd
|
1
|
179
|
architecture RTL of FIFO is
begin
process
begin
a <= b;
end process;
-- Violations below
process
begin
a <= b;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/architecture/rule_005_test_input.fixed.vhd
|
1
|
207
|
architecture RTL of ENT is begin end architecture RTL;
architecture RTL of
ENT is
begin
end;
architecture RTL of
-- Some domment
ENT is
begin
end;
architecture RTL of--some comment
ENT is
begin
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/procedure/rule_501_test_input.fixed_upper.vhd
|
1
|
157
|
architecture RTL of FIFO is
procedure PROC1 is begin end procedure proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
begin
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/variable/rule_002_test_input.fixed_upper.vhd
|
1
|
345
|
architecture RTL of FIFO is
shared VARIABLE shar_var1 : integer;
begin
process
VARIABLE var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared VARIABLE shar_var1 : integer;
begin
process
VARIABLE var1 : integer;
begin
end process;
end architecture RTL;
|
gpl-3.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/sim_models/T80_Reg.vhd
|
15
|
4020
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/subprogram_body/rule_205_test_input.fixed.vhd
|
1
|
246
|
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
-- Violations follow
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
begin
end architecture RTL;
|
gpl-3.0
|
Yarr/Yarr-fw
|
rtl/kintex7/wbexp-core/l2p_arbiter.vhd
|
1
|
9232
|
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-- 20.12.2016 (astaux) Apdapted for AXI-Stream bus
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal axis_tx_tvalid_t : std_logic;
signal axis_tx_tlast_t : std_logic;
signal axis_tx_tdata_t : std_logic_vector(axis_data_width_c - 1 downto 0);
signal axis_tx_tkeep_t : std_logic_vector(axis_data_width_c/8 - 1 downto 0);
constant c_RST_ACTIVE : std_logic := '0';
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
eop_do <= eop;
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_tlast_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_tlast_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_tlast_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
axis_tx_tvalid_t <= wbm_arb_tvalid_i;
axis_tx_tlast_t <= wbm_arb_tlast_i;
axis_tx_tdata_t <= wbm_arb_tdata_i;
axis_tx_tkeep_t <= wbm_arb_tkeep_i;
elsif arb_pdm_gnt = '1' then
axis_tx_tvalid_t <= pdm_arb_tvalid_i;
axis_tx_tlast_t <= pdm_arb_tlast_i;
axis_tx_tdata_t <= pdm_arb_tdata_i;
axis_tx_tkeep_t <= pdm_arb_tkeep_i;
elsif arb_ldm_gnt = '1' then
axis_tx_tvalid_t <= ldm_arb_tvalid_i;
axis_tx_tlast_t <= ldm_arb_tlast_i;
axis_tx_tdata_t <= ldm_arb_tdata_i;
axis_tx_tkeep_t <= ldm_arb_tkeep_i;
else
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
axis_tx_tvalid_o <= '0';
axis_tx_tlast_o <= '0';
axis_tx_tdata_o <= (others => '0');
axis_tx_tkeep_o <= (others => '0');
elsif rising_edge(clk_i) then
axis_tx_tvalid_o <= axis_tx_tvalid_t;
axis_tx_tlast_o <= axis_tx_tlast_t;
axis_tx_tdata_o <= axis_tx_tdata_t;
axis_tx_tkeep_o <= axis_tx_tkeep_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
wbm_arb_tready_o <= axis_tx_tready_i and arb_wbm_gnt;
pdm_arb_tready_o <= axis_tx_tready_i and arb_pdm_gnt;
ldm_arb_tready_o <= axis_tx_tready_i and arb_ldm_gnt;
axis_tx_tuser_o <= "0000";
end rtl;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/if_statement/rule_003_test_input.vhd
|
1
|
274
|
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
end if;
-- Violations below
if(a = '1') then
b <= '0';
end if;
if (a = '1') then
b <= '0';
end if;
end process;
end architecture RTL;
|
gpl-3.0
|
jeremiah-c-leary/vhdl-style-guide
|
vsg/tests/loop_statement/rule_302_test_input.vhd
|
1
|
496
|
architecture RTL of FIFO is
begin
process
begin
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
-- Violations below
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
end process;
end;
|
gpl-3.0
|
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