repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
blutsvente/MIX
|
test/results/case/check/inst_ab_e-e_2.vhd
|
1
|
1569
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e_2.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ab_e-e_2.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
-- No Generated Generics for Entity inst_ab_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
case_ab_p : in _E_CONNTYPE
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_ea_e-e.vhd
|
1
|
1941
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-e.vhd,v 1.1 2004/04/06 10:49:55 wig Exp $
-- $Date: 2004/04/06 10:49:55 $
-- $Log: inst_ea_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:49:55 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ea_e
--
entity inst_ea_e is
-- Generics:
-- No Generated Generics for Entity inst_ea_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end inst_ea_e;
--
-- End of Generated Entity inst_ea_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/configuration/cmdline/ent_t-rtl-conf-c.vhd
|
1
|
2387
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.1 2006/03/16 14:12:14 wig Exp $
-- $Date: 2006/03/16 14:12:14 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/03/16 14:12:14 wig
-- Added testcase for command line -conf add/overload
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: overloading my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_t_rtl_conf / ent_t
--
configuration ent_t_rtl_conf of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_rtl_conf;
end for;
for inst_b : ent_b
use configuration work.ent_b_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_c : ent_c
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_c_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_t_rtl_conf;
--
-- End of Generated Configuration ent_t_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/elab/record.vhd
|
5
|
687
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue131.vhd
|
5
|
352
|
package A_NG is
type STATE_TYPE is (STATE_IDLE, STATE_0, STATE_1);
end package;
package body A_NG is
procedure PROC is
type STATE_TYPE is (STATE_IDLE, STATE_A, STATE_B);
variable state : STATE_TYPE;
begin
state := STATE_A; -- Referenced wrong STATE_TYPE
end procedure;
end package body;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/inst_ed_e-rtl-a.vhd
|
1
|
2163
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: inst_ed_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ed_e
--
architecture rtl of inst_ed_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eda_e
-- No Generated Generics
-- Generated Generics for Entity inst_eda_e
-- End of Generated Generics for Entity inst_eda_e
-- No Generated Port
end component;
-- ---------
component inst_edb_e
-- No Generated Generics
-- Generated Generics for Entity inst_edb_e
-- End of Generated Generics for Entity inst_edb_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eda
inst_eda: inst_eda_e
;
-- End of Generated Instance Port Map for inst_eda
-- Generated Instance Port Map for inst_edb
inst_edb: inst_edb_e
;
-- End of Generated Instance Port Map for inst_edb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/issue82.vhd
|
5
|
739
|
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
var := 4;
end procedure;
begin
nested_proc;
end procedure;
end package body;
entity issue82 is
end entity;
use work.nested_pkg.all;
architecture test of issue82 is
signal s : integer;
begin
process is
variable v : integer := 2;
begin
parent_proc(s, v);
wait for 1 ns;
assert v = 4;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/vhdl/ent_a-e.vhd
|
1
|
1931
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_a-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_a
--
entity ent_a is
-- Generics:
-- No Generated Generics for Entity ent_a
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end ent_a;
--
-- End of Generated Entity ent_a
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/ios_e-rtl-a.vhd
|
1
|
20767
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioblock0_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_2 : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_go => nand_out_2, -- Links ...
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_gi => nand_out_2, -- Links ...
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/nreset2/inst_ebb_e-rtl-a.vhd
|
1
|
1497
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ebb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ebb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:48 wig Exp $
-- $Date: 2004/04/06 10:50:48 $
-- $Log: inst_ebb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:48 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ebb_e
--
architecture rtl of inst_ebb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_k3_k4_e-c.vhd
|
1
|
1305
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k4_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_k3_k4_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k3_k4_rtl_conf / inst_k3_k4_e
--
configuration inst_k3_k4_rtl_conf of inst_k3_k4_e is
for rtl
-- Generated Configuration
end for;
end inst_k3_k4_rtl_conf;
--
-- End of Generated Configuration inst_k3_k4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/elab/elab3.vhd
|
5
|
1328
|
package p is
function log2(x : in integer) return integer;
end package;
package body p is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
entity sub is
generic ( W : integer );
end entity;
use work.p.all;
architecture test of sub is
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
constant C : bit_vector(log2(B) to 1) := (others => '0');
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
s : entity work.sub
generic map ( 10 );
end architecture;
-------------------------------------------------------------------------------
use work.p.all;
entity top2 is
end entity;
architecture test of top2 is
constant W : integer := 10;
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
begin
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_ok_5_e-rtl-a.vhd
|
1
|
1452
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_5_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_5_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_ok_5_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ok_5_e
--
architecture rtl of inst_ok_5_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
#
# Generated Signal List
#
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/names/ios_e-e.vhd
|
1
|
4860
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/nreset2/inst_b_e-rtl-a.vhd
|
1
|
1487
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:37 wig Exp $
-- $Date: 2004/04/06 10:50:37 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:37 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_3_e-rtl-a.vhd
|
1
|
1455
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_3_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_3_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_3_e
--
architecture rtl of inst_3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/ent_a-rtl-a.vhd
|
1
|
7613
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic; -- Use internally test1
port_aa_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 : out std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_aa_6 : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : out std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0) -- Create internal signal name
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic; -- Use internally test1
port_ab_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0) -- Create internal signal name
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0); -- Use internally test2, no port generated
port_ae_5 : in std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_ae_6 : in std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_i_ae : in std_ulogic_vector(6 downto 0); -- Input Bus
sig_o_ae : out std_ulogic_vector(7 downto 0) -- Output Bus
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/inst/inst_ab_e-e.vhd
|
1
|
1510
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_ab_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/hier/auto/inst_b_e-e.vhd
|
1
|
1571
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Tue Apr 4 05:28:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../hier.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2006/04/11 13:36:52 wig Exp $
-- $Date: 2006/04/11 13:36:52 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2006/04/11 13:36:52 wig
-- Updated testcases: left constant/* and verilog/uamn open.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
port_a : in std_logic; -- auto_a from a to b
port_b : in std_ulogic_vector(7 downto 0); -- auto_b from c to a and b
port_e : in std_ulogic_vector(23 downto 0) -- auto_e is O bus with internal in to other module
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/func15.vhd
|
5
|
441
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/ent_aa-rtl-conf-c.vhd
|
1
|
1274
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_aa
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:21 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-rtl-conf-c.vhd,v 1.1 2007/03/05 10:01:23 wig Exp $
-- $Date: 2007/03/05 10:01:23 $
-- $Log: ent_aa-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 10:01:23 wig
-- Create all lowercase filenames since 2007-03-03
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_aa_RTL_CONF / ent_aa
--
configuration ent_aa_RTL_CONF of ent_aa is
for rtl
-- Generated Configuration
end for;
end ent_aa_RTL_CONF;
--
-- End of Generated Configuration ent_aa_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/nreset2/inst_ea_e-rtl-conf-c.vhd
|
1
|
1728
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:42 wig Exp $
-- $Date: 2004/04/06 10:50:42 $
-- $Log: inst_ea_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:42 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ea_e_rtl_conf / inst_ea_e
--
configuration inst_ea_e_rtl_conf of inst_ea_e is
for rtl
-- Generated Configuration
for inst_eaa : inst_eaa_e
use configuration work.inst_eaa_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_eab : inst_eab_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eab_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_eac : inst_eac_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eac_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ea_e_rtl_conf;
--
-- End of Generated Configuration inst_ea_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/access.vhd
|
3
|
2388
|
package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
type string_ptr is access string;
end package;
package body p is
procedure test is
variable v : int_ptr;
variable i : integer;
variable r : rec_ptr;
variable a : int_vec_ptr;
variable s : string_ptr;
begin
v := null; -- OK
i := null; -- Error
deallocate(v); -- OK
v := new integer; -- OK
v := new integer'(5); -- OK
v := new 5; -- Error
v := new i; -- Error
v.all := 5; -- OK
v := 5; -- Error
i := v.all + 5; -- OK
r := new rec; -- OK
r.all.value := 1; -- OK
r.value := 1; -- OK
r.link := r; -- OK
r.link := r.all; -- Error
i := r.value; -- OK
r := r.all.link; -- OK
a := new int_vec(1 to 3); -- OK
a.all(5) := 2; -- OK
a(5) := 2; -- OK
a(1 to 2) := (1, 2); -- OK
s := new string'(""); -- OK
s := new integer'(1); -- Error
s := new s(1 to 3); -- Error
end procedure;
procedure test2(x : inout rec_ptr) is
begin
x.value := x.value + 1;
end procedure;
procedure test3 is
type a;
type a is access integer; -- OK
variable v : a; -- OK
begin
end procedure;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array; -- Error
x := new int_ptr_array(1 to 3); -- OK
x.all := (null, null, null); -- OK
end procedure;
end package body;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/vhdl/ent_aa-e.vhd
|
1
|
1780
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.4 2005/10/13 09:09:43 wig Exp $
-- $Date: 2005/10/13 09:09:43 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.4 2005/10/13 09:09:43 wig
-- Added intermediate CONN sheet split
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_14 : out std_ulogic_vector(6 downto 0)
-- End of Generated Port for Entity ent_aa
);
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/parse/bitstring.vhd
|
3
|
307
|
package bitstring is
constant x : t := X"1234";
constant y : t := O"1234";
constant z : t := X"ab";
constant b : t := B"101";
constant c : t := x"f";
constant d : t := X"a_b";
end package;
package bitstring_error is
constant e1 : t := O"9"; -- Error
end package;
|
gpl-3.0
|
blutsvente/MIX
|
Resources/Examples/pin_master_vhdl_di_tnr/vhdl/di_tnry-e.vhd
|
1
|
2420
|
-- -------------------------------------------------------------
--
-- Entity Declaration for di_tnry
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Version: Revision: 1.3 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity di_tnry
--
entity di_tnry is
-- Generics:
-- No Generated Generics for Entity di_tnry
-- Generated Port Declaration:
port(
-- Generated Port for Entity di_tnry
af_c0_i : in std_ulogic ;
al_c0_i : in std_ulogic;
al_c1_i : in std_ulogic;
ap_c0_i : in std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
clkin : in std_ulogic;
hsync_c_i : in std_ulogic;
nr_dis_c_i : in std_ulogic;
nron_iic_i : in std_ulogic;
tnrabs_iic_i : in std_ulogic;
tnrcly_iic_i : in std_ulogic_vector(3 downto 0);
tnrkvaly_p_o : out std_ulogic_vector(3 downto 0);
tnrmd4y_iic_i : in std_ulogic;
tnrnr4y_iic_i : in std_ulogic;
tnrs0y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs1y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs2y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs3y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs4y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs5y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs6y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs7y_iic_i : in std_ulogic_vector(3 downto 0);
tnrssy_iic_i : in std_ulogic_vector(3 downto 0);
y0_p1_i : in std_ulogic_vector(7 downto 0);
y0_p1_o : out std_ulogic_vector(7 downto 0);
y1_p1_i : in std_ulogic_vector(7 downto 0);
y1_p1_o : out std_ulogic_vector(7 downto 0);
y_p0_i : in std_ulogic_vector(7 downto 0);
y_p0_o : out std_ulogic_vector(7 downto 0);
yblack_p_i : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity di_tnry
);
end di_tnry;
--
-- End of Generated Entity di_tnry
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue173.vhd
|
5
|
594
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/attr7.vhd
|
5
|
519
|
entity attr7 is
end entity;
architecture test of attr7 is
signal vec : bit_vector(1 downto 0);
begin
process (vec(0)) is
begin
report "wakeup " & bit'image(vec(0));
if now > 0 ns then
assert vec(0)'event;
assert now = 3 ns;
end if;
end process;
process is
begin
wait for 1 ns;
vec <= "10";
wait for 1 ns;
vec <= "00";
wait for 1 ns;
vec <= "01";
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/inst_b_e-e.vhd
|
1
|
1269
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2006/04/10 15:42:06 wig Exp $
-- $Date: 2006/04/10 15:42:06 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:06 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_b_e
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/nreset2/vor-e.vhd
|
1
|
1315
|
-- -------------------------------------------------------------
--
-- Entity Declaration for vor
--
-- Generated
-- by: wig
-- on: Wed Nov 30 08:56:01 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-e.vhd,v 1.2 2005/11/30 14:04:02 wig Exp $
-- $Date: 2005/11/30 14:04:02 $
-- $Log: vor-e.vhd,v $
-- Revision 1.2 2005/11/30 14:04:02 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity vor
--
entity vor is
-- Generics:
-- No Generated Generics for Entity vor
-- Generated Port Declaration:
port(
-- Generated Port for Entity vor
reset_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity vor
);
end vor;
--
-- End of Generated Entity vor
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/parse/issue222.vhd
|
5
|
1108
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bugver/ramd/adc-struct-a.vhd
|
1
|
1740
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of adc
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: adc-struct-a.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: adc-struct-a.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of adc
--
architecture struct of adc is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component adc_ctrl --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_adc_ctrl
i_adc_ctrl: adc_ctrl
;
-- End of Generated Instance Port Map for i_adc_ctrl
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/inst_eaa_e-rtl-conf-c.vhd
|
1
|
1307
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eaa_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:06 wig Exp $
-- $Date: 2006/04/10 15:42:06 $
-- $Log: inst_eaa_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:06 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_eaa_e_rtl_conf / inst_eaa_e
--
configuration inst_eaa_e_rtl_conf of inst_eaa_e is
for rtl
-- Generated Configuration
end for;
end inst_eaa_e_rtl_conf;
--
-- End of Generated Configuration inst_eaa_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/typecast/intsig/inst_ab-e.vhd
|
1
|
1795
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:56:39 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: inst_ab-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab
--
entity inst_ab is
-- Generics:
-- No Generated Generics for Entity inst_ab
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab
port_b_1 : in std_logic;
port_b_10 : in std_ulogic;
port_b_11 : in std_ulogic_vector(7 downto 0);
port_b_12 : in std_logic_vector(15 downto 0);
port_b_2 : in std_ulogic;
port_b_3 : in std_logic_vector(7 downto 0);
port_b_4 : in std_ulogic_vector(15 downto 0);
port_b_5 : in std_logic;
port_b_6 : in std_ulogic;
port_b_7 : in std_ulogic_vector(7 downto 0);
port_b_8 : in std_logic_vector(15 downto 0);
port_b_9 : in std_logic
-- End of Generated Port for Entity inst_ab
);
end inst_ab;
--
-- End of Generated Entity inst_ab
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/wait12.vhd
|
5
|
659
|
entity wait12 is
end entity;
architecture test of wait12 is
signal x, y : integer;
begin
a: process is
begin
wait for 1 ns;
x <= 1;
wait for 0 ns;
x <= 2;
wait for 0 ns;
x <= 3;
wait for 1 ns;
x <= 4;
wait on y;
report "wake up other process";
assert y = 2;
wait;
end process;
b: postponed process is
begin
wait on x;
report "wake up postponed process 1";
assert x = 3;
wait on x;
report "wake up postponed process 2";
y <= 2 after 1 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/names/ddrv4-e.vhd
|
1
|
2334
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-e.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ddrv4-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ddrv4
--
entity ddrv4 is
-- Generics:
-- No Generated Generics for Entity ddrv4
-- Generated Port Declaration:
port(
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end ddrv4;
--
-- End of Generated Entity ddrv4
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/given/a_clk-rtl-a.vhd
|
1
|
32150
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic;
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
iosel_bus_port : out std_ulogic_vector(7 downto 0);
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
port (
-- Generated Port for Entity testctrl_e
nand_dir : out std_ulogic;
nand_en : out std_ulogic
-- End of Generated Port for Entity testctrl_e
);
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
-- __I_OUT_OPEN signal iosel_6 : std_ulogic;
-- __I_OUT_OPEN signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
-- __I_OUT_OPEN signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal nand_dir : std_ulogic;
-- __I_OUT_OPEN signal nand_en : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(7) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
port map (
nand_dir => nand_dir, -- Direction (X17)
nand_en => open -- Enable (X17) -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_7_e-c.vhd
|
1
|
1332
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_7_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_7_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_7_rtl_conf / inst_shadow_7_e
--
configuration inst_shadow_7_rtl_conf of inst_shadow_7_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_7_rtl_conf;
--
-- End of Generated Configuration inst_shadow_7_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/ieee2.vhd
|
4
|
1075
|
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
clk <= clk_std;
process (clk_std) is
begin
if rising_edge(clk_std) then
cnt <= cnt + 1;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ieee2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of ieee2 is
signal cnt : integer := 0;
signal clk : std_logic;
begin
sub_i: entity work.sub port map ( clk, cnt );
process (clk) is
begin
if rising_edge(clk) then
report "clock!";
end if;
end process;
process is
begin
wait for 10 ns;
report integer'image(cnt);
assert cnt = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/inst/inst_t_e-e.vhd
|
1
|
1480
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
signal_bb_ab : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/ent_t-rtl-conf-c.vhd
|
1
|
1427
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:27 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.1 2007/03/05 13:35:50 wig Exp $
-- $Date: 2007/03/05 13:35:50 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 13:35:50 wig
-- Reworked testcase sigport (changed case of generated files).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_RTL_CONF / ent_t
--
configuration ent_t_RTL_CONF of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_RTL_CONF;
end for;
for inst_b : ent_b
use configuration work.ent_b_RTL_CONF;
end for;
end for;
end ent_t_RTL_CONF;
--
-- End of Generated Configuration ent_t_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/lower/while1.vhd
|
4
|
245
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
n := n - 1;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/issue153.vhd
|
4
|
2179
|
entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <='1' when G_ROUND_ENABLE else '0';
o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value;
end architecture rtl;
entity issue153 is
end entity issue153;
architecture beh of issue153 is
constant G_ROUND_ENABLE:boolean:=true;
constant C_ADDROUND : bit_vector(7 downto 0):="00001111";
constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0');
signal s_ena:bit_vector(7 downto 0);
type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0);
--signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2
signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error
begin
GEN_MACS_V : for v in 0 to 7 generate
signal C :bit_vector(7 downto 0);
signal D :bit_vector(7 downto 0);
begin
--should fail here, but doesn't
--GHDL failed here with "bound check failure"
-- ghdl drives correct values on each instances, nvc doesn't
C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1
-- below is workaround, but I am lazy enough to not use it :))))
--c_gen: if v=0 and G_ROUND_ENABLE generate
-- C <= C_ADDROUND;
--end generate c_gen;
--nc_gen: if v>0 generate
-- C <= s_value(v-1);
--end generate nc_gen;
test_i : entity work.test_inst
generic map(
G_ROUND => 1
)
port map(
i_value => C,
o_ena => s_ena(v),
o_value => s_value(v)
);
end generate GEN_MACS_V;
process
begin
wait for 1 ns;
assert s_value(0) = not C_ADDROUND;
assert s_value(1) = C_ADDROUND;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_eb_e-rtl-a.vhd
|
1
|
4367
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:24 wig Exp $
-- $Date: 2004/04/06 10:50:24 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:24 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
req_select_o : out std_ulogic_vector(5 downto 0);
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
port (
-- Generated Port for Entity inst_ebc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
p_mix_v_select_5_0_go <= v_select; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
mbist_sum_fail_o => tmi_sbist_fail(12),
req_select_o => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/driver2.vhd
|
5
|
429
|
entity driver2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver2 is
signal x : std_logic;
begin
x <= 'H';
p1: process is
begin
x <= 'Z';
wait for 1 ns;
assert x = 'H';
x <= '0';
wait for 1 ns;
assert x = '0';
x <= 'Z';
wait for 1 ns;
assert x = 'H';
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_b_e-e.vhd
|
1
|
1413
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
port_b_1 : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/ioblock3_e-rtl-a.vhd
|
1
|
11515
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock3_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:23 wig Exp $
-- $Date: 2006/07/05 10:01:23 $
-- $Log: ioblock3_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:23 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock3_e
--
architecture rtl of ioblock3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_g_i
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_di : in std_ulogic; -- data in from pad
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
component ioc_r_io3
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io3
do : in std_ulogic_vector(3 downto 0);
en : in std_ulogic_vector(3 downto 0);
nand_dir : in std_ulogic; -- Direction
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io3
);
end component;
-- ---------
component ioc_r_iou
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_iou
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nand_dir : in std_ulogic; -- Direction
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
p_pu : out std_ulogic; -- pull-up control
pu : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ioc_r_iou
);
end component;
-- ---------
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal ioseldi_0 : std_ulogic;
-- __I_NODRV_I signal ioseldi_1 : std_ulogic;
signal ioseldi_2 : std_ulogic;
signal ioseldi_3 : std_ulogic;
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_g_i_33
ioc_g_i_33: ioc_g_i
port map (
di => data_i33, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_33, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_33
-- Generated Instance Port Map for ioc_g_i_34
ioc_g_i_34: ioc_g_i
port map (
di => data_i34, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_34, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_34
-- Generated Instance Port Map for ioc_g_o_35
ioc_g_o_35: ioc_g_o
port map (
do => data_o35, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_35, -- data out to pad
p_en => pad_en_35, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_35
-- Generated Instance Port Map for ioc_g_o_36
ioc_g_o_36: ioc_g_o
port map (
do => data_o36, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_36, -- data out to pad
p_en => pad_en_36, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_36
-- Generated Instance Port Map for ioc_r_io3_39
ioc_r_io3_39: ioc_r_io3
port map (
do(0) => display_ls(0),
do(1) => display_ls(2),
do(2) => display_ls(4),
do(3) => display_ls(6),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_39, -- data in from pad
p_do => pad_do_39, -- data out to pad
p_en => pad_en_39, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
-- __I_NODRV_I sel(1) => __nodrv__/ioseldi_1, -- __I_BIT_TO_BUSPORT
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_39
-- Generated Instance Port Map for ioc_r_io3_40
ioc_r_io3_40: ioc_r_io3
port map (
do(0) => display_ls(1),
do(1) => display_ls(3),
do(2) => display_ls(5),
do(3) => display_ls(7),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_40, -- data in from pad
p_do => pad_do_40, -- data out to pad
p_en => pad_en_40, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
sel(1) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_40
-- Generated Instance Port Map for ioc_r_iou_31
ioc_r_iou_31: ioc_r_iou
port map (
di => d9_di(0), -- d9io
do => d9_do(0), -- d9io
en => d9_en(0), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_31, -- data in from pad
p_do => pad_do_31, -- data out to pad
p_en => pad_en_31, -- pad output enable
p_pu => pad_pu_31, -- pull-up control
pu => d9_pu(0) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_31
-- Generated Instance Port Map for ioc_r_iou_32
ioc_r_iou_32: ioc_r_iou
port map (
di => d9_di(1), -- d9io
do => d9_do(1), -- d9io
en => d9_en(1), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_32, -- data in from pad
p_do => pad_do_32, -- data out to pad
p_en => pad_en_32, -- pad output enable
p_pu => pad_pu_32, -- pull-up control
pu => d9_pu(1) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_32
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/typecast/inst_aa-e.vhd
|
1
|
1811
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:54:13 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa-e.vhd,v 1.3 2005/04/14 06:53:01 wig Exp $
-- $Date: 2005/04/14 06:53:01 $
-- $Log: inst_aa-e.vhd,v $
-- Revision 1.3 2005/04/14 06:53:01 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa
--
entity inst_aa is
-- Generics:
-- No Generated Generics for Entity inst_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end inst_aa;
--
-- End of Generated Entity inst_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/ent_ad-e.vhd
|
1
|
1410
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ad
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-e.vhd,v 1.3 2005/11/30 14:04:00 wig Exp $
-- $Date: 2005/11/30 14:04:00 $
-- $Log: ent_ad-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:00 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ad
--
entity ent_ad is
-- Generics:
-- No Generated Generics for Entity ent_ad
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end ent_ad;
--
-- End of Generated Entity ent_ad
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/lower/issue134.vhd
|
5
|
231
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/inst_ea_e-e.vhd
|
1
|
1281
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-e.vhd,v 1.3 2005/11/30 14:04:03 wig Exp $
-- $Date: 2005/11/30 14:04:03 $
-- $Log: inst_ea_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:03 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ea_e
--
entity inst_ea_e is
-- Generics:
-- No Generated Generics for Entity inst_ea_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ea_e
end inst_ea_e;
--
-- End of Generated Entity inst_ea_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/vhdl/ent_t-rtl-a.vhd
|
1
|
5093
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/simp/proc.vhd
|
4
|
446
|
entity proc is
end entity;
architecture test of proc is
signal x, y : integer;
procedure proc(n : integer);
begin
-- Test rewrite of process sensitivity list
process (x, y) is
begin
report "awake";
end process;
-- Test rewrite of concurrent assignments
x <= y + 4;
x <= y + 4 when y < 2 else x + 1 when x < 2 else 0;
-- Concurrent procedure call to process
proc(n => 4);
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/perf/dyn_agg.vhd
|
5
|
586
|
entity dyn_agg is
end entity;
architecture test of dyn_agg is
constant WIDTH : integer := 20;
constant ITERS : integer := 14;
signal s : bit_vector(WIDTH - 1 downto 0);
function func(constant W : integer) return bit_vector is
variable r : bit_vector(W - 1 downto 0);
begin
return r;
end function;
begin
process is
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s <= func(WIDTH);
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/wait8.vhd
|
5
|
445
|
entity wait8 is
end entity;
architecture test of wait8 is
procedure foo(signal x : in bit_vector) is
begin
wait on x;
end procedure;
signal s : bit_vector(1 to 2) := "00";
begin
a: process is
begin
foo(s);
assert now = 10 ns;
assert s = "11";
wait;
end process;
b: process is
begin
s <= "11" after 10 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_ok_9_e-c.vhd
|
1
|
1361
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_9_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_9_e-c.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_9_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_9_rtl_conf / inst_shadow_ok_9_e
--
configuration inst_shadow_ok_9_rtl_conf of inst_shadow_ok_9_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_9_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_9_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue176.vhd
|
4
|
1057
|
package pack is
procedure proc;
end package;
package body pack is
procedure proc is
begin
wait for 1 ns;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity ent is
end entity;
use work.pack.all;
architecture a of ent is
begin
main : process
procedure proc_wait is
begin
wait for 1 ns;
end procedure;
procedure proc_wait_indirect is
begin
proc_wait;
end procedure;
impure function fun return integer is
begin
proc_wait_indirect; -- Error
proc_wait; -- Error
return 42;
end function;
variable var : integer;
begin
var := fun;
assert var = 42;
report integer'image(var);
wait until false;
end process;
process is
function fun2 return boolean is
begin
proc; -- Error
return true;
end function;
begin
assert fun2;
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/alias5.vhd
|
5
|
1222
|
entity alias5 is
end entity;
architecture test of alias5 is
subtype bit_vector4 is bit_vector(3 downto 0);
type footype is ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0x, trx1, tr1x, trx0, trxz, trzx);
type bartype01 is array (footype range tr01 to tr10)
of time;
type yahtype01 is array (natural range <>) of bartype01;
procedure bufpath (
constant tpd : in yahtype01
) is
begin
report "tpd'left=" & integer'image(tpd'left);
report "tpd'right=" & integer'image(tpd'right);
end;
procedure vitalmux4 (
variable data : in bit_vector4;
constant tpd_data_q : in yahtype01
) is
alias atpd_data_q : yahtype01(data'range) is tpd_data_q;
begin
bufpath ( atpd_data_q );
assert atpd_data_q(data'left)(tr01) = 1 ns;
assert atpd_data_q(3 downto 3)(3)(tr01) = 1 ns;
end;
begin
process is
variable data : bit_vector4;
variable yah : yahtype01(5 downto 2);
begin
data := X"1";
yah := (others => (others => 1 ns ) );
vitalmux4(data, yah);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/use/ent_ac-e.vhd
|
1
|
1386
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ac
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ac-e.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_ac-e.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ac
--
entity ent_ac is
-- Generics:
-- No Generated Generics for Entity ent_ac
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end ent_ac;
--
-- End of Generated Entity ent_ac
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/inst_ab_e-rtl-a.vhd
|
1
|
1457
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_ab_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ab_e
--
architecture rtl of inst_ab_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/issue169.vhd
|
5
|
332
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bugver/20051018d/ent_aa-e.vhd
|
1
|
1623
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.2 2005/11/02 14:29:09 wig Exp $
-- $Date: 2005/11/02 14:29:09 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.2 2005/11/02 14:29:09 wig
-- Remove extra ; from port map if port has comment
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.66 2005/10/24 15:43:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aa
ramd_oe_i : in std_ulogic_vector(31 downto 0); -- bad conection bits detected
ramd_oe_i_r : in std_ulogic_vector(31 downto 0); -- reverse order
ramdm_oe_i : in std_ulogic_vector(3 downto 0); -- bad conection bits detected
ramdm_oe_i_r : in std_ulogic_vector(3 downto 0) -- reverse order
-- End of Generated Port for Entity ent_aa
);
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/conf/ent_t.vhd
|
1
|
8099
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_t.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_t.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
-- Generated Generics for Entity ent_b
-- End of Generated Generics for Entity ent_b
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic;
port_b_5_2 : in std_ulogic;
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_t.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_rtl_config / ent_t
--
configuration ent_t_rtl_config of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_rtl_config;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_b : ent_b
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_b_rtl_config;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_t_rtl_config;
--
-- End of Generated Configuration ent_t_rtl_config
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/splice/inst_t_e-e.vhd
|
1
|
1374
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Feb 15 09:42:21 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE -nodelta ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2006/03/14 08:13:24 wig Exp $
-- $Date: 2006/03/14 08:13:24 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2006/03/14 08:13:24 wig
-- Adding testcase macro/splice: started development for macros iterating over signal bits
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.76 2006/01/19 08:49:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_3_e-rtl-a.vhd
|
1
|
1490
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_3_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_3_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_3_e
--
architecture rtl of inst_shadow_3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/lower/issue215.vhd
|
4
|
726
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/inst_ec_e-rtl-a.vhd
|
1
|
4067
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.4 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.4 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eca_e
-- No Generated Generics
-- Generated Generics for Entity inst_eca_e
-- End of Generated Generics for Entity inst_eca_e
port (
-- Generated Port for Entity inst_eca_e
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CPUinterface
v_select : in std_ulogic_vector(5 downto 0) -- RequestBusinterface:RequestBus#6(VPU)
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecb_e
-- End of Generated Generics for Entity inst_ecb_e
port (
-- Generated Port for Entity inst_ecb_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecc_e
-- End of Generated Generics for Entity inst_ecc_e
port (
-- Generated Port for Entity inst_ecc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUInterface
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select => v_select -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bugver/20060404c/cgu-e.vhd
|
1
|
1362
|
-- -------------------------------------------------------------
--
-- Entity Declaration for cgu
--
-- Generated
-- by: wig
-- on: Tue Apr 18 07:50:26 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: cgu-e.vhd,v 1.1 2006/04/19 07:33:12 wig Exp $
-- $Date: 2006/04/19 07:33:12 $
-- $Log: cgu-e.vhd,v $
-- Revision 1.1 2006/04/19 07:33:12 wig
-- Updated/added testcase for 20060404c issue. Needs more work!
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity cgu
--
entity cgu is
-- Generics:
-- No Generated Generics for Entity cgu
-- Generated Port Declaration:
port(
-- Generated Port for Entity cgu
selclk_out2_par_i : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity cgu
);
end cgu;
--
-- End of Generated Entity cgu
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_6_e-e.vhd
|
1
|
1278
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_6_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_6_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_6_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_6_e
--
entity inst_6_e is
-- Generics:
-- No Generated Generics for Entity inst_6_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_6_e
end inst_6_e;
--
-- End of Generated Entity inst_6_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio2/pads_eastsouth-struct-a.vhd
|
1
|
6002
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_eastsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_eastsouth-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_eastsouth-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_eastsouth
--
architecture struct of pads_eastsouth is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_96 : std_ulogic;
signal mix_logic1_97 : std_ulogic;
signal mix_logic0_32 : std_ulogic;
signal mix_logic0_35 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal ramclkin_o : std_ulogic;
signal ramd_12 : std_ulogic;
signal ramd_byp_i : std_ulogic;
signal ramd_enq_i : std_ulogic;
signal ramd_i : std_ulogic_vector(12) -- __W_SINGLE_BIT_BUS;
-- __I_OUT_OPEN signal ramd_o : std_ulogic_vector(12) -- __W_SINGLE_BIT_BUS;
signal ramd_oe_i : std_ulogic;
signal ramd_pd_i : std_ulogic;
signal ramd_tenq_i : std_ulogic;
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_ramd_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_ramd_12 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_96 <= '1';
mix_logic1_97 <= '1';
mix_logic0_32 <= '0';
mix_logic0_35 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_ramd_12
ioc_ramd_12: ioc
port map (
bypass(0) => ramd_byp_i, -- __I_BIT_TO_BUSPORT
clk(0) => ramclkin_o, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => open, -- __I_OUT_OPEN
do(0 downto 0) => ramd_i, -- __W_PORT
do(1) => mix_logic1_96, -- __I_BIT_TO_BUSPORT
enq => ramd_enq_i,
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
oe(0) => ramd_oe_i, -- __I_BIT_TO_BUSPORT
oe(1) => mix_logic0_32, -- __I_BIT_TO_BUSPORT
pad => ramd_12,
pd(0) => ramd_pd_i, -- __I_BIT_TO_BUSPORT
pd(1) => mix_logic1_97, -- __I_BIT_TO_BUSPORT
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_35,
scan_o => open,
serial_input_i => s_in_ramd_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
tenq => ramd_tenq_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_ramd_12
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_ok_3_e-c.vhd
|
1
|
1296
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ok_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_3_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_ok_3_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ok_3_rtl_conf / inst_ok_3_e
--
configuration inst_ok_3_rtl_conf of inst_ok_3_e is
for rtl
-- Generated Configuration
end for;
end inst_ok_3_rtl_conf;
--
-- End of Generated Configuration inst_ok_3_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/inst_t_e-rtl-a.vhd
|
1
|
2847
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- b instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- b instance
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/afifo.vhd
|
20
|
9200
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
|
gpl-3.0
|
kuba-moo/VHDL-precise-packet-generator
|
counter64.vhd
|
1
|
1477
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter
entity counter is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Cnt : out std_logic_vector (N_BITS - 1 downto 0));
end counter;
-- Operation:
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again
architecture Behavioral of counter is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
count <= count + 1;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/common/dummy_ctrl_regs.vhd
|
2
|
7652
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from dummy_ctrl_regs_wb_slave.wb
-- Created : Fri May 13 11:28:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_ctrl_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Ports for PASS_THROUGH field: 'IRQ' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_1_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_reg_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for LED control' in reg: 'DUMMY_LED'
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_wr_o <= '0';
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dummy_reg_1_wr_o <= '0';
ack_in_progress <= '0';
else
dummy_reg_1_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
dummy_reg_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
dummy_reg_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
dummy_reg_led_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_led_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- IRQ
-- pass-through field: IRQ in register: DUMMY_1
dummy_reg_1_o <= wrdata_reg(31 downto 0);
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
dummy_reg_3_o <= dummy_reg_3_int;
-- Dummy register for LED control
dummy_reg_led_o <= dummy_reg_led_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
gpl-3.0
|
kuba-moo/VHDL-precise-packet-generator
|
mdio_ctrl.vhd
|
1
|
5913
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Theory of operation:
-- 1. set input values
-- 2. wait for busy to go '0'
-- 3. set kick to '1'
-- 4. wait for busy to go '0'; for reads data_o is valid on the same clock; for writes MDIO is done
entity mdio_ctrl is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- counter bits
cnt_5 : in STD_LOGIC;
cnt_23 : in STD_LOGIC;
-- external I/O
mdc : out STD_LOGIC;
mdio_i : in STD_LOGIC;
mdio_o : out STD_LOGIC;
mdio_t : out STD_LOGIC;
-- client interface
op : in STD_LOGIC; -- '0' - read; '1' - write
addr : in STD_LOGIC_VECTOR( 4 downto 0); -- address of register
data_i : in STD_LOGIC_VECTOR(15 downto 0); -- register value for write
data_o : out STD_LOGIC_VECTOR(15 downto 0); -- register value for read
busy : out STD_LOGIC; -- core is busy
kick : in STD_LOGIC -- start processing the operation
);
end mdio_ctrl;
architecture Behavioral of mdio_ctrl is
-- MDC is driven by cnt5 (period: 640ns, edge: 320ns | min: 400/180ns)
-- state changes happen on MDC falling edge
-- Operation:
-- 1. after each reset wait for at least 50ms (we wait at least 84ms - cnt_23)
-- 2. wait for command -> kick to go high
type state_t is (wait_rst_done_b1, -- wait for cnt_23 to go high
wait_rst_done_b0, -- wait for cnt_23 to go low
idle, -- do nothing, wait for command
preable, -- preable -> 32x '1'
start_of_frame, -- sof -> 0 1
op_code, -- opcode -> 1 0 read; 0 1 write
phy_addr, -- phy_addr -> 5x 0
reg_addr, -- reg_addr -> 5x b
turn_around,
read_in,
write_out);
signal state, next_state : state_t := wait_rst_done_b1;
signal cnt, next_cnt : integer range 0 to 31;
signal value, next_value : STD_LOGIC_VECTOR(0 to 15);
-- 'mdio_i' value latched on rising edge of MDC
-- (state transitions on falling edge which is too far - PHY holds value for 300ns only)
signal bit_in : STD_LOGIC;
-- detection of falling edge of MDC
signal MDIO_clk, prev_MDIO_clk : STD_LOGIC := '0';
-- latched inputs
signal m_op : STD_LOGIC;
signal m_addr : STD_LOGIC_VECTOR(0 to 4); -- swap direction here to make it easier
signal m_data : STD_LOGIC_VECTOR(0 to 15); -- to iterate over the vector with cnt
signal m_kick : STD_LOGIC;
begin
busy <= '0' when state = idle and m_kick = '0' else '1';
data_o <= value;
-- Async state machine
NEXT_fsm: process (next_state, state, next_cnt, cnt, mdio_i, cnt_23, value, bit_in,
m_kick, m_op, m_addr, m_data)
begin
mdio_o <= '0';
mdio_t <= '0';
next_state <= state;
next_cnt <= cnt + 1;
next_value <= value;
case state is
when wait_rst_done_b1 =>
if cnt_23 = '1' then
next_state <= wait_rst_done_b0;
end if;
when wait_rst_done_b0 =>
if cnt_23 = '0' then
next_state <= idle;
end if;
when idle =>
if m_kick = '1' then
next_state <= preable;
next_cnt <= 0;
end if;
when preable =>
if cnt = 31 then
next_state <= start_of_frame;
next_cnt <= 0;
end if;
mdio_o <= '1';
when start_of_frame =>
mdio_o <= CONV_std_logic_vector(cnt, 1)(0);
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
next_state <= op_code;
next_cnt <= 0;
end if;
when op_code =>
mdio_o <= not m_op xor CONV_std_logic_vector(cnt, 1)(0);
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
next_state <= phy_addr;
next_cnt <= 0;
end if;
when phy_addr =>
mdio_o <= '0';
if cnt = 4 then
next_state <= reg_addr;
next_cnt <= 0;
end if;
when reg_addr =>
mdio_o <= m_addr(cnt);
if cnt = 4 then
next_state <= turn_around;
next_cnt <= 0;
end if;
when turn_around =>
mdio_o <= 'Z';
mdio_t <= '1';
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
if m_op = '0' then
next_state <= read_in;
else
next_state <= write_out;
end if;
next_cnt <= 0;
end if;
when read_in =>
mdio_o <= 'Z';
mdio_t <= '1';
next_value(cnt) <= bit_in;
if cnt = 15 then
next_state <= idle;
end if;
when write_out =>
mdio_o <= m_data(cnt);
if cnt = 15 then
next_state <= idle;
end if;
end case;
end process;
fsm: process (clk)
begin
if RISING_EDGE(clk) then
if state = idle and kick = '1' then
m_op <= op;
m_addr <= addr;
m_data <= data_i;
m_kick <= '1';
end if;
if MDIO_clk = '0' and prev_MDIO_clk = '1' then
state <= next_state;
cnt <= next_cnt;
value <= next_value;
m_kick <= '0';
end if;
if MDIO_clk = '1' and prev_MDIO_clk = '0' then
bit_in <= mdio_i;
end if;
if rst = '1' then
state <= wait_rst_done_b1;
cnt <= 0;
end if;
end if;
end process;
-- Genearate clock
MDIO_clk <= cnt_5;
prev_MDIO_clk <= cnt_5 when RISING_EDGE(clk);
mdc <= MDIO_clk;
end Behavioral;
|
gpl-3.0
|
metaspace/ghdl_extra
|
lfsr4/test_a3p125.vhdl
|
1
|
1467
|
-- test_a3p125.vhd
-- just a file that fills a whole FPGA with LFSRs
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity test_a3p125 is
generic ( size : integer := 64);
port ( clk, reset, sig_in : in std_ulogic;
sig_out : inout std_ulogic_vector(size downto 1));
end test_a3p125;
architecture test of test_a3p125 is
signal sigtmp : std_ulogic_vector(size downto 1);
begin
lab: for iterateur in 1 to size generate
dut : entity work.lfsr4
generic map(size => 46)
-- 46+6=48, 48*64=3072tiles => A3P125
port map (
clk => clk,
reset => reset,
din => sigtmp(iterateur),
s => sig_out(iterateur),
lfsr => open);
end generate lab;
sigtmp <= sig_out(size-1 downto 1) & sig_in;
end test;
|
gpl-3.0
|
Project-Bonfire/Bonfire
|
RTL/virtual_channel/xbar.vhd
|
1
|
1701
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
North_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (9 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in, North_vc_in, East_vc_in, West_vc_in, South_vc_in, Local_vc_in) begin
case(sel) is
when "0000000001" =>
Data_out <= Local_in;
when "0000000010" =>
Data_out <= South_in;
when "0000000100" =>
Data_out <= West_in;
when "0000001000" =>
Data_out <= East_in;
when "0000010000" =>
Data_out <= North_in;
when "0000100000" =>
Data_out <= Local_vc_in;
when "0001000000" =>
Data_out <= South_vc_in;
when "0010000000" =>
Data_out <= West_vc_in;
when "0100000000" =>
Data_out <= East_vc_in;
when others =>
Data_out <= North_vc_in;
end case;
end process;
end;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/trigger-logic/eudet_tlu.vhd
|
1
|
5563
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eudet_tlu is
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end eudet_tlu;
architecture rtl of eudet_tlu is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
-- constants
signal C_DEADTIME : integer := 300; -- clk_i cycles
signal C_CLKDIVIDER : integer := 4; -- 40 MHz -> 10Mhz
-- State machine
type state_type is (IDLE, TRIGGER, RECEIVE, DEAD);
signal state : state_type;
-- Sync inputs
signal sync_eudet_trig_i : std_logic;
signal sync_eudet_rst_i : std_logic;
signal trig_tag_t : std_logic_vector(15 downto 0); -- only 15:1 good
signal eudet_busy_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_bust_t : std_logic;
signal clk_counter : unsigned (3 downto 0);
signal bit_counter : unsigned (4 downto 0);
signal dead_counter : unsigned (9 downto 0);
begin
-- Sync async inputs
trig_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_trig_i, sync_out => sync_eudet_trig_i);
rst_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_rst_i, sync_out => sync_eudet_rst_i);
eudet_busy_o <= eudet_busy_t;
eudet_clk_o <= eudet_clk_t;
rst_o <= '0';
state_machine: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
state <= IDLE;
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
dead_counter <= (others => '0');
trig_tag_t <= (others => '0');
trig_tag_o <= (others => '0');
trig_o <= '0';
elsif rising_edge(clk_i) then
case state is
when IDLE =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_o <= '0';
if (sync_eudet_trig_i = '1') then
state <= TRIGGER;
end if;
when TRIGGER =>
-- Raise busy and wit until trigger is negated
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_tag_t <= (others => '0');
dead_counter <= (others => '0');
if (sync_eudet_trig_i = '0' and simple_mode_i = '0') then
state <= RECEIVE;
elsif (sync_eudet_trig_i = '0' and simple_mode_i = '1') then
state <= DEAD;
end if;
when RECEIVE =>
eudet_busy_t <= '1';
trig_o <= '0';
clk_counter <= clk_counter + 1;
dead_counter <= (others => '0');
if (clk_counter = (C_CLKDIVIDER-1)) then
clk_counter <= (others => '0');
eudet_clk_t <= not eudet_clk_t;
if (eudet_clk_t = '1') then --sampling on negative edge
bit_counter <= bit_counter + 1;
trig_tag_t <= eudet_trig_i & trig_tag_t(15 downto 1); -- do not need synced vers here
end if;
end if;
if (bit_counter = "10000") then
state <= DEAD;
trig_tag_o <= '0' & trig_tag_t(14 downto 0);
end if;
when DEAD =>
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
if (dead_counter = 0) then
trig_o <= '1'; -- Trigger now (16 clock cycles after the inital trigger?)
end if;
dead_counter <= dead_counter + 1;
if (dead_counter = C_DEADTIME) then
state <= IDLE;
end if;
when others =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
state <= IDLE;
end case;
end if;
end process state_machine;
end rtl;
|
gpl-3.0
|
kuba-moo/VHDL-precise-packet-generator
|
tb_eth_rx.vhd
|
1
|
4216
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_eth_rx IS
END tb_eth_rx;
ARCHITECTURE behavior OF tb_eth_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ethernet_receive
PORT(
clk : IN std_logic;
rst : IN std_logic;
PhyRxd : IN std_logic_vector(3 downto 0);
PhyRxDv : IN std_logic;
PhyRxClk : IN std_logic;
Led : OUT std_logic_vector(4 downto 0);
-- Some temporary debug stuff
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0);
data : OUT std_logic_vector(7 downto 0);
busPkt : OUT std_logic;
busDesc : OUT std_logic
);
END COMPONENT;
COMPONENT phy_tx
PORT(
clk : IN std_logic;
rst : IN std_logic;
PhyTxClk : IN std_logic;
data : IN std_logic_vector(7 downto 0);
busPkt : IN std_logic;
busDesc : IN std_logic;
PhyTxd : OUT std_logic_vector(3 downto 0);
PhyTxEn : OUT std_logic;
PhyTxEr : OUT std_logic;
Led : OUT std_logic_vector(1 downto 0);
-- Some temporary debug stuff
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal PhyRxd, PhyTxd : std_logic_vector(3 downto 0) := (others => '0');
signal PhyRxDv, PhyTxEn : std_logic := '0';
signal PhyRxClk : std_logic := '0';
--Outputs
signal Led : std_logic_vector(4 downto 0);
signal data : std_logic_vector(7 downto 0);
signal busPkt, PhyTxEr : std_logic;
signal busDesc : std_logic;
signal LedTx : std_logic_vector(1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant PhyRxClk_period : time := 42 ns;
signal clk_o : std_logic;
BEGIN
clk_o <= transport clk after 8 ns;
-- Instantiate the Unit Under Test (UUT)
uut: ethernet_receive PORT MAP (
clk => clk,
rst => rst,
PhyRxd => PhyRxd,
PhyRxDv => PhyRxDv,
PhyRxClk => PhyRxClk,
Led => Led,
data => data,
busPkt => busPkt,
busDesc => busDesc,
sw => ( others => '0' )
);
Inst_phy_tx: phy_tx PORT MAP(
clk => clk,
rst => rst,
PhyTxd => PhyTxd,
PhyTxEn => PhyTxEn,
PhyTxClk => PhyRxClk,
PhyTxEr => PhyTxEr,
Led => LedTx,
data => data,
busPkt => busPkt,
busDesc => busDesc,
sw => ( others => '0' )
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
PhyRxClk_process :process
begin
PhyRxClk <= '0';
wait for PhyRxClk_period/2;
PhyRxClk <= '1';
wait for PhyRxClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for PhyRxClk_period * 2;
-- hold reset state for 100 ns.
rst <= '0';
wait for PhyRxClk_period * 10;
PhyRxDv <= '1';
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
for i in 0 to 15 loop
PhyRxd <= CONV_std_logic_vector(i, 4);
wait for PhyRxClk_period;
end loop;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxDv <= '0';
PhyRxd <= ( others => '0' );
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/sp6_data_gen.vhd
|
20
|
37259
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
gpl-3.0
|
Candyroot/Floating-Point-Addition
|
pda/@small_@alu/_primary.vhd
|
4
|
368
|
library verilog;
use verilog.vl_types.all;
entity Small_Alu is
port(
clk : in vl_logic;
res : in vl_logic;
a : in vl_logic_vector(31 downto 0);
b : in vl_logic_vector(31 downto 0);
outp : out vl_logic_vector(8 downto 0)
);
end Small_Alu;
|
gpl-3.0
|
metaspace/ghdl_extra
|
int_bool/sha-1.vhdl
|
1
|
2657
|
-- sha-1.vhdl : microbenchmark pour simulation comportementale
-- création : 2011/02/01 par [email protected]
-- code dérivé du pseudo-code disponible à http://en.wikipedia.org/wiki/SHA-1
library work;
-- Décommenter l'une de ces 4 possibilités :
-- version integer simple :
--use work.int_ops.all;
--use work.int_integer.all;
-- version integer avec détection des dépassements :
--use work.int_ops.all;
--use work.int_integer_range.all;
-- version à base de bit_vector :
use work.int_bitvector.all;
library IEEE; use IEEE.numeric_bit.all;
-- version à base de std_ulogic_vector :
--use work.int_sulv.all;
--library IEEE; use IEEE.numeric_std.all;
entity sha1 is end sha1;
architecture comportement of sha1 is
begin
process
constant k1 : int_32 := from_int( 1518500249,32); -- sqrt( 2)*2^30
constant k2 : int_32 := from_int( 1859775393,32); -- sqrt( 3)*2^30
constant k3 : int_32 := from_int( -253476060,32); -- sqrt( 5)*2^30
constant k4 : int_32 := from_int(-1247986134,32); -- sqrt(10)*2^30
variable i, j: integer; -- compteurs de boucles
variable h0 : int_32 := from_int( 19088743,32); -- 0x01234567
variable h1 : int_32 := from_int(-1985229329,32); -- 0x89ABCDEF
variable h2 : int_32 := from_int( -19088744,32); -- 0xFEDCBA98
variable h3 : int_32 := from_int( 1985229328,32); -- 0x76543210
variable h4 : int_32 := from_int( -253635901,32); -- 0xF0E1D2C3
variable A, B, C, D, E, F, k, t : int_32;
type type_array80 is array(0 to 79) of int_32;
variable w : type_array80;
begin
-- boucle principale (à faire varier pour prendre plus de temps) :
for j in 0 to 200 loop
-- expansion des 16 premiers mots :
for i in 16 to 79 loop
w(i) := (w(i-3) xor w(i-8) xor w(i-14) xor w(i-16)) rol 1;
end loop;
-- initialisation des variables :
A:=h0; B:=h1; C:=h2; D:=h3; E:=h4;
for i in 0 to 79 loop
if i < 40 then
if i < 20 then
F := (B and C) or ((not B) and D);
k := k1;
else
F := B xor C xor D;
k := k2;
end if;
else
if i < 60 then
F := (B and C) or (B and D) or (C and D);
k := k3;
else
F := B xor C xor D;
k := k4;
end if;
end if;
t := (A rol 5) + F + E + k + w(i);
E := D; D := C;
C := B rol 30;
B := A; A := t;
end loop;
-- recombinaison des résultats :
h0 := h0 + A; h1 := h1 + B;
h2 := h2 + C; h3 := h3 + D;
h4 := h4 + E;
end loop;
wait;
end process;
end comportement;
|
gpl-3.0
|
maxx04/cam_sim
|
cam_sim.srcs/sim_1/imports/BMP/sim_bmppack.vhd
|
1
|
8349
|
-------------------------------------------------------------------------------
-- Title : BMP Package
-- Project :
-------------------------------------------------------------------------------
-- File : sim_bmppack.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-10-29
-- Platform : ModelSIM 6.0
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006 by Kest
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
-- http://de.wikipedia.org/wiki/Windows_Bitmap
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
package sim_bmppack is
-- maximale Größe des Speichers
constant cMAX_X : integer := 1300;
constant cMAX_Y : integer := 1300;
constant cBytesPerPixel : integer := 3;
constant cMaxMemSize : integer := cMAX_X * cMAX_Y * cBytesPerPixel;
subtype file_element is std_logic_vector(7 downto 0);
type mem_array is array(cMaxMemSize downto 0) of file_element;
type header_array is array(53 downto 0) of file_element;
procedure ReadFile(FileName : in string);
procedure WriteFile(FileName : in string);
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0));
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0));
function GetWidth(header : in header_array) return integer;
procedure GetWidth(signal width : out integer);
function GetHeigth(header : in header_array) return integer;
procedure GetHeigth(signal height : out integer);
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0));
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
end package sim_bmppack;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body sim_bmppack is
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
shared variable memory_in : mem_array;
shared variable memory_out : mem_array;
shared variable header : header_array;
shared variable pImageSize : integer;
shared variable pImageWidth : integer;
shared variable pImageHeight : integer;
-----------------------------------------------------------------------------
-- This code reads a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure ReadFile(FileName : in string) is
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
variable index : integer := 0;
type bit_vector_file is file of bit_vector;
file read_file : bit_vector_file open read_mode is FileName;
begin
report "Read File";
report FileName;
index := 0;
---------------------------------------------------------------------------
-- Header einlesen
---------------------------------------------------------------------------
report "Read Header";
for i in 0 to 53 loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
header(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
index := index + 1;
end if;
end loop;
pImageWidth := GetWidth(header);
pImageHeight := GetHeigth(header);
pImageSize := pImageWidth * pImageHeight;
report "Read Image";
index := 0;
while not endfile(read_file) loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
memory_in(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
memory_out(index) := x"45";
index := index + 1;
end if;
end loop;
report "Okay";
end ReadFile;
-----------------------------------------------------------------------------
-- Read one byte from Memory
-----------------------------------------------------------------------------
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0)) is
begin
data := memory_in(adr);
end ReadByteFromMemory;
-----------------------------------------------------------------------------
-- Pixel Operationen
-----------------------------------------------------------------------------
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
data(23 downto 16) <= memory_in(x*3 + 3*y*GetWidth(header));
data(15 downto 8) <= memory_in(x*3+1 + 3*y*GetWidth(header));
data(7 downto 0) <= memory_in(x*3+2 + 3*y*GetWidth(header));
end if;
end GetPixel;
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
memory_out(x*3+y*(GetWidth(header)*3)) := data(23 downto 16);
memory_out(x*3+1+y*(GetWidth(header)*3)) := data(15 downto 8);
memory_out(x*3+2+y*(GetWidth(header)*3)) := data(7 downto 0);
end if;
end SetPixel;
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
constant CrossSize : integer := 5;
begin
for n in -CrossSize to CrossSize loop
SetPixel(x+n,y,data);
SetPixel(x,y+n,data);
end loop;
end DrawCross;
-----------------------------------------------------------------------------
-- Write one byte to Memory
-----------------------------------------------------------------------------
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0)) is
begin
memory_out(adr) := data;
end WriteByteToMemory;
-- Get Width of Image
function GetWidth(header : in header_array) return integer is
begin
return conv_integer(header(21) & header(20) & header(19) & header(18));
end function GetWidth;
procedure GetWidth(signal width : out integer) is
begin
width <= pImageWidth;
end GetWidth;
-- Get Height of Image
function GetHeigth(header : in header_array) return integer is
begin
return conv_integer(header(25) & header(24) & header(23) & header(22));
end function GetHeigth;
procedure GetHeigth(signal height : out integer) is
begin
height <= pImageHeight;
end GetHeigth;
-----------------------------------------------------------------------------
-- This code write a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure WriteFile(FileName : in string) is
variable next_vector : character;
variable index : integer := 0;
type char_file is file of character;
file write_file : char_file open write_mode is FileName;
begin
report "Write File...";
report FileName;
report "write Header";
index := 0;
for i in 0 to 53 loop
next_vector := character'val(conv_integer(header(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "write Image";
index := 0;
while index < pImageSize*3 loop
next_vector := character'val(conv_integer(memory_out(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "Okay";
end WriteFile;
end sim_bmppack;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/fe65p2_addon.vhd
|
2
|
16786
|
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim ([email protected])
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity fe65p2_addon is
port (
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
-- TO FMC
clk_bx_o : out std_logic;
trig_o : out std_logic;
clk_cnfg_o : out std_logic;
en_pix_sr_cnfg_o : out std_logic;
ld_cnfg_o : out std_logic;
si_cnfg_o : out std_logic;
pix_d_cnfg_o : out std_logic;
clk_data_o : out std_logic;
rst_0_o : out std_logic;
rst_1_o : out std_logic;
dac_sclk_o : out std_logic;
dac_sdi_o : out std_logic;
dac_ld_o : out std_logic;
dac_cs_o : out std_logic;
inj_sw_o : out std_logic
);
end fe65p2_addon;
architecture behavioral of fe65p2_addon is
-- System signals
signal sys_rst : std_logic;
signal clk_40 : std_logic;
-- clocks
signal clk_bx_t : std_logic;
signal clk_cnfg_t : std_logic;
signal clk_data_t : std_logic;
signal en_bx_clk : std_logic;
signal en_conf_clk : std_logic;
signal en_data_clk : std_logic;
-- cmd deserialiser
signal yarr_cmd : std_logic;
signal cmd_count : unsigned(7 downto 0);
signal cmd_valid : std_logic;
signal cmd_sreg : std_logic_vector(31 downto 0);
-- cmd decoder
signal new_cmd : std_logic;
signal adr : std_logic_vector(15 downto 0);
signal payload : std_logic_vector(15 downto 0);
-- registers
signal conf_reg : std_logic_vector(159 downto 0);
signal pix_reg : std_logic_vector(255 downto 0);
signal static_reg : std_logic_vector(15 downto 0);
signal pulser_reg : std_logic_vector(15 downto 0);
signal latency : unsigned(8 downto 0);
signal dac_setting : std_logic_vector(15 downto 0);
signal trig_multiplier : unsigned(3 downto 0);
signal delay_setting : std_logic_vector(7 downto 0);
-- config serialiser
signal conf_load : std_logic_vector(7 downto 0);
signal conf_sreg_cnt : unsigned(7 downto 0);
signal conf_sreg : std_logic_vector(144 downto 0);
signal pix_sreg_cnt : unsigned(8 downto 0);
signal pix_sreg : std_logic_vector(255 downto 0);
signal en_pix_reg : std_logic;
-- inject & trigger
signal dig_inj : std_logic;
signal trigger : std_logic;
signal pulser_trig_t : std_logic_vector(40 downto 0);
signal inject_cnt : unsigned(8 downto 0);
signal trig_cnt : unsigned(4 downto 0);
signal en_inj : std_logic;
signal inj_sw_t : std_logic;
-- DAC
signal dac_load : std_logic_vector(15 downto 0);
signal dac_cs_t : std_logic;
signal dac_sreg_cnt : unsigned(7 downto 0);
signal dac_sreg : std_logic_vector(15 downto 0);
signal dac_sclk_t : std_logic;
component delay_line
generic (
width : positive := 8);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0) );
end component delay_line;
begin
sys_rst <= not rst_n;
clk_40 <= clk_i;
clk_bx_t <= clk_40;
clk_cnfg_t <= clk_40;
clk_data_t <= clk_rx_i;
-- Outputs
trig_o <= trigger;
en_pix_sr_cnfg_o <= en_pix_reg;
ld_cnfg_o <= conf_load(4) or conf_load(5) or conf_load(6) or conf_load(7) or dig_inj;
si_cnfg_o <= conf_sreg(144) or pix_sreg(255);
dac_sclk_o <= dac_sclk_t;
dac_sdi_o <= dac_sreg(15);
dac_ld_o <= not (dac_load(15) or dac_load(14) or dac_load(13) or dac_load(12) or dac_load(11) or
dac_load(10) or dac_load(9) or dac_load(8) or dac_load(7) or dac_load(6) or dac_load(5));
dac_cs_o <= dac_cs_t;
inj_sw_t <= '0' when (unsigned(pulser_trig_t) = 0) else '1';
-- Fine delay for pulser
cmp_inj_delay: delay_line
GENERIC MAP(
width => 7)
PORT MAP(
clk => clk_40,
rst => sys_rst,
input => inj_sw_t,
output => inj_sw_o,
setting => delay_setting(6 downto 0)
);
-- Static settings
en_data_clk <= static_reg(0);
en_bx_clk <= static_reg(1);
pix_d_cnfg_o <= static_reg(2);
en_inj <= static_reg(3);
rst_0_o <= not static_reg(4);
rst_1_o <= not static_reg(5);
yarr_cmd <= serial_in;
cmd_deserialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
cmd_sreg <= (others => '0');
cmd_count <= (others => '0');
cmd_valid <= '0';
elsif rising_edge(clk_40) then
cmd_sreg <= cmd_sreg(30 downto 0) & yarr_cmd;
if (cmd_count = TO_UNSIGNED(31,8)) then
cmd_count <= (others => '0');
cmd_valid <= '1';
elsif (cmd_count > 0) then
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
elsif (yarr_cmd = '1' and cmd_count = TO_UNSIGNED(0,8)) then -- start bit
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
else
cmd_valid <= '0';
end if;
end if;
end process cmd_deserialiser;
cmd_decoder: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
new_cmd <= '0';
adr <= (others => '0');
payload <= (others => '0');
conf_reg <= (others => '0');
pix_reg <= (others => '0');
static_reg <= (others => '0');
pulser_reg <= (others => '0');
latency <= (others => '0');
dac_setting <= (others => '0');
trig_multiplier <= x"5";
delay_setting <= (others => '0');
elsif rising_edge(clk_40) then
new_cmd <= '0';
if (cmd_valid = '1') then
adr <= '0' & cmd_sreg(30 downto 16);
payload <= cmd_sreg(15 downto 0);
new_cmd <= '1';
end if;
-- pulses 1 clk cycle
pulser_reg <= (others => '0');
-- [0] : start shift conf reg
-- [1] : inject & trigger
-- [2] : start shift pixel reg
-- [3] : pulse load line
-- [4] : shift SR by one
-- [5] : load DAC
-- [6] : switch pulser
-- [7] : trigger (no inject)
if (new_cmd = '1') then
case (adr) is
-- Global Shift reg (145 bit)
when x"0000" => conf_reg(0) <= payload(0);
when x"0001" => conf_reg(1) <= payload(0);
when x"0002" => conf_reg(2) <= payload(0);
when x"0003" => conf_reg(6 downto 3) <= payload(3 downto 0);
when x"0004" => conf_reg(8 downto 7) <= payload(1 downto 0);
when x"0005" => conf_reg(9) <= payload(0);
when x"0006" => conf_reg(10) <= payload(0);
when x"0007" => conf_reg(11) <= payload(0);
when x"0008" => conf_reg(20 downto 12) <= payload(8 downto 0);
when x"0009" => conf_reg(36 downto 21) <= payload(15 downto 0);
when x"000a" => conf_reg(52 downto 37) <= payload(15 downto 0);
when x"000b" => conf_reg(56 downto 53) <= payload(3 downto 0);
when x"000c" => conf_reg(64 downto 57) <= payload(7 downto 0);
when x"000d" => conf_reg(72 downto 65) <= payload(7 downto 0);
when x"000e" => conf_reg(80 downto 73) <= payload(7 downto 0);
when x"000f" => conf_reg(88 downto 81) <= payload(7 downto 0);
when x"0010" => conf_reg(96 downto 89) <= payload(7 downto 0);
when x"0011" => conf_reg(104 downto 97) <= payload(7 downto 0);
when x"0012" => conf_reg(112 downto 105) <= payload(7 downto 0);
when x"0013" => conf_reg(120 downto 113) <= payload(7 downto 0);
when x"0014" => conf_reg(128 downto 121) <= payload(7 downto 0);
when x"0015" => conf_reg(136 downto 129) <= payload(7 downto 0);
when x"0016" => conf_reg(144 downto 137) <= payload(7 downto 0);
-- Pixel Shift reg (256 bit)
when x"0020" => pix_reg(15 downto 0) <= payload(15 downto 0);
when x"0021" => pix_reg(31 downto 16) <= payload(15 downto 0);
when x"0022" => pix_reg(47 downto 32) <= payload(15 downto 0);
when x"0023" => pix_reg(63 downto 48) <= payload(15 downto 0);
when x"0024" => pix_reg(79 downto 64) <= payload(15 downto 0);
when x"0025" => pix_reg(95 downto 80) <= payload(15 downto 0);
when x"0026" => pix_reg(111 downto 96) <= payload(15 downto 0);
when x"0027" => pix_reg(127 downto 112) <= payload(15 downto 0);
when x"0028" => pix_reg(143 downto 128) <= payload(15 downto 0);
when x"0029" => pix_reg(159 downto 144) <= payload(15 downto 0);
when x"002a" => pix_reg(175 downto 160) <= payload(15 downto 0);
when x"002b" => pix_reg(191 downto 176) <= payload(15 downto 0);
when x"002c" => pix_reg(207 downto 192) <= payload(15 downto 0);
when x"002d" => pix_reg(223 downto 208) <= payload(15 downto 0);
when x"002e" => pix_reg(239 downto 224) <= payload(15 downto 0);
when x"002f" => pix_reg(255 downto 240) <= payload(15 downto 0);
-- Modes
when x"0030" => static_reg <= payload;
when x"0031" => pulser_reg <= payload;
when x"0032" => latency <= unsigned(payload(8 downto 0));
when x"0033" => dac_setting <= payload(15 downto 0);
when x"0034" => trig_multiplier <= unsigned(payload(3 downto 0));
when x"0035" => delay_setting <= payload(7 downto 0);
when others =>
end case;
end if;
end if;
end process cmd_decoder;
conf_serialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
conf_sreg_cnt <= (others => '0');
conf_sreg <= (others => '0');
en_conf_clk <= '0';
conf_load <= (others => '0');
pix_sreg_cnt <= (others => '0');
pix_sreg <= (others => '0');
en_pix_reg <= '0';
elsif rising_edge(clk_40) then
-- Configuration serialiser
conf_load(0) <= '0';
if (pulser_reg(0) = '1') then
conf_sreg_cnt <= TO_UNSIGNED(145, 8);
conf_sreg <= conf_reg(144 downto 0);
en_conf_clk <= '1';
elsif (conf_sreg_cnt = TO_UNSIGNED(1, 8)) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_load(0) <= '1';
en_conf_clk <= '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
elsif (conf_sreg_cnt > 0) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
en_conf_clk <= '1';
end if;
-- Pulse load line
if (pulser_reg(3) = '1') then
conf_load(0) <= '1';
end if;
-- Pixel sreg serialiser
en_pix_reg <= '0';
if (pulser_reg(2) = '1') then
pix_sreg_cnt <= TO_UNSIGNED(256, 9);
pix_sreg <= pix_reg(255 downto 0);
en_conf_clk <= '1';
en_pix_reg <= '1';
elsif (pix_sreg_cnt = TO_UNSIGNED(1, 9)) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
--conf_load <= '1';
en_pix_reg <= '0';
en_conf_clk <= '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
elsif (pix_sreg_cnt > 0) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
en_conf_clk <= '1';
en_pix_reg <= '1';
end if;
conf_load(1) <= conf_load(0);
conf_load(2) <= conf_load(1);
conf_load(3) <= conf_load(2);
conf_load(4) <= conf_load(3);
conf_load(5) <= conf_load(4);
conf_load(6) <= conf_load(5);
conf_load(7) <= conf_load(6);
end if;
end process conf_serialiser;
inject_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
inject_cnt <= (others => '0');
trig_cnt <= (others => '0');
elsif rising_edge(clk_40) then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
if (pulser_reg(1) = '1') then
inject_cnt <= TO_UNSIGNED((TO_INTEGER(latency) + 2), 9); -- Latency vonfig
if (en_inj = '0') then
dig_inj <= '1';
else
pulser_trig_t(0) <= '1';
end if;
elsif (inject_cnt > ((TO_INTEGER(latency) - 6))) then -- TODO change to pulse length
if (en_inj = '0') then
dig_inj <= '1';
end if;
inject_cnt <= inject_cnt - 1;
elsif ((inject_cnt <= (TO_INTEGER(trig_multiplier))) and inject_cnt > 1) then -- TODO change to trigger multiplier
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt = 1) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt > 0) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
end if;
if (pulser_reg(7) = '1') then
trig_cnt <= TO_UNSIGNED((TO_INTEGER(trig_multiplier) + 1), 5);
elsif (trig_cnt > 0) then
trig_cnt <= trig_cnt - 1;
trigger <= '1';
end if;
end if;
end process inject_proc;
pulse_delay: for I in 1 to pulser_trig_t'length-1 generate
begin
delay_proc: process(clk_40)
begin
if (sys_rst = '1') then
pulser_trig_t(I) <= '0';
elsif rising_edge(clk_40) then
pulser_trig_t(I) <= pulser_trig_t(I-1);
end if;
end process delay_proc;
end generate;
dac_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dac_load <= (others => '0');
dac_cs_t <= '1';
dac_sreg_cnt <= (others => '0');
dac_sreg <= (others => '0');
dac_sclk_t <= '0';
elsif rising_edge(clk_40) then
dac_load(0) <= '0';
dac_cs_t <= '1';
if (pulser_reg(5) = '1') then
dac_sreg_cnt <= TO_UNSIGNED(160, 8);
dac_sreg <= dac_setting(15 downto 0);
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt = TO_UNSIGNED(1, 8)) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
dac_load(0) <= '1';
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt > 0) then
if ((dac_sreg_cnt mod 10) = 1) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
end if;
if ((dac_sreg_cnt mod 5) = 1) then
dac_sclk_t <= not dac_sclk_t;
end if;
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_cs_t <= '0';
end if;
dac_load(1) <= dac_load(0);
dac_load(2) <= dac_load(1);
dac_load(3) <= dac_load(2);
dac_load(4) <= dac_load(3);
dac_load(5) <= dac_load(4);
dac_load(6) <= dac_load(5);
dac_load(7) <= dac_load(6);
dac_load(8) <= dac_load(7);
dac_load(9) <= dac_load(8);
dac_load(10) <= dac_load(9);
dac_load(11) <= dac_load(10);
dac_load(12) <= dac_load(11);
dac_load(13) <= dac_load(12);
dac_load(14) <= dac_load(13);
dac_load(15) <= dac_load(14);
end if;
end process dac_proc;
-- clock ddr2 buffers
conf_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_cnfg_o, -- 1-bit output data
C0 => clk_cnfg_t, -- 1-bit clock input
C1 => not clk_cnfg_t, -- 1-bit clock input
CE => en_conf_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
bx_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_bx_o, -- 1-bit output data
C0 => clk_bx_t, -- 1-bit clock input
C1 => not clk_bx_t, -- 1-bit clock input
CE => en_bx_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
data_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_data_o, -- 1-bit output data
C0 => clk_data_T, -- 1-bit clock input
C1 => not clk_data_t, -- 1-bit clock input
CE => en_data_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
end behavioral;
|
gpl-3.0
|
metaspace/ghdl_extra
|
access_c/ghdl_access.vhdl
|
1
|
1567
|
-- fichier ghdl_access.vhdl
-- created by Yann Guidon / ygdes.com
-- version jeu. avril 10 01:03:13 CEST 2014
-- Copyright (C) 2014 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
package ghdl_access is
-- Définit un pointeur vers un entier :
type int_access is access integer;
-- déclaration des fonctions en C
function get_ptr return int_access;
attribute foreign of get_ptr :
function is "VHPIDIRECT get_ptr";
procedure change_int(f : integer);
attribute foreign of change_int :
procedure is "VHPIDIRECT change_int";
-- crée une variable aliasée vers la variable en C
shared variable my_data : int_access := get_ptr;
end ghdl_access;
package body ghdl_access is
function get_ptr return int_access is
begin
assert false report "VHPI" severity failure;
end get_ptr;
procedure change_int(f : integer) is
begin
assert false report "VHPI" severity failure;
end change_int;
end ghdl_access;
|
gpl-3.0
|
Project-Bonfire/Bonfire
|
RTL/base_line/FIFO_one_hot_credit_based.vhd
|
5
|
5364
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd
|
19
|
18779
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/gn4124-core/spartan6/serdes_n_to_1_s2_diff.vhd
|
2
|
11029
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_n_to_1_s2_diff is
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_s2_diff;
architecture arch_serdes_n_to_1_s2_diff of serdes_n_to_1_s2_diff is
signal cascade_di : std_logic_vector(D-1 downto 0);
signal cascade_do : std_logic_vector(D-1 downto 0);
signal cascade_ti : std_logic_vector(D-1 downto 0);
signal cascade_to : std_logic_vector(D-1 downto 0);
signal mdataina : std_logic_vector(D*8 downto 0);
signal mdatainb : std_logic_vector(D*4 downto 0);
signal tx_data_out : std_logic_vector(D-1 downto 0);
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0'); -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i);
end generate;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i);
end generate;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate;
end generate;
end arch_serdes_n_to_1_s2_diff;
|
gpl-3.0
|
metaspace/ghdl_extra
|
io_port/telecran.vhdl
|
1
|
2557
|
-- Fichier : telecran.vhdl
-- création : dim. oct. 31 13:00:03 CET 2010
-- An example program using the "buttons" package
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library work; use work.boutons.all; -- boutons
use work.fb_ghdl.all; -- framebuffer
use work.rt_utils.all; -- horloge
library ieee; use ieee.std_logic_1164.all;
entity telecran is end telecran;
architecture tele of telecran is
signal clk, stop : std_ulogic := '0';
begin
-- instanciation de l'horloge :
horloge : entity work.rt_clk
generic map(ms => 10)
port map(clk => clk, stop => stop);
process(clk)
variable couleur : integer := -1; -- couleur initiale : blanc
variable l : integer := 10; -- longueur des côtés du carré
-- coordonnées d'origine : au centre de l'écran
variable x : integer := fbx/2;
variable y : integer := fby/2;
procedure dessine_carre is
variable i,j : integer;
begin
for i in 0 to l-1 loop
for j in 0 to l-1 loop
pixel(y+i,x+j) := couleur;
end loop;
end loop;
couleur := couleur - 1; -- change lentement la couleur;
end procedure;
variable b1, b2, b3, b4 : std_ulogic;
begin
lecture_boutons(b1, b2, b3, b4);
if b1='1' then -- aller à gauche : décrémenter x
if x > 0 then
x := x-1;
end if;
else
if b2='1' then -- aller à droite : incrémenter x
if x < (fbx1-l) then
x := x+1;
end if;
else
if b3='1' then -- aller en haut : décrémenter y
if y > 0 then
y := y-1;
end if;
else
if b4='1' then -- aller en bas : incrémenter y
if y < (fby1-l) then
y := y+1;
end if;
end if;
end if;
end if;
end if;
-- affiche en continu le carré :
dessine_carre;
end process;
end tele;
|
gpl-3.0
|
maxx04/cam_sim
|
cam_sim.srcs/sim_1/new/s_top.vhd
|
1
|
4234
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 19:03:41
-- Design Name:
-- Module Name: s_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity s_top is
end s_top;
architecture Behavioral of s_top is
signal reset : std_logic := '1';
signal clk, clk_out : std_logic := '0';
signal pclk, cam_hsync, cam_vsync, cam_href : std_logic := '0';
signal px_data : std_logic_vector(7 downto 0);
signal data_to_wreiter_ready : std_logic := '0';
signal data_to_wreiter : std_logic_vector(23 downto 0);
signal x, y : integer := 0;
signal tmp_sensor : sensor_vector;
signal tmp_sensor_ready : std_logic := '0';
component sim_tb_bmpread
port(resetn : in std_logic;
pclk : in std_logic;
pixel_data : out std_logic_vector(7 downto 0);
pixel_out_hsync, pixel_out_vsync, pixel_out_href : out std_logic);
end component;
component cam_move is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
hsync_in : in std_logic;
vsync_in : in std_logic;
href_in : in std_logic;
cam_pxdata : in STD_LOGIC_VECTOR(7 downto 0);
-----
cam_clk : out STD_LOGIC;
px_number : out natural range 0 to 1024 := 0;
line_number : out natural range 0 to 1024 := 0;
pixel_data : out std_logic_vector(23 downto 0);
pixel_data_ready : out STD_LOGIC;
sensor_data : out sensor_vector;
sensor_data_ready : out STD_LOGIC
);
end component;
component bmp_wreiter is
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
start_frame : in STD_LOGIC;
x, y : in positive;
pixel_data : in std_logic_vector(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : in sensor_vector;
sensor_data_ready : in STD_LOGIC);
end component;
begin
input : sim_tb_bmpread
port map(
resetn => reset,
pclk => pclk,
pixel_data => px_data,
pixel_out_hsync => cam_hsync,
pixel_out_vsync => cam_vsync,
pixel_out_href => cam_href
);
modul : cam_move
port map(clk => clk,
resetn => reset,
hsync_in => cam_hsync,
vsync_in => cam_vsync,
href_in => cam_href,
cam_pxdata => px_data,
---
cam_clk => pclk,
px_number => x,
line_number => y,
pixel_data => data_to_wreiter,
pixel_data_ready => data_to_wreiter_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_ready
);
output : bmp_wreiter
port map(
resetn => reset,
clk => clk,
start_frame => cam_vsync,
x => x,
y => y,
pixel_data => data_to_wreiter,
pixel_data_ready => data_to_wreiter_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_ready
);
clk <= not clk after 10 ns;
reset <= '0', '1' after 20 ns;
end Behavioral;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/rx-core/data_alignment.vhd
|
3
|
4097
|
-- word alignment
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_alignment is
port
(
clk : in std_logic := '0';
reset : in std_logic := '0';
din : in std_logic_vector(1 downto 0) := "00";
din_valid : in std_logic_vector(1 downto 0) := "00";
dout : out std_logic_vector(9 downto 0) := (others => '0');
dout_valid : out std_logic := '0';
dout_sync : out std_logic := '0'
);
end data_alignment;
architecture Behavioral of data_alignment is
-- FE-I4 Encoded Komma Words used for Alignment of the Decoder
constant idle_word : std_logic_vector(9 downto 0) := "0011111001";
constant sof_word : std_logic_vector(9 downto 0) := "0011111000";
constant eof_word : std_logic_vector(9 downto 0) := "0011111010";
-- Count of Bits before a new sync word is necessary (currently arbitrary)
constant fei4syncPeriod: integer := 160000000;
signal data_sr : std_logic_vector(10 downto 0) := (others => '0');
signal dcnt : integer range 0 to 11 := 0;
signal scnt : integer range 0 to fei4syncPeriod := 0;
signal sync : std_logic := '0';
signal sync_word : std_logic_vector(1 downto 0) := (others => '0');
signal sync_holdoff : std_logic := '0';
begin
-- search for sync words
process (reset, data_sr) begin
if reset = '1' then
sync_word <= "00";
else
if sync_holdoff = '0' then
if (data_sr(9 downto 0) = idle_word) or (data_sr(9 downto 0) = not idle_word) or
(data_sr(9 downto 0) = sof_word) or (data_sr(9 downto 0) = not sof_word) or
(data_sr(9 downto 0) = eof_word) or (data_sr(9 downto 0) = not eof_word) then
sync_word <= "01";
elsif (data_sr(10 downto 1) = idle_word) or (data_sr(10 downto 1) = not idle_word) or
(data_sr(10 downto 1) = sof_word) or (data_sr(10 downto 1) = not sof_word) or
(data_sr(10 downto 1) = eof_word) or (data_sr(10 downto 1) = not eof_word) then
sync_word <= "10";
else
sync_word <= "00";
end if;
else
sync_word <= "00";
end if;
end if;
end process;
-- data alignment
process begin
wait until rising_edge(clk);
if reset = '1' then
dout <= (others => '0');
dout_valid <= '0';
sync <= '0';
data_sr <= (others => '0');
dcnt <= 0;
scnt <= 0;
else
-- clear sync flag
if scnt = fei4syncPeriod then
sync <= '0';
scnt <= 0;
else
scnt <= scnt + 1;
end if;
-- shift in new data
if din_valid = "01" then
data_sr <= data_sr(9 downto 0) & din(0);
if sync_word = "01" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
sync_holdoff <= '1';
elsif sync_word = "10" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
sync_holdoff <= '1';
else
dcnt <= dcnt + 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 1;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 2;
else
dout_valid <= '0';
end if;
elsif din_valid = "11" then
data_sr <= data_sr(8 downto 0) & din(0) & din(1);
if sync_word = "01" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
elsif sync_word = "10" then
sync <= '1';
scnt <= 3;
dcnt <= 3;
else
dcnt <= dcnt + 2;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 2;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 3;
else
dout_valid <= '0';
end if;
else
if sync_word = "01" then
sync <= '1';
scnt <= 0;
dcnt <= 0;
elsif sync_word = "10" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 0;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 1;
else
dout_valid <= '0';
end if;
end if;
end if;
end process;
dout_sync <= sync;
end Behavioral;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/iodrp_controller.vhd
|
19
|
14635
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 02/06/09: Initial version for MIG wrapper.
-- 1.1: 02/01/09: updates to indentations.
-- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
-- for state machine always block. Also, assigned
-- intial value to load_shift_n to avoid latch
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues
-- to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
-- added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end entity iodrp_controller;
architecture trans of iodrp_controller is
constant READY : std_logic_vector(2 downto 0) := "000";
constant DECIDE : std_logic_vector(2 downto 0) := "001";
constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(7 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal capture_read_data : std_logic;
signal state : std_logic_vector(2 downto 0);
signal nextstate : std_logic_vector(2 downto 0);
signal data_out_mux : std_logic_vector(7 downto 0);
signal DRP_SDI_pre : std_logic;
signal ALMOST_READY_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
begin
--synthesis translate_off
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY => -- case(state)
-- state_ascii <= "ALMOST_READY";
-- when others =>
-- null;
-- end case;
-- end process;
--synthesis translate_on
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when (state = READY) else '0';
data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
data_reg;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "00000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
-- capture_read_data <= 1'b0;
read_data <= "00000000";
else
-- capture_read_data <= (state == DATA_PHASE);
-- if(capture_read_data)
if (state = ALMOST_READY) then
-- else
-- read_data <= read_data;
read_data <= shift_through_reg;
end if;
end if;
end if;
end process;
ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD <= ADDR_PHASE_ST1;
DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
-- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
-- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the read access.
when ADDR_PHASE =>
if (BIT_CNT7 = '1') then
if (rd_not_write_reg = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
nextstate <= READY;
when others =>
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
gpl-3.0
|
Candyroot/Floating-Point-Addition
|
pda/@big_@alu/_primary.vhd
|
4
|
365
|
library verilog;
use verilog.vl_types.all;
entity Big_Alu is
port(
clk : in vl_logic;
res : in vl_logic;
a : in vl_logic_vector(26 downto 0);
b : in vl_logic_vector(31 downto 0);
outp : out vl_logic_vector(27 downto 0)
);
end Big_Alu;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/cmd_prbs_gen.vhd
|
20
|
8359
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel use LFSR to generate random address, isntructions
-- or burst_length.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END cmd_prbs_gen;
ARCHITECTURE trans OF cmd_prbs_gen IS
SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
function logb2 (val : integer) return integer is
variable vec_con : integer;
variable rtn : integer := 1;
begin
vec_con := val;
for index in 0 to 31 loop
if(vec_con = 1) then
rtn := rtn + 1;
return(rtn);
end if;
vec_con := vec_con/2;
rtn := rtn + 1;
end loop;
end function logb2;
BEGIN
ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
lfsr_q(63) <= lfsr_q(62) ;
lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(64) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
prbs <= lfsr_q(32 DOWNTO 1);
END PROCESS;
END GENERATE;
xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= prbs_seed_i ;
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
lfsr_q(2) <= lfsr_q(1) ;
lfsr_q(1) <= lfsr_q(32) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
IF (FAMILY = "SPARTAN6") THEN
FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
ELSE
FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(20) <= lfsr_q(19) ;
lfsr_q(19) <= lfsr_q(18) ;
lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(20) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
BEGIN
prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
END PROCESS;
END GENERATE;
prbs_o <= prbs;
END trans;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/mcb_traffic_gen.vhd
|
20
|
37533
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_traffic_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level module of memory traffic generator which can
-- generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
-- hard memory controller core.
-- Reference:
-- Revision History: 2009 Brought out internal signals cmp_data and cmp_error as outputs.
-- 2010/01/09 Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
-- 2010/05/03 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
-- 2010/05/20 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_traffic_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
SIMULATION : STRING := "FALSE";
MEM_BURST_LEN : INTEGER := 8;
PORT_MODE : STRING := "BI_MODE";
DATA_PATTERN : STRING := "DGEN_ADDR";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
CMP_DATA_PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
NUM_DQ_PINS : INTEGER := 16;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : INTEGER := 3;
DWIDTH : INTEGER := 32;
EYE_TEST : STRING := "FALSE";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
run_traffic_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
bram_cmd_i : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
mcb_cmd_en_o : OUT STD_LOGIC;
mcb_cmd_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_cmd_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
mcb_cmd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_en_o : OUT STD_LOGIC;
mcb_wr_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_wr_data_end_o : OUT STD_LOGIC;
mcb_wr_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
mcb_wr_full_i : IN STD_LOGIC;
mcb_wr_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
mcb_rd_en_o : OUT STD_LOGIC;
mcb_rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_rd_empty_i : IN STD_LOGIC;
mcb_rd_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
counts_rst : IN STD_LOGIC;
wr_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
rd_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
error : OUT STD_LOGIC;
cmp_data_valid : OUT STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
cmp_error : out std_logic;
cmp_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
mem_rd_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END mcb_traffic_gen;
ARCHITECTURE trans OF mcb_traffic_gen IS
COMPONENT mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_gen IS
GENERIC (
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_PRBS";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END COMPONENT;
component afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component read_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
CMP_DATA_PIPE_STAGES : INTEGER := 3;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
DQ_ERROR_WIDTH : INTEGER := 1;
SEL_VICTIM_LINE : integer := 3;
MEM_COL_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
manual_clear_error : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_o : OUT STD_LOGIC;
data_valid_i : IN STD_LOGIC;
data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
last_word_rd_o : OUT STD_LOGIC;
data_error_o : OUT STD_LOGIC;
cmp_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_mdata_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_data_valid : OUT STD_LOGIC;
cmp_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error_r :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END component;
component write_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
MEM_COL_WIDTH : INTEGER := 10;
EYE_TEST : string := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
last_word_wr_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
data_wr_end_o : out std_logic
);
END component;
component tg_status IS
GENERIC (
TCQ : TIME := 100 ps;
DWIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
data_error_i : IN STD_LOGIC;
cmp_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_full_i : IN STD_LOGIC;
mcb_rd_empty_i : IN STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
error : OUT STD_LOGIC
);
END component;
attribute KEEP : STRING;
attribute MAX_FANOUT : STRING;
function MEM_BLENGTH return integer is
begin
if (MEM_BURST_LEN = 4) then
return 4;
elsif (MEM_BURST_LEN = 8) then
return 8;
else
return 8;
end if;
end function MEM_BLENGTH;
constant MEM_BLEN : INTEGER := MEM_BLENGTH;
SIGNAL mcb_wr_en : STD_LOGIC;
SIGNAL cmd2flow_valid : STD_LOGIC;
SIGNAL cmd2flow_cmd : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL cmd2flow_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd2flow_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL last_word_rd : STD_LOGIC;
SIGNAL last_word_wr : STD_LOGIC;
SIGNAL flow2cmd_rdy : STD_LOGIC;
SIGNAL wr_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rd_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL run_traffic_reg : STD_LOGIC;
SIGNAL wr_validB : STD_LOGIC;
SIGNAL wr_valid : STD_LOGIC;
SIGNAL wr_validC : STD_LOGIC;
SIGNAL bram_addr_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bram_instr_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bram_bl_i : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL addr_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL m_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL dcount_rst : STD_LOGIC;
SIGNAL rd_addr_error : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_rdy : STD_LOGIC;
SIGNAL cmp_error_int : STD_LOGIC;
SIGNAL cmd_full : STD_LOGIC;
SIGNAL cmp_data_int : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mem_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL cmp_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmp_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rst_ra : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_rb : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL mcb_wr_full_r1 : STD_LOGIC;
SIGNAL mcb_wr_full_r2 : STD_LOGIC;
SIGNAL mcb_rd_empty_r : STD_LOGIC;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL rd_buff_avail : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL data_mode_r_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_c : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tmp_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL error_access_range : STD_LOGIC ;
SIGNAL mcb_rd_empty : STD_LOGIC;
SIGNAL mcb_wr_full : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_rdy : STD_LOGIC;
SIGNAL rd_valid : STD_LOGIC;
SIGNAL cmd_rd_en : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL xhdl17 : STD_LOGIC;
SIGNAL xhdl19 : STD_LOGIC;
SIGNAL ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bram_rdy_o_xhdl0 : STD_LOGIC;
SIGNAL mcb_cmd_en_o_xhdl5 : STD_LOGIC;
SIGNAL mcb_cmd_instr_o_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL mcb_cmd_addr_o_xhdl3 : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL mcb_cmd_bl_o_xhdl4 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mcb_wr_data_o_xhdl9 : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
SIGNAL mcb_wr_mask_o_xhdl10 : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
SIGNAL mcb_rd_en : STD_LOGIC;
SIGNAL wr_data_counts_xhdl12 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL rd_data_counts_xhdl11 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL error_xhdl1 : STD_LOGIC;
SIGNAL error_status_xhdl2 : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
SIGNAL cmd_fifo_wr : STD_LOGIC;
SIGNAL xfer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fifo_error : STD_LOGIC;
SIGNAL cmd_fifo_rd : STD_LOGIC;
SIGNAL cmd_fifo_empty : STD_LOGIC;
SIGNAL xfer_cmd_bl : STD_LOGIC;
SIGNAL cmd_fifo_full : STD_LOGIC;
SIGNAL rd_mdata_afull_set : STD_LOGIC;
SIGNAL rd_mdata_fifo_afull : STD_LOGIC;
SIGNAL rdpath_data_valid_i : STD_LOGIC;
SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
SIGNAL rd_v6_mdata : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mdata_wren : STD_LOGIC;
attribute KEEP of rst_ra : signal is "TRUE";
attribute KEEP of rst_rb : signal is "TRUE";
attribute KEEP of mcb_wr_full_r1 : signal is "TRUE";
attribute KEEP of mcb_wr_full_r2 : signal is "TRUE";
attribute MAX_FANOUT of rst_ra : signal is "20";
attribute MAX_FANOUT of rst_rb : signal is "20";
BEGIN
mem_rd_data <= mem_rd_data_i;
ZEROS <= (others => '0');
cmp_data <= cmp_data_int;
cmp_error <= cmp_error_int;
-- Drive referenced outputs
bram_rdy_o <= bram_rdy_o_xhdl0;
mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
mcb_rd_en_o <= mcb_rd_en;
wr_data_counts <= wr_data_counts_xhdl12;
rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
error <= error_xhdl1;
error_status <= error_status_xhdl2;
tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
-- tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
--synthesis translate_off
PROCESS
BEGIN
IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
END IF;
WAIT;
END PROCESS;
PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
BEGIN
IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
report "Error ! Data access beyond address range"; -- severity ERROR;
error_access_range <= '1';
-- $stop();
END IF;
END PROCESS;
--synthesis translate_on
mcb_rd_empty <= mcb_rd_empty_i;
mcb_wr_full <= mcb_wr_full_i;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_r_a <= data_mode_i;
data_mode_r_b <= data_mode_i;
data_mode_r_c <= data_mode_i;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_wr_full_r1 <= '0';
ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
mcb_wr_full_r1 <= '1';
mcb_wr_full_r2 <= '1';
ELSE
mcb_wr_full_r1 <= '0';
mcb_wr_full_r2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_rd_empty_r <= '1';
ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
mcb_rd_empty_r <= '1';
ELSE
mcb_rd_empty_r <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_reg <= run_traffic_i;
END IF;
END PROCESS;
bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
dcount_rst <= counts_rst OR rst_ra(0);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
wr_data_counts_xhdl12 <= (OTHERS => '0');
ELSIF (mcb_wr_en = '1') THEN
wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
rd_data_counts_xhdl11 <= (others => '0');
ELSIF (mcb_rd_en = '1') THEN
rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
xhdl13 : IF (SIMULATION = "TRUE") GENERATE
cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_o_xhdl5 = '1') THEN
if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
fifo_error <= '1';
ELSE
fifo_error <= '0';
END IF;
END IF;
END IF;
END PROCESS;
cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
xfer_cmd_bl <= xhdl15(32);
xfer_addr <= xhdl15(31 downto 0);
cmd_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => 38,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_ra(0),
wr_en => cmd_fifo_wr,
wr_data => xhdl14,
rd_en => cmd_fifo_rd,
rd_clk => clk_i,
rd_data => xhdl15,
full => cmd_fifo_full,
almost_full => open,
empty => cmd_fifo_empty
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i;
END IF;
END PROCESS;
u_c_gen : cmd_gen
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
PORT_MODE => PORT_MODE,
MEM_BURST_LEN => MEM_BLEN,
NUM_DQ_PINS => NUM_DQ_PINS,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => ADDR_WIDTH,
DWIDTH => DWIDTH,
MEM_COL_WIDTH => MEM_COL_WIDTH,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
PRBS_SADDR_MASK_POS => PRBS_SADDR_MASK_POS,
PRBS_EADDR => PRBS_EADDR,
PRBS_SADDR => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
rd_buff_avail_i => rd_buff_avail,
reading_rd_data_i => mcb_rd_en,
force_wrcmd_gen_i => force_wrcmd_gen,
run_traffic_i => run_traffic_reg,
start_addr_i => start_addr_i,
end_addr_i => end_addr_r,
cmd_seed_i => cmd_seed_i,
data_seed_i => data_seed_i,
load_seed_i => load_seed_i,
addr_mode_i => addr_mode_i,
data_mode_i => data_mode_r_a,
instr_mode_i => instr_mode_i,
bl_mode_i => bl_mode_i,
mode_load_i => mode_load_i,
fixed_bl_i => fixed_bl_i,
fixed_addr_i => fixed_addr_i,
fixed_instr_i => fixed_instr_i,
bram_addr_i => bram_addr_i,
bram_instr_i => bram_instr_i,
bram_bl_i => bram_bl_i,
bram_valid_i => bram_valid_i,
bram_rdy_o => bram_rdy_o_xhdl0,
rdy_i => flow2cmd_rdy,
instr_o => cmd2flow_cmd,
addr_o => cmd2flow_addr,
bl_o => cmd2flow_bl,
-- m_addr_o => m_addr,
cmd_o_vld => cmd2flow_valid
);
mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
cmd_full <= mcb_cmd_full_i;
mcb_control : mcb_flow_control
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
cmd_rdy_o => flow2cmd_rdy,
cmd_valid_i => cmd2flow_valid,
cmd_i => cmd2flow_cmd,
addr_i => cmd2flow_addr,
bl_i => cmd2flow_bl,
mcb_cmd_full => cmd_full,
cmd_o => mcb_cmd_instr_o_xhdl6,
addr_o => addr_o,
bl_o => mcb_cmd_bl_o_xhdl4,
cmd_en_o => mcb_cmd_en_o_xhdl5,
last_word_wr_i => last_word_wr,
wdp_rdy_i => wr_rdy,
wdp_valid_o => wr_valid,
wdp_validB_o => wr_validB,
wdp_validC_o => wr_validC,
wr_addr_o => wr_addr,
wr_bl_o => wr_bl,
last_word_rd_i => last_word_rd,
rdp_rdy_i => rd_rdy,
rdp_valid_o => rd_valid,
rd_addr_o => rd_addr,
rd_bl_o => rd_bl
);
mdata_wren <= not mcb_rd_empty;
rd_mdata_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_rb(0),
wr_en => mdata_wren,
wr_data => mcb_rd_data_i,
rd_en => mcb_rd_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
almost_full => open,
empty => rd_mdata_fifo_empty
);
cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_rb(0) = '1') THEN
rd_mdata_afull_set <= '0';
ELSIF (rd_mdata_fifo_afull = '1') THEN
rd_mdata_afull_set <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
ELSE
rdpath_data_valid_i <= not(mcb_rd_empty);
END IF;
END PROCESS;
PROCESS(rd_v6_mdata,mcb_rd_data_i)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_rd_data_i <= rd_v6_mdata;
ELSE
rdpath_rd_data_i <= mcb_rd_data_i;
END IF;
END PROCESS;
RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl17 <= NOT(mcb_rd_empty);
read_data_path_inst : read_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
cmp_data_pipe_stages => CMP_DATA_PIPE_STAGES,
addr_width => ADDR_WIDTH,
sel_victim_line => SEL_VICTIM_LINE,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
mem_col_width => MEM_COL_WIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
manual_clear_error => manual_clear_error,
cmd_rdy_o => rd_rdy,
cmd_valid_i => rd_valid,
prbs_fseed_i => data_seed_i,
cmd_sent => mcb_cmd_instr_o_xhdl6,
bl_sent => mcb_cmd_bl_o_xhdl4,
cmd_en_i => cmd_rd_en,
data_mode_i => data_mode_r_b,
last_word_rd_o => last_word_rd,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => rd_addr,
bl_i => rd_bl,
data_rdy_o => mcb_rd_en,
data_valid_i => rdpath_data_valid_i,
data_i => rdpath_rd_data_i,
data_error_o => cmp_error_int,
cmp_data_o => cmp_data_int,
rd_mdata_o => mem_rd_data_i,
cmp_data_valid => cmp_data_valid,
cmp_addr_o => cmp_addr,
cmp_bl_o => cmp_bl,
force_wrcmd_gen_o => force_wrcmd_gen,
rd_buff_avail_o => rd_buff_avail,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
cumlative_dq_lane_error_r => cumlative_dq_lane_error
);
END GENERATE;
write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
cmp_error_int <= '0';
END GENERATE;
xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl19 <= NOT(mcb_wr_full);
write_data_path_inst : write_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
addr_width => ADDR_WIDTH,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
mem_col_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
cmd_rdy_o => wr_rdy,
cmd_valid_i => wr_valid,
cmd_validb_i => wr_validB,
cmd_validc_i => wr_validC,
prbs_fseed_i => data_seed_i,
data_mode_i => data_mode_r_c,
last_word_wr_o => last_word_wr,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => wr_addr,
bl_i => wr_bl,
data_rdy_i => xhdl19,
data_valid_o => mcb_wr_en,
data_o => mcb_wr_data_o_xhdl9,
data_mask_o => mcb_wr_mask_o_xhdl10,
data_wr_end_o => mcb_wr_data_end_o_xhdl8
-- tpt_hdata =>
);
END GENERATE;
mcb_wr_en_o <= mcb_wr_en;
tg_status_inst : tg_status
GENERIC MAP (
dwidth => DWIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra(2),
manual_clear_error => manual_clear_error,
data_error_i => cmp_error_int,
cmp_data_i => cmp_data_int,
rd_data_i => mem_rd_data_i,
cmp_addr_i => cmp_addr,
cmp_bl_i => cmp_bl,
mcb_cmd_full_i => mcb_cmd_full_i,
mcb_wr_full_i => mcb_wr_full,
mcb_rd_empty_i => mcb_rd_empty,
error_status => error_status_xhdl2,
error => error_xhdl1
);
END trans;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
|
20
|
37533
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_traffic_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level module of memory traffic generator which can
-- generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
-- hard memory controller core.
-- Reference:
-- Revision History: 2009 Brought out internal signals cmp_data and cmp_error as outputs.
-- 2010/01/09 Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
-- 2010/05/03 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
-- 2010/05/20 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_traffic_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
SIMULATION : STRING := "FALSE";
MEM_BURST_LEN : INTEGER := 8;
PORT_MODE : STRING := "BI_MODE";
DATA_PATTERN : STRING := "DGEN_ADDR";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
CMP_DATA_PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
NUM_DQ_PINS : INTEGER := 16;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : INTEGER := 3;
DWIDTH : INTEGER := 32;
EYE_TEST : STRING := "FALSE";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
run_traffic_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
bram_cmd_i : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
mcb_cmd_en_o : OUT STD_LOGIC;
mcb_cmd_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_cmd_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
mcb_cmd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_en_o : OUT STD_LOGIC;
mcb_wr_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_wr_data_end_o : OUT STD_LOGIC;
mcb_wr_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
mcb_wr_full_i : IN STD_LOGIC;
mcb_wr_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
mcb_rd_en_o : OUT STD_LOGIC;
mcb_rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_rd_empty_i : IN STD_LOGIC;
mcb_rd_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
counts_rst : IN STD_LOGIC;
wr_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
rd_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
error : OUT STD_LOGIC;
cmp_data_valid : OUT STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
cmp_error : out std_logic;
cmp_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
mem_rd_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END mcb_traffic_gen;
ARCHITECTURE trans OF mcb_traffic_gen IS
COMPONENT mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_gen IS
GENERIC (
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_PRBS";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END COMPONENT;
component afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component read_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
CMP_DATA_PIPE_STAGES : INTEGER := 3;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
DQ_ERROR_WIDTH : INTEGER := 1;
SEL_VICTIM_LINE : integer := 3;
MEM_COL_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
manual_clear_error : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_o : OUT STD_LOGIC;
data_valid_i : IN STD_LOGIC;
data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
last_word_rd_o : OUT STD_LOGIC;
data_error_o : OUT STD_LOGIC;
cmp_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_mdata_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_data_valid : OUT STD_LOGIC;
cmp_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error_r :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END component;
component write_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
MEM_COL_WIDTH : INTEGER := 10;
EYE_TEST : string := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
last_word_wr_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
data_wr_end_o : out std_logic
);
END component;
component tg_status IS
GENERIC (
TCQ : TIME := 100 ps;
DWIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
data_error_i : IN STD_LOGIC;
cmp_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_full_i : IN STD_LOGIC;
mcb_rd_empty_i : IN STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
error : OUT STD_LOGIC
);
END component;
attribute KEEP : STRING;
attribute MAX_FANOUT : STRING;
function MEM_BLENGTH return integer is
begin
if (MEM_BURST_LEN = 4) then
return 4;
elsif (MEM_BURST_LEN = 8) then
return 8;
else
return 8;
end if;
end function MEM_BLENGTH;
constant MEM_BLEN : INTEGER := MEM_BLENGTH;
SIGNAL mcb_wr_en : STD_LOGIC;
SIGNAL cmd2flow_valid : STD_LOGIC;
SIGNAL cmd2flow_cmd : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL cmd2flow_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd2flow_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL last_word_rd : STD_LOGIC;
SIGNAL last_word_wr : STD_LOGIC;
SIGNAL flow2cmd_rdy : STD_LOGIC;
SIGNAL wr_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rd_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL run_traffic_reg : STD_LOGIC;
SIGNAL wr_validB : STD_LOGIC;
SIGNAL wr_valid : STD_LOGIC;
SIGNAL wr_validC : STD_LOGIC;
SIGNAL bram_addr_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bram_instr_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bram_bl_i : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL addr_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL m_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL dcount_rst : STD_LOGIC;
SIGNAL rd_addr_error : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_rdy : STD_LOGIC;
SIGNAL cmp_error_int : STD_LOGIC;
SIGNAL cmd_full : STD_LOGIC;
SIGNAL cmp_data_int : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mem_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL cmp_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmp_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rst_ra : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_rb : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL mcb_wr_full_r1 : STD_LOGIC;
SIGNAL mcb_wr_full_r2 : STD_LOGIC;
SIGNAL mcb_rd_empty_r : STD_LOGIC;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL rd_buff_avail : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL data_mode_r_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_c : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tmp_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL error_access_range : STD_LOGIC ;
SIGNAL mcb_rd_empty : STD_LOGIC;
SIGNAL mcb_wr_full : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_rdy : STD_LOGIC;
SIGNAL rd_valid : STD_LOGIC;
SIGNAL cmd_rd_en : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL xhdl17 : STD_LOGIC;
SIGNAL xhdl19 : STD_LOGIC;
SIGNAL ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bram_rdy_o_xhdl0 : STD_LOGIC;
SIGNAL mcb_cmd_en_o_xhdl5 : STD_LOGIC;
SIGNAL mcb_cmd_instr_o_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL mcb_cmd_addr_o_xhdl3 : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL mcb_cmd_bl_o_xhdl4 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mcb_wr_data_o_xhdl9 : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
SIGNAL mcb_wr_mask_o_xhdl10 : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
SIGNAL mcb_rd_en : STD_LOGIC;
SIGNAL wr_data_counts_xhdl12 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL rd_data_counts_xhdl11 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL error_xhdl1 : STD_LOGIC;
SIGNAL error_status_xhdl2 : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
SIGNAL cmd_fifo_wr : STD_LOGIC;
SIGNAL xfer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fifo_error : STD_LOGIC;
SIGNAL cmd_fifo_rd : STD_LOGIC;
SIGNAL cmd_fifo_empty : STD_LOGIC;
SIGNAL xfer_cmd_bl : STD_LOGIC;
SIGNAL cmd_fifo_full : STD_LOGIC;
SIGNAL rd_mdata_afull_set : STD_LOGIC;
SIGNAL rd_mdata_fifo_afull : STD_LOGIC;
SIGNAL rdpath_data_valid_i : STD_LOGIC;
SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
SIGNAL rd_v6_mdata : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mdata_wren : STD_LOGIC;
attribute KEEP of rst_ra : signal is "TRUE";
attribute KEEP of rst_rb : signal is "TRUE";
attribute KEEP of mcb_wr_full_r1 : signal is "TRUE";
attribute KEEP of mcb_wr_full_r2 : signal is "TRUE";
attribute MAX_FANOUT of rst_ra : signal is "20";
attribute MAX_FANOUT of rst_rb : signal is "20";
BEGIN
mem_rd_data <= mem_rd_data_i;
ZEROS <= (others => '0');
cmp_data <= cmp_data_int;
cmp_error <= cmp_error_int;
-- Drive referenced outputs
bram_rdy_o <= bram_rdy_o_xhdl0;
mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
mcb_rd_en_o <= mcb_rd_en;
wr_data_counts <= wr_data_counts_xhdl12;
rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
error <= error_xhdl1;
error_status <= error_status_xhdl2;
tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
-- tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
--synthesis translate_off
PROCESS
BEGIN
IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
END IF;
WAIT;
END PROCESS;
PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
BEGIN
IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
report "Error ! Data access beyond address range"; -- severity ERROR;
error_access_range <= '1';
-- $stop();
END IF;
END PROCESS;
--synthesis translate_on
mcb_rd_empty <= mcb_rd_empty_i;
mcb_wr_full <= mcb_wr_full_i;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_r_a <= data_mode_i;
data_mode_r_b <= data_mode_i;
data_mode_r_c <= data_mode_i;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_wr_full_r1 <= '0';
ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
mcb_wr_full_r1 <= '1';
mcb_wr_full_r2 <= '1';
ELSE
mcb_wr_full_r1 <= '0';
mcb_wr_full_r2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_rd_empty_r <= '1';
ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
mcb_rd_empty_r <= '1';
ELSE
mcb_rd_empty_r <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_reg <= run_traffic_i;
END IF;
END PROCESS;
bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
dcount_rst <= counts_rst OR rst_ra(0);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
wr_data_counts_xhdl12 <= (OTHERS => '0');
ELSIF (mcb_wr_en = '1') THEN
wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
rd_data_counts_xhdl11 <= (others => '0');
ELSIF (mcb_rd_en = '1') THEN
rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
xhdl13 : IF (SIMULATION = "TRUE") GENERATE
cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_o_xhdl5 = '1') THEN
if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
fifo_error <= '1';
ELSE
fifo_error <= '0';
END IF;
END IF;
END IF;
END PROCESS;
cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
xfer_cmd_bl <= xhdl15(32);
xfer_addr <= xhdl15(31 downto 0);
cmd_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => 38,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_ra(0),
wr_en => cmd_fifo_wr,
wr_data => xhdl14,
rd_en => cmd_fifo_rd,
rd_clk => clk_i,
rd_data => xhdl15,
full => cmd_fifo_full,
almost_full => open,
empty => cmd_fifo_empty
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i;
END IF;
END PROCESS;
u_c_gen : cmd_gen
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
PORT_MODE => PORT_MODE,
MEM_BURST_LEN => MEM_BLEN,
NUM_DQ_PINS => NUM_DQ_PINS,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => ADDR_WIDTH,
DWIDTH => DWIDTH,
MEM_COL_WIDTH => MEM_COL_WIDTH,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
PRBS_SADDR_MASK_POS => PRBS_SADDR_MASK_POS,
PRBS_EADDR => PRBS_EADDR,
PRBS_SADDR => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
rd_buff_avail_i => rd_buff_avail,
reading_rd_data_i => mcb_rd_en,
force_wrcmd_gen_i => force_wrcmd_gen,
run_traffic_i => run_traffic_reg,
start_addr_i => start_addr_i,
end_addr_i => end_addr_r,
cmd_seed_i => cmd_seed_i,
data_seed_i => data_seed_i,
load_seed_i => load_seed_i,
addr_mode_i => addr_mode_i,
data_mode_i => data_mode_r_a,
instr_mode_i => instr_mode_i,
bl_mode_i => bl_mode_i,
mode_load_i => mode_load_i,
fixed_bl_i => fixed_bl_i,
fixed_addr_i => fixed_addr_i,
fixed_instr_i => fixed_instr_i,
bram_addr_i => bram_addr_i,
bram_instr_i => bram_instr_i,
bram_bl_i => bram_bl_i,
bram_valid_i => bram_valid_i,
bram_rdy_o => bram_rdy_o_xhdl0,
rdy_i => flow2cmd_rdy,
instr_o => cmd2flow_cmd,
addr_o => cmd2flow_addr,
bl_o => cmd2flow_bl,
-- m_addr_o => m_addr,
cmd_o_vld => cmd2flow_valid
);
mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
cmd_full <= mcb_cmd_full_i;
mcb_control : mcb_flow_control
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
cmd_rdy_o => flow2cmd_rdy,
cmd_valid_i => cmd2flow_valid,
cmd_i => cmd2flow_cmd,
addr_i => cmd2flow_addr,
bl_i => cmd2flow_bl,
mcb_cmd_full => cmd_full,
cmd_o => mcb_cmd_instr_o_xhdl6,
addr_o => addr_o,
bl_o => mcb_cmd_bl_o_xhdl4,
cmd_en_o => mcb_cmd_en_o_xhdl5,
last_word_wr_i => last_word_wr,
wdp_rdy_i => wr_rdy,
wdp_valid_o => wr_valid,
wdp_validB_o => wr_validB,
wdp_validC_o => wr_validC,
wr_addr_o => wr_addr,
wr_bl_o => wr_bl,
last_word_rd_i => last_word_rd,
rdp_rdy_i => rd_rdy,
rdp_valid_o => rd_valid,
rd_addr_o => rd_addr,
rd_bl_o => rd_bl
);
mdata_wren <= not mcb_rd_empty;
rd_mdata_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_rb(0),
wr_en => mdata_wren,
wr_data => mcb_rd_data_i,
rd_en => mcb_rd_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
almost_full => open,
empty => rd_mdata_fifo_empty
);
cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_rb(0) = '1') THEN
rd_mdata_afull_set <= '0';
ELSIF (rd_mdata_fifo_afull = '1') THEN
rd_mdata_afull_set <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
ELSE
rdpath_data_valid_i <= not(mcb_rd_empty);
END IF;
END PROCESS;
PROCESS(rd_v6_mdata,mcb_rd_data_i)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_rd_data_i <= rd_v6_mdata;
ELSE
rdpath_rd_data_i <= mcb_rd_data_i;
END IF;
END PROCESS;
RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl17 <= NOT(mcb_rd_empty);
read_data_path_inst : read_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
cmp_data_pipe_stages => CMP_DATA_PIPE_STAGES,
addr_width => ADDR_WIDTH,
sel_victim_line => SEL_VICTIM_LINE,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
mem_col_width => MEM_COL_WIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
manual_clear_error => manual_clear_error,
cmd_rdy_o => rd_rdy,
cmd_valid_i => rd_valid,
prbs_fseed_i => data_seed_i,
cmd_sent => mcb_cmd_instr_o_xhdl6,
bl_sent => mcb_cmd_bl_o_xhdl4,
cmd_en_i => cmd_rd_en,
data_mode_i => data_mode_r_b,
last_word_rd_o => last_word_rd,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => rd_addr,
bl_i => rd_bl,
data_rdy_o => mcb_rd_en,
data_valid_i => rdpath_data_valid_i,
data_i => rdpath_rd_data_i,
data_error_o => cmp_error_int,
cmp_data_o => cmp_data_int,
rd_mdata_o => mem_rd_data_i,
cmp_data_valid => cmp_data_valid,
cmp_addr_o => cmp_addr,
cmp_bl_o => cmp_bl,
force_wrcmd_gen_o => force_wrcmd_gen,
rd_buff_avail_o => rd_buff_avail,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
cumlative_dq_lane_error_r => cumlative_dq_lane_error
);
END GENERATE;
write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
cmp_error_int <= '0';
END GENERATE;
xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl19 <= NOT(mcb_wr_full);
write_data_path_inst : write_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
addr_width => ADDR_WIDTH,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
mem_col_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
cmd_rdy_o => wr_rdy,
cmd_valid_i => wr_valid,
cmd_validb_i => wr_validB,
cmd_validc_i => wr_validC,
prbs_fseed_i => data_seed_i,
data_mode_i => data_mode_r_c,
last_word_wr_o => last_word_wr,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => wr_addr,
bl_i => wr_bl,
data_rdy_i => xhdl19,
data_valid_o => mcb_wr_en,
data_o => mcb_wr_data_o_xhdl9,
data_mask_o => mcb_wr_mask_o_xhdl10,
data_wr_end_o => mcb_wr_data_end_o_xhdl8
-- tpt_hdata =>
);
END GENERATE;
mcb_wr_en_o <= mcb_wr_en;
tg_status_inst : tg_status
GENERIC MAP (
dwidth => DWIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra(2),
manual_clear_error => manual_clear_error,
data_error_i => cmp_error_int,
cmp_data_i => cmp_data_int,
rd_data_i => mem_rd_data_i,
cmp_addr_i => cmp_addr,
cmp_bl_i => cmp_bl,
mcb_cmd_full_i => mcb_cmd_full_i,
mcb_wr_full_i => mcb_wr_full,
mcb_rd_empty_i => mcb_rd_empty,
error_status => error_status_xhdl2,
error => error_xhdl1
);
END trans;
|
gpl-3.0
|
Project-Bonfire/Bonfire
|
RTL/base_line/NI.vhd
|
1
|
14622
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end; --entity NI
architecture logic of NI is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
-- this old address is put here to make it compatible with Plasma processor!
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_write_en: std_logic;
type MEM is array (0 to NI_depth-1) of std_logic_vector(31 downto 0);
signal P2N_FIFO, P2N_FIFO_in : MEM;
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO, N2P_FIFO_in : MEM;
signal N2P_Data_out : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= (others=>'0');
P2N_FIFO_write_pointer <= (others=>'0');
P2N_FIFO <= (others => (others=>'0'));
credit_counter_out <= "11";
packet_length_counter_out <= "00000000000000";
state <= IDLE;
packet_counter_out <= "00000000000000";
------------------------------------------------
N2P_FIFO <= (others => (others=>'0'));
N2P_FIFO_read_pointer <= (others=>'0');
N2P_FIFO_write_pointer <= (others=>'0');
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO <= P2N_FIFO_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO <= N2P_FIFO_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO) begin
P2N_FIFO_in <= P2N_FIFO;
P2N_FIFO_in(to_integer(unsigned(P2N_FIFO_write_pointer))) <= storage;
end process;
FIFO_Data_out <= P2N_FIFO(to_integer(unsigned(P2N_FIFO_read_pointer)));
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer +1 ;
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer +1;
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-- Process for updating full and empty signals
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer - 1 then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out)
begin
-- Some initializations
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
process(RX, N2P_FIFO_write_pointer, N2P_FIFO) begin
N2P_FIFO_in <= N2P_FIFO;
N2P_FIFO_in(to_integer(unsigned(N2P_FIFO_write_pointer))) <= RX;
end process;
N2P_Data_out <= N2P_FIFO(to_integer(unsigned(N2P_FIFO_read_pointer)));
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer + 1;
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer + 1;
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer-1 then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & "000000000000000000000000000000";
irq_out <= '0';
end; --architecture logic
|
gpl-3.0
|
cretingame/Yarr-fw
|
ip-cores/spartan6/rx_bridge_ctrl_fifo.vhd
|
2
|
10274
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_bridge_ctrl_fifo.vhd when simulating
-- the core, rx_bridge_ctrl_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_bridge_ctrl_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END rx_bridge_ctrl_fifo;
ARCHITECTURE rx_bridge_ctrl_fifo_a OF rx_bridge_ctrl_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_bridge_ctrl_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_bridge_ctrl_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 8,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 64,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 255,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 254,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 8,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 8,
c_wr_depth => 256,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 8,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_bridge_ctrl_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END rx_bridge_ctrl_fifo_a;
|
gpl-3.0
|
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/traffic_gen/v6_data_gen.vhd
|
20
|
127738
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
gpl-3.0
|
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