repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
KiwiOnChip/Projet_VHDL_-_Paint
|
01_Sources/Display_Management/Video_Memory/Tools_Memory.vhd
|
1
|
2749
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.Display_Management_pkg.all;
entity Tools_Memory is --===========================================================================
generic(
enable_debug : boolean := true;
resolution : string := "1920x1080@60Hz"
);
port(
------globally routed signals-------
Pixel_Clock : in std_logic;
Reset_n : in std_logic;
--=========== Read part ==============
-- Color of the Pixel to display
addr_read_tools_mem : in std_logic_vector(16 downto 0);
color_readed : out color_type
);
end Tools_Memory;
architecture arch_Tools_Memory of Tools_Memory is --============================================
-- ============================= Parameters ======================================================
------------ General Parameters ----------------
constant format : format_type := init_video_type(enable_debug, resolution);
constant timing : timing_type := init_timing_type(format);
-- ============================= End of the Parameters ===========================================
component tools_memory_ip_xilinx is
port (
clka : in std_logic;
addra : in std_logic_vector ( 14 downto 0 );
douta : out std_logic_vector ( 11 downto 0 )
);
end component tools_memory_ip_xilinx;
--------------------------------------------------------------
-- Signals
--------------------------------------------------------------
signal data_out_from_memory : std_logic_vector(11 downto 0) ;
signal addra : std_logic_vector(14 downto 0) ;
begin --==========================================================================================
--------------------------------------------------------------
-- Drawing_Memory : "Simple" Dual Port Memory
--------------------------------------------------------------
tools_memory_ip_xilinx_inst : component tools_memory_ip_xilinx
port map(
-- Port A : Write
clka => Pixel_Clock, -- : in std_logic; --Clock Port A
addra => addra, -- : in std_logic_vector(14 downto 0); -- Addresse of writing Port A
douta => data_out_from_memory -- : in std_logic_vector(11 downto 0); -- Data to write in Port A
);
addra <= addr_read_tools_mem(14 downto 0);
color_readed.blue <= data_out_from_memory(3 downto 0);
color_readed.green <= data_out_from_memory(7 downto 4);
color_readed.red <= data_out_from_memory(11 downto 8);
------------------
-- /!\ Stub /!\ --
------------------
-- color_readed.red <= X"A";
-- color_readed.green <= X"0";
-- color_readed.blue <= X"A";
end arch_Tools_Memory;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/inst_a_e-rtl-a.vhd
|
1
|
5453
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.5 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.5 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_1 : out std_ulogic; -- Use internally test1
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_o : out std_ulogic_vector(10 downto 3);
port_o02 : out std_ulogic_vector(10 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_ab_1 : in std_ulogic; -- Use internally test1
port_i : in std_ulogic_vector(10 downto 3);
port_i02 : in std_ulogic_vector(10 downto 1)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_2 : in std_ulogic_vector(4 downto 0); -- Bus with hole in the middle
port_3 : in std_ulogic_vector(3 downto 0) -- Bus combining o.k.
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_port_offset_01 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02b : std_ulogic_vector(1 downto 0);
signal test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal test2 : std_ulogic_vector(4 downto 0);
signal test3 : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_test1_go <= test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_1 => test1, -- Use internally test1
port_2 => test2(0), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(0), -- Bus combining o.k.
port_o => s_port_offset_01,
port_o02(1 downto 0) => s_port_offset_02b, -- __W_PORT
port_o02(10 downto 3) => s_port_offset_02 -- __W_PORT
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_2 => test2(1), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(1), -- Bus combining o.k.
port_ab_1 => test1, -- Use internally test1
port_i => s_port_offset_01,
port_i02(10 downto 3) => s_port_offset_02, -- __W_PORT
port_i02(2 downto 1) => s_port_offset_02b -- __W_PORT
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_2 => test2(3), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(2) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_2 => test2(4), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(3) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_2 => test2, -- Bus with hole in the middleNeeds input to be happy
port_3 => test3 -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/verilog/inst_bb_e-rtl-a.vhd
|
1
|
1632
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_bb_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bb_e-rtl-a.vhd,v 1.2 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_bb_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
udc: HEAD HOOK inst_bb_i
--
--
-- Start of Generated Architecture rtl of inst_bb_e
--
architecture rtl of inst_bb_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
udc: DECL HOOK VHDL inst_bb_i
begin
udc: BODY BOOK VHDL inst_bb_i
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
udc: FOOT HOOK two lines inst_bb_i
second line inst_bb_i, config here inst_bb_e_rtl_conf and description bb instance
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/inst_ac_e-rtl-a.vhd
|
1
|
1457
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_ac_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ac_e
--
architecture rtl of inst_ac_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/inst_a_e-rtl-a.vhd
|
1
|
8785
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_1_e
generic (
-- Generated Generics for Entity inst_1_e
FOO : integer -- Generic generator, value __W_NODEFAULT
-- End of Generated Generics for Entity inst_1_e
);
-- No Generated Port
end component;
-- ---------
component inst_10_e
generic (
-- Generated Generics for Entity inst_10_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_10_e
);
-- No Generated Port
end component;
-- ---------
component inst_2_e
generic (
-- Generated Generics for Entity inst_2_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_2_e
);
-- No Generated Port
end component;
-- ---------
component inst_3_e
generic (
-- Generated Generics for Entity inst_3_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_3_e
);
-- No Generated Port
end component;
-- ---------
component inst_4_e
generic (
-- Generated Generics for Entity inst_4_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_4_e
);
-- No Generated Port
end component;
-- ---------
component inst_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_6_e
generic (
-- Generated Generics for Entity inst_6_e
FOO : integer := 34 -- Generic generator
-- End of Generated Generics for Entity inst_6_e
);
-- No Generated Port
end component;
-- ---------
component inst_7_e
generic (
-- Generated Generics for Entity inst_7_e
FOO : integer := 34 -- Generic generatorGeneric generator
-- End of Generated Generics for Entity inst_7_e
);
-- No Generated Port
end component;
-- ---------
component inst_8_e
generic (
-- Generated Generics for Entity inst_8_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_8_e
);
-- No Generated Port
end component;
-- ---------
component inst_9_e
generic (
-- Generated Generics for Entity inst_9_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_9_e
);
-- No Generated Port
end component;
-- ---------
component inst_aa_e
generic (
-- Generated Generics for Entity inst_aa_e
NO_DEFAULT : string; -- Generic without default __W_NODEFAULT
NO_NAME : string; -- Parameter without Name __W_NODEFAULT
PRE_GENERIC : something := 7; -- Apply predefined generic
WIDTH : integer := 7 -- Generic width of control
-- End of Generated Generics for Entity inst_aa_e
);
-- No Generated Port
end component;
-- ---------
component inst_ab_e
generic (
-- Generated Generics for Entity inst_ab_e
FOO : integer := 64; -- Generic width for entity
WIDTH : integer -- apply generic value 31 to inst_ab __W_NODEFAULT
-- End of Generated Generics for Entity inst_ab_e
);
-- No Generated Port
end component;
-- ---------
component inst_ac_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ad_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ae_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_m_e
generic (
-- Generated Generics for Entity inst_m_e
FOO : integer := 19 -- Generic generator
-- End of Generated Generics for Entity inst_m_e
);
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_1
inst_1: inst_1_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_1
-- Generated Instance Port Map for inst_10
inst_10: inst_10_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_10
-- Generated Instance Port Map for inst_2
inst_2: inst_2_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_2
-- Generated Instance Port Map for inst_3
inst_3: inst_3_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_3
-- Generated Instance Port Map for inst_4
inst_4: inst_4_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_4
-- Generated Instance Port Map for inst_5
inst_5: inst_5_e
;
-- End of Generated Instance Port Map for inst_5
-- Generated Instance Port Map for inst_6
inst_6: inst_6_e
;
-- End of Generated Instance Port Map for inst_6
-- Generated Instance Port Map for inst_7
inst_7: inst_7_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_7
-- Generated Instance Port Map for inst_8
inst_8: inst_8_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_8
-- Generated Instance Port Map for inst_9
inst_9: inst_9_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_9
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
generic map (
NO_DEFAULT => "nodefault",
NO_NAME => "noname",
WIDTH => 15
)
;
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
generic map (
WIDTH => 31
)
;
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
;
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: inst_ad_e
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: inst_ae_e
;
-- End of Generated Instance Port Map for inst_ae
-- Generated Instance Port Map for inst_m1
inst_m1: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m1
-- Generated Instance Port Map for inst_m10
inst_m10: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m10
-- Generated Instance Port Map for inst_m2
inst_m2: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m2
-- Generated Instance Port Map for inst_m3
inst_m3: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m3
-- Generated Instance Port Map for inst_m4
inst_m4: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m4
-- Generated Instance Port Map for inst_m5
inst_m5: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m5
-- Generated Instance Port Map for inst_m6
inst_m6: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m6
-- Generated Instance Port Map for inst_m7
inst_m7: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m7
-- Generated Instance Port Map for inst_m8
inst_m8: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m8
-- Generated Instance Port Map for inst_m9
inst_m9: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m9
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/inst/inst_bb_e-e.vhd
|
1
|
1511
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_bb_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bb_e-e.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_bb_e-e.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_bb_e
--
entity inst_bb_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_bb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end inst_bb_e;
--
-- End of Generated Entity inst_bb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/constant/inst_ac_e-rtl-a.vhd
|
1
|
1485
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:02 wig Exp $
-- $Date: 2004/08/18 10:47:02 $
-- $Log: inst_ac_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:02 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ac_e
--
architecture rtl of inst_ac_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/case1.vhd
|
5
|
409
|
entity case1 is
end entity;
architecture test of case1 is
begin
process is
variable x : integer;
begin
x := 5;
wait for 1 ns;
case x is
when 1 =>
assert false;
when 5 =>
report "five!";
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_t_e-e.vhd
|
1
|
1329
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/perf/tounsigned.vhd
|
3
|
513
|
entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s <= to_unsigned(j, WIDTH);
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/ent_bb-e.vhd
|
1
|
1251
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_bb
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_bb-e.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: ent_bb-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_bb
--
entity ent_bb is
-- Generics:
-- No Generated Generics for Entity ent_bb
-- Generated Port Declaration:
-- No Generated Port for Entity ent_bb
end ent_bb;
--
-- End of Generated Entity ent_bb
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bugver/20051004c/test_e-e.vhd
|
1
|
1255
|
-- -------------------------------------------------------------
--
-- Entity Declaration for test_e
--
-- Generated
-- by: wig
-- on: Thu Oct 6 12:55:50 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: test_e-e.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $
-- $Date: 2005/10/06 13:36:57 $
-- $Log: test_e-e.vhd,v $
-- Revision 1.1 2005/10/06 13:36:57 wig
-- New testcase or generics
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity test_e
--
entity test_e is
-- Generics:
-- No Generated Generics for Entity test_e
-- Generated Port Declaration:
-- No Generated Port for Entity test_e
end test_e;
--
-- End of Generated Entity test_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/mixed/ent_ad-rtl-a.vhd
|
1
|
1473
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ad
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-a.vhd,v 1.5 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_ad-rtl-a.vhd,v $
-- Revision 1.5 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ad
--
architecture rtl of ent_ad is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/names/ioblock1_e-rtl-a.vhd
|
1
|
14821
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_io --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_disp_2
ioc_disp_2: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_2
-- Generated Instance Port Map for ioc_disp_3
ioc_disp_3: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_3
-- Generated Instance Port Map for ioc_disp_4
ioc_disp_4: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_4
-- Generated Instance Port Map for ioc_disp_5
ioc_disp_5: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_5
-- Generated Instance Port Map for ioc_disp_6
ioc_disp_6: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_6
-- Generated Instance Port Map for ioc_disp_7
ioc_disp_7: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_7
-- Generated Instance Port Map for ioc_disp_8
ioc_disp_8: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_8
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_7_e-e.vhd
|
1
|
1341
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_7_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_7_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_7_e
--
entity inst_shadow_7_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_7_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_7_e
end inst_shadow_7_e;
--
-- End of Generated Entity inst_shadow_7_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_k1_k2_e-e.vhd
|
1
|
1377
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_k1_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_k1_k2_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_k1_k2_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_k1_k2_e
--
entity inst_shadow_k1_k2_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_k1_k2_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_k1_k2_e
end inst_shadow_k1_k2_e;
--
-- End of Generated Entity inst_shadow_k1_k2_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/inst_xa_e-e.vhd
|
1
|
1514
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_xa_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-e.vhd,v 1.3 2006/01/19 08:50:40 wig Exp $
-- $Date: 2006/01/19 08:50:40 $
-- $Log: inst_xa_e-e.vhd,v $
-- Revision 1.3 2006/01/19 08:50:40 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_xa_e
--
entity inst_xa_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_xa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end inst_xa_e;
--
-- End of Generated Entity inst_xa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/ent_ab-rtl-a.vhd
|
1
|
1488
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-a.vhd,v 1.1 2006/04/10 15:42:07 wig Exp $
-- $Date: 2006/04/10 15:42:07 $
-- $Log: ent_ab-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:07 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ab
--
architecture rtl of ent_ab is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/vhdl/ent_b-e.vhd
|
1
|
1736
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_b-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_b
--
entity ent_b is
-- Generics:
-- No Generated Generics for Entity ent_b
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end ent_b;
--
-- End of Generated Entity ent_b
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/elab/genagg.vhd
|
5
|
1071
|
entity genagg_sub_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub_sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity genagg_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub is
begin
slave_i: entity work.genagg_sub_sub
generic map (
DEVA => DEVA )
port map (
clk => clk,
reset => reset );
end architecture;
-------------------------------------------------------------------------------
entity genagg is
end entity;
architecture test of genagg is
signal clk : bit := '0';
signal reset : bit := '1';
begin
uut: entity work.genagg_sub
generic map (
DEVA => "0000101" )
port map (
clk => clk,
reset => reset );
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/portlist/portlist_i_e-rtl-a.vhd
|
1
|
1464
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:52 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: portlist_i_e-rtl-a.vhd,v 1.1 2007/03/05 15:35:27 wig Exp $
-- $Date: 2007/03/05 15:35:27 $
-- $Log: portlist_i_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 15:35:27 wig
-- Changed case of filenames.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of PORTLIST_i_e
--
architecture rtl of PORTLIST_i_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/driver5.vhd
|
5
|
513
|
entity driver5 is
end entity;
architecture test of driver5 is
type int_vec is array (integer range <>) of integer;
function resolved(x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal s : rint;
begin
s <= 5;
process is
begin
assert s = 2;
wait for 0 ns;
assert s = 2;
s <= 4;
wait for 1 ns;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/vhpi3.vhd
|
3
|
225
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio2/padframe-struct-conf-c.vhd
|
1
|
2052
|
-- -------------------------------------------------------------
--
-- Generated Configuration for padframe
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:44:48 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: padframe-struct-conf-c.vhd,v 1.4 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: padframe-struct-conf-c.vhd,v $
-- Revision 1.4 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration padframe_struct_conf / padframe
--
configuration padframe_struct_conf of padframe is
for struct
-- Generated Configuration
for i_pads_en : pads_eastnord
use configuration work.pads_eastnord_struct_conf;
end for;
for i_pads_es : pads_eastsouth
use configuration work.pads_eastsouth_struct_conf;
end for;
for i_pads_ne : pads_nordeast
use configuration work.pads_nordeast_struct_conf;
end for;
for i_pads_nw : pads_nordwest
use configuration work.pads_nordwest_struct_conf;
end for;
for i_pads_se : pads_southeast
use configuration work.pads_southeast_struct_conf;
end for;
for i_pads_sw : pads_southwest
use configuration work.pads_southwest_struct_conf;
end for;
for i_pads_ws : pads_westsouth
use configuration work.pads_westsouth_struct_conf;
end for;
end for;
end padframe_struct_conf;
--
-- End of Generated Configuration padframe_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_a_e-rtl-a.vhd
|
1
|
5527
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_1 : out std_ulogic; -- Use internally test1
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_o : out std_ulogic_vector(10 downto 3);
port_o02 : out std_ulogic_vector(10 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_ab_1 : in std_ulogic; -- Use internally test1
port_i : in std_ulogic_vector(10 downto 3);
port_i02 : in std_ulogic_vector(10 downto 1)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_2 : in std_ulogic_vector(4 downto 0); -- Bus with hole in the middle
port_3 : in std_ulogic_vector(3 downto 0) -- Bus combining o.k.
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_port_offset_01 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02b : std_ulogic_vector(1 downto 0);
signal test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal test2 : std_ulogic_vector(4 downto 0);
signal test3 : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_test1_go <= test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_1 => test1, -- Use internally test1
port_2 => test2(0), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(0), -- Bus combining o.k.
port_o => s_port_offset_01,
port_o02(1 downto 0) => s_port_offset_02b, -- __W_PORT
port_o02(10 downto 3) => s_port_offset_02 -- __W_PORT
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_2 => test2(1), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(1), -- Bus combining o.k.
port_ab_1 => test1, -- Use internally test1
port_i => s_port_offset_01,
port_i02(10 downto 3) => s_port_offset_02, -- __W_PORT
port_i02(2 downto 1) => s_port_offset_02b -- __W_PORT
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_2 => test2(3), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(2) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_2 => test2(4), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(3) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_2 => test2, -- Bus with hole in the middleNeeds input to be happy
port_3 => test3 -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/arith1.vhd
|
3
|
778
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod 3 = 2;
assert 5 rem 3 = 2;
assert (-5) rem 3 = -2;
assert (-5) mod 3 = 2;
assert x = +x;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_b_e-rtl-conf-c.vhd
|
1
|
1295
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_b_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-conf-c.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_b_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_ok_7_e-e.vhd
|
1
|
1305
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ok_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_7_e-e.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_ok_7_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ok_7_e
--
entity inst_ok_7_e is
-- Generics:
-- No Generated Generics for Entity inst_ok_7_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ok_7_e
end inst_ok_7_e;
--
-- End of Generated Entity inst_ok_7_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/autoopen/noaopen/inst_t_e-rtl-a.vhd
|
1
|
2029
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
s_open_i : in std_ulogic;
s_open_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_open_i : std_ulogic;
signal s_open_o : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
s_open_i => s_open_i, -- open input
s_open_o => s_open_o -- open output
);
-- End of Generated Instance Port Map for inst_a
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/inst_a_e-e.vhd
|
1
|
1856
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
unsplice_a1 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_ok_9_e-e.vhd
|
1
|
1367
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_ok_9_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_9_e-e.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_9_e-e.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_ok_9_e
--
entity inst_shadow_ok_9_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_ok_9_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_ok_9_e
end inst_shadow_ok_9_e;
--
-- End of Generated Entity inst_shadow_ok_9_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/ioblock0_e-e.vhd
|
1
|
1961
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:20:57 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-e.vhd,v 1.4 2005/12/14 12:38:04 wig Exp $
-- $Date: 2005/12/14 12:38:04 $
-- $Log: ioblock0_e-e.vhd,v $
-- Revision 1.4 2005/12/14 12:38:04 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ioblock0_e
--
entity ioblock0_e is
-- Generics:
-- No Generated Generics for Entity ioblock0_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end ioblock0_e;
--
-- End of Generated Entity ioblock0_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/elab10.vhd
|
4
|
623
|
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab10 is
end entity;
architecture test of elab10 is
signal x : bit_vector(1 to 5);
signal y : bit_vector(6 to 10);
begin
sub1_i: entity work.sub
port map ( x );
sub2_i: entity work.sub
port map ( y );
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_e_e-e.vhd
|
1
|
3376
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_e_e
video_i : in std_ulogic_vector(3 downto 0);
widesig_i : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/verilog/inst_b_e-rtl-conf-c.vhd
|
1
|
1966
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_b_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
for inst_ba_i : inst_xa_e
use configuration work.inst_xa_e_rtl_conf;
end for;
for inst_bb_i : inst_bb_e
use configuration work.inst_bb_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_bc_i : inst_vb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_vb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_bd_i : inst_vb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_vb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_be_i : inst_be_i
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_be_i_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/func6.vhd
|
5
|
825
|
entity func6 is
end entity;
architecture test of func6 is
function flip(x : bit_vector(3 downto 0)) return bit_vector is
variable r : bit_vector(3 downto 0);
begin
r(0) := x(3);
r(1) := x(2);
r(2) := x(1);
r(3) := x(0);
return r;
end function;
function flipu(x : bit_vector) return bit_vector is
begin
return flip(x);
end function;
function flipu2(x : bit_vector) return bit_vector is
begin
return flip(x(3 downto 0));
end function;
begin
process is
variable b : bit_vector(3 downto 0);
begin
assert flip("1010") = "0101";
b := "1100";
assert flip(b) = "0011";
assert flipu(b) = "0011";
assert flipu2(b) = "0011";
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/bus/ioblock0_e-conf-c.vhd
|
1
|
1422
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-conf-c.vhd,v 1.1 2004/04/06 10:44:20 wig Exp $
-- $Date: 2004/04/06 10:44:20 $
-- $Log: ioblock0_e-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:44:20 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ioblock0_e_conf / ioblock0_e
--
configuration ioblock0_e_conf of ioblock0_e is
for rtl
-- Generated Configuration
for ioc_data_i1 : ioc_g_i
use configuration work.ioc_g_i_conf;
end for;
for ioc_data_o1 : ioc_g_o
use configuration work.ioc_g_o_conf;
end for;
end for;
end ioblock0_e_conf;
--
-- End of Generated Configuration ioblock0_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/conf/ent_a.vhd
|
1
|
11080
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_a
--
entity ent_a is
-- Generics:
-- No Generated Generics for Entity ent_a
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end ent_a;
--
-- End of Generated Entity ent_a
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa --
-- No Generated Generics
-- Generated Generics for Entity ent_aa
-- End of Generated Generics for Entity ent_aa
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic;
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab --
-- No Generated Generics
-- Generated Generics for Entity ent_ab
-- End of Generated Generics for Entity ent_ab
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic;
port_ab_2 : out std_ulogic;
sig_13 : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac --
-- No Generated Generics
-- Generated Generics for Entity ent_ac
-- End of Generated Generics for Entity ent_ac
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae --
-- No Generated Generics
-- Generated Generics for Entity ent_ae
-- End of Generated Generics for Entity ent_ae
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_a_rtl_config / ent_a
--
configuration ent_a_rtl_config of ent_a is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_aa : ent_aa
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_aa_rtl_config;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ab : ent_ab
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ab_rtl_config;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ac : ent_ac
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ac_rtl_config;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_ad : ent_ad
use configuration work.ent_ad_rtl_config;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ae : ent_ae
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ae_rtl_config;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_a_rtl_config;
--
-- End of Generated Configuration ent_a_rtl_config
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/udc/verilog/inst_b_e-e.vhd
|
1
|
1449
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/inst_aa_e-rtl-a.vhd
|
1
|
1457
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_aa_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_aa_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_aa_e
--
architecture rtl of inst_aa_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/nreset2/inst_d_e-e.vhd
|
1
|
1270
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_d_e-e.vhd,v 1.1 2004/04/06 10:50:39 wig Exp $
-- $Date: 2004/04/06 10:50:39 $
-- $Log: inst_d_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:39 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_d_e
--
entity inst_d_e is
-- Generics:
-- No Generated Generics for Entity inst_d_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_d_e
end inst_d_e;
--
-- End of Generated Entity inst_d_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/constant/inst_a_e-e.vhd
|
1
|
1263
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.3 2004/08/18 10:47:00 wig Exp $
-- $Date: 2004/08/18 10:47:00 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:00 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_a_e
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_eg_e-rtl-a.vhd
|
1
|
1492
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eg_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eg_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:12 wig Exp $
-- $Date: 2004/04/06 10:50:12 $
-- $Log: inst_eg_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:12 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eg_e
--
architecture rtl of inst_eg_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_eba_e-rtl-a.vhd
|
1
|
1497
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eba_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eba_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:00 wig Exp $
-- $Date: 2004/04/06 10:50:00 $
-- $Log: inst_eba_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:00 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eba_e
--
architecture rtl of inst_eba_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_k3_k2_e-rtl-a.vhd
|
1
|
1475
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_k3_k2_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k2_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_k3_k2_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_k3_k2_e
--
architecture rtl of inst_k3_k2_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/alias2.vhd
|
5
|
1073
|
entity alias2 is
end entity;
architecture test of alias2 is
type int_array is array (integer range <>) of integer;
function print(x : int_array) return integer is
alias y : int_array(1 to x'length) is x;
alias z : int_array(x'length downto 1) is x;
begin
report "--- X ---";
for i in x'range loop
report integer'image(x(i));
end loop;
report "--- Y ---";
for i in y'range loop
report integer'image(y(i));
end loop;
report "--- Z ---";
for i in z'range loop
report integer'image(z(i));
end loop;
return 0;
end function;
begin
process is
variable x : int_array(7 downto 4) := (1, 2, 3, 4);
variable dummy : integer;
begin
dummy := print(x);
wait;
end process;
process is
variable x : int_array(4 to 7) := (1, 2, 3, 4);
variable dummy : integer;
begin
wait for 1 ns;
dummy := print(x);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/highlow/ent_b-rtl-a.vhd
|
1
|
1917
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.3 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.3 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_k3_k2_e-c.vhd
|
1
|
1305
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k2_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_k3_k2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k3_k2_rtl_conf / inst_k3_k2_e
--
configuration inst_k3_k2_rtl_conf of inst_k3_k2_e is
for rtl
-- Generated Configuration
end for;
end inst_k3_k2_rtl_conf;
--
-- End of Generated Configuration inst_k3_k2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/constant/inst_t_e-rtl-a.vhd
|
1
|
1930
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:07 wig Exp $
-- $Date: 2004/08/18 10:47:07 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:07 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
;
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
;
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/while1.vhd
|
5
|
417
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
report integer'image(n);
n := n - 1;
end loop;
while n < 5 loop
report integer'image(n);
n := n + 1;
wait for 1 ns;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/simp/args.vhd
|
5
|
466
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/func1.vhd
|
5
|
355
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
assert r = 3 report integer'image(r);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/constant/inst_ae_e-rtl-a.vhd
|
1
|
2474
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ae_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ae_e-rtl-a.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_ae_e-rtl-a.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ae_e
--
architecture rtl of inst_ae_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aea_e
bus20040728_altop_i : in std_ulogic_vector(7 downto 0);
bus20040728_top_i : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_aea_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal bus20040728_altop : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal bus20040728_top : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
bus20040728_altop <= bus20040728_altop_i; -- __I_I_BUS_PORT
--!wig: ERROR: bus20040728_top(7 downto 4) <= p_mix_bus20040728_top_7_4_gi(3 downto 0); -- __I_I_SLICE_PORT
bus20040728_top <= p_mix_bus20040728_top_7_0_gi; -- __I_I_SLICE_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aea
inst_aea: inst_aea_e
port map (
bus20040728_altop_i => bus20040728_altop,
bus20040728_top_i => bus20040728_top
);
-- End of Generated Instance Port Map for inst_aea
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/operator3.vhd
|
5
|
934
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/agg3.vhd
|
5
|
524
|
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
variable y : integer;
begin
x := (6 => 7) & (6 => 2, 7 => 9);
assert x = (7, 2, 9);
x := get_array;
assert x = (3, 4, 5);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bugver/ramd/clkgen-struct-conf-c.vhd
|
1
|
1409
|
-- -------------------------------------------------------------
--
-- Generated Configuration for clkgen
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: clkgen-struct-conf-c.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: clkgen-struct-conf-c.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration clkgen_struct_conf / clkgen
--
configuration clkgen_struct_conf of clkgen is
for struct
-- Generated Configuration
for i_clkgen_sc : clkgen_sc
use configuration work.clkgen_sc_struct_conf;
end for;
end for;
end clkgen_struct_conf;
--
-- End of Generated Configuration clkgen_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_b_e-rtl-a.vhd
|
1
|
1487
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:17 wig Exp $
-- $Date: 2004/04/06 10:50:17 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:17 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/veriovhd/inst_m_e-rtl-a.vhd
|
1
|
1449
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_m_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_m_e-rtl-a.vhd,v 1.2 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_m_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_m_e
--
architecture rtl of inst_m_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/generic/veriovhd/inst_2_e-rtl-a.vhd
|
1
|
1449
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_2_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_2_e-rtl-a.vhd,v 1.5 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_2_e-rtl-a.vhd,v $
-- Revision 1.5 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_2_e
--
architecture rtl of inst_2_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_8_e-e.vhd
|
1
|
1341
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_8_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_8_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_8_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_8_e
--
entity inst_shadow_8_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_8_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_8_e
end inst_shadow_8_e;
--
-- End of Generated Entity inst_shadow_8_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue53.vhd
|
5
|
175
|
entity c is
port (i : in bit);
begin
assert (i = '0') report "not '0'" severity note; -- OK
assert (i = '1') report "not '1'" severity note; -- OK
end entity c;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/highlow/lownobus/ent_b-rtl-a.vhd
|
1
|
1929
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Tue Sep 27 05:17:18 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.3 2005/10/25 13:31:24 wig Exp $
-- $Date: 2005/10/25 13:31:24 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.3 2005/10/25 13:31:24 wig
-- Testcase result update
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.58 2005/09/14 14:40:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_ba --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/attr4.vhd
|
5
|
397
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/group/arrayref3.vhd
|
3
|
385
|
entity arrayref3 is
end entity;
architecture test of arrayref3 is
type ram_t is array (integer range <>) of bit_vector(3 downto 0);
signal ram : ram_t(0 to 3); -- 0..15
signal addr : integer; -- 16
begin
process (addr) is
begin
ram(addr)(1 downto 0) <= "11";
ram(addr)(3 downto 2) <= "00";
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_ec_e-rtl-a.vhd
|
1
|
4139
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eca_e
-- No Generated Generics
-- Generated Generics for Entity inst_eca_e
-- End of Generated Generics for Entity inst_eca_e
port (
-- Generated Port for Entity inst_eca_e
v_select : in std_ulogic_vector(5 downto 0); -- RequestBusinterface:RequestBus#6(VPU)
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUinterface
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecb_e
-- End of Generated Generics for Entity inst_ecb_e
port (
-- Generated Port for Entity inst_ecb_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecc_e
-- End of Generated Generics for Entity inst_ecc_e
port (
-- Generated Port for Entity inst_ecc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUInterface
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select => v_select -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/bus/a_clk-e.vhd
|
1
|
2329
|
-- -------------------------------------------------------------
--
-- Entity Declaration for a_clk
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-e.vhd,v 1.1 2004/04/06 10:44:17 wig Exp $
-- $Date: 2004/04/06 10:44:17 $
-- $Log: a_clk-e.vhd,v $
-- Revision 1.1 2004/04/06 10:44:17 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity a_clk
--
entity a_clk is
-- Generics:
-- No Generated Generics for Entity a_clk
-- Generated Port Declaration:
port(
-- Generated Port for Entity a_clk
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity a_clk
);
end a_clk;
--
-- End of Generated Entity a_clk
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/lower/func1.vhd
|
4
|
309
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/given/pad_pads_e-rtl-a.vhd
|
1
|
13174
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:54:04 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.3 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
--
-- Generated Signal List
--
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for pad_1
pad_1: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for pad_1
-- Generated Instance Port Map for pad_12
pad_12: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for pad_12
-- Generated Instance Port Map for pad_13
pad_13: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for pad_13
-- Generated Instance Port Map for pad_14
pad_14: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for pad_14
-- Generated Instance Port Map for pad_15
pad_15: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for pad_15
-- Generated Instance Port Map for pad_16
pad_16: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for pad_16
-- Generated Instance Port Map for pad_17
pad_17: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for pad_17
-- Generated Instance Port Map for pad_18
pad_18: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for pad_18
-- Generated Instance Port Map for pad_2
pad_2: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for pad_2
-- Generated Instance Port Map for pad_31
pad_31: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for pad_31
-- Generated Instance Port Map for pad_32
pad_32: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_32
-- Generated Instance Port Map for pad_33
pad_33: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for pad_33
-- Generated Instance Port Map for pad_34
pad_34: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for pad_34
-- Generated Instance Port Map for pad_35
pad_35: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for pad_35
-- Generated Instance Port Map for pad_36
pad_36: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for pad_36
-- Generated Instance Port Map for pad_37
pad_37: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_37
-- Generated Instance Port Map for pad_38
pad_38: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_38
-- Generated Instance Port Map for pad_39
pad_39: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for pad_39
-- Generated Instance Port Map for pad_40
pad_40: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for pad_40
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/ent_ac-rtl-a.vhd
|
1
|
1491
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ac-rtl-a.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_ac-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ac
--
architecture rtl of ent_ac is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/hier/auto/inst_a_e-e.vhd
|
1
|
1702
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Apr 4 05:28:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../hier.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1 2006/04/11 13:36:52 wig Exp $
-- $Date: 2006/04/11 13:36:52 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.1 2006/04/11 13:36:52 wig
-- Updated testcases: left constant/* and verilog/uamn open.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
port_a : out std_logic; -- auto_a from a to b
port_b : in std_ulogic_vector(7 downto 0); -- auto_b from c to a and b
port_c : in std_ulogic_vector(15 downto 0); -- auto_c is I
port_d : out std_ulogic_vector(31 downto 0); -- auto_d is O bus
port_e : out std_ulogic_vector(23 downto 0) -- auto_e is O bus with internal in to other module
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/typecast/intsig/inst_aa-e.vhd
|
1
|
1807
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:56:39 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: inst_aa-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa
--
entity inst_aa is
-- Generics:
-- No Generated Generics for Entity inst_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end inst_aa;
--
-- End of Generated Entity inst_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/case/inst_ac_e-e.vhd
|
1
|
1341
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ac_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-e.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_ac_e-e.vhd,v $
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ac_e
--
entity inst_ac_e is
-- Generics:
-- No Generated Generics for Entity inst_ac_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ac_e
end inst_ac_e;
--
-- End of Generated Entity inst_ac_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/const3.vhd
|
5
|
311
|
entity const3 is
end entity;
architecture test of const3 is
type bit_str_map is array (bit) of string(1 to 4);
constant const : bit_str_map := ( "zero", "one " );
begin
process is
begin
report const('0');
report const('1');
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_3_e-e.vhd
|
1
|
1341
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_3_e-e.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_shadow_3_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_3_e
--
entity inst_shadow_3_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_3_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_3_e
end inst_shadow_3_e;
--
-- End of Generated Entity inst_shadow_3_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_ok_7_e-c.vhd
|
1
|
1361
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_7_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_7_e-c.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_7_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_7_rtl_conf / inst_shadow_ok_7_e
--
configuration inst_shadow_ok_7_rtl_conf of inst_shadow_ok_7_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_7_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_7_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/verilog/vhdl/ent_aa-rtl-a.vhd
|
1
|
1515
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_aa
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_aa-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_aa
--
architecture rtl of ent_aa is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/given/pad_pads_e-conf-c.vhd
|
1
|
2749
|
-- -------------------------------------------------------------
--
-- Generated Configuration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-conf-c.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: pad_pads_e-conf-c.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration pad_pads_e_conf / pad_pads_e
--
configuration pad_pads_e_conf of pad_pads_e is
for rtl
-- Generated Configuration
for pad_1 : w_pad_i
use configuration work.w_pad_i_conf;
end for;
for pad_12 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_13 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_14 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_15 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_16 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_17 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_18 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_2 : w_pad_o
use configuration work.w_pad_o_conf;
end for;
for pad_31 : w_data2
use configuration work.w_data2_conf;
end for;
for pad_32 : w_data3
use configuration work.w_data3_conf;
end for;
for pad_33 : w_pad_i
use configuration work.w_pad_i_conf;
end for;
for pad_34 : w_pad_i
use configuration work.w_pad_i_conf;
end for;
for pad_35 : w_pad_o
use configuration work.w_pad_o_conf;
end for;
for pad_36 : w_pad_o
use configuration work.w_pad_o_conf;
end for;
for pad_37 : w_pad_dir
use configuration work.w_pad_dir_conf;
end for;
for pad_38 : w_pad_dire
use configuration work.w_pad_dire_conf;
end for;
for pad_39 : w_disp
use configuration work.w_disp_conf;
end for;
for pad_40 : w_disp
use configuration work.w_disp_conf;
end for;
end for;
end pad_pads_e_conf;
--
-- End of Generated Configuration pad_pads_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/bitsplice/connport/inst_c_e-rtl-a.vhd
|
1
|
1498
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_c_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: inst_c_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_c_e
--
architecture rtl of inst_c_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/perf/arraycase.vhd
|
5
|
1448
|
entity arraycase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of arraycase is
constant LOOPS : integer := 100;
begin
process is
variable vec : unsigned(15 downto 0) := (others => '0');
variable a, b, c, d, e, f : natural;
begin
for l in 1 to LOOPS loop
for i in 0 to integer'((2 ** 16) - 1) loop
vec := vec + X"0001";
case vec is
when X"0005" | X"ac3d" | X"9141" | X"2562" | X"0001" =>
a := a + 1;
when X"5101" | X"bbbb" | X"cccc" | X"dddd" =>
b := b + 1;
when X"0000" | X"ffff" =>
c := c + 1;
when X"2510" | X"1510" | X"babc" | X"aaad" | X"1591" =>
d := d + 1;
when X"9151" | X"abfd" | X"ab41" =>
e := e + 1;
when X"1111" | X"9150" =>
f := f + 1;
when others =>
null;
end case;
wait for 1 ns;
end loop;
end loop;
report integer'image(a) & " " & integer'image(b) & " "
& integer'image(c) & " " & integer'image(d) & " "
& integer'image(e) & " " & integer'image(f);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_ok_9_e-e.vhd
|
1
|
1305
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ok_9_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_9_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_ok_9_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ok_9_e
--
entity inst_ok_9_e is
-- Generics:
-- No Generated Generics for Entity inst_ok_9_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ok_9_e
end inst_ok_9_e;
--
-- End of Generated Entity inst_ok_9_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/universal.vhd
|
5
|
472
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/bounds5.vhd
|
5
|
350
|
entity bounds5 is
end entity;
architecture test of bounds5 is
type int_vec is array (natural range <>) of integer;
signal s : int_vec(8 downto 0);
begin
process is
variable k : integer;
begin
k := 9;
wait for 1 ns;
s(k downto 1) <= (others => 1);
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_t_e-rtl-a.vhd
|
1
|
19503
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 13:29:42 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.5 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.5 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
gensig_1 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
port_mac_b : in std_ulogic_vector(3 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
gensig_1 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : out std_ulogic_vector(7 downto 0) -- Generated signals, connecting b to a
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_k1_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port_mac : out std_ulogic; -- Macro test 0 k1_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_k1_k2_e
);
end component;
-- ---------
component inst_k1_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port_mac : out std_ulogic; -- Macro test 1 k1_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 1 k1_k4
-- End of Generated Port for Entity inst_k1_k4_e
);
end component;
-- ---------
component inst_k3_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port_mac : out std_ulogic; -- Macro test 2 k3_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 2 k3_k2
-- End of Generated Port for Entity inst_k3_k2_e
);
end component;
-- ---------
component inst_k3_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port_mac : out std_ulogic; -- Macro test 3 k3_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 3 k3_k4
-- End of Generated Port for Entity inst_k3_k4_e
);
end component;
-- ---------
component inst_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_a_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_b_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_t_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal gensig_1 : std_ulogic_vector(7 downto 0);
signal gensig_10 : std_ulogic_vector(7 downto 0);
signal gensig_2 : std_ulogic_vector(7 downto 0);
signal gensig_3 : std_ulogic_vector(7 downto 0);
signal gensig_4 : std_ulogic_vector(7 downto 0);
signal gensig_5 : std_ulogic_vector(7 downto 0);
signal gensig_6 : std_ulogic_vector(7 downto 0);
signal gensig_7 : std_ulogic_vector(7 downto 0);
signal gensig_8 : std_ulogic_vector(7 downto 0);
signal gensig_9 : std_ulogic_vector(7 downto 0);
signal macro_sigc : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9, -- Generated signals, connecting b to a
port_mac_b => macro_sigc -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9 -- Generated signals, connecting b to a
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_k1_k2
inst_k1_k2: inst_k1_k2_e
port map (
port1 => macro_sig1_k1_k2, -- Macro test 0 k1_k2
port2 => macro_sig2_k1_k2, -- Macro test 0 k1_k2
port3 => macro_sign_0, -- Macro test 0 k1_k2
port_mac => macro_sigc(0), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k2 -- Macro test 0 k1_k2
);
-- End of Generated Instance Port Map for inst_k1_k2
-- Generated Instance Port Map for inst_k1_k4
inst_k1_k4: inst_k1_k4_e
port map (
port1 => macro_sig1_k1_k4, -- Macro test 1 k1_k4
port2 => macro_sig2_k1_k4, -- Macro test 1 k1_k4
port3 => macro_sign_1, -- Macro test 1 k1_k4
port_mac => macro_sigc(1), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k4 -- Macro test 1 k1_k4
);
-- End of Generated Instance Port Map for inst_k1_k4
-- Generated Instance Port Map for inst_k3_k2
inst_k3_k2: inst_k3_k2_e
port map (
port1 => macro_sig1_k3_k2, -- Macro test 2 k3_k2
port2 => macro_sig2_k3_k2, -- Macro test 2 k3_k2
port3 => macro_sign_2, -- Macro test 2 k3_k2
port_mac => macro_sigc(2), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k2 -- Macro test 2 k3_k2
);
-- End of Generated Instance Port Map for inst_k3_k2
-- Generated Instance Port Map for inst_k3_k4
inst_k3_k4: inst_k3_k4_e
port map (
port1 => macro_sig1_k3_k4, -- Macro test 3 k3_k4
port2 => macro_sig2_k3_k4, -- Macro test 3 k3_k4
port3 => macro_sign_3, -- Macro test 3 k3_k4
port_mac => macro_sigc(3), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k4 -- Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_k3_k4
-- Generated Instance Port Map for inst_ok_1
inst_ok_1: inst_ok_1_e
;
-- End of Generated Instance Port Map for inst_ok_1
-- Generated Instance Port Map for inst_ok_10
inst_ok_10: inst_ok_10_e
;
-- End of Generated Instance Port Map for inst_ok_10
-- Generated Instance Port Map for inst_ok_2
inst_ok_2: inst_ok_2_e
;
-- End of Generated Instance Port Map for inst_ok_2
-- Generated Instance Port Map for inst_ok_3
inst_ok_3: inst_ok_3_e
;
-- End of Generated Instance Port Map for inst_ok_3
-- Generated Instance Port Map for inst_ok_4
inst_ok_4: inst_ok_4_e
;
-- End of Generated Instance Port Map for inst_ok_4
-- Generated Instance Port Map for inst_ok_5
inst_ok_5: inst_ok_5_e
;
-- End of Generated Instance Port Map for inst_ok_5
-- Generated Instance Port Map for inst_ok_6
inst_ok_6: inst_ok_6_e
;
-- End of Generated Instance Port Map for inst_ok_6
-- Generated Instance Port Map for inst_ok_7
inst_ok_7: inst_ok_7_e
;
-- End of Generated Instance Port Map for inst_ok_7
-- Generated Instance Port Map for inst_ok_8
inst_ok_8: inst_ok_8_e
;
-- End of Generated Instance Port Map for inst_ok_8
-- Generated Instance Port Map for inst_ok_9
inst_ok_9: inst_ok_9_e
;
-- End of Generated Instance Port Map for inst_ok_9
-- Generated Instance Port Map for inst_shadow_1
inst_shadow_1: inst_shadow_1_e
;
-- End of Generated Instance Port Map for inst_shadow_1
-- Generated Instance Port Map for inst_shadow_10
inst_shadow_10: inst_shadow_10_e
;
-- End of Generated Instance Port Map for inst_shadow_10
-- Generated Instance Port Map for inst_shadow_2
inst_shadow_2: inst_shadow_2_e
;
-- End of Generated Instance Port Map for inst_shadow_2
-- Generated Instance Port Map for inst_shadow_3
inst_shadow_3: inst_shadow_3_e
;
-- End of Generated Instance Port Map for inst_shadow_3
-- Generated Instance Port Map for inst_shadow_4
inst_shadow_4: inst_shadow_4_e
;
-- End of Generated Instance Port Map for inst_shadow_4
-- Generated Instance Port Map for inst_shadow_5
inst_shadow_5: inst_shadow_5_e
;
-- End of Generated Instance Port Map for inst_shadow_5
-- Generated Instance Port Map for inst_shadow_6
inst_shadow_6: inst_shadow_6_e
;
-- End of Generated Instance Port Map for inst_shadow_6
-- Generated Instance Port Map for inst_shadow_7
inst_shadow_7: inst_shadow_7_e
;
-- End of Generated Instance Port Map for inst_shadow_7
-- Generated Instance Port Map for inst_shadow_8
inst_shadow_8: inst_shadow_8_e
;
-- End of Generated Instance Port Map for inst_shadow_8
-- Generated Instance Port Map for inst_shadow_9
inst_shadow_9: inst_shadow_9_e
;
-- End of Generated Instance Port Map for inst_shadow_9
-- Generated Instance Port Map for inst_shadow_a
inst_shadow_a: inst_shadow_a_e
;
-- End of Generated Instance Port Map for inst_shadow_a
-- Generated Instance Port Map for inst_shadow_b
inst_shadow_b: inst_shadow_b_e
;
-- End of Generated Instance Port Map for inst_shadow_b
-- Generated Instance Port Map for inst_shadow_k1_k2
inst_shadow_k1_k2: inst_shadow_k1_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k2
-- Generated Instance Port Map for inst_shadow_k1_k4
inst_shadow_k1_k4: inst_shadow_k1_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k4
-- Generated Instance Port Map for inst_shadow_k3_k2
inst_shadow_k3_k2: inst_shadow_k3_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k2
-- Generated Instance Port Map for inst_shadow_k3_k4
inst_shadow_k3_k4: inst_shadow_k3_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k4
-- Generated Instance Port Map for inst_shadow_ok_1
inst_shadow_ok_1: inst_shadow_ok_1_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_1
-- Generated Instance Port Map for inst_shadow_ok_10
inst_shadow_ok_10: inst_shadow_ok_10_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_10
-- Generated Instance Port Map for inst_shadow_ok_2
inst_shadow_ok_2: inst_shadow_ok_2_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_2
-- Generated Instance Port Map for inst_shadow_ok_3
inst_shadow_ok_3: inst_shadow_ok_3_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_3
-- Generated Instance Port Map for inst_shadow_ok_4
inst_shadow_ok_4: inst_shadow_ok_4_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_4
-- Generated Instance Port Map for inst_shadow_ok_5
inst_shadow_ok_5: inst_shadow_ok_5_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_5
-- Generated Instance Port Map for inst_shadow_ok_6
inst_shadow_ok_6: inst_shadow_ok_6_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_6
-- Generated Instance Port Map for inst_shadow_ok_7
inst_shadow_ok_7: inst_shadow_ok_7_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_7
-- Generated Instance Port Map for inst_shadow_ok_8
inst_shadow_ok_8: inst_shadow_ok_8_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_8
-- Generated Instance Port Map for inst_shadow_ok_9
inst_shadow_ok_9: inst_shadow_ok_9_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_9
-- Generated Instance Port Map for inst_shadow_t
inst_shadow_t: inst_shadow_t_e
;
-- End of Generated Instance Port Map for inst_shadow_t
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_shadow_8_e-rtl-a.vhd
|
1
|
1490
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_8_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_8_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_8_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_8_e
--
architecture rtl of inst_shadow_8_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/issue185.vhd
|
5
|
1259
|
entity issue185 is
end entity;
architecture a of issue185 is
type record_t is record
field : natural;
end record;
procedure proc_rec(constant value : in record_t := (field => 0)) is
begin
report integer'image(value.field);
wait for 0 ns;
report integer'image(value.field);
end procedure;
procedure proc_integer(constant value : in integer := 0) is
begin
report integer'image(value);
wait for 0 ns;
report integer'image(value);
end procedure;
procedure proc_string(constant value : in string := "hello") is
begin
report value;
wait for 0 ns;
report value;
end procedure;
procedure proc_bit_vector(constant value : in bit_vector := "0") is
begin
report bit'image(value(0));
wait for 0 ns;
report bit'image(value(0));
end procedure;
begin
main : process
begin
report "record parameter does not work";
proc_rec;
proc_rec(value => (field => 1));
report "integer parameter works";
proc_integer;
proc_integer(value => 1);
report "string parameter works";
proc_string;
proc_string(value => "foobar");
report "bit_vector parameter works";
proc_bit_vector;
proc_bit_vector(value => "1");
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/delay1.vhd
|
5
|
1675
|
entity delay1 is
end entity;
architecture test of delay1 is
signal x, y1, y2 : bit;
begin
y1 <= transport x after 450 ps;
y2 <= reject 500 ps inertial x after 950 ps;
process is
begin
-- Test transport delay mechanism
x <= '1'; -- 0
wait for 1 ns;
assert y1 = '1'; -- 1000
x <= '0';
wait for 200 ps;
assert y1 = '1'; -- 1200
x <= '1';
wait for 100 ps;
assert y1 = '1'; -- 1300
x <= '0';
wait for 200 ps;
assert y1 = '0'; -- 1500
wait for 200 ps;
assert y1 = '1'; -- 1700
wait for 100 ps;
assert y1 = '0'; -- 1800
x <= transport '1' after 100 ps;
x <= transport '0' after 100 ps;
wait for 500 ps;
assert x = '0'; -- 2300
assert y1 = '0';
x <= transport '1' after 200 ps;
x <= transport '0' after 100 ps;
wait for 700 ps;
assert x = '0'; -- 3000
assert y1 = '0';
assert now = 3000 ps;
-- Test inertial delay mechanism
assert y2 = '0';
x <= '1';
wait for 500 ps;
x <= '0'; -- 3500
wait for 200 ps;
x <= '1'; -- 3700
wait for 300 ps;
assert y2 = '0'; -- 4000
wait for 500 ps;
assert y2 = '0'; -- 4500
wait for 200 ps;
assert y2 = '1'; -- 4700
wait;
end process;
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue188.vhd
|
3
|
1276
|
entity issue188 is
end entity;
architecture test of issue188 is
type ft is file of boolean;
function file_func return boolean is
file f : ft; -- Error
variable b : boolean;
begin
read(f, b);
return b;
end function;
impure function file_func_impure return boolean is
file f : ft; -- OK
variable b : boolean;
begin
read(f, b);
return b;
end function;
file f : ft;
function file_func2 return boolean is
variable b : boolean;
begin
read(f, b); -- Error
return b;
end function;
procedure read_b(b : out boolean) is
begin
read(f, b);
end procedure;
procedure call_read_b(b : out boolean) is
begin
read_b(b);
end procedure;
function call_call_read_b return boolean is
variable b : boolean;
begin
call_read_b(b); -- Error
return b;
end procedure;
shared variable x : integer;
procedure update_x is
begin
x := 2;
end procedure;
function call_update_x return boolean is
begin
update_x;
return true;
end procedure;
begin
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/parse/access.vhd
|
4
|
206
|
architecture a of e is
begin
process is
begin
x.all := 1;
v := x.all + 5;
p := new t;
p := a.all(1 to 3);
q := a.all(3);
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/padio/bus/ios_e-conf-c.vhd
|
1
|
1557
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ios_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-conf-c.vhd,v 1.1 2004/04/06 10:44:24 wig Exp $
-- $Date: 2004/04/06 10:44:24 $
-- $Log: ios_e-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:44:24 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ios_e_conf / ios_e
--
configuration ios_e_conf of ios_e is
for rtl
-- Generated Configuration
for ioblock_0 : ioblock0_e
use configuration work.ioblock0_e_conf;
end for;
for ioblock_1 : ioblock1_e
use configuration work.ioblock1_e_conf;
end for;
for ioblock_2 : ioblock2_e
use configuration work.ioblock2_e_conf;
end for;
for ioblock_3 : ioblock3_e
use configuration work.ioblock3_e_conf;
end for;
end for;
end ios_e_conf;
--
-- End of Generated Configuration ios_e_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/lower/signal2.vhd
|
4
|
221
|
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/open/inst_t_e-e.vhd
|
1
|
1270
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jan 27 08:21:01 2005
-- cmd: h:/work/mix_new/mix/mix_0.pl -strip -nodelta ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.2 2005/01/27 07:29:29 wig Exp $
-- $Date: 2005/01/27 07:29:29 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.2 2005/01/27 07:29:29 wig
-- reworked %OPEN% setup and testcase
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.48 2005/01/26 14:01:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/elab20.vhd
|
5
|
854
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/issue88.vhd
|
5
|
729
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
gpl-3.0
|
mitchsm/nvc
|
test/regress/elab17.vhd
|
5
|
843
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/verilog/sigport-c.vhd
|
1
|
4484
|
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: sigport-c.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: sigport-c.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_a_RTL_CONF / ent_a
--
configuration ent_a_RTL_CONF of ent_a is
for rtl
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_RTL_CONF;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_RTL_CONF;
end for;
for inst_ac : ent_ac
use configuration work.ent_ac_RTL_CONF;
end for;
for inst_ad : ent_ad
use configuration work.ent_ad_RTL_CONF;
end for;
for inst_ae : ent_ae
use configuration work.ent_ae_RTL_CONF;
end for;
end for;
end ent_a_RTL_CONF;
--
-- End of Generated Configuration ent_a_RTL_CONF
--
--
-- Start of Generated Configuration ent_aa_RTL_CONF / ent_aa
--
configuration ent_aa_RTL_CONF of ent_aa is
for rtl
-- Generated Configuration
end for;
end ent_aa_RTL_CONF;
--
-- End of Generated Configuration ent_aa_RTL_CONF
--
--
-- Start of Generated Configuration ent_ab_RTL_CONF / ent_ab
--
configuration ent_ab_RTL_CONF of ent_ab is
for rtl
-- Generated Configuration
end for;
end ent_ab_RTL_CONF;
--
-- End of Generated Configuration ent_ab_RTL_CONF
--
--
-- Start of Generated Configuration ent_ac_RTL_CONF / ent_ac
--
configuration ent_ac_RTL_CONF of ent_ac is
for rtl
-- Generated Configuration
end for;
end ent_ac_RTL_CONF;
--
-- End of Generated Configuration ent_ac_RTL_CONF
--
--
-- Start of Generated Configuration ent_ad_RTL_CONF / ent_ad
--
configuration ent_ad_RTL_CONF of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_RTL_CONF;
--
-- End of Generated Configuration ent_ad_RTL_CONF
--
--
-- Start of Generated Configuration ent_ae_RTL_CONF / ent_ae
--
configuration ent_ae_RTL_CONF of ent_ae is
for rtl
-- Generated Configuration
end for;
end ent_ae_RTL_CONF;
--
-- End of Generated Configuration ent_ae_RTL_CONF
--
--
-- Start of Generated Configuration ent_b_RTL_CONF / ent_b
--
configuration ent_b_RTL_CONF of ent_b is
for rtl
-- Generated Configuration
// __I_NO_CONFIG_VERILOG //for inst_ba : ent_ba
// __I_NO_CONFIG_VERILOG // use configuration work.ent_ba_RTL_CONF;
// __I_NO_CONFIG_VERILOG //end for;
// __I_NO_CONFIG_VERILOG //for inst_bb : ent_bb
// __I_NO_CONFIG_VERILOG // use configuration work.ent_bb_RTL_CONF;
// __I_NO_CONFIG_VERILOG //end for;
end for;
end ent_b_RTL_CONF;
--
-- End of Generated Configuration ent_b_RTL_CONF
--
--
-- Start of Generated Configuration ent_ba_RTL_CONF / ent_ba
--
configuration ent_ba_RTL_CONF of ent_ba is
for rtl
-- Generated Configuration
end for;
end ent_ba_RTL_CONF;
--
-- End of Generated Configuration ent_ba_RTL_CONF
--
--
-- Start of Generated Configuration ent_bb_RTL_CONF / ent_bb
--
configuration ent_bb_RTL_CONF of ent_bb is
for rtl
-- Generated Configuration
end for;
end ent_bb_RTL_CONF;
--
-- End of Generated Configuration ent_bb_RTL_CONF
--
--
-- Start of Generated Configuration ent_t_RTL_CONF / ent_t
--
configuration ent_t_RTL_CONF of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_RTL_CONF;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_b : ent_b
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_b_RTL_CONF;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_t_RTL_CONF;
--
-- End of Generated Configuration ent_t_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/implicit.vhd
|
4
|
576
|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
--assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/macro/inst_ok_3_e-rtl-a.vhd
|
1
|
1452
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_3_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_ok_3_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ok_3_e
--
architecture rtl of inst_ok_3_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
#
# Generated Signal List
#
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
mitchsm/nvc
|
test/sem/generics.vhd
|
4
|
2489
|
entity bot is
generic ( N : integer );
port ( o : out integer );
end entity;
architecture a of bot is
begin
process is
begin
o <= N;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
signal x : integer;
begin
bot0: entity work.bot -- OK
generic map ( N => 5 )
port map ( o => x );
bot1: entity work.bot -- OK
generic map ( 5 )
port map ( o => x );
bot3: entity work.bot -- Missing N
port map ( o => x );
bot4: entity work.bot -- Too many generics
generic map ( 1, 2 )
port map ( o => x );
end architecture;
-------------------------------------------------------------------------------
entity bad is
generic (
X : integer;
Y : integer := X + 1 ); -- X not visible
port (
p : in integer := X );
end entity;
-------------------------------------------------------------------------------
entity class is
generic (
constant X : integer; -- OK
signal Y : integer ); -- Error
end entity;
-------------------------------------------------------------------------------
package p is
component c is
generic ( X : integer ); -- OK
port ( p : in integer range 1 to X; -- OK
q : in integer range 1 to Y ); -- Error
end component;
end package;
-------------------------------------------------------------------------------
entity static is
generic ( X : integer );
end entity;
architecture a of static is
constant k : integer := X + 1;
signal s : bit_vector(1 to 3);
alias sx : bit is s(X);
alias sx1 : bit is s(X + 1);
alias sx2 : bit_vector is s(k to 3);
function f(x : bit_vector) return integer;
component c is
generic (
x : bit_vector(2 downto 0) );
end component;
component d is
generic (
t : time );
end component;
begin
i1: entity work.bot
generic map (
N => f("100") )
port map (
o => open );
i2: component c
generic map ( x => "00" & '1' ); -- OK
i3: component c
generic map ( x => "00" & sx ); -- Error
i4: component d
generic map ( t => 100 ns ); -- OK
end architecture;
|
gpl-3.0
|
blutsvente/MIX
|
test/results/configuration/cmdline/ent_t-e.vhd
|
1
|
1801
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.1 2006/03/16 14:12:15 wig Exp $
-- $Date: 2006/03/16 14:12:15 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.1 2006/03/16 14:12:15 wig
-- Added testcase for command line -conf add/overload
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding to vhdl_use_enty
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
typedef use_enty_private std_ulogic_vector;
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
blutsvente/MIX
|
test/results/sigport/ent_ab-rtl-a.vhd
|
1
|
1491
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-a.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_ab-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ab
--
architecture rtl of ent_ab is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
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