repo_name
stringlengths 6
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stringlengths 5
236
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stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/bd/block_design/ipshared/analogdeviceinc.com/axi_i2s_adi_v1_0/hdl/i2s_clkgen.vhd
|
8
|
4899
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd
|
5
|
25002
|
-------------------------------------------------------------------------------
-- axi_datamover_fifo.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_11.axi_datamover_afifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 )))
or
(C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 0 )
generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_datamover_v5_1_11.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_datamover_v5_1_11.axi_datamover_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Ainit_Rd_clk => fifo_async_rd_reset ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd
|
5
|
50564
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_11.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/ip_repo/axi_i2s_adi_1.0/hdl/adi_common/axi_ctrlif.vhd
|
7
|
5573
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ctrlif is
generic
(
C_NUM_REG : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6"
);
port
(
-- AXI bus interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
rd_addr : out integer range 0 to C_NUM_REG - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
rd_stb : in std_logic;
wr_addr : out integer range 0 to C_NUM_REG - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_ack : in std_logic;
wr_stb : out std_logic
);
end entity axi_ctrlif;
architecture Behavioral of axi_ctrlif is
type state_type is (IDLE, RESP, ACK);
signal rd_state : state_type;
signal wr_state : state_type;
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
rd_state <= IDLE;
else
case rd_state is
when IDLE =>
if S_AXI_ARVALID = '1' then
rd_state <= RESP;
rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2)));
end if;
when RESP =>
if rd_stb = '1' and S_AXI_RREADY = '1' then
rd_state <= IDLE;
end if;
when others => null;
end case;
end if;
end if;
end process;
S_AXI_ARREADY <= '1' when rd_state = IDLE else '0';
S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0';
S_AXI_RRESP <= "00";
rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0';
S_AXI_RDATA <= rd_data;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
wr_state <= IDLE;
else
case wr_state is
when IDLE =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then
wr_state <= ACK;
end if;
when ACK =>
wr_state <= RESP;
when RESP =>
if S_AXI_BREADY = '1' then
wr_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0';
wr_data <= S_AXI_WDATA;
wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2)));
S_AXI_AWREADY <= '1' when wr_state = ACK else '0';
S_AXI_WREADY <= '1' when wr_state = ACK else '0';
S_AXI_BRESP <= "00";
S_AXI_BVALID <= '1' when wr_state = RESP else '0';
end;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/bd/block_design/ip/block_design_axi_i2s_adi_0_0/sim/block_design_axi_i2s_adi_0_0.vhd
|
2
|
13502
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: analogdeviceinc.com:adi:axi_i2s_adi:1.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY adi_common_v1_00_a;
USE adi_common_v1_00_a.axi_i2s_adi;
ENTITY block_design_axi_i2s_adi_0_0 IS
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END block_design_axi_i2s_adi_0_0;
ARCHITECTURE block_design_axi_i2s_adi_0_0_arch OF block_design_axi_i2s_adi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_i2s_adi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_i2s_adi IS
GENERIC (
C_SLOT_WIDTH : INTEGER;
C_LRCLK_POL : INTEGER;
C_BCLK_POL : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_DMA_TYPE : INTEGER;
C_NUM_CH : INTEGER;
C_HAS_TX : INTEGER;
C_HAS_RX : INTEGER
);
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END COMPONENT axi_i2s_adi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_TX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_TX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_RX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_RX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
BEGIN
U0 : axi_i2s_adi
GENERIC MAP (
C_SLOT_WIDTH => 24,
C_LRCLK_POL => 0,
C_BCLK_POL => 0,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_DMA_TYPE => 1,
C_NUM_CH => 1,
C_HAS_TX => 1,
C_HAS_RX => 1
)
PORT MAP (
DATA_CLK_I => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
MUTEN_O => MUTEN_O,
S_AXIS_ACLK => '0',
S_AXIS_ARESETN => '0',
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXIS_TLAST => '0',
S_AXIS_TVALID => '0',
M_AXIS_ACLK => '0',
M_AXIS_TREADY => '0',
DMA_REQ_TX_ACLK => DMA_REQ_TX_ACLK,
DMA_REQ_TX_RSTN => DMA_REQ_TX_RSTN,
DMA_REQ_TX_DAVALID => DMA_REQ_TX_DAVALID,
DMA_REQ_TX_DATYPE => DMA_REQ_TX_DATYPE,
DMA_REQ_TX_DAREADY => DMA_REQ_TX_DAREADY,
DMA_REQ_TX_DRVALID => DMA_REQ_TX_DRVALID,
DMA_REQ_TX_DRTYPE => DMA_REQ_TX_DRTYPE,
DMA_REQ_TX_DRLAST => DMA_REQ_TX_DRLAST,
DMA_REQ_TX_DRREADY => DMA_REQ_TX_DRREADY,
DMA_REQ_RX_ACLK => DMA_REQ_RX_ACLK,
DMA_REQ_RX_RSTN => DMA_REQ_RX_RSTN,
DMA_REQ_RX_DAVALID => DMA_REQ_RX_DAVALID,
DMA_REQ_RX_DATYPE => DMA_REQ_RX_DATYPE,
DMA_REQ_RX_DAREADY => DMA_REQ_RX_DAREADY,
DMA_REQ_RX_DRVALID => DMA_REQ_RX_DRVALID,
DMA_REQ_RX_DRTYPE => DMA_REQ_RX_DRTYPE,
DMA_REQ_RX_DRLAST => DMA_REQ_RX_DRLAST,
DMA_REQ_RX_DRREADY => DMA_REQ_RX_DRREADY,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
END block_design_axi_i2s_adi_0_0_arch;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_s2mm_linebuf.vhd
|
4
|
141497
|
-------------------------------------------------------------------------------
-- axi_vdma_s2mm_linebuf
-------------------------------------------------------------------------------
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_s2mm_linebuf.vhd
-- Description: This entity encompases the line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_s2mm_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_S_AXIS_S2MM_TUSER_BITS : integer range 1 to 1 := 1;
-- Slave AXI Stream User Width for S2MM Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AF_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost full threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_USE_S2MM_FSYNC : integer range 0 to 2 := 2; --2013.1
C_USE_FSYNC : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
--
s2mm_axis_linebuf_reset_out : out std_logic ; --
--
strm_not_finished : in std_logic ; --
-- Graceful shut down control --
run_stop : in std_logic ; --
dm_halt : in std_logic ; -- CR591965
dm_halt_cmplt : in std_logic ; -- CR591965
s2mm_fsize_mismatch_err_s : in std_logic ; -- CR591965
s2mm_fsize_mismatch_err : in std_logic ; -- CR591965
--
-- Line Tracking Control --
crnt_vsize : in std_logic_vector -- CR575884
(VSIZE_DWIDTH-1 downto 0) ; -- CR575884
crnt_vsize_d2_s : out std_logic_vector -- CR575884
(VSIZE_DWIDTH-1 downto 0) ; -- CR575884
chnl_ready_external : in std_logic ; -- CR575884
s2mm_fsync_core : out std_logic ; -- CR575884
s2mm_fsync : in std_logic ; -- CR575884
s2mm_tuser_fsync_top : in std_logic ; -- CR575884
mm2s_axis_resetn : in std_logic := '1' ; --
m_axis_mm2s_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
fsync_src_select_s : out std_logic_vector(1 downto 0) ; --
drop_fsync_d_pulse_gen_fsize_less_err : out std_logic ; --
hold_dummy_tready_low : out std_logic ; --
hold_dummy_tready_low2 : out std_logic ; --
s2mm_dmasr_fsize_less_err : in std_logic ; --
no_fsync_before_vsize_sel_00_01 : in std_logic ; -- CR575884
s2mm_fsize_mismatch_err_flag : in std_logic ; -- CR575884
fsync_out_m : out std_logic ; -- CR575884
fsync_out : in std_logic ; -- CR575884
frame_sync : in std_logic ; -- CR575884
--
-- Line Buffer Threshold --
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
-- Stream In --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
s_axis_tuser : in std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0); --
capture_dm_done_vsize_counter : out std_logic_vector(12 downto 0); --
-- Stream Out --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
--
-- Fifo Status Flags --
s2mm_fifo_full : out std_logic ; --
s2mm_fifo_almost_full : out std_logic ; --
s2mm_all_lines_xfred : out std_logic ; -- CR591965
all_lasts_rcvd : out std_logic ;
s2mm_tuser_fsync : out std_logic
);
end axi_vdma_s2mm_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_s2mm_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8)*C_INCLUDE_S2MM_DRE + 1; --tkeep
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_TWO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(2,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0):= (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_wrcount : std_logic_vector(DATACOUNT_WIDTH-1 downto 0);
signal fifo_almost_full_i : std_logic := '0'; -- CR604273/CR604272
signal s_axis_tready_i : std_logic := '0';
signal s_axis_tvalid_i : std_logic := '0';
signal s_axis_tlast_i : std_logic := '0';
signal s_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal s_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tuser_i : std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0');
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal decr_vcount : std_logic := '0';
signal chnl_ready : std_logic := '0';
signal s_axis_tready_out : std_logic := '0';
signal slv2skid_s_axis_tvalid : std_logic := '0';
signal data_count_af_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_af_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_af_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal s_data_count_af_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal dm_halt_reg : std_logic := '0'; -- CR591965
signal run_stop_reg : std_logic := '0'; -- CR591965
signal s_axis_fifo_ainit : std_logic := '0';
signal s_axis_tuser_d1 : std_logic := '0';
signal tuser_fsync : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0'; -- CR623449
signal done_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR623449
signal m_axis_tlast_i : std_logic := '0'; -- CR623449
signal m_axis_tvalid_i : std_logic := '0'; -- CR623449
signal done_decr_vcount : std_logic := '0'; -- CR623449
signal p_fsync_out : std_logic := '0';
-- Added for CR626585
signal s2mm_all_lines_xfred_i : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal s2mm_axis_linebuf_reset_out_inv : std_logic := '0';
signal s2mm_tuser_fsync_sig : std_logic := '0';
signal s2mm_dmasr_fsize_less_err_d1 : std_logic := '0';
signal s2mm_dmasr_fsize_less_err_fe : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_af_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_af_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
fsync_out_m <= p_fsync_out;
s2mm_axis_linebuf_reset_out_inv <= s_axis_fifo_ainit_nosync ;
s2mm_tuser_fsync <= s2mm_tuser_fsync_sig ;
crnt_vsize_d2_s <= crnt_vsize_d2 ;
s2mm_axis_linebuf_reset_out <= not(s2mm_axis_linebuf_reset_out_inv) ;
s_axis_fifo_ainit_nosync <= '1' when (s_axis_resetn = '0')
or (dm_halt_reg = '1')
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
m_axis_fifo_ainit_nosync <= '1' when (m_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- fifo ainit in the S_AXIS clock domain
s_axis_fifo_ainit <= '1' when (s_axis_resetn = '0')
or (fsync_out = '1') -- CR591965
or (dm_halt_reg = '1') -- CR591965
else '0';
m_axis_fifo_ainit <= '1' when (m_axis_resetn = '0')
or (frame_sync = '1') -- CR623449
or (dm_halt = '1') -- CR623449
else '0'; -- CR623449
GEN_VSIZE_SNAPSHOT_LOGIC : if (C_USE_FSYNC = 1 and (C_ENABLE_DEBUG_INFO_12 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
S2MM_DMASR_BIT7_D1 : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
s2mm_dmasr_fsize_less_err_d1 <= '0';
else
s2mm_dmasr_fsize_less_err_d1 <= s2mm_dmasr_fsize_less_err;
end if;
end if;
end process S2MM_DMASR_BIT7_D1;
s2mm_dmasr_fsize_less_err_fe <= s2mm_dmasr_fsize_less_err_d1 and not s2mm_dmasr_fsize_less_err;
DM_VSIZE_AT_FSIZE_LESS_ERR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or s2mm_dmasr_fsize_less_err_fe = '1')then
capture_dm_done_vsize_counter <= (others => '0');
elsif (s2mm_fsize_mismatch_err = '1' and s2mm_dmasr_fsize_less_err = '0')then
capture_dm_done_vsize_counter <= done_vsize_counter;
end if;
end if;
end process DM_VSIZE_AT_FSIZE_LESS_ERR;
end generate GEN_VSIZE_SNAPSHOT_LOGIC;
GEN_NO_VSIZE_SNAPSHOT_LOGIC : if (C_USE_FSYNC = 0 or (C_ENABLE_DEBUG_INFO_12 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
capture_dm_done_vsize_counter <= (others => '0');
end generate GEN_NO_VSIZE_SNAPSHOT_LOGIC;
GEN_S2MM_DRE_ON : if C_INCLUDE_S2MM_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_S2MM_DRE_ON;
GEN_S2MM_DRE_OFF : if C_INCLUDE_S2MM_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_S2MM_DRE_OFF;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_FSYNC_LOGIC : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 0) generate
type STRM_WR_SM_TYPE is (STRM_WR_IDLE,
STRM_WR_START,
STRM_WR_RUNNING,
STRM_WR_LAST
);
signal strm_write_ns : STRM_WR_SM_TYPE;
signal strm_write_cs : STRM_WR_SM_TYPE;
type FIFO_RD_SM_TYPE is (FIFO_RD_IDLE,
-- FIFO_RD_START,
FIFO_RD_RUNNING,
FIFO_RD_FSYNC,
FIFO_RD_FSYNC_LAST,
FIFO_RD_LAST
);
signal fifo_read_ns : FIFO_RD_SM_TYPE;
signal fifo_read_cs : FIFO_RD_SM_TYPE;
signal load_counter : std_logic := '0';
signal load_counter_sm : std_logic := '0';
signal strm_write_pending_sm : std_logic := '0';
signal strm_write_pending : std_logic := '0';
signal fifo_rd_pending_sm : std_logic := '0';
signal fifo_rd_pending : std_logic := '0';
signal stop_tready_sm : std_logic := '0';
signal stop_tready : std_logic := '0';
signal strm_write_pending_m_axi : std_logic := '0';
signal stop_tready_s_axi : std_logic := '0';
signal dm_halt_frame : std_logic := '0';
begin
s2mm_all_lines_xfred <= s2mm_all_lines_xfred_i;
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
------ GEN_THRESHOLD_ENABLED_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
------ begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig ;
----- end generate GEN_THRESHOLD_ENABLED_NO_SOF;
-----
-----
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED;
----- GEN_MSTR_SKID_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
----- begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
---- I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
---- generic map(
---- C_WDATA_WIDTH => C_DATA_WIDTH ,
---- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
----
---- )
---- port map(
---- -- System Ports
---- ACLK => s_axis_aclk ,
---- ARST => s_axis_fifo_ainit ,
----
---- -- Shutdown control (assert for 1 clk pulse)
---- skid_stop => '0' ,
----
---- -- Slave Side (Stream Data Input)
---- S_VALID => slv2skid_s_axis_tvalid ,
---- S_READY => s_axis_tready_out ,
---- S_Data => s_axis_tdata ,
---- S_STRB => s_axis_tkeep ,
---- S_Last => s_axis_tlast ,
---- S_User => s_axis_tuser ,
----
---- -- Master Side (Stream Data Output)
---- M_VALID => s_axis_tvalid_i ,
---- M_READY => s_axis_tready_i ,
---- M_Data => s_axis_tdata_i ,
---- M_STRB => s_axis_tkeep_i ,
---- M_Last => s_axis_tlast_i ,
---- M_User => s_axis_tuser_i
---- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
----- end generate GEN_MSTR_SKID_NO_SOF;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
--s_axis_tready <= s_axis_tready_out and not chnl_fsync ;
s_axis_tready <= s_axis_tready_out and chnl_ready and
not stop_tready_s_axi ;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready and
not stop_tready_s_axi ;
-- Generate start of frame fsync
------- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
------- begin
-------
------- TUSER_RE_PROCESS : process(s_axis_aclk)
------- begin
------- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
------- if(s_axis_fifo_ainit_nosync = '1')then
------- s_axis_tuser_d1 <= '0';
------- else
------- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
------- end if;
------- end if;
------- end process TUSER_RE_PROCESS;
-------
------- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
-------
------- end generate GEN_SOF_FSYNC;
-------
------- -- Do not generate start of frame fsync
------- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
------- begin
tuser_fsync <= '0';
------- end generate GEN_NO_SOF_FSYNC;
-------
-------
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid and chnl_ready and
not stop_tready_s_axi;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
s_axis_tready_i <= m_axis_tready and chnl_ready and
not stop_tready_s_axi;
s_axis_tready_out <= m_axis_tready and chnl_ready and
not stop_tready_s_axi;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-- Generate start of frame fsync
----- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
----- begin
-----
----- TUSER_RE_PROCESS : process(s_axis_aclk)
----- begin
----- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
----- if(s_axis_fifo_ainit_nosync = '1')then
----- s_axis_tuser_d1 <= '0';
----- else
----- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
----- end if;
----- end if;
----- end process TUSER_RE_PROCESS;
-----
----- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
-----
----- end generate GEN_SOF_FSYNC;
-----
----- -- Do not generate start of frame fsync
----- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
----- begin
tuser_fsync <= '0';
----- end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_1_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_1_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
TUSER_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
-- WR_PENDING_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
-- generic map(
-- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
-- C_VECTOR_WIDTH => DATACOUNT_WIDTH
-- )
-- port map (
-- prmry_aclk => m_axis_aclk ,
-- prmry_resetn => m_axis_resetn ,
-- scndry_aclk => s_axis_aclk ,
-- scndry_resetn => s_axis_resetn ,
-- scndry_in => '0' ,
-- prmry_out => open ,
-- prmry_in => stop_tready ,
-- scndry_out => stop_tready_s_axi ,
-- scndry_vect_s_h => '0' ,
-- scndry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0),
-- prmry_vect_out => open ,
-- prmry_vect_s_h => '1' ,
-- prmry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0) ,
-- scndry_vect_out => open
-- );
--
WR_PENDING_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => stop_tready,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => stop_tready_s_axi,
scndry_vect_out => open
);
---- WR_PENDING_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => DATACOUNT_WIDTH
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => strm_write_pending ,
---- prmry_out => strm_write_pending_m_axi ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '1' ,
---- prmry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0) ,
---- scndry_vect_out => open
---- );
----
WR_PENDING_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => strm_write_pending,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => strm_write_pending_m_axi,
scndry_vect_out => open
);
--GEN_FIFO_SIDE_DM_HALT_REG_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
--begin
FIFO_SIDE_DM_HALT_REG : process(m_axis_aclk) is
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' and p_fsync_out = '0')then
dm_halt_frame <= '0';
elsif (p_fsync_out = '1') then
dm_halt_frame <= '0';
elsif (dm_halt = '1') then
dm_halt_frame <= '1';
end if;
end if;
end process FIFO_SIDE_DM_HALT_REG;
--end generate GEN_FIFO_SIDE_DM_HALT_REG_NO_SOF;
end generate GEN_FOR_ASYNC;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
dm_halt_reg <= dm_halt;
run_stop_reg <= run_stop;
dm_halt_frame <= dm_halt;
s2mm_tuser_fsync_sig <= tuser_fsync;
p_fsync_out <= fsync_out;
--s2mm_all_lines_xfred <= all_lines_xfred; -- CR591965/CR623449
s_data_count_af_thresh <= data_count_af_threshold;
strm_write_pending_m_axi <= strm_write_pending;
stop_tready_s_axi <= stop_tready;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_out = '1'
else '0';
----GEN_NO_SOF_SM : if C_S2MM_SOF_ENABLE = 0 generate
----begin
STRM_SIDE_SM: process (strm_write_cs,
fsync_out,
decr_vcount,
vsize_counter)is
begin
strm_write_pending_sm <= '0';
strm_write_ns <= strm_write_cs;
case strm_write_cs is
when STRM_WR_IDLE =>
if(fsync_out = '1') then
strm_write_ns <= STRM_WR_RUNNING;
strm_write_pending_sm <= '1';
end if;
when STRM_WR_RUNNING =>
if (decr_vcount = '1' and
vsize_counter = VSIZE_ONE_VALUE) then
strm_write_ns <= STRM_WR_IDLE;
strm_write_pending_sm <= '0';
elsif (decr_vcount = '1' and
vsize_counter = VSIZE_TWO_VALUE) then
strm_write_ns <= STRM_WR_LAST;
end if;
strm_write_pending_sm <= '1';
when STRM_WR_LAST =>
if (decr_vcount = '1' ) then
strm_write_ns <= STRM_WR_IDLE;
strm_write_pending_sm <= '0';
end if;
strm_write_pending_sm <= '1';
-- coverage off
when others =>
strm_write_ns <= STRM_WR_IDLE;
-- coverage on
end case;
end process STRM_SIDE_SM;
STRM_SIDE_SM_REG : process(s_axis_aclk) is
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1' and fsync_out = '0')then
strm_write_cs <= STRM_WR_IDLE;
strm_write_pending <= '0';
else
strm_write_cs <= strm_write_ns;
strm_write_pending <= strm_write_pending_sm;
end if;
end if;
end process STRM_SIDE_SM_REG;
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
chnl_ready <= '1';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
chnl_ready <= '1';
end if;
end if;
end process VERT_COUNTER;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
elsif(load_counter = '1')then
done_vsize_counter <= crnt_vsize;
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
end if;
end if;
end process DONE_VERT_COUNTER;
FIFO_SIDE_SM: process (fifo_read_cs,
done_decr_vcount,
p_fsync_out,
done_vsize_counter,
strm_write_pending_m_axi,
crnt_vsize)is
begin
fifo_read_ns <= fifo_read_cs;
load_counter_sm <= '0';
fifo_rd_pending_sm <= '0';
stop_tready_sm <= '0';
case fifo_read_cs is
when FIFO_RD_IDLE =>
if(p_fsync_out = '1') then
fifo_rd_pending_sm <= '1';
load_counter_sm <= '1';
if (crnt_vsize = VSIZE_ONE_VALUE) then
fifo_read_ns <= FIFO_RD_LAST;
else
fifo_read_ns <= FIFO_RD_RUNNING;
end if;
end if;
when FIFO_RD_RUNNING =>
if (p_fsync_out = '1') then
if (strm_write_pending_m_axi = '0') then
stop_tready_sm <= '1';
end if;
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_ONE_VALUE) then
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
else
fifo_read_ns <= FIFO_RD_FSYNC;
end if;
else
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_TWO_VALUE) then
fifo_read_ns <= FIFO_RD_LAST;
end if;
end if;
fifo_rd_pending_sm <= '1';
when FIFO_RD_FSYNC =>
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_TWO_VALUE) then
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
end if;
fifo_rd_pending_sm <= '1';
stop_tready_sm <= '1';
when FIFO_RD_FSYNC_LAST =>
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_RUNNING;
load_counter_sm <= '1';
stop_tready_sm <= '0';
end if;
fifo_rd_pending_sm <= '1';
stop_tready_sm <= '1';
when FIFO_RD_LAST =>
if (p_fsync_out = '1') then
if (strm_write_pending_m_axi = '0') then
stop_tready_sm <= '1';
end if;
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_RUNNING;
load_counter_sm <= '1';
else
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
end if;
else
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_IDLE;
fifo_rd_pending_sm <= '0';
end if;
end if;
fifo_rd_pending_sm <= '1';
-- coverage off
when others =>
fifo_read_ns <= FIFO_RD_IDLE;
-- coverage on
end case;
end process FIFO_SIDE_SM;
FIFO_SIDE_SM_REG : process(m_axis_aclk) is
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0' ) or
dm_halt_frame = '1')then
fifo_read_cs <= FIFO_RD_IDLE;
load_counter <= '0';
fifo_rd_pending <= '0';
stop_tready <= '0';
else
fifo_read_cs <= fifo_read_ns;
load_counter <= load_counter_sm;
fifo_rd_pending <= fifo_rd_pending_sm;
stop_tready <= stop_tready_sm;
end if;
end if;
end process FIFO_SIDE_SM_REG;
DONE_XFER_SIG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0')then
s2mm_all_lines_xfred_i <= '1';
elsif(load_counter = '1' )then
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_XFER_SIG;
----end generate GEN_NO_SOF_SM;
all_lasts_rcvd <= not strm_write_pending_m_axi;
s2mm_fsync_core <= s2mm_fsync;
fsync_src_select_s <= (others => '0');
drop_fsync_d_pulse_gen_fsize_less_err <= '0';
hold_dummy_tready_low <= '0';
hold_dummy_tready_low2 <= '0';
end generate GEN_FSYNC_LOGIC;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_NO_FSYNC_LOGIC : if ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
--*****************************************************************************--
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
----
---- GEN_SYNC_FIFO_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
---- end generate GEN_SYNC_FIFO_NO_SOF;
----
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
----
---- GEN_ASYNC_FIFO_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
----
LB_BRAM : if ((C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
---- end generate GEN_ASYNC_FIFO_NO_SOF;
----
----
----
end generate GEN_ASYNC_FIFO;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Generate start of frame fsync
GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
begin
TUSER_RE_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1')then
s_axis_tuser_d1 <= '0';
else
s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
end if;
end if;
end process TUSER_RE_PROCESS;
tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
end generate GEN_SOF_FSYNC;
-- Do not generate start of frame fsync
GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
begin
tuser_fsync <= '0';
end generate GEN_NO_SOF_FSYNC;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
---- GEN_THRESHOLD_ENABLED_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig;
---- end generate GEN_THRESHOLD_ENABLED_NO_SOF;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED;
---- GEN_MSTR_SKID_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
---- I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
---- generic map(
---- C_WDATA_WIDTH => C_DATA_WIDTH ,
---- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
---- )
---- port map(
---- -- System Ports
---- ACLK => s_axis_aclk ,
---- ARST => s_axis_fifo_ainit ,
---- -- Shutdown control (assert for 1 clk pulse)
---- skid_stop => '0' ,
---- -- Slave Side (Stream Data Input)
---- S_VALID => slv2skid_s_axis_tvalid ,
---- S_READY => s_axis_tready_out ,
---- S_Data => s_axis_tdata ,
---- S_STRB => s_axis_tkeep ,
---- S_Last => s_axis_tlast ,
---- S_User => s_axis_tuser ,
---- -- Master Side (Stream Data Output)
---- M_VALID => s_axis_tvalid_i ,
---- M_READY => s_axis_tready_i ,
---- M_Data => s_axis_tdata_i ,
---- M_STRB => s_axis_tkeep_i ,
---- M_Last => s_axis_tlast_i ,
---- M_User => s_axis_tuser_i
---- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
s_axis_tready <= s_axis_tready_out and chnl_ready;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid and chnl_ready;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
s_axis_tready_i <= m_axis_tready and chnl_ready;
s_axis_tready_out <= m_axis_tready and chnl_ready;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-- Generate start of frame fsync
GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
begin
TUSER_RE_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1')then
s_axis_tuser_d1 <= '0';
else
s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
end if;
end if;
end process TUSER_RE_PROCESS;
tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
end generate GEN_SOF_FSYNC;
-- Do not generate start of frame fsync
GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
begin
tuser_fsync <= '0';
end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_0_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_0_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
TUSER_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
dm_halt_reg <= dm_halt;
run_stop_reg <= run_stop;
p_fsync_out <= fsync_out;
s2mm_tuser_fsync_sig <= tuser_fsync;
s_data_count_af_thresh <= data_count_af_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Generate vertical size counter for case when SOF not used
GEN_NO_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 0 generate
begin
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_out = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
chnl_ready <= '1';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
chnl_ready <= '1';
end if;
end if;
end process VERT_COUNTER;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_VERT_COUNTER;
end generate GEN_NO_SOF_VCOUNT;
----
----
----
------ Generate vertical size counter for case when SOF is used
GEN_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 1 generate
begin
chnl_ready <= run_stop_reg;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_VERT_COUNTER;
end generate GEN_SOF_VCOUNT;
s2mm_all_lines_xfred <= s2mm_all_lines_xfred_i;
all_lasts_rcvd <= s2mm_all_lines_xfred_i;
s2mm_fsync_core <= s2mm_fsync;
fsync_src_select_s <= (others => '0');
drop_fsync_d_pulse_gen_fsize_less_err <= '0';
hold_dummy_tready_low <= '0';
hold_dummy_tready_low2 <= '0';
end generate GEN_NO_FSYNC_LOGIC;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_S2MM_FLUSH_SOF_LOGIC : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 1) generate
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal mmap_not_finished : std_logic := '0';
signal mmap_not_finished_s : std_logic := '0';
signal mm2s_fsync_s2mm_s : std_logic := '0';
signal s2mm_fsync_int : std_logic := '0';
signal s2mm_fsync_d_pulse : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done_flag : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done_flag_d1 : std_logic := '0';
signal sig_drop_fsync_d_pulse_gen_fsize_less_err : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER_FLUSH_SOF : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO_FLUSH_SOF;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ((C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ((C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO_FLUSH_SOF;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED_FLUSH_SOF : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig;
end generate GEN_THRESHOLD_ENABLED_FLUSH_SOF;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED_FLUSH_SOF : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED_FLUSH_SOF;
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
-- I_MSTR_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_DATA_WIDTH ,
-- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
-- )
-- port map(
-- -- System Ports
-- ACLK => s_axis_aclk ,
-- ARST => s_axis_fifo_ainit ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => '0' ,
--
-- -- Slave Side (Stream Data Input)
-- S_VALID => slv2skid_s_axis_tvalid ,
-- S_READY => s_axis_tready_out ,
-- S_Data => s_axis_tdata ,
-- S_STRB => s_axis_tkeep ,
-- S_Last => s_axis_tlast ,
-- S_User => s_axis_tuser ,
--
-- -- Master Side (Stream Data Output)
-- M_VALID => s_axis_tvalid_i ,
-- M_READY => s_axis_tready_i ,
-- M_Data => s_axis_tdata_i ,
-- M_STRB => s_axis_tkeep_i ,
-- M_Last => s_axis_tlast_i ,
-- M_User => s_axis_tuser_i
-- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
--------s_axis_tready <= s_axis_tready_out and chnl_ready_external;
s_axis_tready <= s_axis_tready_out ;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
------slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready_external;
slv2skid_s_axis_tvalid <= s_axis_tvalid ;
end generate GEN_LINEBUFFER_FLUSH_SOF;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER_FLUSH_SOF : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid;
--------------------m_axis_tvalid_i <= s_axis_tvalid and chnl_ready_external;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
----------s_axis_tready_i <= m_axis_tready and chnl_ready_external;
s_axis_tready_i <= m_axis_tready;
---------s_axis_tready_out <= m_axis_tready and chnl_ready_external;
s_axis_tready_out <= m_axis_tready;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-------------------------- -- Generate start of frame fsync
-------------------------- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
-------------------------- begin
--------------------------
-------------------------- TUSER_RE_PROCESS : process(s_axis_aclk)
-------------------------- begin
-------------------------- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
-------------------------- if(s_axis_fifo_ainit_nosync = '1')then
-------------------------- s_axis_tuser_d1 <= '0';
-------------------------- else
-------------------------- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
-------------------------- end if;
-------------------------- end if;
-------------------------- end process TUSER_RE_PROCESS;
--------------------------
-------------------------- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
--------------------------
-------------------------- end generate GEN_SOF_FSYNC;
--------------------------
-------------------------- -- Do not generate start of frame fsync
-------------------------- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
-------------------------- begin
-------------------------- tuser_fsync <= '0';
-------------------------- end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER_FLUSH_SOF;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
TUSER_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
---- MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => mmap_not_finished ,
---- scndry_out => mmap_not_finished_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => mmap_not_finished,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mmap_not_finished_s,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
GEN_FOR_ASYNC_CROSS_FSYNC : if C_INCLUDE_MM2S = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_mm2s_aclk ,
---- prmry_resetn => mm2s_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => mm2s_fsync ,
---- scndry_out => mm2s_fsync_s2mm_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_mm2s_aclk,
prmry_resetn => mm2s_axis_resetn,
prmry_in => mm2s_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fsync_s2mm_s,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC_CROSS_FSYNC;
GEN_FOR_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_fsync_s2mm_s <= '0';
end generate GEN_FOR_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC_FLUSH_SOF;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
mmap_not_finished_s <= mmap_not_finished;
fsync_src_select_s_int <= fsync_src_select;
dm_halt_reg <= dm_halt;
--dm_halt_cmplt_s <= dm_halt_cmplt;
run_stop_reg <= run_stop;
p_fsync_out <= fsync_out;
s2mm_tuser_fsync_sig <= tuser_fsync;
s_data_count_af_thresh <= data_count_af_threshold;
GEN_FOR_SYNC_CROSS_FSYNC : if C_INCLUDE_MM2S = 1 generate
begin
mm2s_fsync_s2mm_s <= mm2s_fsync;
end generate GEN_FOR_SYNC_CROSS_FSYNC;
GEN_FOR_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_fsync_s2mm_s <= '0';
end generate GEN_FOR_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC_FLUSH_SOF;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-----------------------GEN_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 1 generate
-----------------------begin
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER_FLUSH_SOF : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and p_fsync_out = '0') or s2mm_fsize_mismatch_err_flag = '1')then
done_vsize_counter <= (others => '0');
mmap_not_finished <= '0';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
mmap_not_finished <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
mmap_not_finished <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
mmap_not_finished <= '1';
end if;
end if;
end process DONE_VERT_COUNTER_FLUSH_SOF;
delay_s2mm_fsync_core_till_mmap_done <= '1' when mmap_not_finished_s = '1' and strm_not_finished = '0' and s2mm_fsync_int = '1' and delay_s2mm_fsync_core_till_mmap_done_flag = '0'
else '0';
hold_dummy_tready_low <= delay_s2mm_fsync_core_till_mmap_done or delay_s2mm_fsync_core_till_mmap_done_flag;
HOLD_DELAY_FSYNC_IN_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or mmap_not_finished_s = '0' or sig_drop_fsync_d_pulse_gen_fsize_less_err = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag <= '0';
elsif(delay_s2mm_fsync_core_till_mmap_done = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag <= '1';
end if;
end if;
end process HOLD_DELAY_FSYNC_IN_FLAG;
D1_HOLD_DELAY_FSYNC_IN_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or sig_drop_fsync_d_pulse_gen_fsize_less_err = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag_d1 <= '0';
else
delay_s2mm_fsync_core_till_mmap_done_flag_d1 <= delay_s2mm_fsync_core_till_mmap_done_flag;
end if;
end if;
end process D1_HOLD_DELAY_FSYNC_IN_FLAG;
s2mm_fsync_d_pulse <= delay_s2mm_fsync_core_till_mmap_done_flag_d1 and (not delay_s2mm_fsync_core_till_mmap_done_flag) ;
s2mm_fsync_core <= (s2mm_fsync_int and not (delay_s2mm_fsync_core_till_mmap_done) and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or s2mm_fsync_d_pulse or d_fsync_halt_cmplt_s;
sig_drop_fsync_d_pulse_gen_fsize_less_err <= '1' when delay_s2mm_fsync_core_till_mmap_done_flag = '1' and s2mm_fsync_int = '1'
else '0';
GEN_FOR_C_USE_S2MM_FSYNC_1 : if C_USE_S2MM_FSYNC = 1 generate
begin
s2mm_fsync_int <= s2mm_fsync and run_stop_reg and no_fsync_before_vsize_sel_00_01;
end generate GEN_FOR_C_USE_S2MM_FSYNC_1;
GEN_FOR_C_USE_S2MM_FSYNC_2 : if C_USE_S2MM_FSYNC = 2 generate
begin
s2mm_fsync_int <= s2mm_tuser_fsync_top and run_stop_reg;
end generate GEN_FOR_C_USE_S2MM_FSYNC_2;
-- Frame sync cross bar
------ FSYNC_CROSSBAR_S2MM_S : process(fsync_src_select_s_int,
------ run_stop_reg,
------ s2mm_fsync,
------ mm2s_fsync_s2mm_s, no_fsync_before_vsize_sel_00_01,
------ s2mm_tuser_fsync_top)
------ begin
------ case fsync_src_select_s_int is
------
------ when "00" => -- primary fsync (default)
------ s2mm_fsync_int <= s2mm_fsync and run_stop_reg and no_fsync_before_vsize_sel_00_01;
------ when "01" => -- other channel fsync
------ s2mm_fsync_int <= mm2s_fsync_s2mm_s and run_stop_reg and no_fsync_before_vsize_sel_00_01;
------ when "10" => -- s2mm_tuser_fsync_top fsync (used only by s2mm)
------ s2mm_fsync_int <= s2mm_tuser_fsync_top and run_stop_reg;
------ when others =>
------ s2mm_fsync_int <= '0';
------ end case;
------ end process FSYNC_CROSSBAR_S2MM_S;
------
-----------------------end generate GEN_SOF_VCOUNT;
S2MM_FSIZE_ERR_TO_DM_HALT_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process S2MM_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= s2mm_fsize_mismatch_err_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and s2mm_fsync_int = '1'
else '0';
FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process FSIZE_LESS_DM_HALT_CMPLT_FLAG;
REG_D_FSYNC : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
hold_dummy_tready_low2 <= delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s or delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
s2mm_all_lines_xfred <= '0';
all_lasts_rcvd <= '0';
tuser_fsync <= '0';
fsync_src_select_s <= fsync_src_select_s_int;
drop_fsync_d_pulse_gen_fsize_less_err <= sig_drop_fsync_d_pulse_gen_fsize_less_err;
end generate GEN_S2MM_FLUSH_SOF_LOGIC;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_s2mm_linebuf.vhd
|
4
|
141497
|
-------------------------------------------------------------------------------
-- axi_vdma_s2mm_linebuf
-------------------------------------------------------------------------------
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_s2mm_linebuf.vhd
-- Description: This entity encompases the line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_s2mm_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_S_AXIS_S2MM_TUSER_BITS : integer range 1 to 1 := 1;
-- Slave AXI Stream User Width for S2MM Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AF_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost full threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_USE_S2MM_FSYNC : integer range 0 to 2 := 2; --2013.1
C_USE_FSYNC : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
--
s2mm_axis_linebuf_reset_out : out std_logic ; --
--
strm_not_finished : in std_logic ; --
-- Graceful shut down control --
run_stop : in std_logic ; --
dm_halt : in std_logic ; -- CR591965
dm_halt_cmplt : in std_logic ; -- CR591965
s2mm_fsize_mismatch_err_s : in std_logic ; -- CR591965
s2mm_fsize_mismatch_err : in std_logic ; -- CR591965
--
-- Line Tracking Control --
crnt_vsize : in std_logic_vector -- CR575884
(VSIZE_DWIDTH-1 downto 0) ; -- CR575884
crnt_vsize_d2_s : out std_logic_vector -- CR575884
(VSIZE_DWIDTH-1 downto 0) ; -- CR575884
chnl_ready_external : in std_logic ; -- CR575884
s2mm_fsync_core : out std_logic ; -- CR575884
s2mm_fsync : in std_logic ; -- CR575884
s2mm_tuser_fsync_top : in std_logic ; -- CR575884
mm2s_axis_resetn : in std_logic := '1' ; --
m_axis_mm2s_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
fsync_src_select_s : out std_logic_vector(1 downto 0) ; --
drop_fsync_d_pulse_gen_fsize_less_err : out std_logic ; --
hold_dummy_tready_low : out std_logic ; --
hold_dummy_tready_low2 : out std_logic ; --
s2mm_dmasr_fsize_less_err : in std_logic ; --
no_fsync_before_vsize_sel_00_01 : in std_logic ; -- CR575884
s2mm_fsize_mismatch_err_flag : in std_logic ; -- CR575884
fsync_out_m : out std_logic ; -- CR575884
fsync_out : in std_logic ; -- CR575884
frame_sync : in std_logic ; -- CR575884
--
-- Line Buffer Threshold --
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
-- Stream In --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
s_axis_tuser : in std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0); --
capture_dm_done_vsize_counter : out std_logic_vector(12 downto 0); --
-- Stream Out --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
--
-- Fifo Status Flags --
s2mm_fifo_full : out std_logic ; --
s2mm_fifo_almost_full : out std_logic ; --
s2mm_all_lines_xfred : out std_logic ; -- CR591965
all_lasts_rcvd : out std_logic ;
s2mm_tuser_fsync : out std_logic
);
end axi_vdma_s2mm_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_s2mm_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8)*C_INCLUDE_S2MM_DRE + 1; --tkeep
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_TWO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(2,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0):= (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_wrcount : std_logic_vector(DATACOUNT_WIDTH-1 downto 0);
signal fifo_almost_full_i : std_logic := '0'; -- CR604273/CR604272
signal s_axis_tready_i : std_logic := '0';
signal s_axis_tvalid_i : std_logic := '0';
signal s_axis_tlast_i : std_logic := '0';
signal s_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal s_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tuser_i : std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0');
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal decr_vcount : std_logic := '0';
signal chnl_ready : std_logic := '0';
signal s_axis_tready_out : std_logic := '0';
signal slv2skid_s_axis_tvalid : std_logic := '0';
signal data_count_af_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_af_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_af_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal s_data_count_af_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal dm_halt_reg : std_logic := '0'; -- CR591965
signal run_stop_reg : std_logic := '0'; -- CR591965
signal s_axis_fifo_ainit : std_logic := '0';
signal s_axis_tuser_d1 : std_logic := '0';
signal tuser_fsync : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0'; -- CR623449
signal done_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR623449
signal m_axis_tlast_i : std_logic := '0'; -- CR623449
signal m_axis_tvalid_i : std_logic := '0'; -- CR623449
signal done_decr_vcount : std_logic := '0'; -- CR623449
signal p_fsync_out : std_logic := '0';
-- Added for CR626585
signal s2mm_all_lines_xfred_i : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal s2mm_axis_linebuf_reset_out_inv : std_logic := '0';
signal s2mm_tuser_fsync_sig : std_logic := '0';
signal s2mm_dmasr_fsize_less_err_d1 : std_logic := '0';
signal s2mm_dmasr_fsize_less_err_fe : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_af_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_af_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
fsync_out_m <= p_fsync_out;
s2mm_axis_linebuf_reset_out_inv <= s_axis_fifo_ainit_nosync ;
s2mm_tuser_fsync <= s2mm_tuser_fsync_sig ;
crnt_vsize_d2_s <= crnt_vsize_d2 ;
s2mm_axis_linebuf_reset_out <= not(s2mm_axis_linebuf_reset_out_inv) ;
s_axis_fifo_ainit_nosync <= '1' when (s_axis_resetn = '0')
or (dm_halt_reg = '1')
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
m_axis_fifo_ainit_nosync <= '1' when (m_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- fifo ainit in the S_AXIS clock domain
s_axis_fifo_ainit <= '1' when (s_axis_resetn = '0')
or (fsync_out = '1') -- CR591965
or (dm_halt_reg = '1') -- CR591965
else '0';
m_axis_fifo_ainit <= '1' when (m_axis_resetn = '0')
or (frame_sync = '1') -- CR623449
or (dm_halt = '1') -- CR623449
else '0'; -- CR623449
GEN_VSIZE_SNAPSHOT_LOGIC : if (C_USE_FSYNC = 1 and (C_ENABLE_DEBUG_INFO_12 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
S2MM_DMASR_BIT7_D1 : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
s2mm_dmasr_fsize_less_err_d1 <= '0';
else
s2mm_dmasr_fsize_less_err_d1 <= s2mm_dmasr_fsize_less_err;
end if;
end if;
end process S2MM_DMASR_BIT7_D1;
s2mm_dmasr_fsize_less_err_fe <= s2mm_dmasr_fsize_less_err_d1 and not s2mm_dmasr_fsize_less_err;
DM_VSIZE_AT_FSIZE_LESS_ERR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or s2mm_dmasr_fsize_less_err_fe = '1')then
capture_dm_done_vsize_counter <= (others => '0');
elsif (s2mm_fsize_mismatch_err = '1' and s2mm_dmasr_fsize_less_err = '0')then
capture_dm_done_vsize_counter <= done_vsize_counter;
end if;
end if;
end process DM_VSIZE_AT_FSIZE_LESS_ERR;
end generate GEN_VSIZE_SNAPSHOT_LOGIC;
GEN_NO_VSIZE_SNAPSHOT_LOGIC : if (C_USE_FSYNC = 0 or (C_ENABLE_DEBUG_INFO_12 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
capture_dm_done_vsize_counter <= (others => '0');
end generate GEN_NO_VSIZE_SNAPSHOT_LOGIC;
GEN_S2MM_DRE_ON : if C_INCLUDE_S2MM_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_S2MM_DRE_ON;
GEN_S2MM_DRE_OFF : if C_INCLUDE_S2MM_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_S2MM_DRE_OFF;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_FSYNC_LOGIC : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 0) generate
type STRM_WR_SM_TYPE is (STRM_WR_IDLE,
STRM_WR_START,
STRM_WR_RUNNING,
STRM_WR_LAST
);
signal strm_write_ns : STRM_WR_SM_TYPE;
signal strm_write_cs : STRM_WR_SM_TYPE;
type FIFO_RD_SM_TYPE is (FIFO_RD_IDLE,
-- FIFO_RD_START,
FIFO_RD_RUNNING,
FIFO_RD_FSYNC,
FIFO_RD_FSYNC_LAST,
FIFO_RD_LAST
);
signal fifo_read_ns : FIFO_RD_SM_TYPE;
signal fifo_read_cs : FIFO_RD_SM_TYPE;
signal load_counter : std_logic := '0';
signal load_counter_sm : std_logic := '0';
signal strm_write_pending_sm : std_logic := '0';
signal strm_write_pending : std_logic := '0';
signal fifo_rd_pending_sm : std_logic := '0';
signal fifo_rd_pending : std_logic := '0';
signal stop_tready_sm : std_logic := '0';
signal stop_tready : std_logic := '0';
signal strm_write_pending_m_axi : std_logic := '0';
signal stop_tready_s_axi : std_logic := '0';
signal dm_halt_frame : std_logic := '0';
begin
s2mm_all_lines_xfred <= s2mm_all_lines_xfred_i;
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
------ GEN_THRESHOLD_ENABLED_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
------ begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig ;
----- end generate GEN_THRESHOLD_ENABLED_NO_SOF;
-----
-----
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED;
----- GEN_MSTR_SKID_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
----- begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
---- I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
---- generic map(
---- C_WDATA_WIDTH => C_DATA_WIDTH ,
---- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
----
---- )
---- port map(
---- -- System Ports
---- ACLK => s_axis_aclk ,
---- ARST => s_axis_fifo_ainit ,
----
---- -- Shutdown control (assert for 1 clk pulse)
---- skid_stop => '0' ,
----
---- -- Slave Side (Stream Data Input)
---- S_VALID => slv2skid_s_axis_tvalid ,
---- S_READY => s_axis_tready_out ,
---- S_Data => s_axis_tdata ,
---- S_STRB => s_axis_tkeep ,
---- S_Last => s_axis_tlast ,
---- S_User => s_axis_tuser ,
----
---- -- Master Side (Stream Data Output)
---- M_VALID => s_axis_tvalid_i ,
---- M_READY => s_axis_tready_i ,
---- M_Data => s_axis_tdata_i ,
---- M_STRB => s_axis_tkeep_i ,
---- M_Last => s_axis_tlast_i ,
---- M_User => s_axis_tuser_i
---- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
----- end generate GEN_MSTR_SKID_NO_SOF;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
--s_axis_tready <= s_axis_tready_out and not chnl_fsync ;
s_axis_tready <= s_axis_tready_out and chnl_ready and
not stop_tready_s_axi ;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready and
not stop_tready_s_axi ;
-- Generate start of frame fsync
------- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
------- begin
-------
------- TUSER_RE_PROCESS : process(s_axis_aclk)
------- begin
------- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
------- if(s_axis_fifo_ainit_nosync = '1')then
------- s_axis_tuser_d1 <= '0';
------- else
------- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
------- end if;
------- end if;
------- end process TUSER_RE_PROCESS;
-------
------- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
-------
------- end generate GEN_SOF_FSYNC;
-------
------- -- Do not generate start of frame fsync
------- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
------- begin
tuser_fsync <= '0';
------- end generate GEN_NO_SOF_FSYNC;
-------
-------
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid and chnl_ready and
not stop_tready_s_axi;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
s_axis_tready_i <= m_axis_tready and chnl_ready and
not stop_tready_s_axi;
s_axis_tready_out <= m_axis_tready and chnl_ready and
not stop_tready_s_axi;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-- Generate start of frame fsync
----- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
----- begin
-----
----- TUSER_RE_PROCESS : process(s_axis_aclk)
----- begin
----- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
----- if(s_axis_fifo_ainit_nosync = '1')then
----- s_axis_tuser_d1 <= '0';
----- else
----- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
----- end if;
----- end if;
----- end process TUSER_RE_PROCESS;
-----
----- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
-----
----- end generate GEN_SOF_FSYNC;
-----
----- -- Do not generate start of frame fsync
----- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
----- begin
tuser_fsync <= '0';
----- end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_1_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_1_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
TUSER_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
-- WR_PENDING_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
-- generic map(
-- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
-- C_VECTOR_WIDTH => DATACOUNT_WIDTH
-- )
-- port map (
-- prmry_aclk => m_axis_aclk ,
-- prmry_resetn => m_axis_resetn ,
-- scndry_aclk => s_axis_aclk ,
-- scndry_resetn => s_axis_resetn ,
-- scndry_in => '0' ,
-- prmry_out => open ,
-- prmry_in => stop_tready ,
-- scndry_out => stop_tready_s_axi ,
-- scndry_vect_s_h => '0' ,
-- scndry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0),
-- prmry_vect_out => open ,
-- prmry_vect_s_h => '1' ,
-- prmry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0) ,
-- scndry_vect_out => open
-- );
--
WR_PENDING_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => stop_tready,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => stop_tready_s_axi,
scndry_vect_out => open
);
---- WR_PENDING_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => DATACOUNT_WIDTH
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => strm_write_pending ,
---- prmry_out => strm_write_pending_m_axi ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '1' ,
---- prmry_vect_in => ZERO_VALUE_VECT(DATACOUNT_WIDTH-1 downto 0) ,
---- scndry_vect_out => open
---- );
----
WR_PENDING_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => strm_write_pending,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => strm_write_pending_m_axi,
scndry_vect_out => open
);
--GEN_FIFO_SIDE_DM_HALT_REG_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
--begin
FIFO_SIDE_DM_HALT_REG : process(m_axis_aclk) is
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' and p_fsync_out = '0')then
dm_halt_frame <= '0';
elsif (p_fsync_out = '1') then
dm_halt_frame <= '0';
elsif (dm_halt = '1') then
dm_halt_frame <= '1';
end if;
end if;
end process FIFO_SIDE_DM_HALT_REG;
--end generate GEN_FIFO_SIDE_DM_HALT_REG_NO_SOF;
end generate GEN_FOR_ASYNC;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
dm_halt_reg <= dm_halt;
run_stop_reg <= run_stop;
dm_halt_frame <= dm_halt;
s2mm_tuser_fsync_sig <= tuser_fsync;
p_fsync_out <= fsync_out;
--s2mm_all_lines_xfred <= all_lines_xfred; -- CR591965/CR623449
s_data_count_af_thresh <= data_count_af_threshold;
strm_write_pending_m_axi <= strm_write_pending;
stop_tready_s_axi <= stop_tready;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_out = '1'
else '0';
----GEN_NO_SOF_SM : if C_S2MM_SOF_ENABLE = 0 generate
----begin
STRM_SIDE_SM: process (strm_write_cs,
fsync_out,
decr_vcount,
vsize_counter)is
begin
strm_write_pending_sm <= '0';
strm_write_ns <= strm_write_cs;
case strm_write_cs is
when STRM_WR_IDLE =>
if(fsync_out = '1') then
strm_write_ns <= STRM_WR_RUNNING;
strm_write_pending_sm <= '1';
end if;
when STRM_WR_RUNNING =>
if (decr_vcount = '1' and
vsize_counter = VSIZE_ONE_VALUE) then
strm_write_ns <= STRM_WR_IDLE;
strm_write_pending_sm <= '0';
elsif (decr_vcount = '1' and
vsize_counter = VSIZE_TWO_VALUE) then
strm_write_ns <= STRM_WR_LAST;
end if;
strm_write_pending_sm <= '1';
when STRM_WR_LAST =>
if (decr_vcount = '1' ) then
strm_write_ns <= STRM_WR_IDLE;
strm_write_pending_sm <= '0';
end if;
strm_write_pending_sm <= '1';
-- coverage off
when others =>
strm_write_ns <= STRM_WR_IDLE;
-- coverage on
end case;
end process STRM_SIDE_SM;
STRM_SIDE_SM_REG : process(s_axis_aclk) is
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1' and fsync_out = '0')then
strm_write_cs <= STRM_WR_IDLE;
strm_write_pending <= '0';
else
strm_write_cs <= strm_write_ns;
strm_write_pending <= strm_write_pending_sm;
end if;
end if;
end process STRM_SIDE_SM_REG;
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
chnl_ready <= '1';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
chnl_ready <= '1';
end if;
end if;
end process VERT_COUNTER;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
elsif(load_counter = '1')then
done_vsize_counter <= crnt_vsize;
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
end if;
end if;
end process DONE_VERT_COUNTER;
FIFO_SIDE_SM: process (fifo_read_cs,
done_decr_vcount,
p_fsync_out,
done_vsize_counter,
strm_write_pending_m_axi,
crnt_vsize)is
begin
fifo_read_ns <= fifo_read_cs;
load_counter_sm <= '0';
fifo_rd_pending_sm <= '0';
stop_tready_sm <= '0';
case fifo_read_cs is
when FIFO_RD_IDLE =>
if(p_fsync_out = '1') then
fifo_rd_pending_sm <= '1';
load_counter_sm <= '1';
if (crnt_vsize = VSIZE_ONE_VALUE) then
fifo_read_ns <= FIFO_RD_LAST;
else
fifo_read_ns <= FIFO_RD_RUNNING;
end if;
end if;
when FIFO_RD_RUNNING =>
if (p_fsync_out = '1') then
if (strm_write_pending_m_axi = '0') then
stop_tready_sm <= '1';
end if;
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_ONE_VALUE) then
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
else
fifo_read_ns <= FIFO_RD_FSYNC;
end if;
else
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_TWO_VALUE) then
fifo_read_ns <= FIFO_RD_LAST;
end if;
end if;
fifo_rd_pending_sm <= '1';
when FIFO_RD_FSYNC =>
if (done_decr_vcount = '1' and
done_vsize_counter = VSIZE_TWO_VALUE) then
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
end if;
fifo_rd_pending_sm <= '1';
stop_tready_sm <= '1';
when FIFO_RD_FSYNC_LAST =>
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_RUNNING;
load_counter_sm <= '1';
stop_tready_sm <= '0';
end if;
fifo_rd_pending_sm <= '1';
stop_tready_sm <= '1';
when FIFO_RD_LAST =>
if (p_fsync_out = '1') then
if (strm_write_pending_m_axi = '0') then
stop_tready_sm <= '1';
end if;
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_RUNNING;
load_counter_sm <= '1';
else
fifo_read_ns <= FIFO_RD_FSYNC_LAST;
end if;
else
if (done_decr_vcount = '1' ) then
fifo_read_ns <= FIFO_RD_IDLE;
fifo_rd_pending_sm <= '0';
end if;
end if;
fifo_rd_pending_sm <= '1';
-- coverage off
when others =>
fifo_read_ns <= FIFO_RD_IDLE;
-- coverage on
end case;
end process FIFO_SIDE_SM;
FIFO_SIDE_SM_REG : process(m_axis_aclk) is
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0' ) or
dm_halt_frame = '1')then
fifo_read_cs <= FIFO_RD_IDLE;
load_counter <= '0';
fifo_rd_pending <= '0';
stop_tready <= '0';
else
fifo_read_cs <= fifo_read_ns;
load_counter <= load_counter_sm;
fifo_rd_pending <= fifo_rd_pending_sm;
stop_tready <= stop_tready_sm;
end if;
end if;
end process FIFO_SIDE_SM_REG;
DONE_XFER_SIG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit_nosync = '1' and p_fsync_out = '0')then
s2mm_all_lines_xfred_i <= '1';
elsif(load_counter = '1' )then
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_XFER_SIG;
----end generate GEN_NO_SOF_SM;
all_lasts_rcvd <= not strm_write_pending_m_axi;
s2mm_fsync_core <= s2mm_fsync;
fsync_src_select_s <= (others => '0');
drop_fsync_d_pulse_gen_fsize_less_err <= '0';
hold_dummy_tready_low <= '0';
hold_dummy_tready_low2 <= '0';
end generate GEN_FSYNC_LOGIC;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_NO_FSYNC_LOGIC : if ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
--*****************************************************************************--
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
----
---- GEN_SYNC_FIFO_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
---- end generate GEN_SYNC_FIFO_NO_SOF;
----
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
----
---- GEN_ASYNC_FIFO_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
----
LB_BRAM : if ((C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
---- end generate GEN_ASYNC_FIFO_NO_SOF;
----
----
----
end generate GEN_ASYNC_FIFO;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Generate start of frame fsync
GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
begin
TUSER_RE_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1')then
s_axis_tuser_d1 <= '0';
else
s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
end if;
end if;
end process TUSER_RE_PROCESS;
tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
end generate GEN_SOF_FSYNC;
-- Do not generate start of frame fsync
GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
begin
tuser_fsync <= '0';
end generate GEN_NO_SOF_FSYNC;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
---- GEN_THRESHOLD_ENABLED_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig;
---- end generate GEN_THRESHOLD_ENABLED_NO_SOF;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED;
---- GEN_MSTR_SKID_NO_SOF : if C_S2MM_SOF_ENABLE = 0 generate
---- begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
---- I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
---- generic map(
---- C_WDATA_WIDTH => C_DATA_WIDTH ,
---- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
---- )
---- port map(
---- -- System Ports
---- ACLK => s_axis_aclk ,
---- ARST => s_axis_fifo_ainit ,
---- -- Shutdown control (assert for 1 clk pulse)
---- skid_stop => '0' ,
---- -- Slave Side (Stream Data Input)
---- S_VALID => slv2skid_s_axis_tvalid ,
---- S_READY => s_axis_tready_out ,
---- S_Data => s_axis_tdata ,
---- S_STRB => s_axis_tkeep ,
---- S_Last => s_axis_tlast ,
---- S_User => s_axis_tuser ,
---- -- Master Side (Stream Data Output)
---- M_VALID => s_axis_tvalid_i ,
---- M_READY => s_axis_tready_i ,
---- M_Data => s_axis_tdata_i ,
---- M_STRB => s_axis_tkeep_i ,
---- M_Last => s_axis_tlast_i ,
---- M_User => s_axis_tuser_i
---- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
s_axis_tready <= s_axis_tready_out and chnl_ready;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid and chnl_ready;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
s_axis_tready_i <= m_axis_tready and chnl_ready;
s_axis_tready_out <= m_axis_tready and chnl_ready;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-- Generate start of frame fsync
GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
begin
TUSER_RE_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit_nosync = '1')then
s_axis_tuser_d1 <= '0';
else
s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
end if;
end if;
end process TUSER_RE_PROCESS;
tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
end generate GEN_SOF_FSYNC;
-- Do not generate start of frame fsync
GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
begin
tuser_fsync <= '0';
end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_0_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_0_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
TUSER_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
dm_halt_reg <= dm_halt;
run_stop_reg <= run_stop;
p_fsync_out <= fsync_out;
s2mm_tuser_fsync_sig <= tuser_fsync;
s_data_count_af_thresh <= data_count_af_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Generate vertical size counter for case when SOF not used
GEN_NO_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 0 generate
begin
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_out = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
chnl_ready <= '1';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
chnl_ready <= '0';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
chnl_ready <= '1';
end if;
end if;
end process VERT_COUNTER;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_VERT_COUNTER;
end generate GEN_NO_SOF_VCOUNT;
----
----
----
------ Generate vertical size counter for case when SOF is used
GEN_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 1 generate
begin
chnl_ready <= run_stop_reg;
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and p_fsync_out = '0')then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
s2mm_all_lines_xfred_i <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
s2mm_all_lines_xfred_i <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
s2mm_all_lines_xfred_i <= '0';
end if;
end if;
end process DONE_VERT_COUNTER;
end generate GEN_SOF_VCOUNT;
s2mm_all_lines_xfred <= s2mm_all_lines_xfred_i;
all_lasts_rcvd <= s2mm_all_lines_xfred_i;
s2mm_fsync_core <= s2mm_fsync;
fsync_src_select_s <= (others => '0');
drop_fsync_d_pulse_gen_fsize_less_err <= '0';
hold_dummy_tready_low <= '0';
hold_dummy_tready_low2 <= '0';
end generate GEN_NO_FSYNC_LOGIC;
--*****************************************************************************--
--** USE FSYNC MODE **--
--*****************************************************************************--
GEN_S2MM_FLUSH_SOF_LOGIC : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 1) generate
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal mmap_not_finished : std_logic := '0';
signal mmap_not_finished_s : std_logic := '0';
signal mm2s_fsync_s2mm_s : std_logic := '0';
signal s2mm_fsync_int : std_logic := '0';
signal s2mm_fsync_d_pulse : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done_flag : std_logic := '0';
signal delay_s2mm_fsync_core_till_mmap_done_flag_d1 : std_logic := '0';
signal sig_drop_fsync_d_pulse_gen_fsize_less_err : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER_FLUSH_SOF : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_af_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_wrcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO_FLUSH_SOF;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ((C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => fifo_wrcount ,
rd_data_count => open
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ((C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "RD_CLK" , --WR_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO_FLUSH_SOF;
GEN_S2MM_DRE_ENABLED_TKEEP : if C_INCLUDE_S2MM_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tkeep_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_S2MM_DRE_ENABLED_TKEEP;
GEN_NO_S2MM_DRE_DISABLE_TKEEP : if C_INCLUDE_S2MM_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast_i & s_axis_tdata_i;
fifo_wren <= s_axis_tvalid_i and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig;
m_axis_tdata <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_signal <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tlast <= m_axis_tlast_i;
m_axis_tvalid <= m_axis_tvalid_i;
end generate GEN_NO_S2MM_DRE_DISABLE_TKEEP;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED_FLUSH_SOF : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost full flag
-- This flag is only used by S2MM and the threshold has been adjusted to allow registering
-- of the flag for timing and also to assert and deassert from an outside S2MM perspective
REG_ALMST_FULL : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
fifo_almost_full_i <= '0';
-- write count greater than or equal to threshold value therefore assert thresold flag
elsif(fifo_wrcount >= s_data_count_af_thresh or (fifo_full_i='1' or wr_rst_busy_sig = '1')) then
fifo_almost_full_i <= '1';
-- In all other cases de-assert flag
else
fifo_almost_full_i <= '0';
end if;
end if;
end process REG_ALMST_FULL;
-- Drive fifo flags out if Linebuffer included
s2mm_fifo_almost_full <= fifo_almost_full_i or fifo_full_i or wr_rst_busy_sig;
s2mm_fifo_full <= fifo_full_i or wr_rst_busy_sig;
end generate GEN_THRESHOLD_ENABLED_FLUSH_SOF;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED_FLUSH_SOF : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
fifo_almost_full_i <= '0';
s2mm_fifo_almost_full <= '0';
s2mm_fifo_full <= '0';
end generate GEN_THRESHOLD_DISABLED_FLUSH_SOF;
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
-- I_MSTR_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_DATA_WIDTH ,
-- C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
-- )
-- port map(
-- -- System Ports
-- ACLK => s_axis_aclk ,
-- ARST => s_axis_fifo_ainit ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => '0' ,
--
-- -- Slave Side (Stream Data Input)
-- S_VALID => slv2skid_s_axis_tvalid ,
-- S_READY => s_axis_tready_out ,
-- S_Data => s_axis_tdata ,
-- S_STRB => s_axis_tkeep ,
-- S_Last => s_axis_tlast ,
-- S_User => s_axis_tuser ,
--
-- -- Master Side (Stream Data Output)
-- M_VALID => s_axis_tvalid_i ,
-- M_READY => s_axis_tready_i ,
-- M_Data => s_axis_tdata_i ,
-- M_STRB => s_axis_tkeep_i ,
-- M_Last => s_axis_tlast_i ,
-- M_User => s_axis_tuser_i
-- );
s_axis_tvalid_i <= slv2skid_s_axis_tvalid;
s_axis_tdata_i <= s_axis_tdata;
s_axis_tkeep_i <= s_axis_tkeep_signal;
s_axis_tlast_i <= s_axis_tlast;
s_axis_tuser_i <= s_axis_tuser;
s_axis_tready_out <= s_axis_tready_i;
-- Pass out top level
-- Qualify with channel ready to 'turn off' ready
-- at end of video frame
--------s_axis_tready <= s_axis_tready_out and chnl_ready_external;
s_axis_tready <= s_axis_tready_out ;
-- Qualify with channel ready to 'turn off' writes to
-- fifo at end of video frame
------slv2skid_s_axis_tvalid <= s_axis_tvalid and chnl_ready_external;
slv2skid_s_axis_tvalid <= s_axis_tvalid ;
end generate GEN_LINEBUFFER_FLUSH_SOF;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
GEN_NO_LINEBUFFER_FLUSH_SOF : if (C_LINEBUFFER_DEPTH = 0) generate
begin
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep <= s_axis_tkeep_signal;
m_axis_tvalid_i <= s_axis_tvalid;
--------------------m_axis_tvalid_i <= s_axis_tvalid and chnl_ready_external;
m_axis_tlast_i <= s_axis_tlast;
m_axis_tvalid <= m_axis_tvalid_i;
m_axis_tlast <= m_axis_tlast_i;
----------s_axis_tready_i <= m_axis_tready and chnl_ready_external;
s_axis_tready_i <= m_axis_tready;
---------s_axis_tready_out <= m_axis_tready and chnl_ready_external;
s_axis_tready_out <= m_axis_tready;
s_axis_tready <= s_axis_tready_i;
-- fifo signals not used
s2mm_fifo_full <= '0';
s2mm_fifo_almost_full <= '0';
-------------------------- -- Generate start of frame fsync
-------------------------- GEN_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 1 generate
-------------------------- begin
--------------------------
-------------------------- TUSER_RE_PROCESS : process(s_axis_aclk)
-------------------------- begin
-------------------------- if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
-------------------------- if(s_axis_fifo_ainit_nosync = '1')then
-------------------------- s_axis_tuser_d1 <= '0';
-------------------------- else
-------------------------- s_axis_tuser_d1 <= s_axis_tuser_i(0) and s_axis_tvalid_i;
-------------------------- end if;
-------------------------- end if;
-------------------------- end process TUSER_RE_PROCESS;
--------------------------
-------------------------- tuser_fsync <= s_axis_tuser_i(0) and s_axis_tvalid_i and not s_axis_tuser_d1;
--------------------------
-------------------------- end generate GEN_SOF_FSYNC;
--------------------------
-------------------------- -- Do not generate start of frame fsync
-------------------------- GEN_NO_SOF_FSYNC : if C_S2MM_SOF_ENABLE = 0 generate
-------------------------- begin
-------------------------- tuser_fsync <= '0';
-------------------------- end generate GEN_NO_SOF_FSYNC;
end generate GEN_NO_LINEBUFFER_FLUSH_SOF;
-- Instantiate Clock Domain Crossing for Asynchronous clock
GEN_FOR_ASYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
VSIZE_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross datamover halt and fifo threshold to secondary for reset use
---- STRM_WR_HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => dm_halt , -- CR591965
---- scndry_out => dm_halt_reg , -- CR591965
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STRM_WR_HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
data_count_af_threshold_cdc_tig <= data_count_af_threshold;
data_count_af_threshold_d1 <= data_count_af_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
s_data_count_af_thresh <= data_count_af_threshold_d1;
-- Cross run_stop to secondary
---- RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => run_stop ,
---- scndry_out => run_stop_reg ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
-- CR623449 cross fsync_out back to primary
---- FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => fsync_out ,
---- prmry_out => p_fsync_out ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => p_fsync_out,
scndry_vect_out => open
);
-- Cross tuser fsync to primary
---- TUSER_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => tuser_fsync ,
---- prmry_out => s2mm_tuser_fsync_sig ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
TUSER_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => tuser_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_tuser_fsync_sig,
scndry_vect_out => open
);
---- MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => mmap_not_finished ,
---- scndry_out => mmap_not_finished_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => mmap_not_finished,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mmap_not_finished_s,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
GEN_FOR_ASYNC_CROSS_FSYNC : if C_INCLUDE_MM2S = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_mm2s_aclk ,
---- prmry_resetn => mm2s_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => mm2s_fsync ,
---- scndry_out => mm2s_fsync_s2mm_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_mm2s_aclk,
prmry_resetn => mm2s_axis_resetn,
prmry_in => mm2s_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fsync_s2mm_s,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC_CROSS_FSYNC;
GEN_FOR_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_fsync_s2mm_s <= '0';
end generate GEN_FOR_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC_FLUSH_SOF;
-- Synchronous clock therefore just map signals across
GEN_FOR_SYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
crnt_vsize_d2 <= crnt_vsize;
mmap_not_finished_s <= mmap_not_finished;
fsync_src_select_s_int <= fsync_src_select;
dm_halt_reg <= dm_halt;
--dm_halt_cmplt_s <= dm_halt_cmplt;
run_stop_reg <= run_stop;
p_fsync_out <= fsync_out;
s2mm_tuser_fsync_sig <= tuser_fsync;
s_data_count_af_thresh <= data_count_af_threshold;
GEN_FOR_SYNC_CROSS_FSYNC : if C_INCLUDE_MM2S = 1 generate
begin
mm2s_fsync_s2mm_s <= mm2s_fsync;
end generate GEN_FOR_SYNC_CROSS_FSYNC;
GEN_FOR_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_fsync_s2mm_s <= '0';
end generate GEN_FOR_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC_FLUSH_SOF;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-----------------------GEN_SOF_VCOUNT : if C_S2MM_SOF_ENABLE = 1 generate
-----------------------begin
-- decrement based on master axis signals for determining done (CR623449)
done_decr_vcount <= '1' when m_axis_tlast_i = '1'
and m_axis_tvalid_i = '1'
and m_axis_tready = '1'
else '0';
-- CR623449 - base done on master clock domain
DONE_VERT_COUNTER_FLUSH_SOF : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and p_fsync_out = '0') or s2mm_fsize_mismatch_err_flag = '1')then
done_vsize_counter <= (others => '0');
mmap_not_finished <= '0';
elsif(p_fsync_out = '1')then
done_vsize_counter <= crnt_vsize;
mmap_not_finished <= '1';
elsif(done_decr_vcount = '1' and done_vsize_counter = VSIZE_ONE_VALUE)then
done_vsize_counter <= (others => '0');
mmap_not_finished <= '0';
elsif(done_decr_vcount = '1' and done_vsize_counter /= VSIZE_ZERO_VALUE)then
done_vsize_counter <= std_logic_vector(unsigned(done_vsize_counter) - 1);
mmap_not_finished <= '1';
end if;
end if;
end process DONE_VERT_COUNTER_FLUSH_SOF;
delay_s2mm_fsync_core_till_mmap_done <= '1' when mmap_not_finished_s = '1' and strm_not_finished = '0' and s2mm_fsync_int = '1' and delay_s2mm_fsync_core_till_mmap_done_flag = '0'
else '0';
hold_dummy_tready_low <= delay_s2mm_fsync_core_till_mmap_done or delay_s2mm_fsync_core_till_mmap_done_flag;
HOLD_DELAY_FSYNC_IN_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or mmap_not_finished_s = '0' or sig_drop_fsync_d_pulse_gen_fsize_less_err = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag <= '0';
elsif(delay_s2mm_fsync_core_till_mmap_done = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag <= '1';
end if;
end if;
end process HOLD_DELAY_FSYNC_IN_FLAG;
D1_HOLD_DELAY_FSYNC_IN_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or sig_drop_fsync_d_pulse_gen_fsize_less_err = '1')then
delay_s2mm_fsync_core_till_mmap_done_flag_d1 <= '0';
else
delay_s2mm_fsync_core_till_mmap_done_flag_d1 <= delay_s2mm_fsync_core_till_mmap_done_flag;
end if;
end if;
end process D1_HOLD_DELAY_FSYNC_IN_FLAG;
s2mm_fsync_d_pulse <= delay_s2mm_fsync_core_till_mmap_done_flag_d1 and (not delay_s2mm_fsync_core_till_mmap_done_flag) ;
s2mm_fsync_core <= (s2mm_fsync_int and not (delay_s2mm_fsync_core_till_mmap_done) and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or s2mm_fsync_d_pulse or d_fsync_halt_cmplt_s;
sig_drop_fsync_d_pulse_gen_fsize_less_err <= '1' when delay_s2mm_fsync_core_till_mmap_done_flag = '1' and s2mm_fsync_int = '1'
else '0';
GEN_FOR_C_USE_S2MM_FSYNC_1 : if C_USE_S2MM_FSYNC = 1 generate
begin
s2mm_fsync_int <= s2mm_fsync and run_stop_reg and no_fsync_before_vsize_sel_00_01;
end generate GEN_FOR_C_USE_S2MM_FSYNC_1;
GEN_FOR_C_USE_S2MM_FSYNC_2 : if C_USE_S2MM_FSYNC = 2 generate
begin
s2mm_fsync_int <= s2mm_tuser_fsync_top and run_stop_reg;
end generate GEN_FOR_C_USE_S2MM_FSYNC_2;
-- Frame sync cross bar
------ FSYNC_CROSSBAR_S2MM_S : process(fsync_src_select_s_int,
------ run_stop_reg,
------ s2mm_fsync,
------ mm2s_fsync_s2mm_s, no_fsync_before_vsize_sel_00_01,
------ s2mm_tuser_fsync_top)
------ begin
------ case fsync_src_select_s_int is
------
------ when "00" => -- primary fsync (default)
------ s2mm_fsync_int <= s2mm_fsync and run_stop_reg and no_fsync_before_vsize_sel_00_01;
------ when "01" => -- other channel fsync
------ s2mm_fsync_int <= mm2s_fsync_s2mm_s and run_stop_reg and no_fsync_before_vsize_sel_00_01;
------ when "10" => -- s2mm_tuser_fsync_top fsync (used only by s2mm)
------ s2mm_fsync_int <= s2mm_tuser_fsync_top and run_stop_reg;
------ when others =>
------ s2mm_fsync_int <= '0';
------ end case;
------ end process FSYNC_CROSSBAR_S2MM_S;
------
-----------------------end generate GEN_SOF_VCOUNT;
S2MM_FSIZE_ERR_TO_DM_HALT_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process S2MM_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= s2mm_fsize_mismatch_err_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and s2mm_fsync_int = '1'
else '0';
FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process FSIZE_LESS_DM_HALT_CMPLT_FLAG;
REG_D_FSYNC : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
hold_dummy_tready_low2 <= delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s or delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
s2mm_all_lines_xfred <= '0';
all_lasts_rcvd <= '0';
tuser_fsync <= '0';
fsync_src_select_s <= fsync_src_select_s_int;
drop_fsync_d_pulse_gen_fsize_less_err <= sig_drop_fsync_d_pulse_gen_fsize_less_err;
end generate GEN_S2MM_FLUSH_SOF_LOGIC;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_reg_mux.vhd
|
4
|
592541
|
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/bd/block_design/ipshared/digilent/axi_dispctrl_v1_0/hdl/axi_dispctrl_v1_0.vhd
|
7
|
18671
|
--------------------------------------------------------------------------------
--
-- File:
-- axi_dispctrl_v1_0.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author:
-- Tinghui Wang (Steve)
-- Sam Bobrowicz
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dispctrl_v1_0 is
generic (
-- Users to add parameters here
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
-- Clock Signals
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
-- Display Signals
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
-- Debug Signals
DEBUG_O : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXIS_MM2S
s_axis_mm2s_aclk : in std_logic;
s_axis_mm2s_aresetn : in std_logic;
s_axis_mm2s_tready : out std_logic;
s_axis_mm2s_tdata : in std_logic_vector(C_S_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
s_axis_mm2s_tstrb : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
s_axis_mm2s_tlast : in std_logic;
s_axis_mm2s_tvalid : in std_logic
);
end axi_dispctrl_v1_0;
architecture arch_imp of axi_dispctrl_v1_0 is
-- component declaration
component axi_dispctrl_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
FRAME_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dispctrl_v1_0_S_AXI;
component mmcme2_drp
generic (
DIV_F : integer
);
port(
SEN : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
S1_CLKOUT0 : in std_logic_vector(35 downto 0);
S1_CLKFBOUT : in std_logic_vector(35 downto 0);
S1_DIVCLK : in std_logic_vector(13 downto 0);
S1_LOCK : in std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : in std_logic_vector(9 downto 0);
REF_CLK : in std_logic;
CLKFBOUT_I : in std_logic;
CLKFBOUT_O : out std_logic;
SRDY : out std_logic;
PXL_CLK : out std_logic;
LOCKED_O : out std_logic
);
end component;
component vdma_to_vga
generic (
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port(
LOCKED_I : in std_logic;
ENABLE_I : in std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
USR_WIDTH_I : in std_logic_vector(11 downto 0);
USR_HEIGHT_I : in std_logic_vector(11 downto 0);
USR_HPS_I : in std_logic_vector(11 downto 0);
USR_HPE_I : in std_logic_vector(11 downto 0);
USR_HPOL_I : in std_logic;
USR_HMAX_I : in std_logic_vector(11 downto 0);
USR_VPS_I : in std_logic_vector(11 downto 0);
USR_VPE_I : in std_logic_vector(11 downto 0);
USR_VPOL_I : in std_logic;
USR_VMAX_I : in std_logic_vector(11 downto 0);
RUNNING_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0)
);
end component;
signal CTRL_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal STAT_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal FRAME_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_O_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FB_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FRAC_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_DIV_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_LOCK_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FLTR_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal clk_state : CLK_STATE_TYPE := RESET;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal pxl_clk : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal vga_running : std_logic;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_dispctrl_v1_0_S_AXI_inst : axi_dispctrl_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
CTRL_REG => CTRL_REG,
STAT_REG => STAT_REG,
FRAME_REG => FRAME_REG,
HPARAM1_REG => HPARAM1_REG,
HPARAM2_REG => HPARAM2_REG,
VPARAM1_REG => VPARAM1_REG,
VPARAM2_REG => VPARAM2_REG,
CLK_O_REG => CLK_O_REG,
CLK_FB_REG => CLK_FB_REG,
CLK_FRAC_REG => CLK_FRAC_REG,
CLK_DIV_REG => CLK_DIV_REG,
CLK_LOCK_REG => CLK_LOCK_REG,
CLK_FLTR_REG => CLK_FLTR_REG,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
PXL_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED =>
-- This state ensures that the initial SRDY pulse
-- doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
generic map (
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => s_axis_mm2s_aclk,
S_AXIS_ARESETN => s_axis_mm2s_aresetn,
S_AXIS_TREADY => s_axis_mm2s_tready,
S_AXIS_TDATA => s_axis_mm2s_tdata,
S_AXIS_TSTRB => s_axis_mm2s_tstrb,
S_AXIS_TLAST => s_axis_mm2s_tlast,
S_AXIS_TVALID => s_axis_mm2s_tvalid,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DEBUG_O => DEBUG_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
STAT_REG(C_S_AXI_DATA_WIDTH-1 downto 1) <= (others => '0');
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd
|
19
|
4781
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ip/block_design_axi_i2s_adi_0_0/synth/block_design_axi_i2s_adi_0_0.vhd
|
1
|
13817
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: analogdeviceinc.com:adi:axi_i2s_adi:1.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY adi_common_v1_00_a;
USE adi_common_v1_00_a.axi_i2s_adi;
ENTITY block_design_axi_i2s_adi_0_0 IS
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END block_design_axi_i2s_adi_0_0;
ARCHITECTURE block_design_axi_i2s_adi_0_0_arch OF block_design_axi_i2s_adi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_i2s_adi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_i2s_adi IS
GENERIC (
C_SLOT_WIDTH : INTEGER;
C_LRCLK_POL : INTEGER;
C_BCLK_POL : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_DMA_TYPE : INTEGER;
C_NUM_CH : INTEGER;
C_HAS_TX : INTEGER;
C_HAS_RX : INTEGER
);
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END COMPONENT axi_i2s_adi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF block_design_axi_i2s_adi_0_0_arch: ARCHITECTURE IS "axi_i2s_adi,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_i2s_adi_0_0_arch : ARCHITECTURE IS "block_design_axi_i2s_adi_0_0,axi_i2s_adi,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_TX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_TX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_RX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_RX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
BEGIN
U0 : axi_i2s_adi
GENERIC MAP (
C_SLOT_WIDTH => 24,
C_LRCLK_POL => 0,
C_BCLK_POL => 0,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_DMA_TYPE => 1,
C_NUM_CH => 1,
C_HAS_TX => 1,
C_HAS_RX => 1
)
PORT MAP (
DATA_CLK_I => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
MUTEN_O => MUTEN_O,
S_AXIS_ACLK => '0',
S_AXIS_ARESETN => '0',
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXIS_TLAST => '0',
S_AXIS_TVALID => '0',
M_AXIS_ACLK => '0',
M_AXIS_TREADY => '0',
DMA_REQ_TX_ACLK => DMA_REQ_TX_ACLK,
DMA_REQ_TX_RSTN => DMA_REQ_TX_RSTN,
DMA_REQ_TX_DAVALID => DMA_REQ_TX_DAVALID,
DMA_REQ_TX_DATYPE => DMA_REQ_TX_DATYPE,
DMA_REQ_TX_DAREADY => DMA_REQ_TX_DAREADY,
DMA_REQ_TX_DRVALID => DMA_REQ_TX_DRVALID,
DMA_REQ_TX_DRTYPE => DMA_REQ_TX_DRTYPE,
DMA_REQ_TX_DRLAST => DMA_REQ_TX_DRLAST,
DMA_REQ_TX_DRREADY => DMA_REQ_TX_DRREADY,
DMA_REQ_RX_ACLK => DMA_REQ_RX_ACLK,
DMA_REQ_RX_RSTN => DMA_REQ_RX_RSTN,
DMA_REQ_RX_DAVALID => DMA_REQ_RX_DAVALID,
DMA_REQ_RX_DATYPE => DMA_REQ_RX_DATYPE,
DMA_REQ_RX_DAREADY => DMA_REQ_RX_DAREADY,
DMA_REQ_RX_DRVALID => DMA_REQ_RX_DRVALID,
DMA_REQ_RX_DRTYPE => DMA_REQ_RX_DRTYPE,
DMA_REQ_RX_DRLAST => DMA_REQ_RX_DRLAST,
DMA_REQ_RX_DRREADY => DMA_REQ_RX_DRREADY,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
END block_design_axi_i2s_adi_0_0_arch;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_sm.vhd
|
4
|
49804
|
-------------------------------------------------------------------------------
-- axi_vdma_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sm.vhd
-- Description: This entity contains the DMA Controller State Machine and
-- manages primary data transfers.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_sm is
generic (
C_INCLUDE_SF : integer range 0 to 1 := 0;
-- Include or exclude store and forward module
-- 0 = excluded
-- 1 = included
C_USE_FSYNC : integer range 0 to 1 := 0; -- CR591965
-- Specifies VDMA operation synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0; -- CR591965
-- Specifies VDMA Flush on Frame sync enabled
-- 0 = Disabled
-- 1 = Enabled
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_EXTEND_DM_COMMAND : integer range 0 to 1 := 0;
-- Extend datamover command by padding BTT with 1's for
-- indeterminate BTT mode
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Control and Status --
frame_sync : in std_logic ; --
video_prmtrs_valid : in std_logic ; --
packet_sof : in std_logic ; --
run_stop : in std_logic ; --
stop : in std_logic ; --
halt : in std_logic ; --
--
-- sm status --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
zero_size_err : out std_logic ; -- CR579593/CR579597
fsize_mismatch_err_flag : out std_logic ; -- CR591965
fsize_mismatch_err : out std_logic ; -- CR591965
s2mm_fsize_mismatch_err_s : out std_logic ; -- CR591965
mm2s_fsize_mismatch_err_s : in std_logic ;
mm2s_fsize_mismatch_err_m : in std_logic ;
all_lines_xfred : in std_logic ; -- CR616211
all_lasts_rcvd : in std_logic ; -- --
s2mm_strm_all_lines_rcvd : in std_logic ; --
drop_fsync_d_pulse_gen_fsize_less_err : in std_logic ; --
s2mm_fsync_core : in std_logic ;
s2mm_fsync_out_m : in std_logic ;
mm2s_fsync_out_m : in std_logic ;
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
cmnd_pending : in std_logic ; --
sts_received : in std_logic ; --
--
-- Descriptor Fields --
crnt_start_address : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); --
--
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) --
);
end axi_vdma_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := 8;
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
constant PAD_VALUE : std_logic_vector(22 - HSIZE_DWIDTH downto 0)
:= (others => '0');
constant ONES_PAD_VALUE : std_logic_vector(22 - HSIZE_DWIDTH downto 0)
:= (others => '1');
constant ZERO_VCOUNT : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
constant EXTND_STRIDE_PAD : std_logic_vector((C_M_AXI_ADDR_WIDTH - STRIDE_DWIDTH) - 1 downto 0)
:= (others => '0');
-- Zero HSIZE Constant for error check
constant ZERO_HSIZE : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
-- Zero VSIZE Constant for error check
constant ZERO_VSIZE : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_STATE_TYPE is (
IDLE,
WAIT_PIPE1,
WAIT_PIPE2,
CALC_CMD_ADDR,
EXECUTE_XFER,
CHECK_DONE
);
signal dmacntrl_cs : SG_STATE_TYPE;
signal dmacntrl_ns : SG_STATE_TYPE;
-- State Machine Signals
signal calc_new_addr : std_logic := '0';
signal load_new_addr : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal cmnd_idle_i : std_logic := '0';
-- address calc signals
signal extend_crnt_stride : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal dm_address : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal vert_count : std_logic_vector(VSIZE_DWIDTH - 1 downto 0)
:= (others => '0');
signal horz_count : std_logic_vector(HSIZE_DWIDTH - 1 downto 0)
:= (others => '0');
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal frame_sync_d2 : std_logic := '0';
signal frame_sync_d3 : std_logic := '0';
signal frame_sync_reg : std_logic := '0';
signal axis_data_available : std_logic := '0';
signal zero_vsize_err : std_logic := '0'; -- CR579593/CR579597
signal zero_hsize_err : std_logic := '0'; -- CR579593/CR579597
signal xfers_done : std_logic := '0'; -- CR616211
signal all_lines_xfred_d1 : std_logic := '0';
signal all_lines_xfred_fe : std_logic := '0';
signal xfred_started : std_logic := '0';
signal mm2s_fsize_mismatch_err_int : std_logic := '0';
signal fsize_mismatch_err_int : std_logic := '0';
signal fsize_mismatch_err_flag_int : std_logic := '0';
signal fsize_mismatch_err_flag_int_d1 : std_logic := '0';
signal fsize_mismatch_err_flag_int_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cmnd_wr <= cmnd_wr_i;
cmnd_idle <= cmnd_idle_i;
REG_FRAME_SYCN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_sync_d1 <= '0';
frame_sync_d2 <= '0';
frame_sync_d3 <= '0';
frame_sync_reg <= '0';
else
frame_sync_d1 <= frame_sync;
frame_sync_d2 <= frame_sync_d1;
frame_sync_d3 <= frame_sync_d2;
frame_sync_reg <= frame_sync_d3;
end if;
end if;
end process REG_FRAME_SYCN;
-------------------------------------------------------------------------------
-- Stream Data Started
-- On S2MM, this is used to prevent issuing CMDs to DataMover until axi_stream
-- data is present on the S2MM interface. This prevents write requests
-- from being issued out to axi_interconnect when no data available to write.
-------------------------------------------------------------------------------
GEN_NO_STORE_AND_FORWARD : if C_INCLUDE_SF = 0 generate
begin
STM_DATA_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
axis_data_available <= '0';
elsif(cmnd_idle_i = '1' and run_stop = '0')then
axis_data_available <= '0';
-- Set if sof detected on axi stream
elsif(packet_sof = '1')then
axis_data_available <= '1';
-- New set of video parameters, therefore clear flag
-- New s2mm packets for new parameters must come after
-- sync.
elsif(frame_sync = '1' )then
axis_data_available <= '0';
end if;
end if;
end process STM_DATA_PROCESS;
end generate GEN_NO_STORE_AND_FORWARD;
-- with store and forward then store-and-forward logic will
-- regulate datamover requests.
GEN_STORE_AND_FORWARD : if C_INCLUDE_SF = 1 generate
begin
axis_data_available <= '1';
end generate GEN_STORE_AND_FORWARD;
-------------------------------------------------------------------------------
-- Transfer State Machine
-------------------------------------------------------------------------------
DMA_CNTRL_MACHINE : process(dmacntrl_cs,
frame_sync_reg,
video_prmtrs_valid,
cmnd_pending,
run_stop,fsize_mismatch_err_flag_int_d2,
stop,
halt,
vert_count,
axis_data_available) -- CR579593/CR579597
begin
-- Default signal assignment
calc_new_addr <= '0';
load_new_addr <= '0';
write_cmnd_cmb <= '0';
cmnd_idle_i <= '0';
dmacntrl_ns <= dmacntrl_cs;
case dmacntrl_cs is
-------------------------------------------------------------------
when IDLE =>
-- If video parameters are valid and at frame sync and no errors
-- then start
if( video_prmtrs_valid = '1' and frame_sync_reg = '1'
and stop = '0' and halt = '0' and run_stop = '1' and fsize_mismatch_err_flag_int_d2 = '0') then
dmacntrl_ns <= WAIT_PIPE1;
else
cmnd_idle_i <= '1';
end if;
-------------------------------------------------------------------
-- pipeline delay for valid address from vidreg_module
when WAIT_PIPE1 =>
-- CR589083 need to also look at run_Stop to compensate for
-- pipeline delays when in frame count enable mode
-- CR591965 need to reset to idle on frame sync
--if(stop = '1' or halt = '1' or run_stop = '0')then
if(stop = '1' or halt = '1' or run_stop = '0' or frame_sync_reg='1' or fsize_mismatch_err_flag_int_d2 = '1')then
dmacntrl_ns <= IDLE;
else
dmacntrl_ns <= WAIT_PIPE2;
end if;
-------------------------------------------------------------------
-- pipeline delay for valid address from vidreg_module
when WAIT_PIPE2 =>
-- CR589083 need to also look at run_Stop to compensate for
-- pipeline delays when in frame count enable mode
-- CR591965 need to reset to idle on frame sync
--if(stop = '1' or halt = '1' or run_stop = '0')then
if(stop = '1' or halt = '1' or run_stop = '0' or frame_sync_reg='1' or fsize_mismatch_err_flag_int_d2 = '1')then
dmacntrl_ns <= IDLE;
else
load_new_addr <= '1';
dmacntrl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when CALC_CMD_ADDR =>
-- CR591965 need to reset to idle on frame sync
--if(stop = '1' or halt = '1')then
if(stop = '1' or halt = '1' or frame_sync_reg='1' or fsize_mismatch_err_flag_int_d2 = '1')then
dmacntrl_ns <= IDLE;
else
calc_new_addr <= '1';
dmacntrl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
-- CR591965 need to reset to idle on frame sync
--if(stop = '1' or halt = '1'
--or zero_hsize_err = '1' or zero_vsize_err = '1')then -- CR579593/CR579597
if(stop = '1' or halt = '1' or frame_sync_reg='1' or fsize_mismatch_err_flag_int_d2 = '1') then -- CR591965
dmacntrl_ns <= IDLE;
-- Write another command if there is not one already pending
-- and data available on stream (used for s2mm only)
elsif(cmnd_pending = '0'
and axis_data_available = '1')then
write_cmnd_cmb <= '1';
dmacntrl_ns <= CHECK_DONE;
else
dmacntrl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when CHECK_DONE =>
-- VSIZE commands issued to datamover then done
-- CR591965 need to reset to idle on frame sync
--if(vert_count = ZERO_VCOUNT or stop = '1' or halt = '1')then
if(vert_count = ZERO_VCOUNT or stop = '1'
or halt = '1' or frame_sync_reg='1' or fsize_mismatch_err_flag_int_d2 = '1')then
dmacntrl_ns <= IDLE;
else
dmacntrl_ns <= CALC_CMD_ADDR;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
dmacntrl_ns <= IDLE;
-- coverage on
end case;
end process DMA_CNTRL_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacntrl_cs <= IDLE;
else
dmacntrl_cs <= dmacntrl_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Stride Holding Register
-------------------------------------------------------------------------------
----STRIDE_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- extend_crnt_stride <= (others => '0');
----
---- elsif(load_new_addr = '1')then
---- -- 0 extend stride to match addr width
---- extend_crnt_stride <= EXTND_STRIDE_PAD & crnt_stride;
---- end if;
---- end if;
---- end process STRIDE_REGISTER;
extend_crnt_stride <= EXTND_STRIDE_PAD & crnt_stride;
-------------------------------------------------------------------------------
-- Command Address Calculator
-------------------------------------------------------------------------------
ADDRESS_CALC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_address <= (others => '0');
elsif(load_new_addr = '1')then
dm_address <= crnt_start_address;
elsif(calc_new_addr = '1')then
dm_address <= std_logic_vector(unsigned(dm_address) + unsigned(extend_crnt_stride));
end if;
end if;
end process ADDRESS_CALC;
-------------------------------------------------------------------------------
-- Vertical Line Counter
-------------------------------------------------------------------------------
VERT_COUNTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
vert_count <= (others => '0');
elsif(load_new_addr = '1')then
vert_count <= crnt_vsize;
elsif(write_cmnd_cmb = '1')then
vert_count <= std_logic_vector(unsigned(vert_count) - 1);
end if;
end if;
end process VERT_COUNTER;
-------------------------------------------------------------------------------
-- Horizontal Holding Register
-------------------------------------------------------------------------------
----HORZ_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- horz_count <= (others => '0');
---- elsif(load_new_addr = '1')then
---- horz_count <= crnt_hsize;
---- end if;
---- end if;
---- end process HORZ_REGISTER;
horz_count <= crnt_hsize;
-------------------------------------------------------------------------------
-- HSIZE Zero Error
-- If hsize is set to zero on address load then flag an internal error
-- CR579593/CR579597
-------------------------------------------------------------------------------
CHECK_ZERO_HSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
zero_hsize_err <= '0';
elsif(load_new_addr = '1' and crnt_hsize = ZERO_HSIZE)then
zero_hsize_err <= '1';
else
zero_hsize_err <= '0'; -- CR591965
end if;
end if;
end process CHECK_ZERO_HSIZE;
-------------------------------------------------------------------------------
-- VSIZE Zero Error
-- If vsize is set to zero on address load then flag an internal error
-- CR579593/CR579597
-------------------------------------------------------------------------------
CHECK_ZERO_VSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
zero_vsize_err <= '0';
elsif(load_new_addr = '1' and crnt_vsize = ZERO_VSIZE)then
zero_vsize_err <= '1';
else
zero_vsize_err <= '0'; -- CR591965
end if;
end if;
end process CHECK_ZERO_VSIZE;
-- Drive out for register status bit setting
zero_size_err <= zero_vsize_err or zero_hsize_err;
-- For MM2S and for S2MM when not in Store-And-Forward Mode
GEN_NORMAL_DM_COMMAND : if C_EXTEND_DM_COMMAND = 0 generate
begin
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to cmdsts_if
GEN_DATAMOVER_CMND : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in sg_if.
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- modified for video
& '1' -- not used by video
-- Command
& dm_address -- Calculate address
& '1' -- CMD DRR modified for video
& '1' -- CMD EOF modified for video
& CMD_DSA -- No Destination stream offset
& '1' -- Type no longer used
& PAD_VALUE
& horz_count;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_NORMAL_DM_COMMAND;
-- For S2MM in Store-And-Forward Mode and DRE turned off
-- Need to set the BTT to a greater value than hsize. This will allow
-- the indeterminate BTT mode of the datamover to not generate a bus error
-- on overflow when the hsize values are not stream data width aligned
GEN_EXTENDED_DM_COMMAND : if C_EXTEND_DM_COMMAND = 1 generate
begin
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to cmdsts_if
GEN_DATAMOVER_CMND : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in sg_if.
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- modified for video
& '1' -- not used by video
-- Command
& dm_address -- Calculate address
& '1' -- CMD DRR modified for video
& '1' -- CMD EOF modified for video
& CMD_DSA -- No Destination stream offset
& '1' -- Type no longer used
& ONES_PAD_VALUE -- pad with 1's - want greater than hsize btt
& horz_count;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_EXTENDED_DM_COMMAND;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when cmnd_wr_i = '1' and sts_received = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when cmnd_wr_i = '0' and sts_received = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or stop = '1' or halt = '1')then
cmnds_queued <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
elsif(count_decr = '1')then
cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = ZERO_COUNT and xfers_done = '1'
else '0';
-- CR616211
-- For store-and-foward need to keep track of when
-- AXIS stream is actually complete (For MM2S)
GEN_DONE_FOR_SNF : if C_INCLUDE_SF = 1 generate
begin
-- In free run then condition xfers done with a indication
-- transfers have started. This fixes issue with double
-- frame sync.
GEN_FOR_FREE_RUN : if C_USE_FSYNC = 0 generate
begin
REG_ALLL_XFRED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
all_lines_xfred_d1 <= '0';
else
all_lines_xfred_d1 <= all_lines_xfred;
end if;
end if;
end process REG_ALLL_XFRED;
all_lines_xfred_fe <= not all_lines_xfred and all_lines_xfred_d1;
-- Flag when a transfer as started
REG_XFRED_STARTED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- at start want to be able to gen first fsync so
-- intially set flag to 1 so sts_idle will assert
-- gen first fsync
if(prmry_resetn = '0' or run_stop = '0')then
xfred_started <= '1';
-- when running then utilize frame_sync to clear flag
elsif(frame_sync = '1')then
xfred_started <= '0';
-- set flag whith each falling edge
elsif(all_lines_xfred_fe='1')then
xfred_started <= '1';
end if;
end if;
end process REG_XFRED_STARTED;
end generate GEN_FOR_FREE_RUN;
-- Not in free run so logic not needed
GEN_FOR_XTERN_FSYNC : if C_USE_FSYNC = 1 generate
begin
xfred_started <= '1';
end generate GEN_FOR_XTERN_FSYNC;
xfers_done <= '1' when (xfred_started='1' and all_lines_xfred = '1')
or stop = '1'
or halt = '1'
or run_stop = '0' --CR622584
else '0';
end generate GEN_DONE_FOR_SNF;
-- If store-and-foward off then do not need to keep track
GEN_DONE_NO_SNF : if C_INCLUDE_SF = 0 generate
begin
xfers_done <= '1';
end generate GEN_DONE_NO_SNF;
-------------------------------------------------------------------------------
-- Frame Size MisMatch (CR591965)
-------------------------------------------------------------------------------
-- Frame size mismatch for external frame sync
GEN_FSIZE_MISMATCH : if C_USE_FSYNC = 1 generate
begin
GEN_S2MM_MISMATCH_NON_FLUSH : if C_INCLUDE_S2MM = 1 and C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
-- Frame Size Mismatch Detection - Frame size mismatch error detection to detect when
-- VDMA channel configured for more lines than what could fit in a frame.
FSIZE_MISMATCH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
fsize_mismatch_err_int <= '0';
-- frame sync occurred when not all lines transferred
-- elsif(frame_sync = '1' and all_lines_xfred = '0')then
elsif(frame_sync = '1' and all_lasts_rcvd = '0')then
fsize_mismatch_err_int <= '1';
else
fsize_mismatch_err_int <= '0';
end if;
end if;
end process FSIZE_MISMATCH;
fsize_mismatch_err_flag_int_d2 <= '0';
s2mm_fsize_mismatch_err_s <= '0';
end generate GEN_S2MM_MISMATCH_NON_FLUSH;
GEN_S2MM_MISMATCH_FLUSH_NON_SOF : if C_INCLUDE_S2MM = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 0 generate
begin
-- Frame Size Mismatch Detection - Frame size mismatch error detection to detect when
-- VDMA channel configured for more lines than what could fit in a frame.
FSIZE_MISMATCH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
fsize_mismatch_err_int <= '0';
-- frame sync occurred when not all lines transferred
-- elsif(frame_sync = '1' and all_lines_xfred = '0')then
elsif(frame_sync = '1' and all_lasts_rcvd = '0')then
fsize_mismatch_err_int <= '1';
else
fsize_mismatch_err_int <= '0';
end if;
end if;
end process FSIZE_MISMATCH;
fsize_mismatch_err_flag_int_d2 <= '0';
s2mm_fsize_mismatch_err_s <= '0';
end generate GEN_S2MM_MISMATCH_FLUSH_NON_SOF;
GEN_S2MM_MISMATCH_FLUSH_SOF : if C_INCLUDE_S2MM = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 and C_S2MM_SOF_ENABLE = 1 generate
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
signal s2mm_fsync_out_m_d1 : std_logic := '0';
signal fsize_mismatch_err_s1 : std_logic := '0';
signal fsize_mismatch_err_s : std_logic := '0';
signal drop_fsync_d_pulse_gen_fsize_less_err_d1 : std_logic := '0';
begin
-- Frame Size Mismatch Detection - Frame size mismatch error detection to detect when
-- VDMA channel configured for more lines than what could fit in a frame.
FSIZE_MISMATCH_STRM_FLUSH_SOF : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk='1')then
if(scndry_resetn = '0')then
fsize_mismatch_err_s1 <= '0';
-- frame sync occurred when not all lines transferred
-- elsif(frame_sync = '1' and all_lines_xfred = '0')then
--elsif(s2mm_fsync_core = '1' and (s2mm_strm_all_lines_rcvd = '0' or drop_fsync_d_pulse_gen_fsize_less_err = '1'))then
elsif(s2mm_fsync_core = '1' and s2mm_strm_all_lines_rcvd = '0')then
fsize_mismatch_err_s1 <= '1';
else
fsize_mismatch_err_s1 <= '0';
end if;
end if;
end process FSIZE_MISMATCH_STRM_FLUSH_SOF;
D1_DROP_DELAY_FSYNC : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk = '1')then
if(scndry_resetn = '0')then
drop_fsync_d_pulse_gen_fsize_less_err_d1 <= '0';
else
drop_fsync_d_pulse_gen_fsize_less_err_d1 <= drop_fsync_d_pulse_gen_fsize_less_err;
end if;
end if;
end process D1_DROP_DELAY_FSYNC;
fsize_mismatch_err_s <= fsize_mismatch_err_s1 or drop_fsync_d_pulse_gen_fsize_less_err_d1 ;
s2mm_fsize_mismatch_err_s <= fsize_mismatch_err_s;
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---- FSIZE_MISMATCH_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_S_P_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => prmry_aclk ,
---- prmry_resetn => prmry_resetn ,
---- scndry_aclk => scndry_aclk ,
---- scndry_resetn => scndry_resetn ,
---- scndry_in => fsize_mismatch_err_s , -- Not Used
---- prmry_out => fsize_mismatch_err_int , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
FSIZE_MISMATCH_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => scndry_aclk,
prmry_resetn => scndry_resetn,
prmry_in => fsize_mismatch_err_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_aclk,
scndry_resetn => prmry_resetn,
scndry_out => fsize_mismatch_err_int,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
fsize_mismatch_err_int <= fsize_mismatch_err_s;
end generate GEN_FOR_SYNC;
D1_S2MM_FSYNC_OUT_M : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_fsync_out_m_d1 <= '0';
else
s2mm_fsync_out_m_d1 <= s2mm_fsync_out_m;
end if;
end if;
end process D1_S2MM_FSYNC_OUT_M;
FSIZE_LESS_ERR_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or s2mm_fsync_out_m_d1 = '1')then
fsize_mismatch_err_flag_int <= '0';
elsif(fsize_mismatch_err_int = '1')then
fsize_mismatch_err_flag_int <= '1';
end if;
end if;
end process FSIZE_LESS_ERR_FLAG;
fsize_mismatch_err_flag_int_d2 <= fsize_mismatch_err_flag_int or fsize_mismatch_err_int;
end generate GEN_S2MM_MISMATCH_FLUSH_SOF;
GEN_MM2S_MISMATCH_NO_FLUSH_SOF : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0)) generate
begin
-- Frame Size Mismatch Detection - Frame size mismatch error detection to detect when
-- VDMA channel configured for more lines than what could fit in a frame.
FSIZE_MISMATCH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
mm2s_fsize_mismatch_err_int <= '0';
-- frame sync occurred when not all lines transferred
elsif(frame_sync = '1' and all_lines_xfred = '0')then
mm2s_fsize_mismatch_err_int <= '1';
else
mm2s_fsize_mismatch_err_int <= '0';
end if;
end if;
end process FSIZE_MISMATCH;
s2mm_fsize_mismatch_err_s <= '0';
fsize_mismatch_err_flag_int_d2 <= '0';
fsize_mismatch_err_int <= mm2s_fsize_mismatch_err_int;
end generate GEN_MM2S_MISMATCH_NO_FLUSH_SOF;
GEN_MM2S_MISMATCH_FLUSH_SOF : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1)) generate
signal mm2s_fsync_out_m_d1 : std_logic := '0';
begin
fsize_mismatch_err_int <= mm2s_fsize_mismatch_err_m;
D1_MM2S_FSYNC_OUT_M : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mm2s_fsync_out_m_d1 <= '0';
else
mm2s_fsync_out_m_d1 <= mm2s_fsync_out_m;
end if;
end if;
end process D1_MM2S_FSYNC_OUT_M;
MM2S_FSIZE_LESS_ERR_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or mm2s_fsync_out_m_d1 = '1')then
fsize_mismatch_err_flag_int_d1 <= '0';
elsif(mm2s_fsize_mismatch_err_m = '1')then
fsize_mismatch_err_flag_int_d1 <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_ERR_FLAG;
fsize_mismatch_err_flag_int_d2 <= fsize_mismatch_err_flag_int_d1 or mm2s_fsize_mismatch_err_m;
s2mm_fsize_mismatch_err_s <= '0';
end generate GEN_MM2S_MISMATCH_FLUSH_SOF;
end generate GEN_FSIZE_MISMATCH;
-- No frame size mismatch if in free run mode
GEN_NO_FSIZE_MISMATCH : if C_USE_FSYNC = 0 generate
begin
fsize_mismatch_err_int <= '0';
fsize_mismatch_err_flag_int_d2 <= '0';
s2mm_fsize_mismatch_err_s <= '0';
end generate GEN_NO_FSIZE_MISMATCH;
fsize_mismatch_err_flag <= fsize_mismatch_err_flag_int_d2;
fsize_mismatch_err <= fsize_mismatch_err_int;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_ftch_sm.vhd
|
4
|
48085
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/10/10 v1_00_a
-- ^^^^^^
-- Fixed issue with fetch idle asserting too soon when simultaneous update
-- decode error and stale descriptor error detected. This fixes CR564855.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 12/07/10 v4_03
-- ^^^^^^
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under
-- associated generate
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant FETCH_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
when others =>
ftch_ns <= IDLE;
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
-- When command by sm, drive command to ftch_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cmnd_wr <= '0';
ftch_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
ftch_cmnd_wr <= '1';
ftch_cmnd_data <= FETCH_CMD_RSVD
& FETCH_CMD_TAG
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
else
ftch_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr <= fetch_cmd_addr;
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_ftch_sm.vhd
|
4
|
48085
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/10/10 v1_00_a
-- ^^^^^^
-- Fixed issue with fetch idle asserting too soon when simultaneous update
-- decode error and stale descriptor error detected. This fixes CR564855.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 12/07/10 v4_03
-- ^^^^^^
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under
-- associated generate
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant FETCH_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
when others =>
ftch_ns <= IDLE;
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
-- When command by sm, drive command to ftch_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cmnd_wr <= '0';
ftch_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
ftch_cmnd_wr <= '1';
ftch_cmnd_data <= FETCH_CMD_RSVD
& FETCH_CMD_TAG
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
else
ftch_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr <= fetch_cmd_addr;
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd
|
5
|
69152
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_noqueue.vhd
|
4
|
24781
|
-------------------------------------------------------------------------------
-- axi_sg_updt_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active,
s_axis_updtptr_tvalid,
s_axis_updtsts_tvalid,
s_axis_updtsts_tlast,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
write_curdesc_lsb <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= s_axis_updtsts_tvalid;
if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1'
and s_axis_updtsts_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not s_axis_updtsts_tvalid;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_noqueue.vhd
|
4
|
24781
|
-------------------------------------------------------------------------------
-- axi_sg_updt_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active,
s_axis_updtptr_tvalid,
s_axis_updtsts_tvalid,
s_axis_updtsts_tlast,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
write_curdesc_lsb <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= s_axis_updtsts_tvalid;
if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1'
and s_axis_updtsts_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not s_axis_updtsts_tvalid;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid_buf.vhd
|
18
|
18443
|
-------------------------------------------------------------------------------
-- axi_datamover_skid_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_datamover_skid_buf;
architecture implementation of axi_datamover_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
gpl-3.0
|
David-Estevez/spaceinvaders
|
src/edgeDetector_tb.vhd
|
1
|
2031
|
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector testbench
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity edgeDetector_tb is
end edgeDetector_tb;
architecture Behavioral of edgeDetector_tb is
-- Declare component:
component edgeDetector
port(
clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
end component;
-- Inputs
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal enable: std_logic := '0';
signal input: std_logic := '0';
-- Outputs
signal detected: std_logic;
-- clk period
constant clk_period: time := 20 ns;
begin
-- Instantiation of edgeDetector:
uut: edgeDetector
port map(
clk => clk,
reset => reset,
enable => enable,
input => input,
detected => detected
);
-- Clock signal
clk_process : process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-- Other stimulus
stim_process : process
begin
-- Reset circuit:
reset <= '0';
wait for 80 ns;
reset <= '1';
wait for 20 ns;
-- Test circuit with enable disabled:
enable <= '0';
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
-- Test circuit with enable enabled:
enable <= '1';
wait for 2*clk_period;
input <= '1';
wait for 2*clk_period;
input <= '0';
wait for 2*clk_period;
-- Test circuit with enable disabled again:
enable <= '0';
input <= '1';
wait for 3*clk_period;
input <= '0';
wait for clk_period;
wait;
end process;
end Behavioral;
|
gpl-3.0
|
viniciussmello/SistemasDigitais
|
Trabalho 2/Principal/MaquinaDeDividir.vhd
|
1
|
3063
|
--Bibliotecas Utilizadas
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--Declaração de entidade
entity MaquinaDeDividir is
GENERIC
(
n : NATURAL := 7 --Indica número de bits [0 --> 7]
);
port
(
clock: in std_logic; --Sinal de clock da Spartan3E
dividendo: in std_logic_vector(n downto 0); --Operador
divisor: in std_logic_vector(n downto 0); --Operador
resto: out std_logic_vector(n downto 0); --Resultado
quociente: out std_logic_vector(n downto 0); --Resultado
enable: in std_logic; --Habilita o funcionamento do módulo
finish: out std_logic;
reset: in std_logic
-- codigoErro: out integer --Flag de erro
);
end MaquinaDeDividir;
--Arquitetura da entidade BlocoDivisor
architecture ArcMaquinaDeDividir of MaquinaDeDividir is
begin
--Processo no qual a operação de divisão é realizada
Operacao : process (Dividendo, Divisor, clock)
--Declaração de variáveis
variable inicio: natural:= 0; --Marca o estágio da operação de divisão
variable numDiv: std_logic_vector(n downto 0);
variable UM : std_logic_vector(n downto 0) ;
variable Pquociente : std_logic_vector(n downto 0); --Resultado interno ao processo
variable Pdivisor : std_logic_vector(n downto 0); --Operador interno ao processo
variable Pdividendo : std_logic_vector(n downto 0); --Operador interno ao processo
variable Presto : std_logic_vector(n downto 0); --Resultado interno ao processo
variable numeroDividendo : std_logic_vector(n downto 0); --Vetor auxiliar
variable numeroQuociente: std_logic_vector(n downto 0);
variable t: std_logic_vector(n downto 0);
variable i: integer := n;
variable finishAuxiliar : std_logic := '0';
begin
if (rising_edge(clock) and enable = '1') then
if (inicio = 0) then
finishAuxiliar := '0';
Pdividendo := Dividendo;
Pdivisor := Divisor;
Pquociente := "00000000";
UM := "00000001"; --Variável que armazena o valor 1, em binário
inicio := 1;
elsif (inicio = 1) then
if (Pdivisor = "00000000") then
Resto <= "00000000";
Quociente <= "00000000";
inicio := 2;
else
varredorNumero: for i in n downto 0 loop
numeroDividendo := to_stdlogicvector(to_bitvector(pDividendo) srl i);
if (unsigned(numeroDividendo) >= unsigned(pDivisor))then
numeroQuociente := to_stdlogicvector(to_bitvector(um) sll i);
pQuociente := std_logic_vector(unsigned(pQuociente) + unsigned(numeroQuociente));
numDiv := to_stdlogicvector(to_bitvector(pDivisor) sll i);
t := pDividendo;
pDividendo := std_logic_vector(unsigned(t) - unsigned(numDiv));
end if;
end loop varredorNumero;
Resto <= pDividendo;
Quociente <= pQuociente;
inicio := 3;
end if;
end if;
if inicio = 3 then
finishAuxiliar := '1';
if (reset='1') then
inicio:=0;
end if;
else
finishAuxiliar := '0';
end if;
finish <= finishAuxiliar;
end if;
end process Operacao;
end ArcMaquinaDeDividir;
|
gpl-3.0
|
stefanct/aua
|
hw/io/sc_dummy/sim/dummy_tb.vhd
|
1
|
2407
|
library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity dummy_tb is
end dummy_tb;
architecture dummy_test of dummy_tb is
component sc_test_slave
generic(
sc_base_addr : sc_addr_t -- base = cycle setup register, base+1 = rd/wr test register
);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal address : sc_addr_t;
signal wr_data : sc_data_t;
signal rd : std_logic;
signal wr : std_logic;
signal rd_data : sc_data_t;
signal rdy_cnt : sc_rdy_cnt_t;
begin
sc_test_slave1: sc_test_slave
generic map ( x"FFFE"
)
port map (
clk,
reset,
address,
wr_data,
rd,
wr,
rd_data,
rdy_cnt
);
CLKGEN: process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset <= '1';
address <= x"DEAD";
wr_data <= (others => '0');
wr <= '0';
rd <= '0';
icwait(2);
reset <= '0';
-- test obs eh nix tut, wenn adress nicht aus dem bereich
wr_data <= x"12345678";
wr <= '1';
rd <= '1';
icwait(2);
-- schreibt "8" ins cycle control register (lowest 4 bits of wr_data)
rd <= '0';
address <= x"FFFE";
icwait(1);
-- schreibt ins daten register (transaction 8 cycles long)
wr <= '0';
wr_data <= x"12345678";
address <= x"FFFF";
wr <= '1';
icwait(1);
wr <= '0';
icwait(10);
-- das ganze wieder auslesen (auch 8 cycles)
wr_data <= x"00000000";
rd <= '1';
icwait(1);
rd <= '0';
icwait(9);
-- cycle control register auslesen
address <= x"FFFE";
rd <= '1';
icwait(1);
rd <= '0';
icwait(3);
assert false report "sim finish" SEVERITY failure;
end process TEST;
end dummy_test;
|
gpl-3.0
|
viniciussmello/SistemasDigitais
|
Trabalho 2/Principal/Main.vhd
|
1
|
6290
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY teste IS
PORT (
CLK_50M : IN std_logic; --Clock dado pela Spartan3 em Hz
PS2_CLK1 : IN std_logic; --Sinal de clock interno do teclado
PS2_DATA1 : IN std_logic; --Sinal de dados interno do teclado
seletorSaida: in std_logic; -- Switch utilizado para selecionar operacao a exibir
rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd
lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END teste;
ARCHITECTURE Arcteste OF teste IS
TYPE enviaAscii IS (resultSoma, DoisPontosS, Soma5, Soma4, Soma3, Soma2, Soma1, resultProd, Prod10, Prod9, Prod8, Prod7, Prod6, Prod5, Prod4, Prod3, Prod2, Prod1,
fim);
SIGNAL finishMaquina : std_logic;
SIGNAL entradaA : std_logic_vector(19 DOWNTO 0);
SIGNAL entradaB : std_logic_vector(19 DOWNTO 0);
SIGNAL saidaSomador : std_logic_vector(19 DOWNTO 0);
SIGNAL saidaMultiplicador : std_logic_vector(39 DOWNTO 0);
SIGNAL carryOut : std_logic;
SIGNAL MDDEnable, MDDfinish, MDDreset : std_logic;
SIGNAL reset_lcd, ativa_lcd, lcd_ocupado : std_logic;
SIGNAL receives_input : std_logic;
SIGNAL codigo_lcd : std_logic_vector(9 DOWNTO 0);
SIGNAL entradaA_S : unsigned(19 DOWNTO 0) := unsigned(entradaA);
SIGNAL entradaB_S : unsigned(19 DOWNTO 0) := unsigned(entradaB);
SIGNAL saidaSomador_S : unsigned(19 DOWNTO 0) := (others => '0');
SIGNAL carryOut_S : unsigned(3 DOWNTO 0) := (others => '0');
SIGNAL saidaMultiplicador_S : unsigned(39 DOWNTO 0) := (others => '0');
SIGNAL enviaLCD : enviaAscii := resultSoma;
BEGIN
Controlador_LCD : ENTITY work.lcd_controller
PORT MAP(CLK_50M, reset_lcd, ativa_lcd, codigo_lcd, lcd_ocupado, rw, rs, e, lcd_data);
MaquinaDeEstadosPrincipal : ENTITY work.MaquinaDeEstadosPrincipal
PORT MAP(CLK_50M, PS2_CLK1, PS2_DATA1, entradaA, entradaB, finishMaquina, MDDreset);
Multiplicador : ENTITY work.MultBcd_5x5Dig
PORT MAP(
EntradaA => entradaA_S,
EntradaB => entradaB_S,
saidaZ => saidaMultiplicador_S
);
Somador : ENTITY work.bcd_5_digit_adder
PORT MAP(
Entrada1 => entradaA_S,
Entrada2 => entradaB_S,
sum => saidaSomador_S,
carry => carryOut_S
);
PROCESS (CLK_50M, finishMaquina, MDDfinish, MDDreset)
BEGIN
IF (CLK_50M'EVENT AND CLK_50M = '1') THEN
IF (finishMaquina = '1') THEN
MDDenable <= '1';
ELSE
MDDenable <= '0';
END IF;
IF (MDDfinish = '1') THEN
receives_input <= '1';
ELSE
receives_input <= '0';
END IF;
IF (MDDreset = '1') THEN
reset_lcd <= '0';
enviaLCD <= resultSoma;
ELSE
reset_lcd <= '1';
END IF;
IF (lcd_ocupado = '0' AND ativa_lcd = '0') THEN
IF (seletorSaida = '0') THEN --Exibe soma
CASE (enviaLCD) IS
WHEN resultSoma => -- Exibe S
ativa_lcd <= '1';
codigo_lcd <= "10" & "0101" & "0011";
enviaLCD <= DoisPontosS;
WHEN DoisPontosS => -- Exibe :
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & "1010";
enviaLCD <= Soma5;
WHEN Soma5 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(19 downto 16);
enviaLCD <= Soma4;
WHEN Soma4 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(15 downto 12);
enviaLCD <= Soma3;
WHEN Soma3 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(11 downto 8);
enviaLCD <= Soma2;
WHEN Soma2 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(7 downto 4);
enviaLCD <= Soma1;
WHEN Soma1 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(3 downto 0);
enviaLCD <= fim;
WHEN fim =>
ativa_lcd <= '0';
WHEN others =>
ativa_lcd <= '0';
END CASE;
ELSE -- Exibe Produto
CASE enviaLCD IS
WHEN resultProd => -- Exibe P
ativa_lcd <= '1';
codigo_lcd <= "10" & "0101" & "0000";
enviaLCD <= DoisPontosS;
WHEN DoisPontosS => -- Exibe :
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & "1010";
enviaLCD <= Prod10;
WHEN Prod10 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(39 downto 36);
enviaLCD <= Prod9;
WHEN Prod9 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(35 downto 32);
enviaLCD <= Prod8;
WHEN Prod8 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(31 downto 28);
enviaLCD <= Prod7;
WHEN Prod7 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(27 downto 24);
enviaLCD <= Prod6;
WHEN Prod6 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(23 downto 20);
enviaLCD <= Prod5;
WHEN Prod5 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(19 downto 16);
enviaLCD <= Prod4;
WHEN Prod4 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(15 downto 12);
enviaLCD <= Prod3;
WHEN Prod3 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(11 downto 8);
enviaLCD <= Prod2;
WHEN Prod2 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(7 downto 4);
enviaLCD <= Prod1;
WHEN Prod1 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(3 downto 0);
enviaLCD <= fim;
WHEN fim =>
ativa_lcd <= '0';
WHEN others =>
ativa_lcd <= '0';
END CASE;
END IF; -- Fim: if(seletorSaida = '0')
ELSE
ativa_lcd <= '0';
END IF; -- Fim: if(lcd_ocupado = '0' AND ativa_lcd = '0')
END IF; -- Fim: if(CLK_50M'event and CLK_50M='1')
END PROCESS;
END Arcteste;
|
gpl-3.0
|
viniciussmello/SistemasDigitais
|
Trabalho 2/Somador/bcd_adder.vhd
|
2
|
649
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bcd_adder IS
PORT (
a, b : IN unsigned(3 DOWNTO 0); -- input numbers.
carry_in : IN unsigned (3 DOWNTO 0);
sum : OUT unsigned(3 DOWNTO 0);
carry : OUT unsigned(3 DOWNTO 0)
);
END bcd_adder;
ARCHITECTURE arch OF bcd_adder IS
BEGIN
PROCESS (a, b, carry_in)
VARIABLE sum_temp : unsigned(4 DOWNTO 0);
BEGIN
sum_temp := (('0' & a) + ('0' & b)) + ('0' & carry_in);
IF (sum_temp > 9) THEN
carry <= "0001";
sum <= resize((sum_temp + "00110"), 4);
ELSE
carry <= "0000";
sum <= sum_temp(3 DOWNTO 0);
END IF;
END PROCESS;
END arch;
|
gpl-3.0
|
stefanct/aua
|
hw/io/sc_uart/src/fifo.vhd
|
1
|
3525
|
--
--
-- This file is a part of JOP, the Java Optimized Processor
--
-- Copyright (C) 2001-2008, Martin Schoeberl ([email protected])
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- fifo.vhd
--
-- simple fifo
--
-- uses FF and every rd or wr has to 'bubble' through the hole fifo.
--
-- Author: Martin Schoeberl [email protected]
--
--
-- resources on ACEX1K
--
-- (width+2)*depth-1 LCs
--
--
-- 2002-01-06 first working version
-- 2002-11-03 a signal for reaching threshold
-- 2005-02-20 change entity order for modelsim vcom
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end fifo_elem;
architecture rtl of fifo_elem is
signal buf : std_logic_vector(width-1 downto 0);
signal f : std_logic;
begin
dout <= buf;
process(clk, reset, f)
begin
full <= f;
if (reset='1') then
buf <= (others => '0');
f <= '0';
rd_prev <= '0';
elsif rising_edge(clk) then
rd_prev <= '0';
if f='0' then
if wr='1' then
rd_prev <= '1';
buf <= din;
f <= '1';
end if;
else
if rd='1' then
f <= '0';
end if;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic (width : integer := 8; depth : integer := 4; thres : integer := 2);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
half : out std_logic
);
end fifo ;
architecture rtl of fifo is
component fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end component;
signal r, w, rp, f : std_logic_vector(depth-1 downto 0);
type d_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal di, do : d_array;
begin
g1: for i in 0 to depth-1 generate
f1: fifo_elem generic map (width)
port map (clk, reset, di(i), do(i), r(i), w(i), rp(i), f(i));
x: if i<depth-1 generate
r(i) <= rp(i+1);
w(i+1) <= f(i);
di(i+1) <= do(i);
end generate;
end generate;
di(0) <= din;
dout <= do(depth-1);
w(0) <= wr;
r(depth-1) <= rd;
full <= f(0);
half <= f(depth-thres);
empty <= not f(depth-1);
end rtl;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m3_@b@f@m/_primary.vhd
|
3
|
5944
|
library verilog;
use verilog.vl_types.all;
entity M3_BFM is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 0;
DEBUGLEVEL : integer := 3;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
SYSREG_HRDATA : in vl_logic_vector(31 downto 0);
SYSREG_HREADY : in vl_logic;
SYSREG_HRESP : in vl_logic;
SYSREG_HADDR : out vl_logic_vector(11 downto 0);
SYSREG_HBURST : out vl_logic_vector(2 downto 0);
SYSREG_HMASTLOCK: out vl_logic;
SYSREG_HPROT : out vl_logic_vector(3 downto 0);
SYSREG_HSIZE : out vl_logic_vector(2 downto 0);
SYSREG_HTRANS : out vl_logic_vector(1 downto 0);
SYSREG_HWRITE : out vl_logic;
SYSREG_HWDATA : out vl_logic_vector(31 downto 0);
SYSREG_HSEL : out vl_logic;
INTERRUPT : in vl_logic_vector(255 downto 0)
);
end M3_BFM;
|
gpl-3.0
|
kristofferkoch/ethersound
|
txcrc.vhd
|
1
|
6560
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:53:34 07/04/2008
-- Design Name:
-- Module Name: txcrc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity txcrc is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data_o : out STD_LOGIC_VECTOR (7 downto 0);
data_send : out STD_LOGIC;
data_o_req : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR (7 downto 0);
data_i_v : in STD_LOGIC;
data_i_req : out STD_LOGIC);
end txcrc;
architecture Behavioral of txcrc is
function nextCRC32_D8 (
Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0)
) return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NewCRC: std_logic_vector(31 downto 0);
begin
-- D(0) := Data(7);
-- D(1) := Data(6);
-- D(2) := Data(5);
-- D(3) := Data(4);
-- D(4) := Data(3);
-- D(5) := Data(2);
-- D(6) := Data(1);
-- D(7) := Data(0);
D(0) := Data(3);
D(1) := Data(2);
D(2) := Data(1);
D(3) := Data(0);
D(4) := Data(7);
D(5) := Data(6);
D(6) := Data(5);
D(7) := Data(4);
C := CRC;
NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30);
NewCRC(1) := D(7) xor D(6) xor D(1) xor D(0) xor C(24) xor C(25) xor
C(30) xor C(31);
NewCRC(2) := D(7) xor D(6) xor D(2) xor D(1) xor D(0) xor C(24) xor
C(25) xor C(26) xor C(30) xor C(31);
NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(25) xor C(26) xor
C(27) xor C(31);
NewCRC(4) := D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(24) xor
C(26) xor C(27) xor C(28) xor C(30);
NewCRC(5) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(1) xor
D(0) xor C(24) xor C(25) xor C(27) xor C(28) xor C(29) xor
C(30) xor C(31);
NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor
C(25) xor C(26) xor C(28) xor C(29) xor C(30) xor C(31);
NewCRC(7) := D(7) xor D(5) xor D(3) xor D(2) xor D(0) xor C(24) xor
C(26) xor C(27) xor C(29) xor C(31);
NewCRC(8) := D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor C(24) xor
C(25) xor C(27) xor C(28);
NewCRC(9) := D(5) xor D(4) xor D(2) xor D(1) xor C(1) xor C(25) xor
C(26) xor C(28) xor C(29);
NewCRC(10) := D(5) xor D(3) xor D(2) xor D(0) xor C(2) xor C(24) xor
C(26) xor C(27) xor C(29);
NewCRC(11) := D(4) xor D(3) xor D(1) xor D(0) xor C(3) xor C(24) xor
C(25) xor C(27) xor C(28);
NewCRC(12) := D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor
C(4) xor C(24) xor C(25) xor C(26) xor C(28) xor C(29) xor
C(30);
NewCRC(13) := D(7) xor D(6) xor D(5) xor D(3) xor D(2) xor D(1) xor
C(5) xor C(25) xor C(26) xor C(27) xor C(29) xor C(30) xor
C(31);
NewCRC(14) := D(7) xor D(6) xor D(4) xor D(3) xor D(2) xor C(6) xor
C(26) xor C(27) xor C(28) xor C(30) xor C(31);
NewCRC(15) := D(7) xor D(5) xor D(4) xor D(3) xor C(7) xor C(27) xor
C(28) xor C(29) xor C(31);
NewCRC(16) := D(5) xor D(4) xor D(0) xor C(8) xor C(24) xor C(28) xor
C(29);
NewCRC(17) := D(6) xor D(5) xor D(1) xor C(9) xor C(25) xor C(29) xor
C(30);
NewCRC(18) := D(7) xor D(6) xor D(2) xor C(10) xor C(26) xor C(30) xor
C(31);
NewCRC(19) := D(7) xor D(3) xor C(11) xor C(27) xor C(31);
NewCRC(20) := D(4) xor C(12) xor C(28);
NewCRC(21) := D(5) xor C(13) xor C(29);
NewCRC(22) := D(0) xor C(14) xor C(24);
NewCRC(23) := D(6) xor D(1) xor D(0) xor C(15) xor C(24) xor C(25) xor
C(30);
NewCRC(24) := D(7) xor D(2) xor D(1) xor C(16) xor C(25) xor C(26) xor
C(31);
NewCRC(25) := D(3) xor D(2) xor C(17) xor C(26) xor C(27);
NewCRC(26) := D(6) xor D(4) xor D(3) xor D(0) xor C(18) xor C(24) xor
C(27) xor C(28) xor C(30);
NewCRC(27) := D(7) xor D(5) xor D(4) xor D(1) xor C(19) xor C(25) xor
C(28) xor C(29) xor C(31);
NewCRC(28) := D(6) xor D(5) xor D(2) xor C(20) xor C(26) xor C(29) xor
C(30);
NewCRC(29) := D(7) xor D(6) xor D(3) xor C(21) xor C(27) xor C(30) xor
C(31);
NewCRC(30) := D(7) xor D(4) xor C(22) xor C(28) xor C(31);
NewCRC(31) := D(5) xor C(23) xor C(29);
return NewCRC;
end nextCRC32_D8;
-- type state_t is (Idle, TX, st_CRC);
-- signal state:state_t;
--
-- signal ireg:std_logic_vector(7 downto 0);
-- signal counter:integer range 0 to 3;
-- signal crc, nextcrc:std_logic_vector(31 downto 0);
begin
data_o <= data_i when state = stCRC else crcmux;
-- nextcrc <= nextCRC32_D8(ireg, crc);
-- process(sysclk) is
-- begin
-- if rising_edge(sysclk) then
-- if reset = '1' then
-- data_i_req <= '0';
-- data_send <= '0';
-- state <= Idle;
-- crc <= (OTHERS => '1');
-- data_o <= (OTHERS => '0');
-- else
-- case state is
-- when TX =>
-- if data_o_req = '1' then
-- data_o <= ireg;
-- crc <= nextcrc;
-- data_send <= '1';
-- data_i_req <= '1';
-- else
-- data_i_req <= '0';
-- end if;
-- if data_i_v = '1' then
-- ireg <= data_i;
-- else
-- state <= st_CRC;
-- counter <= 3;
-- ireg <= (OTHERS => '0');
-- end if;
-- when st_CRC =>
-- if data_o_req = '1' then
-- --data_o <= crc(counter*8+7 downto counter*8);
-- data_o(7) <= not crc(counter*8);
-- data_o(6) <= not crc(counter*8+1);
-- data_o(5) <= not crc(counter*8+2);
-- data_o(4) <= not crc(counter*8+3);
-- data_o(3) <= not crc(counter*8+4);
-- data_o(2) <= not crc(counter*8+5);
-- data_o(1) <= not crc(counter*8+6);
-- data_o(0) <= not crc(counter*8+7);
--
-- if counter = 0 then
-- state <= Idle;
-- data_i_req <= '1';
-- else
-- counter <= counter - 1;
-- data_i_req <= '0';
-- end if;
-- end if;
-- when others => --Idle
-- crc <= (OTHERS => '1');
-- if data_o_req = '1' then
-- data_send <= '0';
-- end if;
-- if data_i_v = '1' then
-- ireg <= data_i;
-- data_i_req <= '0';
-- state <= TX;
-- else
-- data_i_req <= '1';
-- end if;
-- end case;
-- end if;
-- end if;
-- end process;
end Behavioral;
|
gpl-3.0
|
kristofferkoch/ethersound
|
deltasigmachannel.vhd
|
1
|
1960
|
-----------------------------------------------------------------------------
-- Delta-sigma modulator
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity deltasigmachannel is
Generic(N:integer:=10);
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (N-1 downto 0);
ds : out STD_LOGIC);
end deltasigmachannel;
architecture Behavioral of deltasigmachannel is
signal deltaAdder, sigmaAdder, sigmaReg, deltaB:unsigned(N+1 downto 0);
constant zeros:std_logic_vector(N-1 downto 0):= (OTHERS => '0');
signal hbit:std_logic;
begin
hbit <= sigmaReg(N+1);
deltaB <= unsigned(hbit & hbit & zeros);
deltaAdder <= unsigned(data) + deltaB;
sigmaAdder <= deltaAdder + sigmaReg;
process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
ds <= '0';
sigmaReg <= unsigned("01" & zeros);
else
sigmaReg <= sigmaAdder;
ds <= sigmaReg(N+1);
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@s@s@e/_primary.vhd
|
3
|
4539
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
HCLK : in vl_logic;
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
PPE_FIFO_FULL : in vl_logic;
PC0_FLAGS : out vl_logic_vector(3 downto 0);
PC1_FLAGS : out vl_logic_vector(3 downto 0);
PC2_FLAGS : out vl_logic_vector(3 downto 0);
ADC0_CALIBRATE_rise: out vl_logic;
ADC1_CALIBRATE_rise: out vl_logic;
ADC2_CALIBRATE_rise: out vl_logic;
ADC0_CALIBRATE_fall: out vl_logic;
ADC1_CALIBRATE_fall: out vl_logic;
ADC2_CALIBRATE_fall: out vl_logic;
ADC0_DATAVALID_rise: out vl_logic;
ADC1_DATAVALID_rise: out vl_logic;
ADC2_DATAVALID_rise: out vl_logic;
FPGA_TRIGGER : in vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
OBD_FPGA0_CLKOUT: in vl_logic;
OBD_FPGA1_CLKOUT: in vl_logic;
OBD_FPGA2_CLKOUT: in vl_logic;
OBD_FPGA0_DOUT : in vl_logic;
OBD_FPGA1_DOUT : in vl_logic;
OBD_FPGA2_DOUT : in vl_logic;
OBD_DOUT0 : out vl_logic;
OBD_DOUT1 : out vl_logic;
OBD_DOUT2 : out vl_logic;
OBD_CLKOUT0 : out vl_logic;
OBD_CLKOUT1 : out vl_logic;
OBD_CLKOUT2 : out vl_logic;
OBD_ENABLE0 : out vl_logic;
OBD_ENABLE1 : out vl_logic;
OBD_ENABLE2 : out vl_logic;
INREADY : out vl_logic;
SSE_ADC0_RESULTS: out vl_logic;
SSE_ADC1_RESULTS: out vl_logic;
SSE_ADC2_RESULTS: out vl_logic
);
end F2DSS_SSE;
|
gpl-3.0
|
kristofferkoch/ethersound
|
tb_deltasigmadac.vhd
|
1
|
2854
|
-----------------------------------------------------------------------------
-- Testbench for deltasigmadac
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_deltasigmadac IS
END tb_deltasigmadac;
ARCHITECTURE behavior OF tb_deltasigmadac IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT deltasigmadac
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
audio : IN std_logic_vector(23 downto 0);
audio_dv : IN std_logic;
audio_left : OUT std_logic;
audio_right : OUT std_logic
);
END COMPONENT;
--Inputs
signal sysclk : std_logic := '0';
signal reset : std_logic := '0';
signal audio : std_logic_vector(23 downto 0) := (others => '0');
signal audio_dv : std_logic := '0';
--Outputs
signal audio_left : std_logic;
signal audio_right : std_logic;
-- Clock period definitions
constant sysclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: deltasigmadac PORT MAP (
sysclk => sysclk,
reset => reset,
audio => audio,
audio_dv => audio_dv,
audio_left => audio_left,
audio_right => audio_right
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for sysclk_period*10;
reset <= '0';
wait for sysclk_period;
audio_dv <= '1';
audio <= x"123456";
wait for sysclk_period;
audio_dv <= '0';
wait for sysclk_period*4;
audio_dv <= '1';
audio <= x"FFFFFF";
wait for sysclk_period;
audio_dv <= '0';
wait for sysclk_period*4;
wait;
end process;
END;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f@a@b@r@i@c@i@f_@f@m/_primary.vhd
|
3
|
1609
|
library verilog;
use verilog.vl_types.all;
entity FABRICIF_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
APB16_XHOLD : out vl_logic_vector(15 downto 0);
DS_FM_HADDR : out vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : out vl_logic;
DS_FM_HSIZE : out vl_logic_vector(1 downto 0);
DS_FM_HTRANS1 : out vl_logic;
DS_FM_HWRITE : out vl_logic;
DS_FM_HWDATA : out vl_logic_vector(31 downto 0);
DS_FM_HRDATA : in vl_logic_vector(31 downto 0);
DS_FM_HREADY : in vl_logic;
DS_FM_HRESP : in vl_logic;
F_FM_ADDR : in vl_logic_vector(31 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_HMASTLOCK : in vl_logic;
F_FM_HSIZE : in vl_logic_vector(1 downto 0);
F_FM_HTRANS1 : in vl_logic;
F_FM_HWRITE : in vl_logic;
F_FM_HSEL : in vl_logic;
F_FM_HREADY : in vl_logic;
F_FM_HREADYOUT : out vl_logic;
F_FM_HRESP : out vl_logic;
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic
);
end FABRICIF_FM;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@c@m@slave@stage/_primary.vhd
|
3
|
2678
|
library verilog;
use verilog.vl_types.all;
entity CMSlaveStage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
HREADYOUT : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS1 : out vl_logic;
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HREADY_S : out vl_logic;
HMASTLOCK : out vl_logic;
COM_WEIGHTEDMODE: in vl_logic;
mAddrSel : in vl_logic_vector(4 downto 0);
mDataSel : in vl_logic_vector(4 downto 0);
mPrevDataSlaveReady: in vl_logic_vector(4 downto 0);
mAddrReady : out vl_logic_vector(4 downto 0);
mDataReady : out vl_logic_vector(4 downto 0);
mHResp : out vl_logic_vector(4 downto 0);
m0GatedHADDR : in vl_logic_vector(31 downto 0);
m0GatedHMASTLOCK: in vl_logic;
m0GatedHSIZE : in vl_logic_vector(2 downto 0);
m0GatedHTRANS1 : in vl_logic;
m0GatedHWRITE : in vl_logic;
m1GatedHADDR : in vl_logic_vector(31 downto 0);
m1GatedHMASTLOCK: in vl_logic;
m1GatedHSIZE : in vl_logic_vector(2 downto 0);
m1GatedHTRANS1 : in vl_logic;
m1GatedHWRITE : in vl_logic;
m2GatedHADDR : in vl_logic_vector(31 downto 0);
m2GatedHMASTLOCK: in vl_logic;
m2GatedHSIZE : in vl_logic_vector(2 downto 0);
m2GatedHTRANS1 : in vl_logic;
m2GatedHWRITE : in vl_logic;
m3GatedHADDR : in vl_logic_vector(31 downto 0);
m3GatedHMASTLOCK: in vl_logic;
m3GatedHSIZE : in vl_logic_vector(2 downto 0);
m3GatedHTRANS1 : in vl_logic;
m3GatedHWRITE : in vl_logic;
m4GatedHADDR : in vl_logic_vector(31 downto 0);
m4GatedHMASTLOCK: in vl_logic;
m4GatedHSIZE : in vl_logic_vector(2 downto 0);
m4GatedHTRANS1 : in vl_logic;
m4GatedHWRITE : in vl_logic;
HWDATA_M0 : in vl_logic_vector(31 downto 0);
HWDATA_M1 : in vl_logic_vector(31 downto 0);
HWDATA_M2 : in vl_logic_vector(31 downto 0);
HWDATA_M3 : in vl_logic_vector(31 downto 0);
HWDATA_M4 : in vl_logic_vector(31 downto 0)
);
end CMSlaveStage;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@c@m@master3@stage/_primary.vhd
|
3
|
1817
|
library verilog;
use verilog.vl_types.all;
entity CMMaster3Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic
);
end CMMaster3Stage;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@s@s@e_@a@p@b3_@p@p@e_@i@f/_primary.vhd
|
3
|
1348
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
SSE_RWB : out vl_logic;
SSE_ADDR : out vl_logic_vector(9 downto 0);
SSE_WDATA : out vl_logic_vector(15 downto 0);
SSE_RDATA : in vl_logic_vector(15 downto 0);
PDMA_decode : out vl_logic
);
end F2DSS_SSE_APB3_PPE_IF;
|
gpl-3.0
|
beiko-lab/gengis
|
bin/Lib/site-packages/wx-2.8-msw-unicode/wx/tools/Editra/tests/syntax/vhdl.vhdl
|
9
|
985
|
-- Syntax Highlighting Test File for VHDL
-- Comments are like this
-- Hello World in VHDL
entity hello_world is
end;
architecture hello_world of hello_world is
begin
stimulus : process
begin
assert false report "Hello World By Deepak"
severity note;
wait;
end process stimulus;
end hello_world;
-- A simple counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
gpl-3.0
|
fgr1986/ddr_MIG_ctrl_interface
|
src/hdl/ram_ddr_wrapper.vhd
|
1
|
22959
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Fernando García Redondo, [email protected]
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Create Date: 26/07/2017
-- Design Name: Nexys4 DDR RAM/DDR2/DDR3 Interface
-- Module Name: ram_ddr_wrapper - behavioral
-- Project Name: ram_ddr_wrapper
-- Target Devices: Nexys4 DDR Development Board, containing a XC7a100t-1 csg324 device
-- Tool versions:
-- Description:
--
-- IMPORTANT: This ddr_xadc module includes already an xadc instance. Do not instantiate outside.
-- IMPORTANT: If xadc is instantiated outside, use ddr IP (not ddr_xadc) and drive to ddr instance
-- IMPORTANT: the xadc sensed temperature.
--
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Project library
library work;
use work.ram_ddr_MIG7_interface_pkg.ALL;
entity ram_ddr_wrapper is
port (
-- Common
clk_200MHz_i : in std_logic;
rst_i : in std_logic;
-- ram control interface
ram_rnw_i : in std_logic; -- operation to be done : 0->READ, 1->WRITE
ram_addr_i : in std_logic_vector(c_DATA_ADDRESS_WIDTH-1 downto 0);
ram_new_instr_i : in std_logic; -- cs, '1' starts operation
ram_new_ack_o : out std_logic; -- ack between clk domains
ram_end_op_i : in std_logic; -- '1' ends the current write or read operation
-- for high performance consecutive writes or reads
ram_rd_ack_o : out std_logic;
ram_rd_valid_o : out std_logic;
ram_wr_ack_o : out std_logic;
ram_data_to_i : in std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_data_from_o : out std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
ram_available_o : out std_logic; -- when available for a different command
-- write to read, read to write
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface
ddr2_addr : out std_logic_vector(c_DDR_ADDRESS_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0)
);
end ram_ddr_wrapper;
architecture behavioral of ram_ddr_wrapper is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr_xadc
port (
-- Inouts
ddr2_dq : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(c_DDR_ADDRESS_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(c_DDR_CMD_WIDTH-1 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
-- device_temp_i : in ...,
init_calib_complete : out std_logic );
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (st_IDLE, st_PREP_OP, st_SEND_WRITE,
st_SEND_READ, st_WAIT_NEXT_WRITE, st_WAIT_NEXT_READ);
------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------
constant c_MASK_DIFF : positive := c_DDR_WDF_MASK_WIDTH - (c_APP_DATA_WIDTH-c_DATA_2_MEM_WIDTH)/8;
--report "The value of 'c_MASK_DIFF' is " & integer'image(c_MASK_DIFF);
constant c_MASK : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0)
:= (c_DDR_WDF_MASK_WIDTH-1 downto c_MASK_DIFF => '1')
& (c_MASK_DIFF-1 downto 0 => '0');
--------------------------------------
-- Signals
--------------------------------------
-- state machine
signal st_state, st_next_state : state_type;
-- active-low reset for the MIG component
signal s_rstn : std_logic;
signal s_rst_d2 : std_logic_vector(1 downto 0);
-- double registered imputs
signal s_ram_rnw_pre : std_logic;
signal s_ram_rnw : std_logic;
signal s_ram_new_instr : std_logic;
signal s_ram_new_instr_pre : std_logic;
signal s_ram_end_op_pre : std_logic;
signal s_ram_end_op : std_logic;
signal s_ram_data_to_pre : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_data_to : std_logic_vector(c_DATA_2_MEM_WIDTH-1 downto 0);
signal s_ram_addr_pre : std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0);
----------------------------------------
-- We will use 'mem_ui_' for UI with ddr
-- ddr user interface signals
--------------------------------------
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal mem_ui_addr : std_logic_vector(c_APP_DATA_ADDRESS_WIDTH-1 downto 0); -- address for current request
signal mem_ui_cmd : std_logic_vector(c_DDR_CMD_WIDTH-1 downto 0); -- command for current request
signal mem_ui_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_ui_wdf_data : std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
signal mem_ui_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_ui_wdf_mask : std_logic_vector(c_DDR_WDF_MASK_WIDTH-1 downto 0);
signal mem_ui_wdf_wren : std_logic;
signal mem_ui_rd_data : std_logic_vector(c_APP_DATA_WIDTH-1 downto 0);
signal mem_ui_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_ui_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal s_calib_complete : std_logic; -- active-high calibration complete
-- enables the sending of CMD to the ddr (1 pulse per command)
signal mem_ui_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
-- if HIGH, the CMD sent when mem_ui_en is HIGH has been accepted
signal mem_ui_rdy : std_logic;
-- registered ack 1 clk pulses
signal s_ram_rd_ack : std_logic;
signal s_ram_wr_ack : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
-- delay because of FSM
------------------------------------------------------------------------
p_rst_sync: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
s_rst_d2 <= s_rst_d2(0) & rst_i;
s_rstn <= not s_rst_d2(1);
end if;
end process p_rst_sync;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
inst_ddr_xadc: ddr_xadc
port map (
-- IOB outputs [Physical Interface]
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => s_rstn,
-- user interface signals
app_addr => mem_ui_addr,
app_cmd => mem_ui_cmd,
app_en => mem_ui_en,
app_wdf_data => mem_ui_wdf_data,
app_wdf_end => mem_ui_wdf_end,
app_wdf_mask => mem_ui_wdf_mask,
app_wdf_wren => mem_ui_wdf_wren,
app_rd_data => mem_ui_rd_data,
app_rd_data_end => mem_ui_rd_data_end,
app_rd_data_valid => mem_ui_rd_data_valid,
app_rdy => mem_ui_rdy,
app_wdf_rdy => mem_ui_wdf_rdy,
app_sr_req => '0', -- see UG586
app_sr_active => open,
app_ref_req => '0', -- see UG586
app_ref_ack => open,
app_zq_req => '0', -- see UG586
app_zq_ack => open,
ui_clk => mem_ui_clk, -- 1/2 or 1/4 of 200Mhz clk, see UG586
ui_clk_sync_rst => mem_ui_rst,
-- device_temp_i => device_temp_i,
init_calib_complete => s_calib_complete
);
------------------------------------------------------------------------
-- Registering handshake ack
------------------------------------------------------------------------
p_new_instr_ack: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' or s_calib_complete='0' then
ram_new_ack_o <= '0';
else
ram_new_ack_o <= ram_new_instr_i;
end if;
end if;
end process p_new_instr_ack;
------------------------------------------------------------------------
-- Double Registering all ctrl inputs to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_in_ctrl: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' then
-- pre-signals
s_ram_rnw_pre <= '0';
s_ram_new_instr_pre <= '0';
s_ram_end_op_pre <= '0';
-- valid signals (faster domain)
s_ram_rnw <= '0';
s_ram_new_instr <= '0';
s_ram_end_op <= '0';
else
-- pre-signals
s_ram_rnw_pre <= ram_rnw_i;
s_ram_new_instr_pre <= ram_new_instr_i;
s_ram_end_op_pre <= ram_end_op_i;
-- valid signals (faster domain)
if s_ram_new_instr = '0' then
s_ram_new_instr <= s_ram_new_instr_pre;
else
s_ram_new_instr <= '0';
end if;
if s_ram_end_op = '0' then
s_ram_end_op <= s_ram_end_op_pre;
else
s_ram_end_op <= '0';
end if;
-- valid signals with no pulse control
s_ram_rnw <= s_ram_rnw_pre;
end if;
end if;
end process p_reg_in_ctrl;
------------------------------------------------------------------------
-- Double Registering all data inputs to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_in_data: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' then
-- pre-signals
s_ram_addr_pre <= (others => '0');
s_ram_data_to_pre <= (others => '0');
-- valid signals (faster domain)
mem_ui_addr <= (others => '0');
s_ram_data_to <= (others => '0');
else
-- pre-signals
s_ram_addr_pre <= '0' & ram_addr_i; -- rank in DDR2 MT47H64M16HR-25 is '0'
s_ram_data_to_pre <= ram_data_to_i;
-- valid signals (faster domain)
-- with control
if s_ram_new_instr_pre='1' then
mem_ui_addr <= s_ram_addr_pre;
s_ram_data_to <= s_ram_data_to_pre;
end if;
end if;
end if;
end process p_reg_in_data;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
p_sync_FSM: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
st_state <= st_IDLE;
else
st_state <= st_next_state;
end if;
end if;
end process p_sync_FSM;
-- Next state logic
p_next_state: process(st_state, s_calib_complete, s_ram_new_instr,
s_ram_rnw, mem_ui_rdy, mem_ui_wdf_rdy, s_ram_end_op)
begin
st_next_state <= st_state;
case(st_state) is
-- If calibration is done successfully
when st_IDLE =>
-- comment for simulation
if s_calib_complete = '1' then
st_next_state <= st_PREP_OP;
end if;
-- In st_PREP_OP We store address (for write/read) and data (for write)
-- operates if conditions are met
when st_PREP_OP =>
if s_ram_new_instr = '1' then
if s_ram_rnw = '1' then
st_next_state <= st_SEND_WRITE;
elsif s_ram_rnw = '0' then
st_next_state <= st_SEND_READ;
end if;
end if;
-- We send write the command until accepted (mem_ui_rdy = '1')
when st_SEND_WRITE =>
-- end operation if s_ram_new_instr (registered for delay) is deaserted
if mem_ui_rdy = '1' and mem_ui_wdf_rdy='1' then
st_next_state <= st_WAIT_NEXT_WRITE;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when st_WAIT_NEXT_WRITE =>
if s_ram_new_instr = '1' then
st_next_state <= st_SEND_WRITE;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
-- We send write the command until accepted (mem_ui_rdy = '1')
when st_SEND_READ =>
-- end operation if s_ram_new_instr (registered for delay) is deaserted
if mem_ui_rdy = '1' then
st_next_state <= st_WAIT_NEXT_READ;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when st_WAIT_NEXT_READ =>
if s_ram_new_instr = '1' then
st_next_state <= st_SEND_READ;
elsif s_ram_end_op = '1' then
st_next_state <= st_PREP_OP;
end if;
when others => st_next_state <= st_IDLE;
end case;
end process;
---------------------------------------------------------------
-- Memory control
-- Creates mem_ui_en pulse
---------------------------------------------------------------
p_mem_ctrl: process(st_state, mem_ui_wdf_rdy)
begin
if st_state = st_SEND_WRITE then
mem_ui_en <= mem_ui_wdf_rdy; -- send control command only if wdf_data can be loaded in fifo
-- until mem_ui_rdy
elsif st_state = st_SEND_READ then
mem_ui_en <= '1';
else
mem_ui_en <= '0';
end if;
end process p_mem_ctrl;
---------------------------------------------------------------
-- Memory control 2
-- Controls CMD Message
---------------------------------------------------------------
p_mem_ctrl_2: process(st_state)
begin
-- select command
if st_state = st_SEND_WRITE then
mem_ui_cmd <= c_CMD_WRITE;
elsif st_state = st_SEND_READ then
mem_ui_cmd <= c_CMD_READ;
else
mem_ui_cmd <= c_CMD_READ;
end if;
end process p_mem_ctrl_2;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
p_mem_ctrl_3: process(st_state, mem_ui_wdf_rdy, s_ram_data_to )
begin
if st_state = st_SEND_WRITE and mem_ui_wdf_rdy='1' then
mem_ui_wdf_data <= (c_APP_DATA_WIDTH-1 downto s_ram_data_to'length => '0') & s_ram_data_to;
mem_ui_wdf_end <= '1';
mem_ui_wdf_mask <= c_MASK;
mem_ui_wdf_wren <= '1';
elsif st_state = st_SEND_READ then
mem_ui_wdf_data <= (others => '0');
mem_ui_wdf_end <= '0';
mem_ui_wdf_mask <= (others => '1');
mem_ui_wdf_wren <= '0';
else
mem_ui_wdf_data <= (others => '0');
mem_ui_wdf_end <= '0';
mem_ui_wdf_mask <= (others => '1');
mem_ui_wdf_wren <= '0';
end if;
end process p_mem_ctrl_3;
------------------------------------------
-- ACK signals if registered at outputs
------------------------------------------
p_ack_ctrl: process(st_state, mem_ui_en, mem_ui_rdy)
begin
s_ram_wr_ack <= '0';
s_ram_rd_ack <= '0';
case(st_state) is
when st_SEND_WRITE =>
if mem_ui_en='1' and mem_ui_rdy='1' then
s_ram_wr_ack <= '1';
else
s_ram_wr_ack <= '0';
end if;
s_ram_rd_ack <= '0';
when st_SEND_READ =>
if mem_ui_en='1' and mem_ui_rdy='1' then
s_ram_rd_ack <= '1';
else
s_ram_rd_ack <= '0';
end if;
s_ram_wr_ack <= '0';
when others =>
s_ram_wr_ack <= '0';
s_ram_rd_ack <= '0';
end case;
end process p_ack_ctrl;
------------------------------------------------------------------------
-- Registering all outputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
p_reg_out: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst='1' or s_calib_complete='0' then
ram_rd_ack_o <= '0';
ram_wr_ack_o <= '0';
ram_data_from_o <= (others => '0');
ram_available_o <= '0';
init_calib_complete_o <= '0';
else
ram_rd_ack_o <= s_ram_rd_ack;
ram_wr_ack_o <= s_ram_wr_ack;
-- if mem_ui_rd_data_end='0' then -- mem_ui_rd_data_end high erases contents on mem_ui_rd_data
ram_rd_valid_o <= mem_ui_rd_data_valid;
ram_data_from_o <= mem_ui_rd_data(ram_data_from_o'length-1 downto 0);
-- end if;
if st_state = st_PREP_OP then
ram_available_o <= '1';
else
ram_available_o <= '0';
end if;
init_calib_complete_o <= s_calib_complete;
end if;
end if;
end process p_reg_out;
end behavioral;
|
gpl-3.0
|
julioamerico/OpenCRC
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/acb_96_bit/_primary.vhd
|
3
|
2560
|
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ACB_RDATA : out vl_logic_vector(7 downto 0);
AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQO_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
DAC0_CONFIG : out vl_logic_vector(1 downto 0);
DAC1_CONFIG : out vl_logic_vector(1 downto 0);
DAC2_CONFIG : out vl_logic_vector(1 downto 0)
);
end acb_96_bit;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.vhdl
|
1
|
1675
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 29 14:16:28 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.vhdl
-- Design : dcfifo_32in_32out_16kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcfifo_32in_32out_16kb is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end dcfifo_32in_32out_16kb;
architecture stub of dcfifo_32in_32out_16kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/digilent_repo/local/ip/axi_dynclk_v1_0/src/axi_dynclk_S00_AXI.vhd
|
11
|
18625
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dynclk_S00_AXI;
architecture arch_imp of axi_dynclk_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
--slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
--slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
when b"011" =>
reg_data_out <= slv_reg3;
when b"100" =>
reg_data_out <= slv_reg4;
when b"101" =>
reg_data_out <= slv_reg5;
when b"110" =>
reg_data_out <= slv_reg6;
when b"111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Users to add ports here
CTRL_REG <= slv_reg0;
slv_reg1 <= STAT_REG;
CLK_O_REG <= slv_reg2;
CLK_FB_REG <= slv_reg3;
CLK_FRAC_REG <= slv_reg4;
CLK_DIV_REG <= slv_reg5;
CLK_LOCK_REG <= slv_reg6;
CLK_FLTR_REG <= slv_reg7;
-- User logic ends
end arch_imp;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
18
|
20439
|
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`protect end_protected
|
gpl-3.0
|
makestuff/fx2fpga
|
vhdl/fx2fpga.vhd
|
1
|
4472
|
--
-- Copyright (C) 2009 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fx2fpga is
generic(
COUNTER_WIDTH: natural := 18
);
port(
reset : in std_logic;
ifclk : in std_logic;
-- Unused connections must be configured as inputs
flagA : in std_logic;
flagB : in std_logic;
int0 : in std_logic; -- PA0
int1 : in std_logic; -- PA1
pa3 : in std_logic; -- PA3
pa7 : in std_logic; -- PA7
clkout : in std_logic;
pd : in std_logic_vector(7 downto 0);
dummy : out std_logic; -- Dummy output, not connected to FX2
-- Data & control from the FX2
fd : in std_logic_vector(7 downto 0);
gotData : in std_logic; -- FLAGC
-- Control to the FX2
sloe : out std_logic; -- PA2
slrd : out std_logic;
slwr : out std_logic;
fifoAddr : out std_logic_vector(1 downto 0); -- PA4 & PA5
pktEnd : out std_logic; -- PA6
-- Onboard peripherals
sseg : out std_logic_vector(7 downto 0);
anode : out std_logic_vector(3 downto 0);
sw : in std_logic_vector(2 downto 0);
led_out : out std_logic_vector(7 downto 0)
);
end fx2fpga;
architecture arch of fx2fpga is
signal counter, counter_next: unsigned(COUNTER_WIDTH-1 downto 0);
signal hex: std_logic_vector(3 downto 0);
signal checksum, checksum_next: unsigned(15 downto 0);
signal led, led_next: std_logic_vector(7 downto 0);
begin
process(ifclk, reset)
begin
if ( reset = '1' ) then
counter <= (others => '0');
checksum <= (others => '0');
led <= (others => '0');
elsif ( ifclk'event and ifclk = '1' ) then
counter <= counter_next;
checksum <= checksum_next;
led <= led_next;
end if;
end process;
-- binary counter
counter_next <= counter + 1;
-- Tri-stating doesn't seem to work...set them all as inputs
dummy <=
flagA and flagB and int0 and int1 and pa3 and pa7 and clkout and
pd(0) and pd(1) and pd(1) and pd(2) and pd(3) and
pd(4) and pd(5) and pd(6) and pd(7);
led_out <= led;
fifoAddr <= sw(1 downto 0) when sw(2) = '1' else (others => 'Z');
sloe <= '0' when sw(2) = '1' else 'Z';
slrd <= '0' when sw(2) = '1' else 'Z';
slwr <= '1' when sw(2) = '1' else 'Z';
pktEnd <= '1' when sw(2) = '1' else 'Z';
checksum_next <=
checksum + unsigned(fd) when gotData = '1'
else checksum;
led_next <=
fd when gotData = '1'
else led;
-- process to choose which 7-seg display to light
process(counter(17 downto 16), checksum)
begin
case counter(17 downto 16) is
when "00" =>
anode <= "1110";
hex <= std_logic_vector(checksum(3 downto 0));
sseg(7) <= '1';
when "01" =>
anode <= "1101";
hex <= std_logic_vector(checksum(7 downto 4));
sseg(7) <= '1';
when "10" =>
anode <= "1011";
hex <= std_logic_vector(checksum(11 downto 8));
sseg(7) <= '1';
when others =>
anode <= "0111";
hex <= std_logic_vector(checksum(15 downto 12));
sseg(7) <= '1';
end case;
end process;
-- combinatorial logic to display the correct pattern based
-- on the output of the selector process above.
with hex select
sseg(6 downto 0) <=
"0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010", -- a
"1100000" when "1011", -- b
"0110001" when "1100", -- c
"1000010" when "1101", -- d
"0110000" when "1110", -- e
"0111000" when others; -- f
end arch;
|
gpl-3.0
|
trsk/etip
|
Projekt1/Implementierung/Test_Versions/implementierung1.vhd
|
1
|
4221
|
----
-- This file is part of etip-ss11-g07.
--
-- Copyright (C) 2011 Lukas Märdian <[email protected]>
-- Copyright (C) 2011 M. S.
-- Copyright (C) 2011 Orest Tarasiuk <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----
LIBRARY ieee;
USE ieee.numeric_std.all;
ENTITY BINBCD IS
PORT(
bin_input : IN std_logic_vector (16 DOWNTO 0);
einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0);
overflow : OUT std_logic
);
END BINBCD;
ARCHITECTURE DoubleDabbleV1 OF BINBCD IS
signal const : std_logic_vector (16 DOWNTO 0) := "11000011010011111";
signal vector : std_logic_vector (36 DOWNTO 0) := "0000000000000000000000000000000000000";
signal i : integer := 0;
BEGIN
overflow <= '0';
FOR i IN 0 TO 16 LOOP
IF (bin_input(i) = '1') AND (const(i) = '0') THEN
overflow <= '1';
EXIT
END IF;
END LOOP;
IF (overflow = "0") THEN
FOR i IN 0 TO 16
vector(i+20) <= bin_input(i);
END LOOP;
FOR i IN 0 TO 15 LOOP
vector sll 1;
-- Hierhin muss noch:
-- -Prüfen, ob vector(0to3), oder vector(4to7), oder vector(8to11), oder vector(12to15), oder vector(16to19) >= 5 sind
-- -Zu den jeweiligen Abschnitten von vector 3 addieren.
-- -Siehe hierfür architecture DoubleDabbleV2.
END LOOP;
vector sll 1;
FOR i IN 0 TO 3
zehntausender(i) <= vector(i);
tausender(i) <= vector(i+4);
hunderter(i) <= vector(i+8);
zehner(i) <= vector(i+12);
einer(i) <= vector(i+16);
END LOOP;
END IF;
END DoubleDabbleV1;
ARCHITECTURE DoubleDabbleV2 OF BINBCD IS
signal int_input : integer := 0;
signal vector : std_logic_vector (36 DOWNTO 0);
signal i : integer := 0;
signal int_bcd_seg : integer := 0;
BEGIN
int_input <= to_integer(unsigned(bin_input));
IF (int_input <= 99999) THEN
vector <= "00000000000000000000" & bin_input;
FOR i IN 0 TO 15 LOOP
vector sll 1;
-- WENN MÖGLICH sollte folgender Block bis zum nächsten Kommentar noch mit einer FOR-Schleife, o. ä. zusammengefasst werden:
int_bcd_seg <= to_integer(unsigned(vector(3 DOWNTO 0)));
IF (int_bcd_seg >= 5) THEN
int_bcd_seg <= int_bcd_seg + 3;
END IF;
vector(3 DOWNTO 0) <= std_logic_vector(to_unsigned(int_bcd_seg));
int_bcd_seg <= to_integer(unsigned(vector(7 DOWNTO 4)));
IF (int_bcd_seg >= 5) THEN
int_bcd_seg <= int_bcd_seg + 3;
END IF;
vector(7 DOWNTO 4) <= std_logic_vector(to_unsigned(int_bcd_seg));
int_bcd_seg <= to_integer(unsigned(vector(11 DOWNTO 8)));
IF (int_bcd_seg >= 5) THEN
int_bcd_seg <= int_bcd_seg + 3;
END IF;
vector(11 DOWNTO 8) <= std_logic_vector(to_unsigned(int_bcd_seg));
int_bcd_seg <= to_integer(unsigned(vector(15 DOWNTO 12)));
IF (int_bcd_seg >= 5) THEN
int_bcd_seg <= int_bcd_seg + 3;
END IF;
vector(15 DOWNTO 12) <= std_logic_vector(to_unsigned(int_bcd_seg));
int_bcd_seg <= to_integer(unsigned(vector(19 DOWNTO 16)));
IF (int_bcd_seg >= 5) THEN
int_bcd_seg <= int_bcd_seg + 3;
END IF;
vector(19 DOWNTO 16) <= std_logic_vector(to_unsigned(int_bcd_seg));
-- Block Ende
END LOOP;
vector sll 1;
zehntausender <= vector(3 DOWNTO 0);
tausender <= vector(7 DOWNTO 4);
hunderter <= vector(11 DOWNTO 8);
zehner <= vector(15 DOWNTO 12);
einer <= vector(19 DOWNTO 16);
ELSE
overflow <= '1'
END IF;
END DoubleDabbleV2;
-- http://www.mikrocontroller.net/topic/90462
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd
|
3
|
18538
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=1,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=1,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=DEADBEEF,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.96515 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_SLAVE_S_AXI RREADY";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 1,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "DEADBEEF",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.96515 mW"
)
PORT MAP (
clka => '0',
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/digilent_repo/local/ip/dvi2rgb_v1_5/src/EEPROM_8b.vhd
|
15
|
8403
|
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module emulates a generic I2C EEPROM. It is byte-addressable, with
-- a customizable address width (and thus capacity). It can be made writable
-- from I2C or not, in which case all writes are ignored.
-- Providing a file name accessible by the synthesizer will initialize the
-- EEPROM with the default values from the file.
-- An example use case for this module would be a DDC EEPROM, storing EDID
-- (Extended display identification data). The I2C bus bus is compatible
-- with both standard and fast mode.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EEPROM_8b is
Generic (
kSampleClkFreqInMHz : natural := 100;
kSlaveAddress : std_logic_vector(7 downto 1) := "1010000";
kAddrBits : natural range 1 to 8 := 8; -- 2**kAddrBits byte EEPROM capacity
kWritable : boolean := true; -- is it writable from I2C?
kInitFileName : string := ""); -- name of file containing init values, leave empty to init with zero
Port (
SampleClk : in STD_LOGIC; --at least fSCL*10
sRst : in std_logic;
-- two-wire interface
aSDA_I : in STD_LOGIC;
aSDA_O : out STD_LOGIC;
aSDA_T : out STD_LOGIC;
aSCL_I : in STD_LOGIC;
aSCL_O : out STD_LOGIC;
aSCL_T : out STD_LOGIC);
end EEPROM_8b;
architecture Behavioral of EEPROM_8b is
constant kRAM_Width : integer := 8;
type eeprom_t is array (0 to 2**kAddrBits - 1) of std_logic_vector(kRAM_Width-1 downto 0);
impure function InitRamFromFile (ramfilename : in string) return eeprom_t is
file ramfile : text is in ramfilename;
variable ramfileline : line;
variable ram_name : eeprom_t;
variable bitvec : bit_vector(kRAM_Width-1 downto 0);
variable good : boolean;
begin
assert good report "Reading EDID data from file " & ramfilename & "." severity NOTE;
for i in eeprom_t'range loop
readline (ramfile, ramfileline);
read (ramfileline, bitvec, good);
assert good report "Failed to parse EEPROM_8b init file " & ramfilename & "at line " & integer'image(i+1) & "." severity FAILURE;
ram_name(i) := to_stdlogicvector(bitvec);
end loop;
return ram_name;
end function;
impure function init_from_file_or_zeroes(ramfile : string) return eeprom_t is
begin
if ramfile = "" then
return (others => (others => '0'));
else
return InitRamFromFile(ramfile);
end if;
end;
signal eeprom : eeprom_t := init_from_file_or_zeroes(kInitFileName);
signal aEeprom_out : std_logic_vector(kRAM_Width-1 downto 0);
signal sAddr : natural range 0 to 2**kAddrBits - 1;
type state_type is (stIdle, stRead, stWrite, stRegAddress);
signal sState, sNstate : state_type;
signal sI2C_DataIn, sI2C_DataOut : std_logic_vector(7 downto 0);
signal sI2C_Stb, sI2C_Done, sI2C_End, sI2C_RdWrn, sWe : std_logic;
begin
-- Instantiate the I2C Slave Transmitter
I2C_SlaveController: entity work.TWI_SlaveCtl
generic map (
SLAVE_ADDRESS => kSlaveAddress & '0',
kSampleClkFreqInMHz => kSampleClkFreqInMHz)
port map (
D_I => sI2C_DataOut,
D_O => sI2C_DataIn,
RD_WRN_O => sI2C_RdWrn,
END_O => sI2C_End,
DONE_O => sI2C_Done,
STB_I => sI2C_Stb,
SampleClk => SampleClk,
SRST => sRst,
--two-wire interface
SDA_I => aSDA_I,
SDA_O => aSDA_O,
SDA_T => aSDA_T,
SCL_I => aSCL_I,
SCL_O => aSCL_O,
SCL_T => aSCL_T);
-- RAM
Writable: if kWritable generate
EEPROM_RAM: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sWe = '1') then
eeprom(sAddr) <= sI2C_DataIn;
end if;
end if;
end process EEPROM_RAM;
end generate Writable;
-- ROM/RAM sync output
RegisteredOutput: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sI2C_DataOut <= eeprom(sAddr);
end if;
end process RegisteredOutput;
RegisterAddress: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress) then
sAddr <= to_integer(resize(unsigned(sI2C_DataIn), kAddrBits));
elsif (sState = stRead) then
sAddr <= sAddr + 1;
end if;
end if;
end if;
end process RegisterAddress;
--Insert the following in the architecture after the begin keyword
SyncProc: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sRst = '1') then
sState <= stIdle;
else
sState <= sNstate;
end if;
end if;
end process SyncProc;
--MOORE State-Machine - Outputs based on state only
sI2C_Stb <= '1' when (sState = stRegAddress or sState = stRead or sState = stWrite) else '0';
sWe <= '1' when (sState = stWrite) else '0';
NextStateDecode: process (sState, sI2C_Done, sI2C_End, sI2C_RdWrn)
begin
--declare default state for next_state to avoid latches
sNstate <= sState;
case (sState) is
when stIdle =>
if (sI2C_Done = '1') then
if (sI2C_RdWrn = '1') then
sNstate <= stRead;
else
sNstate <= stRegAddress;
end if;
end if;
when stRegAddress =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stWrite;
end if;
when stWrite =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stWrite;
end if;
when stRead =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRead;
end if;
when others =>
sNstate <= stIdle;
end case;
end process NextStateDecode;
end Behavioral;
|
gpl-3.0
|
hosaka/hello-vhdl
|
hello.vhd
|
1
|
22085
|
-------------------------------------------------------------------------------
-- VHDL Basics Altera Course: The code is not to be compiled, for study only --
-------------------------------------------------------------------------------
--
-- TODO: Describe Bahavior and Structural Modeling / Register Transfer Level
--
-----------------------
-- VHDL Design Units --
-----------------------
--
-- Entity: used to define external view of a model (analogy: symbol)
entity hello is
-- Generic declaration used to pass information to an entity at compile time
-- Allowing for parameters and variables
generic (
-- <class> object_name: <type> := <value>;
-- type is a data type
constant tplh, tplh : time := 5ns; -- constant is assumed and not required
tphz, tplz : time := 3ns;
default_value : integer := 1;
cnt_dir : string := "up" -- note the absence of ; since it's a list
);
-- Port declaration specifies the input/output to the entity
port (
-- <class> object_name: <mode> <type>;
-- mode is the direction of the port: in, out, inout(bidirect), buffer
-- type is what can be contained in the object
signal clock, clear : in bit; -- signal is assumed and not required
q : out bit
) ;
end entity ; -- hello
-- Architecture: used to define the function of a model (analogy: schematic with symbols)
-- Describes the internal logic, you can see the entity name, params, the
-- outputs, but no visibility of the entity guts
-- Must be associated with an entity, but entity can belong to multiple arch
architecture arch of hello is
-- arch declaration section
signal temp : integer := 1; -- signal declaration is default (optional)
constant load : boolean := true;
type states is (S1, S2, S3, S4); -- type declarations
-- Component decl
-- Subtype decl
-- Attribute decl
-- Attribute spec
-- Subprogram decl
-- Subprogram body
begin
-- Architecture body: contains executable lines executed concurrently
end architecture ; -- arch
-- Configuration: used to associate an entity with an architecture
-- Mostly used in simulation environments than synthesis
configuration config of hello is
for arch
--
end for;
-- can be associated with multiple architectures
end configuration ; -- config
-- Package: Collection of reusable code that can be referenced by VHDL designs
-- Consists of a package declaration and a package body (for functions)
-- two built-in packages: standard (types/operators) and TEXTIO (file io)
-- Libraries: contain a packege or a collection of them (a directory)
-- Standard package, IEEE package, made by silicon vendors or user-made
-- Working library is the lib which the unit is being compiled into
-- All packages must be compiled, otherwise they end up in implicit libraries:
-- WORK or STD - these do not need to be explicitly called out to be used
-- To use an explicit package from another library (usually atop the file)
library IEEE;
use IEEE.std_logic_1164.all;
-- The standard package defines default types: bit, boolean, integer, real, time
-- textio defines file operations. Since it's built-in, no need to call it
-- Standard package types:
-- bit - logic value 1/0, append _vector to indicate array of bits.
-- bit_vector (3 downto 0); or (0 to 3) indicating MSB position
-- but downto is most common.
-- boolean - true/false
-- integer - pos and neg values in decimal (32 bit max?)
-- to limit the value, we can say x : integer range 0 to 255 (8 bit
-- int)
-- character - ascii char
-- string - array of characters
-- time - value includes units of time (ps, us, ns ,ms, sec, min, hr)
-- IEEE Library contains std types, arithmetic signed and unsigned functions
-- IEEE_logic_1164 package types:
-- std_logic - 9 logic value system
-- 1 - logic high H - weak logic high
-- 0 - logic low L - weak logic low
-- X - unknown W - weak unknown
-- U - undefined Z - tri-state
-- - - don't care
-- the standard logic allows for multiple signal drivers, for example two drivers
-- can drive the bus with 1 and Z, the std_logic will resolve this to 1. If the
-- same happened with values 1 and 0, the result would be X.
-- std_ulogic - the same as std_logic, but does not supporte multiple signal
-- drives, resulting in an error
---------------------
-- VHDL Constructs --
---------------------
--
-- Constants: Same as other lang constants, with local (arch) and global (entity)
constant bus_width : integer := 16;
-- Signals: Represent phy interconnect (wire) that communicate between processes
-- (functions). Can be declared in Packages, Entity and Architecture
-- Signals in Entity are essentially I/O
-- Signals in Architecture are internal signals to connect Entities together,
-- invisible to the outside world.
-- Note: vars are signals by default in the entities ports declaration
signal temp : std_logic_vector (7 downto 0);
-- To assign values to signals, '1' for single bit and "101" multi bit assign
temp <= "10101010"; -- bus (vector) value
temp <= x"AA"; -- 93 standard also supports HEX
temp(7) <= '1'; -- Assign a single array bit
temp (7 downto 4) <= "1010"; -- Bit-slicing, like python temp[4:7]
-- Signal assignment <= is an implied process (function) that will synthesize
-- to hardware. Any time the input to the process changes on the right, that
-- process (function) is executed and assigns the result value to the signal.
-- signal <= process
-- Operators in VHDL:
-- Logical: NOT, AND, OR, NAND, NOR, XOR, XNOR (93 only)
-- Relational: =, /= (not equal), <, <=, >, >=
-- Arithmetic: +, -, *, /, mod, rem
-- Misc: ** (exponent), abs, & (concat, say 2 vectors of 4bit, into one 8bit)
--------------------------
-- Operator Overloading --
--------------------------
--
-- Same concept as in other languages, re-define operator behaviour for user
-- data types. Operators are overloaded by defining a function whose name is
-- the same as the operator itself. Normally declared in a package so that it
-- is visible for any design. Enclose the operator in "" when defining functions.
function "+" (l: std_logic_vector; r: integer) return std_logic_vector;
-- To use the overloaded operator, one must use the package where it's defined:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
signal a: in std_logic_vector (4 downto 0);
signal b: in std_logic_vector (4 downto 0);
signal sum: out std_logic_vector (4 downto 0);
sum <= a + b; -- overloaded + on non-built-in data type
-----------------------------------
-- Concurrent Signal Assignments --
-----------------------------------
--
-- (in Architecture body)
-- Take expressions and assign the result to a signal. Represent implied processes
-- that execute in parallel. Trigger from anything on read (right) side of the
-- assignment, executes the process and assignes a new value to the signal on
-- the left. Multiple assignments are concurrent and run in parallel.
-- Simple signal assignment:
-- signal_name <= expression; Implied concurrent processes, order doesn't matter
qa <= r or t;
qb <= (qa and not(g xor h));
-- Conditional signal assignment:
-- Assigned upon meeting a pre-defined condition, has to end with an assignable
-- expression like '0' to deal with default (other) cases
-- Priority MUX
sig_xor <= '1' when a='0' and b='1' else
'1' when a='1' and b='0' else
'0';
sig_and <= '1' when a='1' and b='1' else
'0';
q <= a when sela = '1' else
b when selb = '1' else
c;
-- Selected signal assignment:
-- Similar to case statements, selecting upon meeting a condition. sel is the
-- signal we're "casing" on, and assigning to q when values are "00", "01" etc.
-- this is also an implied process, just like other signal assignments in the
-- architecture body.
-- Wide MUX: All values have an equal chance of being true, no priority.
with sel select
q <= a when "00",
b when "01",
c when "10",
d when others;
-- We can't simply replace "others" with "11" because in std_logic there are
-- other possible values like 'X', 'Z', 'U' etc.
-----------------------------
-- Signal Assignment Delay --
-----------------------------
--
-- Inertial delay: (default)
-- A pulse that is short in duration of the specified delay (10 ns) will not be
-- transmitted in this case.
a <= b after 10 ns; -- the statement waits 10ns before a is assigned to b
-- Transport delay
-- Any pulse is transmitted, no matter how short it was, and assigned to signal
a <= transport b after 10 ns;
-- These pulse durations are set by the simulation tool and used only there, so
-- these need to be set in the simulation tool beforehand.
--------------------------------
-- Explicit Process Statement --
--------------------------------
--
-- Unlike implicit signal processes, we can create explicit process that is run
-- infinitely unless broken by a WAIT statement or sensitivity list. Inside of
-- an explicit process, the statements are executed sequentially. The process
-- itself is still executed concurrently with others, but individual statements
-- inside an explicit process, are sequential.
-- label: process (sensitivity_list)
-- constants
-- types
-- variable
-- begin
-- sequential statements
-- end process;
-- The process is sensitive to a or b, if they change, the process is turned on
-- and executes the statements inside. Once it's done, it'll wait for another
-- transition on a or b
proc1: process (a, b)
begin
-- sequential statements
end process;
-- With no sensitivity list, this starts execution right from the start of the
-- simulation. The wait on statement forces the process to wait until a or b
-- transition (change/pulse etc.), before it loops around and starts executing
-- again.
proc2: process
-- sequential statements
wait on (a, b);
end process;
-- Sequential Statements: Must be used inside of an explicit process. Indicate
-- behavior and express order
-- signal assignment (same as others)
a <= b;
-- if-then
-- conditional signal assignments can not be used in explicit processes, we can
-- only use a series of priority MUXs. Conditional assignments are implied proc
-- on their own and can not be used as a sequential statement.
sel: process (sela, selb, a, b, c)
begin
if sela = '1' then
q <= a;
elsif selb = '1' then
q <= b;
else
q <= c;
end if;
end process;
-- case
-- selected signal assignments can not be used in explicit processes, as it is
-- an implied process on its own. Same as if-then statement
-- 4 input MUX
process (sel, a, b, c, d)
begin
case sel is
when "00" =>
q <= a;
when "01" =>
q <= b;
when "10" =>
q <= c;
when others =>
q <= d;
end case;
end process;
-- looping (all loops support next and exit)
-- loop: infinitely unless exit statement exists
loop_label loop
-- sequential statements
next loop_label when ; -- stop with current execution, and re-run the loop
exit loop_label when ; -- exit upon condition
end loop;
-- while: conditional test to end loop
while condition loop
-- sequential statements
end loop;
-- for (iteration)
for identifier in range loop
-- sequential statements
end loop;
-- wait (limited synthesis usage)
-- used to pause execution of a process until some condition is satisfied
wait on a, b; -- wait on <signal>
wait until (int < 100); -- pause unti lboolean expression is true
wait for 20 ns; -- pause until time expression elapses
wait until (a = '1') for 5 us; -- can be combined, if a isn't '1' in 5 us
--------------------------------
-- Delta and Simulatin Cycles --
--------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
entity simp is
port (
a, b : in std_logic;
y : out std_logic
) ;
end entity ; -- simp
architecture logic of simp is
signal c : std_logic;
begin
---------------------------
-- Equivalent Functions ---
---------------------------
-- Implied processes:
-- this will take 2 delta cycles, but 1 simulation cycle to complete
c <= a AND b;
y <= c;
-- Explicit processes:
-- this will also take 2 delta cycles, and 1 simulation cycle
proc_eq: process (a, b)
begin
c <= a AND b;
end process;
proc2: process(c)
y <= c;
end process;
-----------------------------
-- Unequivalent Functions ---
-----------------------------
-- implied
c <= a AND b;
y <= c;
-- explicit, but with the same signal assignment
-- this will take 2 simulation cycles to be executed
proc_neq: process(a, b)
begin
-- the C is scheduled to be updated, but doesn't propagate until the
-- next delta cycle
c <= a AND b;
-- the Y will get the old value of C and will only update once the
-- process ends, so in order for Y to see the new value of C it would
-- take a second iteration of the process (a or b has to change).
y <= c;
end process;
--------------------------------
-- Equivalent with Variables ---
--------------------------------
-- to work around the above unequivalency, VHDL uses variables
-- this will take 1 simulation cycles to be executed, like the orig function
-- see variable description below
proc_eq_with_vars: process(a, b)
-- C is made a variable in local scope
variable c: std_logic;
begin
-- if A or B trigger the process, the value of C is updated immediately
-- with no delay to wait for the process to finish
c := a AND b;
-- Y will take the new value of C within the same simulation cycle
y <= c;
end process;
end architecture ; -- logic
---------------------------
-- Variable Declarations --
---------------------------
--
-- variables are declared inside a process
-- assignment is represented by :=
-- assignments are updated immediately and do not incur a delay, ie do not wait
-- for the process to end to propagate the result value
-- declare:
-- variable <name> : <data_type> := <value>;
variable temp : std_logic_vector (7 downto 0);
-- operations are the same as signal assignment
temp := "10101010"; -- all bits
temp := x"AA"; -- in VHDL 93
temp(7) := '1'; -- single bit
temp(7 downto 4) := "1010"; -- bit slicing
---------------------------
-- Signals vs. Variables --
---------------------------
-- | Signals | Variables
--------------------------------------------------------------------
-- Assignment | y <= c | y := c |
-- Utility | Circuit interconnect | Local storage |
-- Scope | Global (between proc) | Local (inside process) |
-- Behavior | End of delta update | Immediate update |
--------------------------------------------------------------------
-----------------------------
-- User Defined data types --
-----------------------------
--
-- arrays and enums
architecture logic of my_memory is
-- array is a 2d *datatype* for storing values, must create constant signal
-- or variable of that type, used to create memories and store simulation
-- vectors type <array_type_name> is array (<integer_range) of <data_type>;
-- create new array datatype "mem" which has 64 addr locations,
-- each 8 bit wide
type mem is array(0 to 63) of std_logic_vector (7 downto 0);
-- create 2 - 64x8-bit arrays (of user defined type mem) to use in design
-- these are 512 bit/64 bytes vectors
signal mem_64x8_a, mem_64x8_b : mem;
-- enum is a *datatype* with name and values, used to make code readable
-- and in finate state machines, just like C typedef STATE enum {A=1, B=2};
-- type <enum_type_name> is (enum, states, or, values);
type enum is (idle, fill, heat, wash, drain);
-- create a state signal
signal dishwasher_state : enum;
begin
-- use our defined type signals to store data
-- access individual array vectors with (xx)
mem_64x8_a(12) <= x"F0";
mem_64x8_b(50) <= "11110000";
-- poll current state, using defined enumerator
drain_led <= '1' when dishwasher_state = drain else '0';
end architecture; -- logic
---------------------
-- Logic Synthesis --
---------------------
--
-- RTL Synthesis refers to the act of reading HDL code, and translating it
-- into hardware. Synthesis tool reads the code, translates it into gates, runs
-- optimization to make it smaller and faster. Two types of processes are used:
-- Combinatorial Process: Sensitive to *all* inputs used in combinatorial logic
-- Any signal used on the right hand side (the assignment) inside your process
-- needs to be in the sensitivity list
comb: process(a, b, sel)
variable c: std_logic;
begin
c := a AND b;
q <= c OR sel;
end process;
-- While RTL Synth will assume that you meant to include all inputs in your
-- sensitivity list and will fill in the missing signals. The simulation tool
-- will execute exactly as written. Thus, Sim and Synth processes can differ.
-- Sequential Process: Sensitive to a clock or/and any async control signals,
-- for example RESET, CLEAR etc. Used for building registers.
-- example D Flip-Flop with async clear signal
library IEEE;
use IEEE.std_logic_1164.ALL;
entity dff_b is
port (
clr, clk, d, ena: in std_logic;
q: out std_logic
);
end entity;
architecture rtl of dff_b is
begin
-- if the clock transitions, this process triggers
process(clk, clr)
begin
-- check the clear signal first (async control signal), clear signal
-- does not depend on the clock and checked before the clock check
if (clr = '0') then
q <= '0';
-- IEEE function, signal must be 0 to 1
-- any other clk transition will fail (1 to 0, X, Z etc)
elsif (rising_edge(clk)) then
q <= d;
end if;
-- to have clear synched with the clk, we check the clear inside the
-- rising_edge(), clr='0' now depends on the clock, clk shouldn't be
-- present in the sensitivity list
if (rising_edge(clk)) then
if (clr = '0') then
q <= '0';
else
q <= d;
end if;
-- to combine both of these together: DFF Async clear & Clock Enable
if (clr = '0') then
q <= '0';
elsif (rising_edge(clk)) then
if (ena = '1') then
q <= d;
end if;
-- if ena /= 1, the register retains previous value
end if;
end process;
end architecture;
-- Always stick to either combinatorial or sequential process definition.
-- rising_edge() and falling_edge() functions are recommended to use with clk
-- detection, compared to the older method of (clk'event and clk='1')
-- Synthesizing Registers:
-- Signal assignments infer registers when placed inside if-then statements
-- that check for clock condition.
process (clk)
begin
-- The following will generate a register (d flip-flop)
if (rising_edge(clk)) then
-- each statement will generate individual register
q <= d;
end if;
end process;
-- Counter:
-- Are accumulators (register + adder) that always add/substract a '1'
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity counter is
port (
clk, rst: in std_logic;
q: out std_logic_vector(15 downto 0)
) ;
end entity ;
architecture logic of counter is
signal tmp_q: std_logic_vector(15 downto 0);
begin
process (clk, rst)
begin
if (rst = '0') then
-- just another way of setting all vector elements to one value
tmp_q <= (others >= '0');
elsif (rising_edge(clk)) then
-- count temp q on each rising clock
tmp_q <= tmp_q + 1;
end if;
end process;
-- assign the value output of the counter entity
q <= tmp_q;
end architecture ; -- logic
-------------------------
-- Designing Hierarchy --
-------------------------
--
-- Design Hierarchically - Multiple Design Files
-- VHDL hierarchical design requires Component Declarations and Component
-- Instantiations.
--
-- This is the same concept as having multiple interfaces hidden from the top
-- layer component, for example via header files. The top layer needs not to
-- know the very bottom layer individual components in order to operate.
-- top <- mid <- bottom: the top layer, has no idea about the bottom layer.
-- Component Declaration & Instantiation
--
library IEEE
use IEEE.std_logic_1164.ALL;
entity tolleab is
port (
tclk, tcross, tnickel, tdime, tquarter: in std_logic;
tgreen, tred: out std_logic
) ;
end entity ; -- tolleab
architecture tolleab_arch of tolleab is
-- Declaration: Used to declare the port-types and the data types of the ports
-- for a lower-level design.
component tollv
port (
clk, cross, nickel, dime, quarter: in std_logic;
green, red: out std_logic
);
end component;
begin
-- Instantiation: Concurrent statement used to map the ports of a lower-level
-- design to that of the upper-level design.
-- We're mapping lower-level inputs of tollv to upper-level tolleab
U1: tollv port map (
clk => tclk,
cross => tcross,
nickel => tnickel,
dime => tdime,
quarter => tquarter,
green => tgree,
red => tred
);
-- U1 is the name of the instance, we can create multiple instances with
-- various mappings of the same block tolleab.
end architecture ; -- tolleab_arch
-------------
-- Summary --
-------------
--
-- VHDL Design Units and Constructs to create Models:
-- Entity, Architecture, Signals, Variables, Processes, Logic Synth, Hirarchy
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/scfifo_5in_5out_5kb_synth_1/scfifo_5in_5out_5kb_stub.vhdl
|
2
|
1535
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:12 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_5in_5out_5kb_synth_1/scfifo_5in_5out_5kb_stub.vhdl
-- Design : scfifo_5in_5out_5kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scfifo_5in_5out_5kb is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end scfifo_5in_5out_5kb;
architecture stub of scfifo_5in_5out_5kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[4:0],wr_en,rd_en,dout[4:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_0_0,Vivado 2015.3";
begin
end;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/synth/dcfifo_32in_32out_16kb.vhd
|
1
|
38892
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY dcfifo_32in_32out_16kb IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dcfifo_32in_32out_16kb;
ARCHITECTURE dcfifo_32in_32out_16kb_arch OF dcfifo_32in_32out_16kb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dcfifo_32in_32out_16kb_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dcfifo_32in_32out_16kb_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dcfifo_32in_32out_16kb_arch : ARCHITECTURE IS "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dcfifo_32in_32out_16kb_arch: ARCHITECTURE IS "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=509,C_PROG_FULL_THRESH_NEGATE_VAL=508,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=1,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 9,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 1,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 509,
C_PROG_FULL_THRESH_NEGATE_VAL => 508,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 9,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 1,
C_WR_DEPTH => 512,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 9,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
wr_data_count => wr_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END dcfifo_32in_32out_16kb_arch;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/scfifo_5in_5out_5kb_synth_1/scfifo_5in_5out_5kb_sim_netlist.vhdl
|
2
|
195076
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:12 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_5in_5out_5kb_synth_1/scfifo_5in_5out_5kb_sim_netlist.vhdl
-- Design : scfifo_5in_5out_5kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end scfifo_5in_5out_5kb_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 10) => B"000000",
DIADI(9 downto 8) => din(4 downto 3),
DIADI(7 downto 3) => B"00000",
DIADI(2 downto 0) => din(2 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_20\,
DOBDO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_21\,
DOBDO(9 downto 8) => D(4 downto 3),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_28\,
DOBDO(2 downto 0) => D(2 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => ram_full_fb_i_reg(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg(0),
WEA(0) => ram_full_fb_i_reg(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_compare is
port (
comp0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_compare : entity is "compare";
end scfifo_5in_5out_5kb_compare;
architecture STRUCTURE of scfifo_5in_5out_5kb_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_compare_0 : entity is "compare";
end scfifo_5in_5out_5kb_compare_0;
architecture STRUCTURE of scfifo_5in_5out_5kb_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_1(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_1(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_compare_1 : entity is "compare";
end scfifo_5in_5out_5kb_compare_1;
architecture STRUCTURE of scfifo_5in_5out_5kb_compare_1 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_compare_2 : entity is "compare";
end scfifo_5in_5out_5kb_compare_2;
architecture STRUCTURE of scfifo_5in_5out_5kb_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_1(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_1(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_5in_5out_5kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_5in_5out_5kb_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9 downto 0);
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B4"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \^q\(8),
I1 => \^q\(7),
I2 => \gc0.count[9]_i_2_n_0\,
I3 => \^q\(6),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(9),
Q => \^q\(9)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0),
I1 => \gcc0.gc0.count_reg[9]\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1),
I3 => \gcc0.gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2),
I1 => \gcc0.gc0.count_reg[9]\(2),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3),
I3 => \gcc0.gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4),
I1 => \gcc0.gc0.count_reg[9]\(4),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5),
I3 => \gcc0.gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6),
I1 => \gcc0.gc0.count_reg[9]\(6),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7),
I3 => \gcc0.gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8),
I1 => \gcc0.gc0.count_reg[9]\(8),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9),
I3 => \gcc0.gc0.count_reg[9]\(9),
O => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_rd_fwft is
port (
empty : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_bm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_rd_fwft : entity is "rd_fwft";
end scfifo_5in_5out_5kb_rd_fwft;
architecture STRUCTURE of scfifo_5in_5out_5kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair1";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[9]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF4555"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I4 => Q(0),
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88EA"
)
port map (
I0 => empty_fwft_fb,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0B0F"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => ram_empty_fb_i_reg,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\goreg_bm.dout_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \goreg_bm.dout_i_reg[4]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3B33"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
I3 => curr_fwft_state(0),
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_5in_5out_5kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_5in_5out_5kb_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \scfifo_5in_5out_5kb_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \scfifo_5in_5out_5kb_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \scfifo_5in_5out_5kb_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \scfifo_5in_5out_5kb_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
comp0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0_2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
comp1_3 : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_5in_5out_5kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_5in_5out_5kb_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair7";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9 downto 0);
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B4"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \^q\(8),
I1 => \^q\(7),
I2 => \gcc0.gc0.count[9]_i_2_n_0\,
I3 => \^q\(6),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \^q\(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1),
I1 => \gc0.count_d1_reg[9]\(1),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0),
I3 => \gc0.count_d1_reg[9]\(0),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1),
I1 => \gc0.count_d1_reg[9]\(1),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0),
I3 => \gc0.count_d1_reg[9]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3),
I1 => \gc0.count_d1_reg[9]\(3),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2),
I3 => \gc0.count_d1_reg[9]\(2),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3),
I1 => \gc0.count_d1_reg[9]\(3),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2),
I3 => \gc0.count_d1_reg[9]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5),
I1 => \gc0.count_d1_reg[9]\(5),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4),
I3 => \gc0.count_d1_reg[9]\(4),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5),
I1 => \gc0.count_d1_reg[9]\(5),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4),
I3 => \gc0.count_d1_reg[9]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7),
I1 => \gc0.count_d1_reg[9]\(7),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6),
I3 => \gc0.count_d1_reg[9]\(6),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7),
I1 => \gc0.count_d1_reg[9]\(7),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6),
I3 => \gc0.count_d1_reg[9]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9),
I1 => \gc0.count_d1_reg[9]\(9),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8),
I3 => \gc0.count_d1_reg[9]\(8),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9),
I1 => \gc0.count_d1_reg[9]\(9),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8),
I3 => \gc0.count_d1_reg[9]\(8),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFA22FAAAAA22AA"
)
port map (
I0 => p_18_out,
I1 => comp0,
I2 => E(0),
I3 => wr_en,
I4 => p_1_out,
I5 => comp1,
O => ram_empty_fb_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"131313130F000000"
)
port map (
I0 => comp0_2,
I1 => rst_full_gen_i,
I2 => E(0),
I3 => comp1_3,
I4 => wr_en,
I5 => p_1_out,
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end scfifo_5in_5out_5kb_blk_mem_gen_prim_width;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.scfifo_5in_5out_5kb_blk_mem_gen_prim_wrapper
port map (
D(4 downto 0) => D(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_rd_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_5in_5out_5kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_5in_5out_5kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
c1: entity work.scfifo_5in_5out_5kb_compare_1
port map (
comp0 => comp0,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
c2: entity work.scfifo_5in_5out_5kb_compare_2
port map (
comp1 => comp1,
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_wr_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_5in_5out_5kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_5in_5out_5kb_wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
c0: entity work.scfifo_5in_5out_5kb_compare
port map (
comp0 => comp0,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.scfifo_5in_5out_5kb_compare_0
port map (
comp1 => comp1,
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end scfifo_5in_5out_5kb_blk_mem_gen_generic_cstr;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.scfifo_5in_5out_5kb_blk_mem_gen_prim_width
port map (
D(4 downto 0) => D(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_rd_logic is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
empty : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_bm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_rd_logic : entity is "rd_logic";
end scfifo_5in_5out_5kb_rd_logic;
architecture STRUCTURE of scfifo_5in_5out_5kb_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_18_out\ : STD_LOGIC;
begin
E(0) <= \^e\(0);
p_18_out <= \^p_18_out\;
\gr1.rfwft\: entity work.scfifo_5in_5out_5kb_rd_fwft
port map (
E(0) => \^e\(0),
Q(1 downto 0) => Q(1 downto 0),
clk => clk,
empty => empty,
\goreg_bm.dout_i_reg[4]\(0) => \goreg_bm.dout_i_reg[4]\(0),
ram_empty_fb_i_reg => \^p_18_out\,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\grss.rsts\: entity work.scfifo_5in_5out_5kb_rd_status_flags_ss
port map (
Q(0) => Q(1),
clk => clk,
comp0 => comp0,
comp1 => comp1,
p_18_out => \^p_18_out\,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0)
);
rpntr: entity work.scfifo_5in_5out_5kb_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
clk => clk,
\gcc0.gc0.count_reg[9]\(9 downto 0) => \gcc0.gc0.count_reg[9]\(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_wr_logic is
port (
full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
p_18_out : in STD_LOGIC;
comp0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_wr_logic : entity is "wr_logic";
end scfifo_5in_5out_5kb_wr_logic;
architecture STRUCTURE of scfifo_5in_5out_5kb_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal comp0_1 : STD_LOGIC;
signal comp1_0 : STD_LOGIC;
signal \^gcc0.gc0.count_reg[9]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
\gcc0.gc0.count_reg[9]\(0) <= \^gcc0.gc0.count_reg[9]\(0);
\gwss.wsts\: entity work.scfifo_5in_5out_5kb_wr_status_flags_ss
port map (
E(0) => \^gcc0.gc0.count_reg[9]\(0),
clk => clk,
comp0 => comp0_1,
comp1 => comp1_0,
full => full,
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_full_ff_i => rst_full_ff_i,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.scfifo_5in_5out_5kb_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
comp0 => comp0,
comp0_2 => comp0_1,
comp1 => comp1,
comp1_3 => comp1_0,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
ram_full_fb_i_reg(0) => \^gcc0.gc0.count_reg[9]\(0),
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
v1_reg_1(4 downto 0) => \c0/v1_reg\(4 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_top : entity is "blk_mem_gen_top";
end scfifo_5in_5out_5kb_blk_mem_gen_top;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_top is
begin
\valid.cstr\: entity work.scfifo_5in_5out_5kb_blk_mem_gen_generic_cstr
port map (
D(4 downto 0) => D(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0_synth is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0_synth : entity is "blk_mem_gen_v8_3_0_synth";
end scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0_synth;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.scfifo_5in_5out_5kb_blk_mem_gen_top
port map (
D(4 downto 0) => D(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0 is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0 : entity is "blk_mem_gen_v8_3_0";
end scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0;
architecture STRUCTURE of scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0 is
begin
inst_blk_mem_gen: entity work.scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0_synth
port map (
D(4 downto 0) => D(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_memory : entity is "memory";
end scfifo_5in_5out_5kb_memory;
architecture STRUCTURE of scfifo_5in_5out_5kb_memory is
signal doutb : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.scfifo_5in_5out_5kb_blk_mem_gen_v8_3_0
port map (
D(4 downto 0) => doutb(4 downto 0),
Q(0) => Q(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => \gcc0.gc0.count_d1_reg[9]\(9 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_5in_5out_5kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_5in_5out_5kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_11\ : STD_LOGIC;
signal \grss.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/comp0\ : STD_LOGIC;
signal \grss.rsts/comp1\ : STD_LOGIC;
signal \gwss.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_10_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_14_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_5in_5out_5kb_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_20_out(9 downto 0),
E(0) => p_14_out,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
clk => clk,
comp0 => \grss.rsts/comp0\,
comp1 => \grss.rsts/comp1\,
empty => empty,
\gc0.count_d1_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gcc0.gc0.count_reg[9]\(9 downto 0) => p_9_out(9 downto 0),
\goreg_bm.dout_i_reg[4]\(0) => p_15_out,
p_18_out => p_18_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_11\,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \grss.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_5in_5out_5kb_wr_logic
port map (
AR(0) => \^rst\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_10_out(9 downto 0),
E(0) => p_14_out,
Q(9 downto 0) => p_9_out(9 downto 0),
clk => clk,
comp0 => \grss.rsts/comp0\,
comp1 => \grss.rsts/comp1\,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_20_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gcc0.gc0.count_reg[9]\(0) => p_4_out,
p_18_out => p_18_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_11\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => \grss.rsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_5in_5out_5kb_memory
port map (
E(0) => p_15_out,
Q(0) => rd_rst_i(0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_20_out(9 downto 0),
\gcc0.gc0.count_d1_reg[9]\(9 downto 0) => p_10_out(9 downto 0),
ram_full_fb_i_reg(0) => p_4_out,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.\scfifo_5in_5out_5kb_reset_blk_ramfifo__parameterized0\
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_5in_5out_5kb_fifo_generator_top;
architecture STRUCTURE of scfifo_5in_5out_5kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_5in_5out_5kb_fifo_generator_ramfifo
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_fifo_generator_v13_0_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_fifo_generator_v13_0_0_synth : entity is "fifo_generator_v13_0_0_synth";
end scfifo_5in_5out_5kb_fifo_generator_v13_0_0_synth;
architecture STRUCTURE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_5in_5out_5kb_fifo_generator_top
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
\reset_gen_cc.rstblk_cc\: entity work.scfifo_5in_5out_5kb_reset_blk_ramfifo
port map (
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb_fifo_generator_v13_0_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 11;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 : entity is "fifo_generator_v13_0_0";
end scfifo_5in_5out_5kb_fifo_generator_v13_0_0;
architecture STRUCTURE of scfifo_5in_5out_5kb_fifo_generator_v13_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_5in_5out_5kb_fifo_generator_v13_0_0_synth
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_5in_5out_5kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_5in_5out_5kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_5in_5out_5kb : entity is "scfifo_5in_5out_5kb,fifo_generator_v13_0_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_5in_5out_5kb : entity is "scfifo_5in_5out_5kb,fifo_generator_v13_0_0,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=5,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=5,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_5in_5out_5kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_5in_5out_5kb : entity is "fifo_generator_v13_0_0,Vivado 2015.3";
end scfifo_5in_5out_5kb;
architecture STRUCTURE of scfifo_5in_5out_5kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
begin
U0: entity work.scfifo_5in_5out_5kb_fifo_generator_v13_0_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(10 downto 0) => NLW_U0_data_count_UNCONNECTED(10 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(10 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(10 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(10 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(10 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb_rd_cnt/dcfifo_32in_32out_16kb_rd_cnt_funcsim.vhdl
|
1
|
241919
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 22 03:39:21 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_decoder_prj/project_1.srcs/sources_1/ip/dcfifo_32in_32out_16kb_rd_cnt/dcfifo_32in_32out_16kb_rd_cnt_funcsim.vhdl
-- Design : dcfifo_32in_32out_16kb_rd_cnt
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 5) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 5) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 0) => din(15 downto 0),
DIBDI(15 downto 0) => din(31 downto 16),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => dout(15 downto 0),
DOBDO(15 downto 0) => dout(31 downto 16),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_compare : entity is "compare";
end dcfifo_32in_32out_16kb_rd_cnt_compare;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_compare_0 is
port (
comp2 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_compare_0 : entity is "compare";
end dcfifo_32in_32out_16kb_rd_cnt_compare_0;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \rd_pntr_bin_reg[8]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_compare_1 : entity is "compare";
end dcfifo_32in_32out_16kb_rd_cnt_compare_1;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_compare_1 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \wr_pntr_bin_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_compare_2 : entity is "compare";
end dcfifo_32in_32out_16kb_rd_cnt_compare_2;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_rd_bin_cntr : entity is "rd_bin_cntr";
end dcfifo_32in_32out_16kb_rd_cnt_rd_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair11";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => WR_PNTR_RD(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => WR_PNTR_RD(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => WR_PNTR_RD(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => WR_PNTR_RD(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => WR_PNTR_RD(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => WR_PNTR_RD(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => WR_PNTR_RD(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => WR_PNTR_RD(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => WR_PNTR_RD(8),
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_rd_dc_as : entity is "rd_dc_as";
end dcfifo_32in_32out_16kb_rd_cnt_rd_dc_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_rd_dc_as is
signal minusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \NLW_rd_dc_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rd_dc_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => minusOp(7),
Q => rd_data_count(0)
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_2_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => WR_PNTR_RD(7 downto 4),
O(3 downto 0) => minusOp(7 downto 4),
S(3 downto 0) => \wr_pntr_bin_reg[7]\(3 downto 0)
);
\rd_dc_i_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[7]_i_2_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_2_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_2_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_2_n_3\,
CYINIT => '1',
DI(3 downto 0) => WR_PNTR_RD(3 downto 0),
O(3 downto 0) => minusOp(3 downto 0),
S(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => minusOp(8),
Q => rd_data_count(1)
);
\rd_dc_i_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 0) => \NLW_rd_dc_i_reg[8]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 1) => \NLW_rd_dc_i_reg[8]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => minusOp(8),
S(3) => '0',
S(2) => '0',
S(1) => '0',
S(0) => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end dcfifo_32in_32out_16kb_rd_cnt_reset_blk_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_reset_blk_ramfifo is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
rst_full_ff_i <= rst_d2;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^q\(0),
I1 => p_18_out,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_3 is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_3 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_3;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_4 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_4 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_4;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^wr_pntr_bin_reg[7]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
\out\(0) <= Q_reg(8);
\wr_pntr_bin_reg[7]\(7 downto 0) <= \^wr_pntr_bin_reg[7]\(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^wr_pntr_bin_reg[7]\(3),
O => \^wr_pntr_bin_reg[7]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^wr_pntr_bin_reg[7]\(3),
O => \^wr_pntr_bin_reg[7]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^wr_pntr_bin_reg[7]\(3),
I1 => Q_reg(2),
O => \^wr_pntr_bin_reg[7]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(8),
I2 => Q_reg(6),
I3 => Q_reg(7),
I4 => Q_reg(5),
I5 => Q_reg(3),
O => \^wr_pntr_bin_reg[7]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(8),
I4 => Q_reg(4),
O => \^wr_pntr_bin_reg[7]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(6),
I2 => Q_reg(7),
I3 => Q_reg(5),
O => \^wr_pntr_bin_reg[7]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \^wr_pntr_bin_reg[7]\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \^wr_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_5 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_5 : entity is "synchronizer_ff";
end dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_5;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^rd_pntr_bin_reg[7]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
begin
\out\(0) <= Q_reg(8);
\rd_pntr_bin_reg[7]\(7 downto 0) <= \^rd_pntr_bin_reg[7]\(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(8),
Q => Q_reg(8)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^rd_pntr_bin_reg[7]\(3),
O => \^rd_pntr_bin_reg[7]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^rd_pntr_bin_reg[7]\(3),
O => \^rd_pntr_bin_reg[7]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_bin_reg[7]\(3),
I1 => Q_reg(2),
O => \^rd_pntr_bin_reg[7]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(8),
I2 => Q_reg(6),
I3 => Q_reg(7),
I4 => Q_reg(5),
I5 => Q_reg(3),
O => \^rd_pntr_bin_reg[7]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(8),
I4 => Q_reg(4),
O => \^rd_pntr_bin_reg[7]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(6),
I2 => Q_reg(7),
I3 => Q_reg(5),
O => \^rd_pntr_bin_reg[7]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \^rd_pntr_bin_reg[7]\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \^rd_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_wr_bin_cntr : entity is "wr_bin_cntr";
end dcfifo_32in_32out_16kb_rd_cnt_wr_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gic0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
begin
Q(0) <= \^q\(0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
I4 => wr_pntr_plus2(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
I5 => wr_pntr_plus2(5),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[8]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[8]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[8]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
I3 => \^q\(0),
O => \plusOp__0\(8)
);
\gic0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => wr_pntr_plus2(3),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => wr_pntr_plus2(2),
I5 => wr_pntr_plus2(4),
O => \gic0.gc0.count[8]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_8_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(1),
Q => p_8_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(2),
Q => p_8_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(4),
Q => p_8_out(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(5),
Q => p_8_out(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(6),
Q => p_8_out(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(7),
Q => p_8_out(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(0),
Q => p_8_out(8)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_8_out(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(8),
Q => \^q\(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(0),
I1 => RD_PNTR_WR(0),
I2 => p_8_out(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(2),
I1 => RD_PNTR_WR(2),
I2 => p_8_out(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus2(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(4),
I1 => RD_PNTR_WR(4),
I2 => p_8_out(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus2(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(6),
I1 => RD_PNTR_WR(6),
I2 => p_8_out(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus2(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_8_out(8),
I1 => RD_PNTR_WR(8),
O => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_width;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_wrapper
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_clk_x_pntrs is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 8 downto 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_dc_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_dc_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_clk_x_pntrs : entity is "clk_x_pntrs";
end dcfifo_32in_32out_16kb_rd_cnt_clk_x_pntrs;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_in7_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_1_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_2_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
RD_PNTR_WR(8 downto 0) <= \^rd_pntr_wr\(8 downto 0);
WR_PNTR_RD(8 downto 0) <= \^wr_pntr_rd\(8 downto 0);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => \gc0.count_reg[7]\(1),
I2 => \^wr_pntr_rd\(0),
I3 => \gc0.count_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => \gc0.count_reg[7]\(3),
I2 => \^wr_pntr_rd\(2),
I3 => \gc0.count_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => \gc0.count_reg[7]\(5),
I2 => \^wr_pntr_rd\(4),
I3 => \gc0.count_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => \gc0.count_reg[7]\(7),
I2 => \^wr_pntr_rd\(6),
I3 => \gc0.count_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^rd_pntr_wr\(8),
I1 => \gic0.gc0.count_reg[8]\(0),
O => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(8),
I1 => Q(8),
O => ram_empty_fb_i_reg
);
\gsync_stage[1].rd_stg_inst\: entity work.dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff
port map (
D(8 downto 0) => p_3_out(8 downto 0),
Q(8 downto 0) => wr_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_3
port map (
D(8 downto 0) => p_2_out(8 downto 0),
Q(8 downto 0) => rd_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_4
port map (
D(8 downto 0) => p_3_out(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(8),
rd_clk => rd_clk,
\wr_pntr_bin_reg[7]\(7 downto 0) => p_0_in(7 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.dcfifo_32in_32out_16kb_rd_cnt_synchronizer_ff_5
port map (
D(8 downto 0) => p_2_out(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(8),
\rd_pntr_bin_reg[7]\(7) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[7]\(6) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[7]\(5) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[7]\(4) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[7]\(3) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[7]\(2) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[7]\(1) => \gsync_stage[2].wr_stg_inst_n_7\,
\rd_pntr_bin_reg[7]\(0) => \gsync_stage[2].wr_stg_inst_n_8\,
wr_clk => wr_clk
);
\rd_dc_i[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(0),
I1 => Q(0),
O => \rd_dc_i_reg[7]_0\(0)
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => Q(7),
O => \rd_dc_i_reg[7]\(3)
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
O => \rd_dc_i_reg[7]\(2)
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => Q(5),
O => \rd_dc_i_reg[7]\(1)
);
\rd_dc_i[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(4),
I1 => Q(4),
O => \rd_dc_i_reg[7]\(0)
);
\rd_dc_i[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => Q(3),
O => \rd_dc_i_reg[7]_0\(3)
);
\rd_dc_i[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(2),
I1 => Q(2),
O => \rd_dc_i_reg[7]_0\(2)
);
\rd_dc_i[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => Q(1),
O => \rd_dc_i_reg[7]_0\(1)
);
\rd_dc_i[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(8),
I1 => Q(8),
O => S(0)
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_8\,
Q => \^rd_pntr_wr\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => \^rd_pntr_wr\(8)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \rd_pntr_gc[7]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => rd_pntr_gc(8)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(8),
Q => \^wr_pntr_rd\(8)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(0),
I1 => \gic0.gc0.count_d2_reg[8]\(1),
O => p_0_in7_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(1),
I1 => \gic0.gc0.count_d2_reg[8]\(2),
O => p_0_in7_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(2),
I1 => \gic0.gc0.count_d2_reg[8]\(3),
O => p_0_in7_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(3),
I1 => \gic0.gc0.count_d2_reg[8]\(4),
O => p_0_in7_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(4),
I1 => \gic0.gc0.count_d2_reg[8]\(5),
O => p_0_in7_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(5),
I1 => \gic0.gc0.count_d2_reg[8]\(6),
O => p_0_in7_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(6),
I1 => \gic0.gc0.count_d2_reg[8]\(7),
O => p_0_in7_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(7),
I1 => \gic0.gc0.count_d2_reg[8]\(8),
O => p_0_in7_out(7)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[8]\(8),
Q => wr_pntr_gc(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_rd_status_flags_as : entity is "rd_status_flags_as";
end dcfifo_32in_32out_16kb_rd_cnt_rd_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_rd_status_flags_as is
signal comp0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
signal ram_empty_i_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair8";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_empty_i_i_1 : label is "soft_lutpair8";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
c0: entity work.dcfifo_32in_32out_16kb_rd_cnt_compare_1
port map (
comp0 => comp0,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
c1: entity work.dcfifo_32in_32out_16kb_rd_cnt_compare_2
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i_i_1_n_0,
PRE => Q(0),
Q => \^p_18_out\
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \^p_18_out\,
I3 => comp1,
O => ram_empty_i_i_1_n_0
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i_i_1_n_0,
PRE => Q(0),
Q => empty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_wr_status_flags_as : entity is "wr_status_flags_as";
end dcfifo_32in_32out_16kb_rd_cnt_wr_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_0_out,
O => E(0)
);
c1: entity work.dcfifo_32in_32out_16kb_rd_cnt_compare
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.dcfifo_32in_32out_16kb_rd_cnt_compare_0
port map (
comp2 => comp2,
\rd_pntr_bin_reg[8]\(0) => \rd_pntr_bin_reg[8]\(0),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => p_0_out
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => rst_full_gen_i,
I1 => comp2,
I2 => p_0_out,
I3 => wr_en,
I4 => comp1,
O => ram_full_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_prim_width
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_rd_logic : entity is "rd_logic";
end dcfifo_32in_32out_16kb_rd_cnt_rd_logic;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_14_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
begin
\gras.grdc1.rdc\: entity work.dcfifo_32in_32out_16kb_rd_cnt_rd_dc_as
port map (
Q(0) => Q(0),
S(0) => S(0),
WR_PNTR_RD(7 downto 0) => WR_PNTR_RD(7 downto 0),
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
\wr_pntr_bin_reg[3]\(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0),
\wr_pntr_bin_reg[7]\(3 downto 0) => \wr_pntr_bin_reg[7]\(3 downto 0)
);
\gras.rsts\: entity work.dcfifo_32in_32out_16kb_rd_cnt_rd_status_flags_as
port map (
E(0) => p_14_out,
Q(0) => Q(0),
empty => empty,
\gc0.count_reg[8]\ => rpntr_n_0,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
rpntr: entity work.dcfifo_32in_32out_16kb_rd_cnt_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => p_14_out,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
WR_PNTR_RD(8 downto 0) => WR_PNTR_RD(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(0),
ram_empty_fb_i_reg => rpntr_n_0,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_wr_logic is
port (
full : out STD_LOGIC;
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\rd_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 8 downto 0 );
rst_full_gen_i : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_wr_logic : entity is "wr_logic";
end dcfifo_32in_32out_16kb_rd_cnt_wr_logic;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
WEBWE(0) <= \^webwe\(0);
\gwas.wsts\: entity work.dcfifo_32in_32out_16kb_rd_cnt_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
\rd_pntr_bin_reg[8]\(0) => \rd_pntr_bin_reg[8]\(0),
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \c2/v1_reg\(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.dcfifo_32in_32out_16kb_rd_cnt_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => \^webwe\(0),
Q(0) => Q(0),
RD_PNTR_WR(8 downto 0) => RD_PNTR_WR(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \c2/v1_reg\(3 downto 0),
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_top;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_generic_cstr
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_top
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
end dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2 is
begin
inst_blk_mem_gen: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2_synth
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_memory : entity is "memory";
end dcfifo_32in_32out_16kb_rd_cnt_memory;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.dcfifo_32in_32out_16kb_rd_cnt_blk_mem_gen_v8_2
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_10\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_11\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_15\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_16\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_17\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 8 to 8 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.dcfifo_32in_32out_16kb_rd_cnt_clk_x_pntrs
port map (
Q(8 downto 0) => p_20_out(8 downto 0),
RD_PNTR_WR(8 downto 0) => p_0_out(8 downto 0),
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_10\,
WR_PNTR_RD(8 downto 0) => p_1_out(8 downto 0),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
\gic0.gc0.count_reg[8]\(0) => wr_pntr_plus2(8),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
rd_clk => rd_clk,
\rd_dc_i_reg[7]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_11\,
\rd_dc_i_reg[7]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
\rd_dc_i_reg[7]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
\rd_dc_i_reg[7]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
\rd_dc_i_reg[7]_0\(3) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
\rd_dc_i_reg[7]_0\(2) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\rd_dc_i_reg[7]_0\(1) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\rd_dc_i_reg[7]_0\(0) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(0) => \gwas.wsts/c2/v1_reg\(4),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.dcfifo_32in_32out_16kb_rd_cnt_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_20_out(8 downto 0),
Q(0) => RD_RST,
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_10\,
WR_PNTR_RD(8 downto 0) => p_1_out(8 downto 0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
rd_en => rd_en,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[3]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
\wr_pntr_bin_reg[3]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\wr_pntr_bin_reg[3]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\wr_pntr_bin_reg[3]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
\wr_pntr_bin_reg[7]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_11\,
\wr_pntr_bin_reg[7]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
\wr_pntr_bin_reg[7]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
\wr_pntr_bin_reg[7]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
\wr_pntr_bin_reg[8]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.dcfifo_32in_32out_16kb_rd_cnt_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_9_out(8 downto 0),
Q(0) => wr_pntr_plus2(8),
RD_PNTR_WR(8 downto 0) => p_0_out(8 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
\rd_pntr_bin_reg[8]\(0) => \gwas.wsts/c2/v1_reg\(4),
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.dcfifo_32in_32out_16kb_rd_cnt_memory
port map (
Q(0) => rd_rst_i(0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_20_out(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.dcfifo_32in_32out_16kb_rd_cnt_reset_blk_ramfifo
port map (
Q(2) => RD_RST,
Q(1 downto 0) => rd_rst_i(1 downto 0),
\gic0.gc0.count_reg[0]\(1) => \^rst\,
\gic0.gc0.count_reg[0]\(0) => wr_rst_i(0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_top : entity is "fifo_generator_top";
end dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_top;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_top is
begin
\grf.rf\: entity work.dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0_synth;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 509;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 508;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dcfifo_32in_32out_16kb_rd_cnt : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dcfifo_32in_32out_16kb_rd_cnt : entity is "dcfifo_32in_32out_16kb_rd_cnt,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dcfifo_32in_32out_16kb_rd_cnt : entity is "dcfifo_32in_32out_16kb_rd_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=509,C_PROG_FULL_THRESH_NEGATE_VAL=508,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=2,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dcfifo_32in_32out_16kb_rd_cnt : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dcfifo_32in_32out_16kb_rd_cnt : entity is "fifo_generator_v12_0,Vivado 2015.1";
end dcfifo_32in_32out_16kb_rd_cnt;
architecture STRUCTURE of dcfifo_32in_32out_16kb_rd_cnt is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 509;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 508;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 2;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.dcfifo_32in_32out_16kb_rd_cnt_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8) => '0',
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(8) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(8) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8) => '0',
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(8) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(8) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(1 downto 0) => rd_data_count(1 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/mult_gen_0_synth_1/mult_gen_0_stub.vhdl
|
2
|
1338
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:50:02 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_0_synth_1/mult_gen_0_stub.vhdl
-- Design : mult_gen_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult_gen_0 is
Port (
A : in STD_LOGIC_VECTOR ( 32 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
P : out STD_LOGIC_VECTOR ( 53 downto 0 )
);
end mult_gen_0;
architecture stub of mult_gen_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[32:0],B[13:0],P[53:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_9,Vivado 2015.3";
begin
end;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/digilent_repo/local/ip/rgb2dvi_v1_2/src/SyncAsync.vhd
|
34
|
3727
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/mult_gen_0/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
13
|
96005
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
nk6fnppLgHlzs+TNQpNePIv69B67ibWF4Jvv+BAfKVD+4M9c5ENtop3+Z1Cz6J9J51LrN9wn+K89
GZc9q/N3Ew==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69328)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_stub.vhdl
|
3
|
1553
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_stub.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scfifo_32in_32out_1kb is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end scfifo_32in_32out_1kb;
architecture stub of scfifo_32in_32out_1kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[31:0],wr_en,rd_en,dout[31:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
gpl-3.0
|
tirfil/vhdI2CMaster
|
test/tb_compare.vhd
|
1
|
2505
|
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_COMPARE is
end tb_COMPARE;
architecture stimulus of tb_COMPARE is
-- COMPONENTS --
component COMPARE
port(
MCLK : in std_logic;
nRST : in std_logic;
TIC : in std_logic;
COMPLETED : in std_logic;
RESCAN : out std_logic;
XREG : in std_logic_vector(7 downto 0);
YREG : in std_logic_vector(7 downto 0);
ZREG : in std_logic_vector(7 downto 0);
LEDX : out std_logic;
LEDY : out std_logic;
LEDZ : out std_logic;
SIGN : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal TIC : std_logic;
signal COMPLETED : std_logic;
signal RESCAN : std_logic;
signal XREG : std_logic_vector(7 downto 0);
signal YREG : std_logic_vector(7 downto 0);
signal ZREG : std_logic_vector(7 downto 0);
signal LEDX : std_logic;
signal LEDY : std_logic;
signal LEDZ : std_logic;
signal SIGN : std_logic;
--
signal RUNNING : std_logic := '1';
signal counter : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_COMPARE_0 : COMPARE
port map (
MCLK => MCLK,
nRST => nRST,
TIC => TIC,
COMPLETED => COMPLETED,
RESCAN => RESCAN,
XREG => XREG,
YREG => YREG,
ZREG => ZREG,
LEDX => LEDX,
LEDY => LEDY,
LEDZ => LEDZ,
SIGN => SIGN
);
TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit
GEN: process(MCLK, nRST)
begin
if (nRST = '0') then
counter <= (others=>'0');
elsif (MCLK'event and MCLK='1') then
if (TIC = '1') then
counter <= (others=>'0');
else
counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8));
end if;
end if;
end process GEN;
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
begin
nRST <= '0';
XREG <= "00000000";
YREG <= "10000000";
ZREG <= "10000001";
COMPLETED <= '1';
wait for 1000 ns;
nRST <= '1';
wait for 4000 ns;
XREG <= "00000001";
YREG <= "00000010";
ZREG <= "00000011";
wait for 4000 ns;
XREG <= "10000001";
YREG <= "10000010";
ZREG <= "10000011";
wait for 4000 ns;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encdec_sim_prj/encdec_sim_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb_rd_cnt/dcfifo_32in_32out_16kb_rd_cnt_stub.vhdl
|
1
|
1720
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 22 03:39:21 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_decoder_prj/project_1.srcs/sources_1/ip/dcfifo_32in_32out_16kb_rd_cnt/dcfifo_32in_32out_16kb_rd_cnt_stub.vhdl
-- Design : dcfifo_32in_32out_16kb_rd_cnt
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcfifo_32in_32out_16kb_rd_cnt is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end dcfifo_32in_32out_16kb_rd_cnt;
architecture stub of dcfifo_32in_32out_16kb_rd_cnt is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/mult_gen_0/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd
|
13
|
7774
|
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HTyahHzmlPgwkqNsqhWGcUP1M3PTu7D89FES9ZpXDymAXA+reOzceamPqC31W9uQ4FHioIqDgFVB
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Abaetf89gJe8ekSJjia6sMZufKiMhyCKTPc=
`protect end_protected
|
gpl-3.0
|
tnsrb93/G1_RealTimeDCTSteganography
|
src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_funcsim.vhdl
|
3
|
175961
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_funcsim.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_dmem : entity is "dmem";
end scfifo_32in_32out_1kb_dmem;
architecture STRUCTURE of scfifo_32in_32out_1kb_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_30_31: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_bin_cntr is
port (
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]_0\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_32in_32out_1kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_bin_cntr is
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair4";
begin
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCC8888CCCC8888"
)
port map (
I0 => ram_full_i_i_4_n_0,
I1 => p_18_out,
I2 => ram_empty_fb_i_i_2_n_0,
I3 => \gpregsm1.curr_fwft_state_reg[0]\,
I4 => ram_full_fb_i_reg,
I5 => ram_empty_fb_i_i_5_n_0,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \gcc0.gc0.count_d1_reg[4]\(1),
I2 => \gcc0.gc0.count_d1_reg[4]\(0),
I3 => rd_pntr_plus1(0),
I4 => \gcc0.gc0.count_d1_reg[4]\(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFA8A8FFA8A8A8A8"
)
port map (
I0 => ram_full_fb_i_reg_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]_0\,
I2 => ram_full_i_i_4_n_0,
I3 => \^gpr1.dout_i_reg[1]\(0),
I4 => \gcc0.gc0.count_reg[2]\(0),
I5 => ram_full_i_i_5_n_0,
O => ram_full_comb
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_full_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(2),
I1 => \gcc0.gc0.count_reg[2]\(2),
I2 => \^gpr1.dout_i_reg[1]\(1),
I3 => \gcc0.gc0.count_reg[2]\(1),
I4 => ram_empty_fb_i_reg_0,
I5 => \gcc0.gc0.count_reg[3]\,
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_full_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_fwft is
port (
empty : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_fwft : entity is "rd_fwft";
end scfifo_32in_32out_1kb_rd_fwft;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair2";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[31]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpr1.dout_i[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_i_i_3 : label is "soft_lutpair1";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gc0.count_d1_reg[4]\(0)
);
\goreg_dm.dout_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\gpr1.dout_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gpr1.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => ram_empty_fb_i_reg
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I2 => rd_en,
I3 => p_18_out,
O => ram_full_i_reg_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I3 => curr_fwft_state(0),
I4 => wr_en,
I5 => p_1_out,
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_status_flags_ss is
port (
p_18_out : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_32in_32out_1kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_32in_32out_1kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_32in_32out_1kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair7";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => p_9_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_9_out(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => p_9_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(4),
Q => \gpr1.dout_i_reg[1]\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_9_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_9_out(4)
);
ram_full_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_9_out(3),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_9_out(4),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_status_flags_ss is
port (
\gcc0.gc0.count_reg[4]\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_32in_32out_1kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_status_flags_ss is
signal \^gcc0.gc0.count_reg[4]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair6";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gcc0.gc0.count_reg[4]\ <= \^gcc0.gc0.count_reg[4]\;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^gcc0.gc0.count_reg[4]\,
O => E(0)
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^gcc0.gc0.count_reg[4]\
);
ram_full_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => rst_full_gen_i,
O => ram_full_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_memory : entity is "memory";
end scfifo_32in_32out_1kb_memory;
architecture STRUCTURE of scfifo_32in_32out_1kb_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\gdm.dm\: entity work.scfifo_32in_32out_1kb_dmem
port map (
E(0) => E(0),
Q(31 downto 0) => p_0_out(31 downto 0),
clk => clk,
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => Q(0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_logic is
port (
empty : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_logic : entity is "rd_logic";
end scfifo_32in_32out_1kb_rd_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_logic is
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_5\ : STD_LOGIC;
signal \gr1.rfwft_n_6\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_5 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.scfifo_32in_32out_1kb_rd_fwft
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[4]\(0) => p_14_out,
\gpr1.dout_i_reg[0]\(0) => \gpr1.dout_i_reg[0]\(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gr1.rfwft_n_5\,
ram_full_i_reg => \gr1.rfwft_n_1\,
ram_full_i_reg_0 => \gr1.rfwft_n_6\,
rd_en => rd_en,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_32in_32out_1kb_rd_status_flags_ss
port map (
Q(0) => Q(0),
clk => clk,
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_5
);
rpntr: entity work.scfifo_32in_32out_1kb_rd_bin_cntr
port map (
E(0) => p_14_out,
Q(0) => Q(0),
clk => clk,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => \gcc0.gc0.count_reg[2]\(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gcc0.gc0.count_reg[3]\,
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.rfwft_n_5\,
\gpregsm1.curr_fwft_state_reg[0]_0\ => \gr1.rfwft_n_6\,
p_18_out => p_18_out,
ram_empty_fb_i_reg => rpntr_n_5,
ram_empty_fb_i_reg_0 => \gr1.rfwft_n_1\,
ram_full_comb => ram_full_comb,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_logic : entity is "wr_logic";
end scfifo_32in_32out_1kb_wr_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_32in_32out_1kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\gcc0.gc0.count_reg[4]\ => p_1_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
ram_full_i_reg_0 => ram_full_i_reg_0,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
wpntr: entity work.scfifo_32in_32out_1kb_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gc0.count_d1_reg[4]\(1 downto 0) => \gc0.count_d1_reg[4]\(1 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
ram_full_i_reg => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_32in_32out_1kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal rstblk_n_4 : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_32in_32out_1kb_rd_logic
port map (
E(0) => p_15_out,
Q(0) => RD_RST,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => p_9_out(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\gpr1.dout_i_reg[0]\(0) => ram_rd_en_i,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_20_out(4 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_32in_32out_1kb_wr_logic
port map (
AR(0) => \^rst\,
E(0) => p_4_out,
Q(2 downto 0) => p_9_out(2 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[4]\(1 downto 0) => p_20_out(4 downto 3),
\gpr1.dout_i_reg[1]\(4 downto 0) => p_10_out(4 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_32in_32out_1kb_memory
port map (
E(0) => ram_rd_en_i,
Q(0) => rstblk_n_4,
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
ram_full_fb_i_reg(0) => p_4_out
);
rstblk: entity work.scfifo_32in_32out_1kb_reset_blk_ramfifo
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => rstblk_n_4,
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_32in_32out_1kb_fifo_generator_top;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_ramfifo
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end scfifo_32in_32out_1kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_top
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end scfifo_32in_32out_1kb_fifo_generator_v12_0;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0_synth
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_32in_32out_1kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_32in_32out_1kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_32in_32out_1kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end scfifo_32in_32out_1kb;
architecture STRUCTURE of scfifo_32in_32out_1kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/mlite_pack.vhd
|
3
|
26281
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_defaults.vhd
|
9
|
30146
|
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`protect end_protected
|
gpl-3.0
|
bremathx/AoC_VHDL
|
Mor.vhd
|
1
|
211
|
--- Entity Mor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Mor IS
PORT (
A, B: IN STD_LOGIC;
R: OUT STD_LOGIC
);
END Mor;
ARCHITECTURE pure_logic OF Mor IS
BEGIN
R <= (A OR B);
END pure_logic;
|
gpl-3.0
|
sunoc/vhdl-lz4-variation
|
z_old/lz4_dictionary.vhdl
|
1
|
454
|
library ieee;
use ieee.std_logic_1164.all;
use work.lz4_pkg.all;
entity lz4_dictionary is
port (
clk_i : in std_logic;
reset_i : in std_logic;
-- for the dict comp
startpars_i : in std_logic;
dictLine_o : out std_logic_vector(185 downto 0);
todictLine_i : in std_logic_vector(185 downto 0)
);
end lz4_dictionary;
architecture behavior of lz4_dictionary is
begin
end;
|
gpl-3.0
|
1995parham/FPGA-Homework
|
HW-3/src/p5/p5.vhd
|
1
|
1376
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: p5.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (clk, load : in std_logic;
b : in std_logic_vector(7 downto 0);
serial : out std_logic);
end entity;
architecture rtl of main is
component counter
generic (N : integer := 4);
port (clk, reset : in std_logic;
count : out std_logic_vector (N - 1 downto 0));
end component;
component parity_generator
port (w, clk, reset : in std_logic;
p : out std_logic);
end component;
component shift_register
generic (N : integer := 8);
port (data_in : in std_logic_vector (N - 1 downto 0);
load, clk : in std_logic;
data_out : out std_logic);
end component;
for all:counter use entity work.counter;
for all:parity_generator use entity work.parity_generator;
for all:shift_register use entity work.shift_register;
signal w, p : std_logic;
signal c : std_logic_vector(2 downto 0);
begin
sr:shift_register generic map (8) port map (b, load, clk, w);
pg:parity_generator port map (w, clk, load, p);
cn:counter generic map (3) port map (clk, load, c);
serial <= p when c = "111" else w;
end architecture rtl;
|
gpl-3.0
|
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@m@i@s@c_@r@d@m@u@x/_primary.vhd
|
3
|
2273
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDMUX is
port(
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
COMPARATOR : in vl_logic_vector(11 downto 0);
SSE_IRQ_EN : in vl_logic_vector(20 downto 0);
SSE_IRQ : in vl_logic_vector(20 downto 0);
COMP_IRQ_EN : in vl_logic_vector(23 downto 0);
COMP_IRQ : in vl_logic_vector(23 downto 0);
PPE_FIFO_IRQ : in vl_logic_vector(8 downto 0);
PPE_FIFO_IRQ_EN : in vl_logic_vector(8 downto 0);
PPE_FLAGS0_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS0_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS1_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS1_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS2_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS2_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_FLAGS3_IRQ : in vl_logic_vector(31 downto 0);
PPE_FLAGS3_IRQ_EN: in vl_logic_vector(31 downto 0);
PPE_SFFLAGS_IRQ : in vl_logic_vector(31 downto 0);
PPE_SFFLAGS_IRQ_EN: in vl_logic_vector(31 downto 0);
FPGA_FLAGS_SEL : in vl_logic_vector(9 downto 0);
PPE_PDMA_CTRL : in vl_logic_vector(31 downto 0);
PDMA_STATUS : in vl_logic_vector(31 downto 0);
PPE_PDMA_DATAOUT: in vl_logic_vector(31 downto 0);
PADDR : in vl_logic_vector(12 downto 0);
PRDATA_MISC : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_MISC_RDMUX;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/network_2x2_packet_drop_SHMU_credit_based.vhd
|
3
|
12235
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
---------------------------------------------------------------
-- binding the routers together
-- vertical ins/outs
-- connecting router: 0 to router: 2 and vice versa
RX_N_2<= TX_S_0;
RX_S_0<= TX_N_2;
-------------------
-- connecting router: 1 to router: 3 and vice versa
RX_N_3<= TX_S_1;
RX_S_1<= TX_N_3;
-------------------
-- horizontal ins/outs
-- connecting router: 0 to router: 1 and vice versa
RX_E_0 <= TX_W_1;
RX_W_1 <= TX_E_0;
-------------------
-- connecting router: 2 to router: 3 and vice versa
RX_E_2 <= TX_W_3;
RX_W_3 <= TX_E_2;
-------------------
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_logic_pkt_fifo.vhd
|
9
|
31657
|
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|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/pc_next.vhd
|
14
|
2101
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Processor_NI/pc_next.vhd
|
14
|
2101
|
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
gpl-3.0
|
Project-Bonfire/EHA
|
FPGA-integration/RTL/NI_AXI_wrapper_top.vhd
|
3
|
5323
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_wrapper_top is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4;
NI_DEPTH : integer := 16
);
port (
-- Users to add ports here
signal AXI_RX_IRQ : out std_logic;
--Router connection
R_RX : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end AXI_wrapper_top;
architecture arch_imp of AXI_wrapper_top is
-- component declaration
component AXI_wrapper is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 4;
C_S_AXI_ADDR_WIDTH : integer := 16
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
--Router connection
AXI_RX_IRQ : out std_logic;
--Router connection
R_RX : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic
);
end component AXI_wrapper;
begin
-- Instantiation of Axi Bus Interface S00_AXI
AXI_wrapper_inst : AXI_wrapper
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH,
NI_DEPTH => NI_DEPTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready,
-- Router connection
R_RX => R_RX,
R_DRTS => R_DRTS,
R_CTS => R_CTS,
R_TX => R_TX,
R_DCTS => R_DCTS,
R_RTS => R_RTS,
AXI_RX_IRQ => AXI_RX_IRQ
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/rd_pe_as.vhd
|
9
|
25068
|
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`protect end_protected
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/control.vhd
|
9
|
16953
|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/control.vhd
|
9
|
16953
|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
gpl-3.0
|
sunoc/vhdl-lz4-variation
|
test-bench/lz4_tb.vhdl
|
1
|
2810
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; -- to read files
use work.lz4_pkg.all;
-- Test bench has no ports
entity lz4_tb is
end lz4_tb;
architecture behavior of lz4_tb is
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal entryStream_s : std_logic := '0';
signal outputStream_s : std_logic := '0';
signal outputFlag_s : std_logic := '0';
begin
uut: lz4_top port map (
clk_i => clk_i,
reset_i => reset_i,
entryStream_i => entryStream_s,
outputStream_o => outputStream_s,
outputFlag_o => outputFlag_s
);
-- Clock process definitions
clk_i_process: process
begin
clk_i <= '0';
wait for clk_period/2;
clk_i <= '1';
wait for clk_period/2;
end process;
reset_process: process
begin
reset_i <= '1';
wait for 72 ns;
reset_i <= '0';
wait;
end process;
readfile_process: process
file file_pointer_i : text;
variable r_char : character;
variable line_num_i : line;
variable line_content_i : character;
begin
wait for 5 ns;
if reset_i = '0' then
file_open(file_pointer_i, "./test-bench/test.txt.bit", READ_MODE);
while not endfile(file_pointer_i) loop
readline(file_pointer_i, line_num_i);
read(line_num_i, line_content_i);
r_char := line_content_i;
if (r_char = '0') then
entryStream_s <= '0';
elsif (r_char = '1') then
entryStream_s <= '1';
end if;
wait for 5 ns; -- wait between each value reading
end loop;
file_close(file_pointer_i);
-- send undefined values to mark the eof
for i in 0 to 7 loop
entryStream_s <= 'U';
end loop;
wait;
end if;
end process;
writefile_process: process
file file_pointer_o: text;
variable line_content_o : string(1 to 8000) := (others => '0');
variable line_num_o : line;
begin
file_open(file_pointer_o, "./test-bench/test.lz4", WRITE_MODE);
wait until (outputFlag_s = '1');
while (outputFlag_s = '1') loop
if rising_edge(clk_i) then
for i in 0 to 7999 loop
if (outputStream_s = '1') then
line_content_o(8000-i) := '1';
else
line_content_o(8000-i) := '0';
end if;
end loop;
end if;
end loop;
write(line_num_o, line_content_o);
writeline(file_pointer_o, line_num_o);
wait for 10 ns;
file_close(file_pointer_o);
wait;
end process;
dummy_test: process
begin
assert false report "end of tests" severity note;
wait; -- the final infinit loop
end process;
end;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX.vhd
|
3
|
4775
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch;
|
gpl-3.0
|
Project-Bonfire/EHA
|
FPGA-integration/RTL/NI_AXI_handshake_wrapper.vhd
|
3
|
5784
|
-- Copyright (C) Karl Janson 2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AXI_handshake_wrapper is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 16
);
port (
reset : in std_logic;
clk : in std_logic;
--Router connection
R_RX : in std_logic_vector(DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- Abstraction signals for AXI
AXI_RX_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_RX_IRQ_out : out std_logic;
AXI_data_read_in : in std_logic;
AXI_TX_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_send_en : in std_logic
);
end AXI_handshake_wrapper;
architecture Behavioral of AXI_handshake_wrapper is
component NI is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 16
);
port (
reset : in std_logic;
clk : in std_logic;
RX1 : in std_logic_vector(DATA_WIDTH-1 downto 0);
TX1 : out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS1 : in std_logic;
DCTS1 : in std_logic;
RTS1 : out std_logic;
CTS1 : out std_logic;
RX2 : in std_logic_vector(DATA_WIDTH-1 downto 0);
TX2 : out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS2 : in std_logic;
DCTS2 : in std_logic;
RTS2 : out std_logic;
CTS2 : out std_logic
);
end component;
signal PE_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal PE_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal PE_DRTS : std_logic;
signal PE_DCTS : std_logic;
signal PE_RTS : std_logic;
signal PE_CTS : std_logic;
type send_state_type is (S_IDLE, S_SEND);
type recv_state_type is (S_IDLE, S_RECV, S_WAIT);
signal send_state : send_state_type;
signal recv_state : recv_state_type;
signal RX_en : std_logic;
signal TX_en : std_logic;
signal axi_data_read : std_logic;
signal AXI_RX_IRQ : std_logic;
signal AXI_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_data_read_prev : std_logic;
begin
Network_interface: NI
generic map(
DATA_WIDTH => DATA_WIDTH,
NI_DEPTH => NI_DEPTH)
port map (
reset => reset,
clk => clk,
-- Router connection
RX1 => R_RX,
DRTS1 => R_DRTS,
CTS1 => R_CTS,
TX2 => R_TX,
DCTS2 => R_DCTS,
RTS2 => R_RTS,
-- AXI PE emulation connection
TX1 => PE_RX,
DCTS1 => PE_CTS,
RTS1 => PE_DRTS,
RX2 => PE_TX,
DRTS2 => PE_RTS,
CTS2 => PE_DCTS
);
-- FSM for sending data from AXI to the NI
AXI_TX_FSM: process (clk, reset)
begin
if (reset = '0') then
PE_RTS <= '0';
TX_en <= '0';
send_state <= S_IDLE;
elsif (clk'event and clk = '1') then
case send_state is
when S_IDLE =>
if (AXI_send_en = '1') then
PE_RTS <= '1';
TX_en <= '1';
send_state <= S_SEND;
else
TX_en <= '0';
end if;
when S_SEND =>
if (PE_DCTS = '1') then
PE_RTS <= '0';
send_state <= S_IDLE;
end if;
when others =>
PE_RTS <= '0';
TX_en <= '0';
send_state <= S_IDLE;
end case;
end if;
end process AXI_TX_FSM;
-- FSM for receiving data from the NI to teh AXI bus
AXI_RX_FSM: process (clk, reset)
begin
if (reset = '0') then
PE_CTS <= '0';
RX_en <= '0';
AXI_RX_IRQ <= '0';
recv_state <= S_IDLE;
AXI_data_read <= '1';
elsif (clk'event and clk = '1') then
case recv_state is
when S_IDLE =>
if (AXI_data_read = '1') then
if (PE_DRTS = '1') then
PE_CTS <= '1';
RX_en <= '1';
AXI_RX_IRQ <= '0';
recv_state <= S_RECV;
end if;
else
if (AXI_data_read_in = '1') then
AXI_data_read <= '1';
end if;
end if;
when S_RECV =>
RX_en <= '0';
PE_CTS <= '0';
AXI_RX_IRQ <= '1';
AXI_data_read <= '0';
recv_state <= S_IDLE;
when others =>
PE_CTS <= '0';
RX_en <= '0';
AXI_RX_IRQ <= '0';
recv_state <= S_IDLE;
end case;
end if;
end process AXI_RX_FSM;
RX_store: process (clk, reset)
begin
if (reset = '0') then
AXI_RX <= (others => '0');
elsif (clk'event and clk = '1') then
if (RX_en = '1') then
AXI_RX <= PE_RX;
else
AXI_RX <= AXI_RX;
end if;
end if;
end process RX_store;
PE_TX <= AXI_TX_in when TX_en = '1' else
(others => '0') when TX_en = '0';
AXI_RX_IRQ_out <= AXI_RX_IRQ;
AXI_RX_out <= AXI_RX;
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/arbiter_in.vhd
|
12
|
3876
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_in is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N <= '0';
X_E <= '0';
X_W <= '0';
X_S <= '0';
X_L <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/dp512x32_col/_primary.vhd
|
3
|
1368
|
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in vl_logic;
AA : in vl_logic_vector(8 downto 0);
AB : in vl_logic_vector(8 downto 0);
DIA : in vl_logic_vector(31 downto 0);
DIB : in vl_logic_vector(31 downto 0);
DOA : out vl_logic_vector(31 downto 0);
DOB : out vl_logic_vector(31 downto 0);
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0);
RB_TEST : in vl_logic;
TEST_MODE : in vl_logic
);
end dp512x32_col;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/NI_Test/xbar.vhd
|
20
|
1004
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_defaults.vhd
|
9
|
32415
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22256)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
1995parham/FPGA-Homework
|
Project-Phase1/src/sequential/fitness.vhd
|
1
|
1070
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 31-03-2016
-- Module Name: fitness.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fitness is
port (s : in string (1 to 120);
clk, reset : in std_logic;
a, b : out std_logic_vector (4 downto 0);
done : out std_logic);
end entity fitness;
architecture rtl of fitness is
begin
process (clk)
variable I : integer := 1;
begin
if clk'event and clk = '1' then
if I < 120 then
if s(I) = ' ' then
a <= "11010"; -- a = 26
else
a <= std_logic_vector(to_unsigned(character'pos(s(I)) - 96, 5)); -- a = s[i] - 'a'
end if;
if s(I + 1) = ' ' then
b <= "11010"; -- b = 26
else
b <= std_logic_vector(to_unsigned(character'pos(s(I + 1)) - 96, 5)); -- b = s[i + 1] - 'a'
end if;
I := I + 1;
end if;
end if;
end process;
end architecture rtl;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/TB_Package_32_bit_credit_based.vhd
|
9
|
15781
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX_SELgate.vhd
|
3
|
4908
|
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX_SELgate;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX_SELgate is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= SEL and SR_do(3) and CE;
toSE <= SEL and SR_do(3) and SE;
toUE <= SEL and SR_do(3) and UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_as.vhd
|
9
|
10607
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6112)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
quicky2000/top_mandelbrot_1b
|
testbench/testbench_top_mandel.vhd
|
1
|
2840
|
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench_top_mandel IS
END testbench_top_mandel;
ARCHITECTURE behavior OF testbench_top_mandel IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_mandel
PORT(
clk : IN std_logic;
w1a : INOUT std_logic_vector(15 downto 0);
w1b : INOUT std_logic_vector(15 downto 0);
w2c : INOUT std_logic_vector(15 downto 0);
rx : IN std_logic;
tx : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--BiDirs
signal w1a : std_logic_vector(15 downto 0);
signal w1b : std_logic_vector(15 downto 0);
signal w2c : std_logic_vector(15 downto 0);
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_mandel PORT MAP (
clk => clk,
w1a => w1a,
w1b => w1b,
w2c => w2c,
rx => rx,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_getinit_pkg.vhd
|
9
|
54741
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 38784)
`protect data_block
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|
gpl-3.0
|
1995parham/FPGA-Homework
|
Project-Phase2/hw/FSM.vhd
|
1
|
3898
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 13-05-2016
-- Module Name: FSM.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity FSM is
port (start_state : in std_logic_vector(3 downto 0);
end_state : out std_logic_vector(3 downto 0);
str : in std_logic_vector(31 downto 0);
enable, clk : in std_logic;
done : out std_logic);
end entity;
architecture rtl of FSM is
type state is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9);
signal current_state, next_state : state;
signal current_index, next_index : std_logic_vector(5 downto 0);
signal str_buff : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
if enable = '1' then
current_index <= "000000";
str_buff <= str;
case start_state is
when "0000" => current_state <= S0;
when "0001" => current_state <= S1;
when "0010" => current_state <= S2;
when "0011" => current_state <= S3;
when "0100" => current_state <= S4;
when "0101" => current_state <= S5;
when "0110" => current_state <= S6;
when "0111" => current_state <= S7;
when "1000" => current_state <= S8;
when "1001" => current_state <= S9;
when others => current_state <= S0;
end case;
else
current_state <= next_state;
current_index <= next_index;
end if;
end if;
end process;
process(current_state)
begin
if current_index = "100000" then
done <= '1';
else
done <= '1';
end if;
case current_state is
when S0 => end_state <= "0000";
when S1 => end_state <= "0001";
when S2 => end_state <= "0010";
when S3 => end_state <= "0011";
when S4 => end_state <= "0100";
when S5 => end_state <= "0101";
when S6 => end_state <= "0110";
when S7 => end_state <= "0111";
when S8 => end_state <= "1000";
when S9 => end_state <= "1001";
when others => end_state <= "0000";
end case;
end process;
process(current_state)
begin
if current_index = "100000" then
next_state <= current_state;
next_index <= "000000";
else
case current_state is
when S0 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S5;
else
next_state <= S1;
end if;
when S1 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S2;
else
next_state <= S7;
end if;
when S2 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S8;
else
next_state <= S3;
end if;
when S3 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S0;
else
next_state <= S7;
end if;
when S4 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S4;
else
next_state <= S9;
end if;
when S5 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S0;
else
next_state <= S6;
end if;
when S6 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S1;
else
next_state <= S7;
end if;
when S7 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S9;
else
next_state <= S2;
end if;
when S8 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S4;
else
next_state <= S3;
end if;
when S9 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S3;
else
next_state <= S8;
end if;
when others =>
next_state <= S0;
end case;
next_index <= current_index + "000001";
end if;
end process;
end architecture;
|
gpl-3.0
|
quicky2000/top_mandelbrot_1b
|
top_mandel.vhd
|
1
|
4425
|
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_mandel is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0);
w2c : inout STD_LOGIC_VECTOR (15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC
);
end top_mandel;
architecture Behavioral of top_mandel is
COMPONENT clock_25mhz
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
signal clk_25mhz : std_logic;
signal reset : std_logic;
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
signal screen_right_left : std_logic;
signal screen_up_down : std_logic;
signal r : std_logic_vector ( 5 downto 0);
signal g : std_logic_vector ( 5 downto 0);
signal b : std_logic_vector ( 5 downto 0);
signal audio_right : std_logic;
signal audio_left : std_logic;
signal x_out : std_logic_vector( 9 downto 0);
signal y_out : std_logic_vector( 8 downto 0);
signal vsync_ok : std_logic;
signal hsync_ok : std_logic;
signal enable_ok : std_logic;
-- Signals to write in screen memory
signal addr : std_logic_vector(18 downto 0) := (others => '0');
signal data_in : std_logic;
signal write_enable : std_logic;
signal edge : std_logic;
signal next_step : std_logic;
begin
Inst_clock_25mhz: clock_25mhz PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => clk_25mhz,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
Inst_giovanni_card : entity work.giovanni_card PORT MAP(
w1a => w1a,
w1b => w1b,
scr_red => r,
scr_green => g,
scr_blue => b,
scr_clk => clk_25mhz,
scr_hsync => hsync_ok,
scr_vsync => vsync_ok,
scr_enable => enable_ok,
scr_right_left => screen_right_left,
scr_up_down => screen_up_down,
audio_right => audio_right,
audio_left => audio_left,
audio_stereo_ok => open,
audio_plugged => open,
io => open
);
Inst_driver_sharp : entity work.driver_sharp(behavorial) PORT MAP(
clk => clk_25mhz,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out
);
inst_image_controler : entity work.image_controler PORT MAP(
clk => clk_25mhz,
rst => reset,
r => r,
g => g,
b => b,
x => x_out,
y => y_out,
hsync_in => hsync,
vsync_in => vsync,
enable_in => enable,
write_enable => write_enable,
write_addr => addr,
data_in => data_in,
hsync_out => hsync_ok,
vsync_out => vsync_ok,
enable_out => enable_ok
);
inst_image_generator : entity work.image_generator
port map (
clk => clk_25mhz,
rst => reset,
write_enable => write_enable,
data => data_in,
addr => addr,
next_step => next_step);
inst_falling_edge_detector : entity work.falling_edge_detector
port map (
clk => clk_25mhz,
rst => reset,
input => vsync_ok,
edge => edge);
inst_clk_divider : entity work.clk_divider
port map (
clk => clk_25mhz,
rst => reset,
input => edge,
output => next_step);
reset <= '0';
screen_right_left <= '1';
screen_up_down <= '1';
audio_right <= '0';
audio_left <= '0';
end Behavioral;
|
gpl-3.0
|
Project-Bonfire/EHA
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SReg.vhd
|
3
|
2127
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end SReg;
architecture SReg_arch of SReg is
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (Size-1 downto 0);
component ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
constant ResetValue : STD_LOGIC_VECTOR (Size-1 downto 0) := (others => '0'); -- ResetValue 1'b0
begin
SO <= SR_so; -- Source SR
DO <= SR_do; -- Source SR
SR : ScanRegister
Generic map (Size => Size,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0, -- Source SR[0]
ResetValue => ResetValue)
Port map ( SI => SI, -- ScanInSource SI
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => DI, -- CaptureSource DI
ScanRegister_out => SR_do);
end SReg_arch;
|
gpl-3.0
|
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_bin_cntr.vhd
|
9
|
21696
|
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`protect end_protected
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/fifo_generator_v12_0/hdl/builtin/logic_builtin.vhd
|
6
|
30579
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20896)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd
|
17
|
21293
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13632)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
ipburbank/Raster-Laser-Projector
|
src/Video_In/synthesis/submodules/PI_Controller.vhd
|
2
|
407
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY PI_Controller IS
PORT ( error : IN INTEGER ;
control : OUT INTEGER;
clk : in std_logic;
reset : in std_logic) ;
END PI_Controller;
architecture Behavioral of PI_Controller is
signal u1: std_logic_vector(15 downto 0);
constant k1: std_logic_vector( 6 downto 0 ):="1101011";
begin
process( clk)
begin
end process;
end Behavioral;
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_sim_netlist.vhdl
|
1
|
255611
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed Jul 20 01:57:48 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_sim_netlist.vhdl}
-- Design : shd_pe_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end shd_pe_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => din(31 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => D(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare : entity is "compare";
end shd_pe_fifo_compare;
architecture STRUCTURE of shd_pe_fifo_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_0 is
port (
ram_full_i : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_0_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_0 : entity is "compare";
end shd_pe_fifo_compare_0;
architecture STRUCTURE of shd_pe_fifo_compare_0 is
signal comp2 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF20"
)
port map (
I0 => comp2,
I1 => p_0_out,
I2 => wr_en,
I3 => comp1,
I4 => rst_full_gen_i,
O => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_1 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_2_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_1 : entity is "compare";
end shd_pe_fifo_compare_1;
architecture STRUCTURE of shd_pe_fifo_compare_1 is
signal comp0 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBBAAAAAAAA"
)
port map (
I0 => comp0,
I1 => p_2_out,
I2 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => rd_en,
I5 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_2 : entity is "compare";
end shd_pe_fifo_compare_2;
architecture STRUCTURE of shd_pe_fifo_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end shd_pe_fifo_rd_bin_cntr;
architecture STRUCTURE of shd_pe_fifo_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[9]_i_2\ : label is "soft_lutpair10";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
I5 => \^q\(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gc0.count[9]_i_2_n_0\,
I3 => \^q\(6),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(8),
I1 => \^q\(6),
I2 => \gc0.count[9]_i_2_n_0\,
I3 => \^q\(5),
I4 => \^q\(7),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(9),
I1 => \^q\(7),
I2 => \^q\(5),
I3 => \gc0.count[9]_i_2_n_0\,
I4 => \^q\(6),
I5 => \^q\(8),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(9),
Q => \^q\(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => WR_PNTR_RD(1),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I3 => WR_PNTR_RD(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => WR_PNTR_RD(3),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I3 => WR_PNTR_RD(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => WR_PNTR_RD(5),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I3 => WR_PNTR_RD(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => WR_PNTR_RD(7),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I3 => WR_PNTR_RD(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => WR_PNTR_RD(9),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I3 => WR_PNTR_RD(8),
O => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\goreg_bm.dout_i_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_2_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_fwft : entity is "rd_fwft";
end shd_pe_fifo_rd_fwft;
architecture STRUCTURE of shd_pe_fifo_rd_fwft is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[0]_i_1_n_0\ : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair9";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[9]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair8";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAEFFF"
)
port map (
I0 => Q(0),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I3 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I4 => p_2_out,
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA22"
)
port map (
I0 => empty_fwft_fb,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I2 => rd_en,
I3 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => p_2_out,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I3 => rd_en,
O => E(0)
);
\goreg_bm.dout_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
O => \goreg_bm.dout_i_reg[31]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
O => \gpregsm1.curr_fwft_state[0]_i_1_n_0\
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I2 => rd_en,
I3 => p_2_out,
O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[0]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end shd_pe_fifo_reset_blk_ramfifo;
architecture STRUCTURE of shd_pe_fifo_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_pe_fifo_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_pe_fifo_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \shd_pe_fifo_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \shd_pe_fifo_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_3 is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_3 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_3;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_4 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_4 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_4;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \wr_pntr_bin[0]_i_2_n_0\,
I4 => \wr_pntr_bin[3]_i_2_n_0\,
O => \wr_pntr_bin_reg[8]\(0)
);
\wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \wr_pntr_bin[0]_i_2_n_0\
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \wr_pntr_bin[3]_i_2_n_0\,
I5 => Q_reg(1),
O => \wr_pntr_bin_reg[8]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \wr_pntr_bin[3]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \wr_pntr_bin_reg[8]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \wr_pntr_bin[3]_i_2_n_0\,
O => \wr_pntr_bin_reg[8]\(3)
);
\wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \wr_pntr_bin[3]_i_2_n_0\
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \wr_pntr_bin_reg[8]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \wr_pntr_bin_reg[8]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \wr_pntr_bin_reg[8]\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \wr_pntr_bin_reg[8]\(7)
);
\wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_5 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_5 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_5;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(9),
Q => Q_reg(9)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \rd_pntr_bin[0]_i_2_n_0\,
I4 => \rd_pntr_bin[3]_i_2_n_0\,
O => \rd_pntr_bin_reg[8]\(0)
);
\rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \rd_pntr_bin[0]_i_2_n_0\
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \rd_pntr_bin[3]_i_2_n_0\,
I5 => Q_reg(1),
O => \rd_pntr_bin_reg[8]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \rd_pntr_bin[3]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \rd_pntr_bin_reg[8]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \rd_pntr_bin[3]_i_2_n_0\,
O => \rd_pntr_bin_reg[8]\(3)
);
\rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \rd_pntr_bin[3]_i_2_n_0\
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \rd_pntr_bin_reg[8]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \rd_pntr_bin_reg[8]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \rd_pntr_bin_reg[8]\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \rd_pntr_bin_reg[8]\(7)
);
\rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end shd_pe_fifo_wr_bin_cntr;
architecture STRUCTURE of shd_pe_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_2\ : label is "soft_lutpair13";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gic0.gc0.count_d2_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_d2_reg[9]_0\(9 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
I5 => \^q\(4),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => \^q\(5),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gic0.gc0.count[9]_i_2_n_0\,
I3 => \^q\(6),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(8),
I1 => \^q\(6),
I2 => \gic0.gc0.count[9]_i_2_n_0\,
I3 => \^q\(5),
I4 => \^q\(7),
O => \plusOp__0\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(9),
I1 => \^q\(7),
I2 => \^q\(5),
I3 => \gic0.gc0.count[9]_i_2_n_0\,
I4 => \^q\(6),
I5 => \^q\(8),
O => \plusOp__0\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^q\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[9]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[9]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[9]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[9]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[9]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[9]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(6),
Q => \^gic0.gc0.count_d2_reg[9]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(7),
Q => \^gic0.gc0.count_d2_reg[9]_0\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(8),
Q => \^gic0.gc0.count_d2_reg[9]_0\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(9),
Q => \^gic0.gc0.count_d2_reg[9]_0\(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[9]_0\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end shd_pe_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.shd_pe_fifo_blk_mem_gen_prim_wrapper
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_clk_x_pntrs : entity is "clk_x_pntrs";
end shd_pe_fifo_clk_x_pntrs;
architecture STRUCTURE of shd_pe_fifo_clk_x_pntrs is
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_0_in8_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_1_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
WR_PNTR_RD(9 downto 0) <= \^wr_pntr_rd\(9 downto 0);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => Q(1),
I2 => \^wr_pntr_rd\(0),
I3 => Q(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_d1_reg[9]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_d1_reg[9]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_reg[9]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_reg[9]\(0),
O => v1_reg_1(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => Q(3),
I2 => \^wr_pntr_rd\(2),
I3 => Q(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_d1_reg[9]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_d1_reg[9]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_reg[9]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_reg[9]\(2),
O => v1_reg_1(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => Q(5),
I2 => \^wr_pntr_rd\(4),
I3 => Q(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_d1_reg[9]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_d1_reg[9]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_reg[9]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_reg[9]\(4),
O => v1_reg_1(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => Q(7),
I2 => \^wr_pntr_rd\(6),
I3 => Q(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_d1_reg[9]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_d1_reg[9]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_reg[9]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_reg[9]\(6),
O => v1_reg_1(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(9),
I1 => Q(9),
I2 => \^wr_pntr_rd\(8),
I3 => Q(8),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(9),
I1 => \gic0.gc0.count_d1_reg[9]\(9),
I2 => p_22_out(8),
I3 => \gic0.gc0.count_d1_reg[9]\(8),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(9),
I1 => \gic0.gc0.count_reg[9]\(9),
I2 => p_22_out(8),
I3 => \gic0.gc0.count_reg[9]\(8),
O => v1_reg_1(4)
);
\gsync_stage[1].rd_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_3
port map (
D(9 downto 0) => p_2_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_4
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(9),
rd_clk => rd_clk,
\wr_pntr_bin_reg[8]\(8 downto 0) => p_0_in(8 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_5
port map (
D(9 downto 0) => p_2_out(9 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(9),
\rd_pntr_bin_reg[8]\(8) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[8]\(7) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[8]\(6) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[8]\(5) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[8]\(4) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[8]\(3) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[8]\(2) => \gsync_stage[2].wr_stg_inst_n_7\,
\rd_pntr_bin_reg[8]\(1) => \gsync_stage[2].wr_stg_inst_n_8\,
\rd_pntr_bin_reg[8]\(0) => \gsync_stage[2].wr_stg_inst_n_9\,
wr_clk => wr_clk
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_9\,
Q => p_22_out(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_8\,
Q => p_22_out(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => p_22_out(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => p_22_out(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => p_22_out(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => p_22_out(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => p_22_out(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => p_22_out(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => p_22_out(8)
);
\rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(9),
Q => p_22_out(9)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(0),
I1 => \gc0.count_d1_reg[9]\(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(1),
I1 => \gc0.count_d1_reg[9]\(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(2),
I1 => \gc0.count_d1_reg[9]\(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(3),
I1 => \gc0.count_d1_reg[9]\(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(4),
I1 => \gc0.count_d1_reg[9]\(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(5),
I1 => \gc0.count_d1_reg[9]\(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(6),
I1 => \gc0.count_d1_reg[9]\(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(7),
I1 => \gc0.count_d1_reg[9]\(8),
O => \rd_pntr_gc[7]_i_1_n_0\
);
\rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count_d1_reg[9]\(8),
I1 => \gc0.count_d1_reg[9]\(9),
O => \rd_pntr_gc[8]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[9]\(9),
Q => rd_pntr_gc(9)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(8),
Q => \^wr_pntr_rd\(8)
);
\wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(9),
Q => \^wr_pntr_rd\(9)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => p_0_in8_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => p_0_in8_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => p_0_in8_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => p_0_in8_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => p_0_in8_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => p_0_in8_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => p_0_in8_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => p_0_in8_out(7)
);
\wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => p_0_in8_out(8)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in8_out(8),
Q => wr_pntr_gc(8)
);
\wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_status_flags_as is
port (
p_2_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_status_flags_as : entity is "rd_status_flags_as";
end shd_pe_fifo_rd_status_flags_as;
architecture STRUCTURE of shd_pe_fifo_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \^p_2_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
p_2_out <= \^p_2_out\;
c0: entity work.shd_pe_fifo_compare_1
port map (
comp1 => comp1,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
p_2_out => \^p_2_out\,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
c1: entity work.shd_pe_fifo_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => Q(0),
Q => \^p_2_out\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_status_flags_as : entity is "wr_status_flags_as";
end shd_pe_fifo_wr_status_flags_as;
architecture STRUCTURE of shd_pe_fifo_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_0_out,
O => E(0)
);
c1: entity work.shd_pe_fifo_compare
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.shd_pe_fifo_compare_0
port map (
comp1 => comp1,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => p_0_out
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end shd_pe_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.shd_pe_fifo_blk_mem_gen_prim_width
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_logic is
port (
empty : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_logic : entity is "rd_logic";
end shd_pe_fifo_rd_logic;
architecture STRUCTURE of shd_pe_fifo_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
begin
\gr1.rfwft\: entity work.shd_pe_fifo_rd_fwft
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \gr1.rfwft_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => curr_fwft_state(0),
E(0) => \gr1.rfwft_n_1\,
Q(1 downto 0) => Q(1 downto 0),
empty => empty,
\goreg_bm.dout_i_reg[31]\(0) => E(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.shd_pe_fifo_rd_status_flags_as
port map (
Q(0) => Q(1),
\gpregsm1.curr_fwft_state_reg[1]\(1) => \gr1.rfwft_n_2\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => curr_fwft_state(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0)
);
rpntr: entity work.shd_pe_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gr1.rfwft_n_1\,
Q(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
WR_PNTR_RD(9 downto 0) => WR_PNTR_RD(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
rd_clk => rd_clk,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_logic is
port (
full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_logic : entity is "wr_logic";
end shd_pe_fifo_wr_logic;
architecture STRUCTURE of shd_pe_fifo_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.shd_pe_fifo_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.shd_pe_fifo_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => Q(9 downto 0),
\gic0.gc0.count_d2_reg[9]_0\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end shd_pe_fifo_blk_mem_gen_top;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.shd_pe_fifo_blk_mem_gen_generic_cstr
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_v8_3_1_synth is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end shd_pe_fifo_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.shd_pe_fifo_blk_mem_gen_top
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_v8_3_1 is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
end shd_pe_fifo_blk_mem_gen_v8_3_1;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_v8_3_1 is
begin
inst_blk_mem_gen: entity work.shd_pe_fifo_blk_mem_gen_v8_3_1_synth
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_memory : entity is "memory";
end shd_pe_fifo_memory;
architecture STRUCTURE of shd_pe_fifo_memory is
signal doutb : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.shd_pe_fifo_blk_mem_gen_v8_3_1
port map (
D(31 downto 0) => doutb(31 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(24),
Q => dout(24),
R => Q(0)
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(25),
Q => dout(25),
R => Q(0)
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(26),
Q => dout(26),
R => Q(0)
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(27),
Q => dout(27),
R => Q(0)
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(28),
Q => dout(28),
R => Q(0)
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(29),
Q => dout(29),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(30),
Q => dout(30),
R => Q(0)
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(31),
Q => dout(31),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end shd_pe_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_17_out : STD_LOGIC;
signal p_21_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.shd_pe_fifo_clk_x_pntrs
port map (
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
WR_PNTR_RD(9 downto 0) => p_21_out(9 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gic0.gc0.count_d1_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_11_out(9 downto 0),
\gic0.gc0.count_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
rd_clk => rd_clk,
v1_reg(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gwas.wsts/c1/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.shd_pe_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => p_5_out,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
WR_PNTR_RD(9 downto 0) => p_21_out(9 downto 0),
empty => empty,
\gc0.count_d1_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.shd_pe_fifo_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_11_out(9 downto 0),
E(0) => p_17_out,
Q(9 downto 0) => wr_pntr_plus2(9 downto 0),
full => full,
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => \gwas.wsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.shd_pe_fifo_memory
port map (
E(0) => p_17_out,
Q(0) => rd_rst_i(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_11_out(9 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out,
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.\shd_pe_fifo_reset_blk_ramfifo__parameterized0\
port map (
Q(1) => \^rst\,
Q(0) => wr_rst_i(0),
\gc0.count_reg[1]\(2) => RD_RST,
\gc0.count_reg[1]\(1 downto 0) => rd_rst_i(1 downto 0),
rd_clk => rd_clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_top : entity is "fifo_generator_top";
end shd_pe_fifo_fifo_generator_top;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.shd_pe_fifo_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_v13_0_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_v13_0_1_synth : entity is "fifo_generator_v13_0_1_synth";
end shd_pe_fifo_fifo_generator_v13_0_1_synth;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_v13_0_1_synth is
begin
\gconvfifo.rf\: entity work.shd_pe_fifo_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
\reset_gen_ic.rstblk_cc\: entity work.shd_pe_fifo_reset_blk_ramfifo
port map (
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_v13_0_1 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of shd_pe_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_v13_0_1 : entity is "fifo_generator_v13_0_1";
end shd_pe_fifo_fifo_generator_v13_0_1;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_v13_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.shd_pe_fifo_fifo_generator_v13_0_1_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
m_aclk => m_aclk,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of shd_pe_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of shd_pe_fifo : entity is "shd_pe_fifo,fifo_generator_v13_0_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of shd_pe_fifo : entity is "shd_pe_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shd_pe_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of shd_pe_fifo : entity is "fifo_generator_v13_0_1,Vivado 2015.4";
end shd_pe_fifo;
architecture STRUCTURE of shd_pe_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.shd_pe_fifo_fifo_generator_v13_0_1
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
rbesenczi/real-time-traffic-analyzer
|
src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_afifo_autord.vhd
|
2
|
17893
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 12/21/2009 First Version
-- GAB 3/23/2010 renamed for axi_dma
--
-- GAB 10/15/10 v4_03
-- ^^^^^^
-- - Updated libraries to v4_03
-- ~~~~~~
-- GAB 2/15/11 v4_030_a
-- ^^^^^^
-- Updated libraries to v4_030_a
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-- GAB 7/19/11 v4_03
-- ^^^^^^
-- Update for use with axi_sg_v4_03
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex6"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
-- signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-2 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal afifo_full_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Full <= afifo_full_i;
-- AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Wr_count <= afifo_full_i & wr_count_lil_end;
-- AFIFO_Rd_count <= 'rd_count_lil_end;
AFIFO_Rd_count <= '0' & rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_SYNCHRONIZER_STAGE => 4,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
-- C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_COUNT_WIDTH => C_CNT_WIDTH-1,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
-- C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_COUNT_WIDTH => C_CNT_WIDTH-1,
C_WR_ERR_LOW => 0
--C_WR_ERR_LOW => 0,
--C_USE_EMBEDDED_REG => 1, -- 0 ;
--C_PRELOAD_REGS => 0, -- 0 ;
--C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
-- Full => AFIFO_Full,
Full => afifo_full_i,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_fsm.vhd
|
8
|
83900
|
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`protect end_protected
|
gpl-3.0
|
rbesenczi/real-time-traffic-analyzer
|
src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/d3fab4a1/hdl/src/vhdl/cdc_sync.vhd
|
21
|
47317
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= s_out_d2 xor s_out_d3;
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= s_out_d3 xor s_out_d4;
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= s_out_d4 xor s_out_d5;
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= s_out_d5 xor s_out_d6;
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= s_out_d6 xor s_out_d7;
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/fifo_generator_v12_0/hdl/ramfifo/wr_status_flags_as.vhd
|
6
|
20484
|
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`protect end_protected
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_low_latency.vhd
|
6
|
43742
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
fmadotto/DS_sha256
|
src/hdl/old_design/cla.vhd
|
1
|
2172
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- cla.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity cla is
generic (
n : natural := 32 -- input size (default is 32 bits)
);
port (
x : in std_ulogic_vector(n-1 downto 0); -- first binary number to sum
y : in std_ulogic_vector(n-1 downto 0); -- second binary number to sum
sum : out std_ulogic_vector(n-1 downto 0); -- result of the sum
cout : out std_ulogic -- carry out
);
end entity cla;
architecture rtl of cla is
signal G : std_ulogic_vector(n-1 downto 0); -- generate signal: G_i = x_i * y_i
signal P : std_ulogic_vector(n-1 downto 0); -- propagate signal: P_i = x_i + y_i
signal S : std_ulogic_vector(n-1 downto 0); -- sum signal
signal C : std_ulogic_vector(n downto 0); -- carry signal
begin
FA_gen : for i in 0 to n-1 generate
FA_instance : entity work.full_adder
port map (
x => x(i),
y => y(i),
cin => C(i),
sum => S(i),
cout => open
);
end generate FA_gen;
C(0) <= '0'; -- there is no initial carry
PGC_gen : for j in 0 to n-1 generate
G(j) <= x(j) and y(j);
P(j) <= x(j) or y(j);
C(j+1) <= G(j) or (P(j) and C(j));
end generate PGC_gen;
sum <= S;
cout <= C(n);
end architecture rtl;
|
gpl-3.0
|
rbesenczi/real-time-traffic-analyzer
|
src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/synth/design_1_axi_uartlite_0_0.vhd
|
1
|
8972
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=4800,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 4800,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_funcsim.vhdl
|
1
|
255026
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Oct 25 15:45:18 2015
-- Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_funcsim.vhdl
-- Design : shd_pe_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end shd_pe_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_prim_wrapper is
signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => O1(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => I1(11 downto 0),
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => D(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare is
port (
comp1 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare : entity is "compare";
end shd_pe_fifo_compare;
architecture STRUCTURE of shd_pe_fifo_compare is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(0),
I1 => RD_PNTR_WR(0),
I2 => Q(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(2),
I1 => RD_PNTR_WR(2),
I2 => Q(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(4),
I1 => RD_PNTR_WR(4),
I2 => Q(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(6),
I1 => RD_PNTR_WR(6),
I2 => Q(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(8),
I1 => RD_PNTR_WR(8),
I2 => Q(9),
I3 => RD_PNTR_WR(9),
O => v1_reg(4)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => Q(10),
I1 => RD_PNTR_WR(10),
I2 => Q(11),
I3 => RD_PNTR_WR(11),
O => v1_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_0 is
port (
comp2 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_0 : entity is "compare";
end shd_pe_fifo_compare_0;
architecture STRUCTURE of shd_pe_fifo_compare_0 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(0),
I1 => RD_PNTR_WR(0),
I2 => \out\(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(2),
I1 => RD_PNTR_WR(2),
I2 => \out\(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(4),
I1 => RD_PNTR_WR(4),
I2 => \out\(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(6),
I1 => RD_PNTR_WR(6),
I2 => \out\(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp2,
CO(0) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(8),
I1 => RD_PNTR_WR(8),
I2 => \out\(9),
I3 => RD_PNTR_WR(9),
O => v1_reg(4)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \out\(10),
I1 => RD_PNTR_WR(10),
I2 => \out\(11),
I3 => RD_PNTR_WR(11),
O => v1_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_1 is
port (
comp0 : out STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_1 : entity is "compare";
end shd_pe_fifo_compare_1;
architecture STRUCTURE of shd_pe_fifo_compare_1 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(0),
I1 => O1(0),
I2 => WR_PNTR_RD(1),
I3 => O1(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(2),
I1 => O1(2),
I2 => WR_PNTR_RD(3),
I3 => O1(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(4),
I1 => O1(4),
I2 => WR_PNTR_RD(5),
I3 => O1(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(6),
I1 => O1(6),
I2 => WR_PNTR_RD(7),
I3 => O1(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(8),
I1 => O1(8),
I2 => WR_PNTR_RD(9),
I3 => O1(9),
O => v1_reg(4)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(10),
I1 => O1(10),
I2 => WR_PNTR_RD(11),
I3 => O1(11),
O => v1_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_compare_2 : entity is "compare";
end shd_pe_fifo_compare_2;
architecture STRUCTURE of shd_pe_fifo_compare_2 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(0),
I1 => \out\(0),
I2 => WR_PNTR_RD(1),
I3 => \out\(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(2),
I1 => \out\(2),
I2 => WR_PNTR_RD(3),
I3 => \out\(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(4),
I1 => \out\(4),
I2 => WR_PNTR_RD(5),
I3 => \out\(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(6),
I1 => \out\(6),
I2 => WR_PNTR_RD(7),
I3 => \out\(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(8),
I1 => \out\(8),
I2 => WR_PNTR_RD(9),
I3 => \out\(9),
O => v1_reg(4)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => WR_PNTR_RD(10),
I1 => \out\(10),
I2 => WR_PNTR_RD(11),
I3 => \out\(11),
O => v1_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_bin_cntr is
port (
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
sel : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end shd_pe_fifo_rd_bin_cntr;
architecture STRUCTURE of shd_pe_fifo_rd_bin_cntr is
signal \n_0_gc0.count[0]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[0]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[10]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[10]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[1]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[1]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[2]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[3]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[4]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[4]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[5]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[5]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[6]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[6]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[7]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[7]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[8]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[8]_i_2\ : STD_LOGIC;
signal \n_0_gc0.count_reg[9]_i_1\ : STD_LOGIC;
signal \n_0_gc0.count_reg[9]_i_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gc0.count_reg[1]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \gc0.count_reg[1]_i_2_CARRY4\ : label is "LO:O";
attribute XILINX_LEGACY_PRIM of \gc0.count_reg[5]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP of \gc0.count_reg[5]_i_2_CARRY4\ : label is "LO:O";
attribute XILINX_LEGACY_PRIM of \gc0.count_reg[9]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP of \gc0.count_reg[9]_i_2_CARRY4\ : label is "LO:O";
begin
\out\(11 downto 0) <= \^out\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(0),
O => \n_0_gc0.count[0]_i_2\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(0),
Q => O1(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(10),
Q => O1(10)
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(11),
Q => O1(11)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(1),
Q => O1(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(2),
Q => O1(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(3),
Q => O1(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(4),
Q => O1(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(5),
Q => O1(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(6),
Q => O1(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(7),
Q => O1(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(8),
Q => O1(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \^out\(9),
Q => O1(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => sel,
D => \n_0_gc0.count_reg[0]_i_1\,
PRE => Q(0),
Q => \^out\(0)
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[10]_i_1\,
Q => \^out\(10)
);
\gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[11]_i_1\,
Q => \^out\(11)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[1]_i_1\,
Q => \^out\(1)
);
\gc0.count_reg[1]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gc0.count_reg[4]_i_2\,
CO(2) => \n_0_gc0.count_reg[3]_i_2\,
CO(1) => \n_0_gc0.count_reg[2]_i_2\,
CO(0) => \n_0_gc0.count_reg[1]_i_2\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '1',
O(3) => \n_0_gc0.count_reg[3]_i_1\,
O(2) => \n_0_gc0.count_reg[2]_i_1\,
O(1) => \n_0_gc0.count_reg[1]_i_1\,
O(0) => \n_0_gc0.count_reg[0]_i_1\,
S(3 downto 1) => \^out\(3 downto 1),
S(0) => \n_0_gc0.count[0]_i_2\
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[2]_i_1\,
Q => \^out\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[3]_i_1\,
Q => \^out\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[4]_i_1\,
Q => \^out\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[5]_i_1\,
Q => \^out\(5)
);
\gc0.count_reg[5]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gc0.count_reg[4]_i_2\,
CO(3) => \n_0_gc0.count_reg[8]_i_2\,
CO(2) => \n_0_gc0.count_reg[7]_i_2\,
CO(1) => \n_0_gc0.count_reg[6]_i_2\,
CO(0) => \n_0_gc0.count_reg[5]_i_2\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3) => \n_0_gc0.count_reg[7]_i_1\,
O(2) => \n_0_gc0.count_reg[6]_i_1\,
O(1) => \n_0_gc0.count_reg[5]_i_1\,
O(0) => \n_0_gc0.count_reg[4]_i_1\,
S(3 downto 0) => \^out\(7 downto 4)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[6]_i_1\,
Q => \^out\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[7]_i_1\,
Q => \^out\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[8]_i_1\,
Q => \^out\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => sel,
CLR => Q(0),
D => \n_0_gc0.count_reg[9]_i_1\,
Q => \^out\(9)
);
\gc0.count_reg[9]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gc0.count_reg[8]_i_2\,
CO(3 downto 2) => \NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \n_0_gc0.count_reg[10]_i_2\,
CO(0) => \n_0_gc0.count_reg[9]_i_2\,
CYINIT => '0',
DI(3) => \NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED\(3),
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3) => \n_0_gc0.count_reg[11]_i_1\,
O(2) => \n_0_gc0.count_reg[10]_i_1\,
O(1) => \n_0_gc0.count_reg[9]_i_1\,
O(0) => \n_0_gc0.count_reg[8]_i_1\,
S(3 downto 0) => \^out\(11 downto 8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_fwft is
port (
empty : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sel : out STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_fwft : entity is "rd_fwft";
end shd_pe_fifo_rd_fwft;
architecture STRUCTURE of shd_pe_fifo_rd_fwft is
signal \^o1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair19";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[11]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[7]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair18";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
O1(1 downto 0) <= \^o1\(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABBBBBB"
)
port map (
I0 => Q(0),
I1 => p_18_out,
I2 => rd_en,
I3 => \^o1\(0),
I4 => \^o1\(1),
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA22"
)
port map (
I0 => empty_fwft_fb,
I1 => \^o1\(1),
I2 => rd_en,
I3 => \^o1\(0),
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00BF"
)
port map (
I0 => rd_en,
I1 => \^o1\(0),
I2 => \^o1\(1),
I3 => p_18_out,
O => sel
);
\goreg_bm.dout_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \^o1\(1),
I1 => \^o1\(0),
I2 => rd_en,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^o1\(1),
I1 => rd_en,
I2 => \^o1\(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => rd_en,
I1 => \^o1\(0),
I2 => \^o1\(1),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => \^o1\(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(1),
Q => \^o1\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_reset_blk_ramfifo is
port (
rst_d2 : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end shd_pe_fifo_reset_blk_ramfifo;
architecture STRUCTURE of shd_pe_fifo_reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => rd_clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => O1(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => O1(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => O1(2)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => wr_clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => Q(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
rd_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[10]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[11]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[11]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[9]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(10),
Q => Q(10)
);
\Q_reg_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(11),
Q => Q(11)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(4),
Q => Q(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(5),
Q => Q(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(6),
Q => Q(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(7),
Q => Q(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(8),
Q => Q(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_3 is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_3 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_3;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_3 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[10]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[11]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[11]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[9]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(10),
Q => Q(10)
);
\Q_reg_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(11),
Q => Q(11)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(4),
Q => Q(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(5),
Q => Q(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(6),
Q => Q(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(7),
Q => Q(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(8),
Q => Q(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => I1(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_4 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
rd_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_4 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_4;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_4 is
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[10]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[4]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[5]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[6]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[7]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[8]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[9]\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[10]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[11]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[11]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[9]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[9]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_bin[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_bin[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_bin[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_bin[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[9]_i_1\ : label is "soft_lutpair3";
begin
p_0_in(11 downto 0) <= \^p_0_in\(11 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(10),
Q => \n_0_Q_reg_reg[10]\
);
\Q_reg_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(11),
Q => \^p_0_in\(11)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(4),
Q => \n_0_Q_reg_reg[4]\
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(5),
Q => \n_0_Q_reg_reg[5]\
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(6),
Q => \n_0_Q_reg_reg[6]\
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(7),
Q => \n_0_Q_reg_reg[7]\
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(8),
Q => \n_0_Q_reg_reg[8]\
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => D(9),
Q => \n_0_Q_reg_reg[9]\
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \n_0_Q_reg_reg[0]\,
I3 => \^p_0_in\(3),
O => \^p_0_in\(0)
);
\wr_pntr_bin[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[10]\,
I1 => \^p_0_in\(11),
O => \^p_0_in\(10)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \n_0_Q_reg_reg[3]\,
I3 => \n_0_Q_reg_reg[5]\,
I4 => \^p_0_in\(6),
I5 => \n_0_Q_reg_reg[4]\,
O => \^p_0_in\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[5]\,
I2 => \^p_0_in\(6),
I3 => \n_0_Q_reg_reg[4]\,
I4 => \n_0_Q_reg_reg[2]\,
O => \^p_0_in\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[4]\,
I1 => \^p_0_in\(6),
I2 => \n_0_Q_reg_reg[5]\,
I3 => \n_0_Q_reg_reg[3]\,
O => \^p_0_in\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[5]\,
I1 => \^p_0_in\(6),
I2 => \n_0_Q_reg_reg[4]\,
O => \^p_0_in\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^p_0_in\(6),
I1 => \n_0_Q_reg_reg[5]\,
O => \^p_0_in\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \n_0_Q_reg_reg[7]\,
I1 => \^p_0_in\(11),
I2 => \n_0_Q_reg_reg[9]\,
I3 => \n_0_Q_reg_reg[10]\,
I4 => \n_0_Q_reg_reg[8]\,
I5 => \n_0_Q_reg_reg[6]\,
O => \^p_0_in\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[8]\,
I1 => \n_0_Q_reg_reg[10]\,
I2 => \n_0_Q_reg_reg[9]\,
I3 => \^p_0_in\(11),
I4 => \n_0_Q_reg_reg[7]\,
O => \^p_0_in\(7)
);
\wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^p_0_in\(11),
I1 => \n_0_Q_reg_reg[9]\,
I2 => \n_0_Q_reg_reg[10]\,
I3 => \n_0_Q_reg_reg[8]\,
O => \^p_0_in\(8)
);
\wr_pntr_bin[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[10]\,
I1 => \n_0_Q_reg_reg[9]\,
I2 => \^p_0_in\(11),
O => \^p_0_in\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_synchronizer_ff_5 is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 10 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_synchronizer_ff_5 : entity is "synchronizer_ff";
end shd_pe_fifo_synchronizer_ff_5;
architecture STRUCTURE of shd_pe_fifo_synchronizer_ff_5 is
signal \^o1\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[10]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[4]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[5]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[6]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[7]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[8]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[9]\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[10]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[11]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[11]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[8]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[9]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[9]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[10]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_bin[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_bin[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_bin[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_bin[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_bin[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_bin[8]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_bin[9]_i_1\ : label is "soft_lutpair7";
begin
O1(10 downto 0) <= \^o1\(10 downto 0);
Q(0) <= \^q\(0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(10),
Q => \n_0_Q_reg_reg[10]\
);
\Q_reg_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(11),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(4),
Q => \n_0_Q_reg_reg[4]\
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(5),
Q => \n_0_Q_reg_reg[5]\
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(6),
Q => \n_0_Q_reg_reg[6]\
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(7),
Q => \n_0_Q_reg_reg[7]\
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(8),
Q => \n_0_Q_reg_reg[8]\
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => D(9),
Q => \n_0_Q_reg_reg[9]\
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \n_0_Q_reg_reg[0]\,
I3 => \^o1\(3),
O => \^o1\(0)
);
\rd_pntr_bin[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[10]\,
I1 => \^q\(0),
O => \^o1\(10)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \n_0_Q_reg_reg[3]\,
I3 => \n_0_Q_reg_reg[5]\,
I4 => \^o1\(6),
I5 => \n_0_Q_reg_reg[4]\,
O => \^o1\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[5]\,
I2 => \^o1\(6),
I3 => \n_0_Q_reg_reg[4]\,
I4 => \n_0_Q_reg_reg[2]\,
O => \^o1\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[4]\,
I1 => \^o1\(6),
I2 => \n_0_Q_reg_reg[5]\,
I3 => \n_0_Q_reg_reg[3]\,
O => \^o1\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[5]\,
I1 => \^o1\(6),
I2 => \n_0_Q_reg_reg[4]\,
O => \^o1\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(6),
I1 => \n_0_Q_reg_reg[5]\,
O => \^o1\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \n_0_Q_reg_reg[7]\,
I1 => \^q\(0),
I2 => \n_0_Q_reg_reg[9]\,
I3 => \n_0_Q_reg_reg[10]\,
I4 => \n_0_Q_reg_reg[8]\,
I5 => \n_0_Q_reg_reg[6]\,
O => \^o1\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[8]\,
I1 => \n_0_Q_reg_reg[10]\,
I2 => \n_0_Q_reg_reg[9]\,
I3 => \^q\(0),
I4 => \n_0_Q_reg_reg[7]\,
O => \^o1\(7)
);
\rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^q\(0),
I1 => \n_0_Q_reg_reg[9]\,
I2 => \n_0_Q_reg_reg[10]\,
I3 => \n_0_Q_reg_reg[8]\,
O => \^o1\(8)
);
\rd_pntr_bin[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[10]\,
I1 => \n_0_Q_reg_reg[9]\,
I2 => \^q\(0),
O => \^o1\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_bin_cntr is
port (
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
sel : in STD_LOGIC;
wr_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end shd_pe_fifo_wr_bin_cntr;
architecture STRUCTURE of shd_pe_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \n_0_gic0.gc0.count[0]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[0]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[10]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[10]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[1]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[1]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[2]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[3]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[4]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[4]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[5]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[5]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[6]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[6]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[7]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[7]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[8]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[8]_i_2\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[9]_i_1\ : STD_LOGIC;
signal \n_0_gic0.gc0.count_reg[9]_i_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gic0.gc0.count_reg[1]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \gic0.gc0.count_reg[1]_i_2_CARRY4\ : label is "LO:O";
attribute XILINX_LEGACY_PRIM of \gic0.gc0.count_reg[5]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP of \gic0.gc0.count_reg[5]_i_2_CARRY4\ : label is "LO:O";
attribute XILINX_LEGACY_PRIM of \gic0.gc0.count_reg[9]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP of \gic0.gc0.count_reg[9]_i_2_CARRY4\ : label is "LO:O";
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\out\(11 downto 0) <= \^out\(11 downto 0);
\gic0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(0),
O => \n_0_gic0.gc0.count[0]_i_2\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => sel,
D => \^out\(0),
PRE => I1(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(10),
Q => \^q\(10)
);
\gic0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(11),
Q => \^q\(11)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^out\(9),
Q => \^q\(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(0),
Q => O1(0)
);
\gic0.gc0.count_d2_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(10),
Q => O1(10)
);
\gic0.gc0.count_d2_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(11),
Q => O1(11)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(1),
Q => O1(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(2),
Q => O1(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(3),
Q => O1(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(4),
Q => O1(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(5),
Q => O1(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(6),
Q => O1(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(7),
Q => O1(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(8),
Q => O1(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \^q\(9),
Q => O1(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[0]_i_1\,
Q => \^out\(0)
);
\gic0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[10]_i_1\,
Q => \^out\(10)
);
\gic0.gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[11]_i_1\,
Q => \^out\(11)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => sel,
D => \n_0_gic0.gc0.count_reg[1]_i_1\,
PRE => I1(0),
Q => \^out\(1)
);
\gic0.gc0.count_reg[1]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gic0.gc0.count_reg[4]_i_2\,
CO(2) => \n_0_gic0.gc0.count_reg[3]_i_2\,
CO(1) => \n_0_gic0.gc0.count_reg[2]_i_2\,
CO(0) => \n_0_gic0.gc0.count_reg[1]_i_2\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '1',
O(3) => \n_0_gic0.gc0.count_reg[3]_i_1\,
O(2) => \n_0_gic0.gc0.count_reg[2]_i_1\,
O(1) => \n_0_gic0.gc0.count_reg[1]_i_1\,
O(0) => \n_0_gic0.gc0.count_reg[0]_i_1\,
S(3 downto 1) => \^out\(3 downto 1),
S(0) => \n_0_gic0.gc0.count[0]_i_2\
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[2]_i_1\,
Q => \^out\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[3]_i_1\,
Q => \^out\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[4]_i_1\,
Q => \^out\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[5]_i_1\,
Q => \^out\(5)
);
\gic0.gc0.count_reg[5]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gic0.gc0.count_reg[4]_i_2\,
CO(3) => \n_0_gic0.gc0.count_reg[8]_i_2\,
CO(2) => \n_0_gic0.gc0.count_reg[7]_i_2\,
CO(1) => \n_0_gic0.gc0.count_reg[6]_i_2\,
CO(0) => \n_0_gic0.gc0.count_reg[5]_i_2\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3) => \n_0_gic0.gc0.count_reg[7]_i_1\,
O(2) => \n_0_gic0.gc0.count_reg[6]_i_1\,
O(1) => \n_0_gic0.gc0.count_reg[5]_i_1\,
O(0) => \n_0_gic0.gc0.count_reg[4]_i_1\,
S(3 downto 0) => \^out\(7 downto 4)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[6]_i_1\,
Q => \^out\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[7]_i_1\,
Q => \^out\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[8]_i_1\,
Q => \^out\(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => sel,
CLR => I1(0),
D => \n_0_gic0.gc0.count_reg[9]_i_1\,
Q => \^out\(9)
);
\gic0.gc0.count_reg[9]_i_2_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gic0.gc0.count_reg[8]_i_2\,
CO(3 downto 2) => \NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \n_0_gic0.gc0.count_reg[10]_i_2\,
CO(0) => \n_0_gic0.gc0.count_reg[9]_i_2\,
CYINIT => '0',
DI(3) => \NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED\(3),
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3) => \n_0_gic0.gc0.count_reg[11]_i_1\,
O(2) => \n_0_gic0.gc0.count_reg[10]_i_1\,
O(1) => \n_0_gic0.gc0.count_reg[9]_i_1\,
O(0) => \n_0_gic0.gc0.count_reg[8]_i_1\,
S(3 downto 0) => \^out\(11 downto 8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end shd_pe_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.shd_pe_fifo_blk_mem_gen_prim_wrapper
port map (
D(7 downto 0) => D(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_clk_x_pntrs is
port (
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 11 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_clk_x_pntrs : entity is "clk_x_pntrs";
end shd_pe_fifo_clk_x_pntrs;
architecture STRUCTURE of shd_pe_fifo_clk_x_pntrs is
signal Q_0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[0]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[10]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[1]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[2]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[3]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[4]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[5]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[6]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[7]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[8]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_gc[9]_i_1\ : STD_LOGIC;
signal \n_10_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_10_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_11_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_11_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_5_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_5_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_6_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_6_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_7_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_7_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_8_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_8_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_9_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_9_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_0_in10_out : STD_LOGIC_VECTOR ( 10 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_pntr_gc[8]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rd_pntr_gc[9]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \wr_pntr_gc[8]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_pntr_gc[9]_i_1\ : label is "soft_lutpair12";
begin
\gsync_stage[1].rd_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff
port map (
I1(11 downto 0) => wr_pntr_gc(11 downto 0),
I3(0) => I3(0),
Q(11 downto 0) => Q_0(11 downto 0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_3
port map (
I1(11 downto 0) => rd_pntr_gc(11 downto 0),
I2(0) => I2(0),
Q(11) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(10) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(9) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(8) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(7) => \n_4_gsync_stage[1].wr_stg_inst\,
Q(6) => \n_5_gsync_stage[1].wr_stg_inst\,
Q(5) => \n_6_gsync_stage[1].wr_stg_inst\,
Q(4) => \n_7_gsync_stage[1].wr_stg_inst\,
Q(3) => \n_8_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_9_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_10_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_11_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_4
port map (
D(11 downto 0) => Q_0(11 downto 0),
I3(0) => I3(0),
p_0_in(11 downto 0) => p_0_in(11 downto 0),
rd_clk => rd_clk
);
\gsync_stage[2].wr_stg_inst\: entity work.shd_pe_fifo_synchronizer_ff_5
port map (
D(11) => \n_0_gsync_stage[1].wr_stg_inst\,
D(10) => \n_1_gsync_stage[1].wr_stg_inst\,
D(9) => \n_2_gsync_stage[1].wr_stg_inst\,
D(8) => \n_3_gsync_stage[1].wr_stg_inst\,
D(7) => \n_4_gsync_stage[1].wr_stg_inst\,
D(6) => \n_5_gsync_stage[1].wr_stg_inst\,
D(5) => \n_6_gsync_stage[1].wr_stg_inst\,
D(4) => \n_7_gsync_stage[1].wr_stg_inst\,
D(3) => \n_8_gsync_stage[1].wr_stg_inst\,
D(2) => \n_9_gsync_stage[1].wr_stg_inst\,
D(1) => \n_10_gsync_stage[1].wr_stg_inst\,
D(0) => \n_11_gsync_stage[1].wr_stg_inst\,
I2(0) => I2(0),
O1(10) => \n_1_gsync_stage[2].wr_stg_inst\,
O1(9) => \n_2_gsync_stage[2].wr_stg_inst\,
O1(8) => \n_3_gsync_stage[2].wr_stg_inst\,
O1(7) => \n_4_gsync_stage[2].wr_stg_inst\,
O1(6) => \n_5_gsync_stage[2].wr_stg_inst\,
O1(5) => \n_6_gsync_stage[2].wr_stg_inst\,
O1(4) => \n_7_gsync_stage[2].wr_stg_inst\,
O1(3) => \n_8_gsync_stage[2].wr_stg_inst\,
O1(2) => \n_9_gsync_stage[2].wr_stg_inst\,
O1(1) => \n_10_gsync_stage[2].wr_stg_inst\,
O1(0) => \n_11_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_0_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_11_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(0)
);
\rd_pntr_bin_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(10)
);
\rd_pntr_bin_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(11)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_10_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_9_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_8_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_7_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_6_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_5_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_4_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_3_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(8)
);
\rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => \n_2_gsync_stage[2].wr_stg_inst\,
Q => RD_PNTR_WR(9)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(0),
I1 => I1(1),
O => \n_0_rd_pntr_gc[0]_i_1\
);
\rd_pntr_gc[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(10),
I1 => I1(11),
O => \n_0_rd_pntr_gc[10]_i_1\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(1),
I1 => I1(2),
O => \n_0_rd_pntr_gc[1]_i_1\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(2),
I1 => I1(3),
O => \n_0_rd_pntr_gc[2]_i_1\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(3),
I1 => I1(4),
O => \n_0_rd_pntr_gc[3]_i_1\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(4),
I1 => I1(5),
O => \n_0_rd_pntr_gc[4]_i_1\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(5),
I1 => I1(6),
O => \n_0_rd_pntr_gc[5]_i_1\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(6),
I1 => I1(7),
O => \n_0_rd_pntr_gc[6]_i_1\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(7),
I1 => I1(8),
O => \n_0_rd_pntr_gc[7]_i_1\
);
\rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(8),
I1 => I1(9),
O => \n_0_rd_pntr_gc[8]_i_1\
);
\rd_pntr_gc[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I1(9),
I1 => I1(10),
O => \n_0_rd_pntr_gc[9]_i_1\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[0]_i_1\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[10]_i_1\,
Q => rd_pntr_gc(10)
);
\rd_pntr_gc_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => I1(11),
Q => rd_pntr_gc(11)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[1]_i_1\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[2]_i_1\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[3]_i_1\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[4]_i_1\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[5]_i_1\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[6]_i_1\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[7]_i_1\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[8]_i_1\,
Q => rd_pntr_gc(8)
);
\rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => \n_0_rd_pntr_gc[9]_i_1\,
Q => rd_pntr_gc(9)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(0),
Q => WR_PNTR_RD(0)
);
\wr_pntr_bin_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(10),
Q => WR_PNTR_RD(10)
);
\wr_pntr_bin_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(11),
Q => WR_PNTR_RD(11)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(1),
Q => WR_PNTR_RD(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(2),
Q => WR_PNTR_RD(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(3),
Q => WR_PNTR_RD(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(4),
Q => WR_PNTR_RD(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(5),
Q => WR_PNTR_RD(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(6),
Q => WR_PNTR_RD(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(7),
Q => WR_PNTR_RD(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(8),
Q => WR_PNTR_RD(8)
);
\wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I3(0),
D => p_0_in(9),
Q => WR_PNTR_RD(9)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => p_0_in10_out(0)
);
\wr_pntr_gc[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(10),
I1 => Q(11),
O => p_0_in10_out(10)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => p_0_in10_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => p_0_in10_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => p_0_in10_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => p_0_in10_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => p_0_in10_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => p_0_in10_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => p_0_in10_out(7)
);
\wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => p_0_in10_out(8)
);
\wr_pntr_gc[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => Q(10),
O => p_0_in10_out(9)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(10),
Q => wr_pntr_gc(10)
);
\wr_pntr_gc_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => Q(11),
Q => wr_pntr_gc(11)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(8),
Q => wr_pntr_gc(8)
);
\wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => p_0_in10_out(9),
Q => wr_pntr_gc(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_status_flags_as : entity is "rd_status_flags_as";
end shd_pe_fifo_rd_status_flags_as;
architecture STRUCTURE of shd_pe_fifo_rd_status_flags_as is
signal comp0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_1 : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
c0: entity work.shd_pe_fifo_compare_1
port map (
O1(11 downto 0) => O1(11 downto 0),
WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0),
comp0 => comp0
);
c1: entity work.shd_pe_fifo_compare_2
port map (
WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0),
comp1 => comp1,
\out\(11 downto 0) => \out\(11 downto 0)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEFFFAAAAAAAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => I1(0),
I3 => I1(1),
I4 => \^p_18_out\,
I5 => comp1,
O => n_0_ram_empty_fb_i_i_1
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => n_0_ram_empty_fb_i_i_1,
PRE => Q(0),
Q => \^p_18_out\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_status_flags_as is
port (
full : out STD_LOGIC;
sel : out STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_status_flags_as : entity is "wr_status_flags_as";
end shd_pe_fifo_wr_status_flags_as;
architecture STRUCTURE of shd_pe_fifo_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_0_out,
O => sel
);
c1: entity work.shd_pe_fifo_compare
port map (
Q(11 downto 0) => Q(11 downto 0),
RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0),
comp1 => comp1
);
c2: entity work.shd_pe_fifo_compare_0
port map (
RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0),
comp2 => comp2,
\out\(11 downto 0) => \out\(11 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => p_0_out
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => rst_full_gen_i,
I1 => comp2,
I2 => p_0_out,
I3 => wr_en,
I4 => comp1,
O => ram_full_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end shd_pe_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.shd_pe_fifo_blk_mem_gen_prim_width
port map (
D(7 downto 0) => D(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_rd_logic is
port (
empty : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_rd_logic : entity is "rd_logic";
end shd_pe_fifo_rd_logic;
architecture STRUCTURE of shd_pe_fifo_rd_logic is
signal \^o1\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_2_gr1.rfwft\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
begin
O1(11 downto 0) <= \^o1\(11 downto 0);
\gr1.rfwft\: entity work.shd_pe_fifo_rd_fwft
port map (
E(0) => E(0),
O1(1) => \n_2_gr1.rfwft\,
O1(0) => curr_fwft_state(0),
Q(1 downto 0) => Q(1 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
sel => p_14_out,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.shd_pe_fifo_rd_status_flags_as
port map (
I1(1) => \n_2_gr1.rfwft\,
I1(0) => curr_fwft_state(0),
O1(11 downto 0) => \^o1\(11 downto 0),
Q(0) => Q(1),
WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0),
\out\(11 downto 0) => rd_pntr_plus1(11 downto 0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en
);
rpntr: entity work.shd_pe_fifo_rd_bin_cntr
port map (
O1(11 downto 0) => \^o1\(11 downto 0),
Q(0) => Q(1),
\out\(11 downto 0) => rd_pntr_plus1(11 downto 0),
rd_clk => rd_clk,
sel => p_14_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_wr_logic is
port (
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 );
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_wr_logic : entity is "wr_logic";
end shd_pe_fifo_wr_logic;
architecture STRUCTURE of shd_pe_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 11 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwas.wsts\: entity work.shd_pe_fifo_wr_status_flags_as
port map (
Q(11 downto 0) => p_8_out(11 downto 0),
RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0),
full => full,
\out\(11 downto 0) => wr_pntr_plus2(11 downto 0),
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
sel => \^wea\(0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.shd_pe_fifo_wr_bin_cntr
port map (
I1(0) => Q(0),
O1(11 downto 0) => O1(11 downto 0),
Q(11 downto 0) => p_8_out(11 downto 0),
\out\(11 downto 0) => wr_pntr_plus2(11 downto 0),
sel => \^wea\(0),
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end shd_pe_fifo_blk_mem_gen_top;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.shd_pe_fifo_blk_mem_gen_generic_cstr
port map (
D(7 downto 0) => D(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_blk_mem_gen_v8_2_synth is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end shd_pe_fifo_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of shd_pe_fifo_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.shd_pe_fifo_blk_mem_gen_top
port map (
D(7 downto 0) => D(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_pe_fifo_blk_mem_gen_v8_2__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_pe_fifo_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \shd_pe_fifo_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \shd_pe_fifo_blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.shd_pe_fifo_blk_mem_gen_v8_2_synth
port map (
D(7 downto 0) => D(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
O1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_memory : entity is "memory";
end shd_pe_fifo_memory;
architecture STRUCTURE of shd_pe_fifo_memory is
signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\shd_pe_fifo_blk_mem_gen_v8_2__parameterized0\
port map (
D(7 downto 0) => doutb(7 downto 0),
I1(11 downto 0) => I1(11 downto 0),
O1(11 downto 0) => O1(11 downto 0),
Q(0) => Q(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end shd_pe_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \n_1_gntv_or_sync_fifo.gl0.wr\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.shd_pe_fifo_clk_x_pntrs
port map (
I1(11 downto 0) => p_20_out(11 downto 0),
I2(0) => wr_rst_i(0),
I3(0) => rd_rst_i(1),
Q(11 downto 0) => p_9_out(11 downto 0),
RD_PNTR_WR(11 downto 0) => p_0_out(11 downto 0),
WR_PNTR_RD(11 downto 0) => p_1_out(11 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.shd_pe_fifo_rd_logic
port map (
E(0) => p_15_out,
O1(11 downto 0) => p_20_out(11 downto 0),
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
WR_PNTR_RD(11 downto 0) => p_1_out(11 downto 0),
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.shd_pe_fifo_wr_logic
port map (
O1(11 downto 0) => p_9_out(11 downto 0),
Q(0) => \^rst\,
RD_PNTR_WR(11 downto 0) => p_0_out(11 downto 0),
WEA(0) => \n_1_gntv_or_sync_fifo.gl0.wr\,
full => full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.shd_pe_fifo_memory
port map (
E(0) => p_15_out,
I1(11 downto 0) => p_20_out(11 downto 0),
O1(11 downto 0) => p_9_out(11 downto 0),
Q(0) => rd_rst_i(0),
WEA(0) => \n_1_gntv_or_sync_fifo.gl0.wr\,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.shd_pe_fifo_reset_blk_ramfifo
port map (
O1(2) => RD_RST,
O1(1 downto 0) => rd_rst_i(1 downto 0),
Q(1) => \^rst\,
Q(0) => wr_rst_i(0),
rd_clk => rd_clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_top : entity is "fifo_generator_top";
end shd_pe_fifo_fifo_generator_top;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.shd_pe_fifo_fifo_generator_ramfifo
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_pe_fifo_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end shd_pe_fifo_fifo_generator_v12_0_synth;
architecture STRUCTURE of shd_pe_fifo_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.shd_pe_fifo_fifo_generator_top
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "4kx9";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4095;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4094;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4096;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ : entity is 0;
end \shd_pe_fifo_fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \shd_pe_fifo_fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.shd_pe_fifo_fifo_generator_v12_0_synth
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_pe_fifo is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of shd_pe_fifo : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shd_pe_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of shd_pe_fifo : entity is "fifo_generator_v12_0,Vivado 2014.3";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of shd_pe_fifo : entity is "shd_pe_fifo,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of shd_pe_fifo : entity is "shd_pe_fifo,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4095,C_PROG_FULL_THRESH_NEGATE_VAL=4094,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end shd_pe_fifo;
architecture STRUCTURE of shd_pe_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4095;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4094;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\shd_pe_fifo_fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11) => '0',
prog_empty_thresh(10) => '0',
prog_empty_thresh(9) => '0',
prog_empty_thresh(8) => '0',
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(11) => '0',
prog_empty_thresh_assert(10) => '0',
prog_empty_thresh_assert(9) => '0',
prog_empty_thresh_assert(8) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(11) => '0',
prog_empty_thresh_negate(10) => '0',
prog_empty_thresh_negate(9) => '0',
prog_empty_thresh_negate(8) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11) => '0',
prog_full_thresh(10) => '0',
prog_full_thresh(9) => '0',
prog_full_thresh(8) => '0',
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(11) => '0',
prog_full_thresh_assert(10) => '0',
prog_full_thresh_assert(9) => '0',
prog_full_thresh_assert(8) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(11) => '0',
prog_full_thresh_negate(10) => '0',
prog_full_thresh_negate(9) => '0',
prog_full_thresh_negate(8) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd
|
8
|
79859
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
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bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57376)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
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